KR102648236B1 - Level Shifter with Improved Power Efficiency and Input Voltage Range - Google Patents

Abstract

A level shifter with improved energy efficiency and input voltage range is disclosed.
The level shifter according to an embodiment of the present invention converts the voltage level of the output signal (OUT) according to the voltage level of the input signal (IN) and outputs the input signal (IN) connected to the first power supply voltage. a level shifting unit that receives input, adjusts the voltage level to correspond to the voltage level of the input signal, and outputs the output signal (OUT); and a control signal generator that generates and transmits a control signal that controls the operation of some transistors included in the level shifting unit to convert the voltage level of the output signal (OUT) when converting the voltage level of the input signal (IN). can do.

Description

Level Shifter with Improved Power Efficiency and Input Voltage Range}

The present invention relates to a level shifter with improved energy efficiency and input voltage range.

The content described in this section simply provides background information on embodiments of the present invention and does not constitute prior art.

The use of integrated circuits is increasing due to the increased use of cutting-edge systems such as mobile phones, computers, and self-driving cars. A level shifter is one of the important components used in the connection between blocks within an integrated circuit, and is a key component that enables the use of various voltages of the blocks within the integrated circuit.

General level shifters have problems such as static current flowing, full swing being impossible, and floating high state. In addition, general level shifters have a problem in that they do not operate normally at low voltages where the input voltage range is below a certain level.

The present invention solves the problems of existing level shifters and provides a level shifter that uses energy only when changing a low-voltage input voltage to a high voltage and improves energy efficiency and the range of input voltage by enabling conversion from low-voltage input to high voltage. The main purpose is to

According to one aspect of the present invention, the level shifter for achieving the above object is a level shifter that converts the voltage level of the output signal (OUT) according to the voltage level of the input signal (IN) and outputs the first power supply voltage. A level shifting unit that receives an input signal (IN) connected to and outputs the output signal (OUT) by adjusting the voltage level to correspond to the voltage level of the input signal; and a control signal generator that generates and transmits a control signal that controls the operation of some transistors included in the level shifting unit to convert the voltage level of the output signal (OUT) when converting the voltage level of the input signal (IN). can do.

As described above, the level shifter of the present invention is effective in solving problems such as static current, full swing, and floating that occur in various other existing level shifters.

In addition, the level shifter of the present invention is energy efficient and allows level shifting even at low voltage. Accordingly, the level shifter structure of the present invention can be used in blocks that use low voltage, which can increase the energy efficiency of the integrated circuit and improve operating speed.

1 is a circuit diagram showing a level shifter according to an embodiment of the present invention.
Figure 2 is a diagram for explaining the upward switching operation of the level shifter according to an embodiment of the present invention.
Figure 3 is a diagram for explaining a downward transition operation of a level shifter according to an embodiment of the present invention.
Figure 4 is a diagram showing a level shifter with the fourth PMOS transistor removed to explain the operation of the control signal generator according to an embodiment of the present invention.
Figure 5 is a diagram for explaining the operation of a level shifter by a control signal according to an embodiment of the present invention.
Figure 6 is a diagram for explaining the advantages of a level shifter according to an embodiment of the present invention.
7A and 7B are diagrams showing the transistor stack and FinFET size in the level shifter according to an embodiment of the present invention.
Figure 8 is a diagram showing the operation of a level shifter according to an embodiment of the present invention.
Figure 9 is a diagram showing the results of comparing energy consumption between a level shifter according to an embodiment of the present invention and a conventional level shifter.
Figure 10 is a diagram showing the results of Monte Carlo simulation according to an embodiment of the present invention.
Figure 11 is a diagram showing the results of comparing the degree of delay between a level shifter according to an embodiment of the present invention and a number of conventional level shifters.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings. In describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description will be omitted. In addition, preferred embodiments of the present invention will be described below, but the technical idea of the present invention is not limited or restricted thereto, and of course, it can be modified and implemented in various ways by those skilled in the art. Hereinafter, the level shifter with improved energy efficiency and input voltage range proposed in the present invention will be described in detail with reference to the drawings.

The level shifter according to the present invention can be applied to products such as CPU (Central Processing Unit), SRAM (Static Random Access Memory), and DRAM (Dynamic Random Access Memory). Additionally, the level shifter according to the present invention can be partially applied to products such as mobile phones, wireless earphones, IoT home appliances, computers, and self-driving cars.

1 is a circuit diagram showing a level shifter according to an embodiment of the present invention.

The level shifter 10 according to an embodiment of the present invention blocks static current in CMLS (Current Mirror Based Level Shifter), consumes energy only during level shifting operation, and can level shift even at low voltage. (Level Shifting) This is a circuit regarding possible structures.

The level shifter 10 according to the present invention blocks static current and includes a level shifting unit 100 and a control signal generating unit 200 to solve various level shifter problems. The level shifting unit 100 is a circuit that performs level shifting, and the control signal generating unit 200 is a circuit that generates a control signal (Y signal) transmitted to the level shifting unit 100.

The level shifting unit 100 according to this embodiment receives the input signal (IN) connected to the first power supply voltage (VDDL), and adjusts the voltage level of the output signal (OUT) to correspond to the voltage level of the input signal. Outputs the level-adjusted output signal (OUT).

The level shifting unit 100 includes at least two NMOS transistors and at least four PMOS transistors. Specifically, the level shifting unit 100 includes at least two NMOS transistors including the first NMOS transistor 110 and the second NMOS transistor 120, the first PMOS transistor 130, the second PMOS transistor 140, It may be composed of at least four PMOS transistors including the third PMOS transistor 150 and the fourth PMOS transistor 160.

The level shifting unit 100 has a second power voltage VDDH, a first connection line, and a second connection line connected in parallel. The second PMOS transistor 140, the first PMOS transistor 130, and the first NMOS transistor 110 are connected in series to the first connection line. Additionally, the third PMOS transistor 150, fourth PMOS transistor 160, and second NMOS transistor 120 are connected in series to the second connection line.

In the level shifting unit 100, the gate of the first NMOS transistor 110 is connected to the input node that receives the input signal, and the contact point between the drain of the fourth PMOS transistor 160 and the second NMOS transistor 120 is connected to the output node that outputs the output signal. Additionally, the gate of the first PMOS transistor 130 is connected to the output node to receive feedback from the output signal.

In the level shifting unit 100, the second PMOS transistor 140 and the third PMOS transistor 150 have a current mirror structure, and the second PMOS transistor 140 and the third PMOS transistor 150 have a current mirror structure. The first mirror node (X node) between the gates is connected to the node between the first PMOS transistor 130 and the first NMOS transistor 110.

The control signal generator 200 according to this embodiment controls the operation of some transistors included in the level shifting unit 100 to convert the voltage level of the output signal (OUT) when converting the voltage level of the input signal (IN). Generates and transmits control signals.

The control signal generator 200 is connected to the gate of the fourth PMOS transistor 160 and the second NMOS transistor 120 of the level shifting unit 100, and the fourth PMOS transistor 160 and the second NMOS transistor 120 ) transmits control signals for operation control. Here, the control signal is preferably an inverting signal obtained by inverting the input signal.

The control signal generator 200 includes at least three NMOS transistors and at least three PMOS transistors. Specifically, the control signal generator 200 includes at least three NMOS transistors including a third NMOS transistor 210, a fourth NMOS transistor 220, and a fifth NMOS transistor 230, and a fifth PMOS transistor 240. , may be composed of at least three PMOS transistors including the sixth PMOS transistor 250 and the seventh PMOS transistor 260.

In the control signal generator 200, a second power voltage, a third connection line, and a fourth connection line are connected in parallel. The sixth PMOS transistor 250, the fifth PMOS transistor 240, and the third NMOS transistor 210 are connected in series to the third connection line. Additionally, the seventh PMOS transistor 260, the fourth NMOS transistor 220, and the fifth NMOS transistor 230 are connected in series to the fourth connection line.

In the control signal generator 200, the gates of the fifth PMOS transistor 240 and the third NMOS transistor 210 are connected to the input node that receives the input signal, and the fifth PMOS transistor 240 and the third NMOS transistor 210 are connected to the input node. The contact point between the drains of 210 is connected to a control node that outputs a control signal, and the control node uses the fourth PMOS transistor 160 and the second NMOS transistor 120 to apply a control signal to the level shifting unit 100. ) is connected to the gate of In addition, the gate of the fourth NMOS transistor 220 is connected to an inverting input node that receives an inverting signal for the input signal, and the gate of the fifth NMOS transistor 230 is connected to an output node to receive feedback of the output signal. do.

In the level shifting unit 100, the sixth PMOS transistor 250 and the seventh PMOS transistor 260 have a current mirror structure, and the sixth PMOS transistor 250 and the seventh PMOS transistor 260 have a current mirror structure. The second mirror node between the gates is connected to the node between the seventh PMOS transistor 260 and the fourth NMOS transistor 220.

Hereinafter, the operation of the level shifter 10 according to this embodiment will be described.

The level shifter 10 performs full swing switching according to the voltage of the input signal.

The level shifter 10 causes the voltage of the output signal to rise to the second power supply voltage when the voltage of the input signal is switched upward to a 'high' state, and the voltage of the input signal is switched upward to a 'high' state. After completion, the voltage of the output signal is maintained at the second power supply voltage.

In addition, the level shifter 10 blocks the current due to pull-up through the fourth PMOS transistor 160 when the voltage of the input signal is transitioned to a 'low' state, and the second NMOS transistor Due to (120), the voltage of the output signal is pulled down to 'low' and the voltage of the output signal changes from ground to the second power supply voltage.

Hereinafter, the operation of the level shifter 10 when the voltage level of the input signal is converted upward will be described.

When the voltage of the input signal is converted upward from 'low' to 'high', the level shifter 10 (i) turns on the first NMOS transistor 110 by the voltage of the input signal, causing the first mirror node to turn 'low'. falls to low, the second PMOS transistor 140 and the third PMOS transistor 150 are turned on, and at the same time, (ii) the third NMOS transistor 210 is turned on by the voltage of the input signal, so that the voltage of the control signal is low. ', and the fourth PMOS transistor 160 is turned on. The level shifter 10 (iii) outputs an output signal whose voltage is increased to 'high' to the output node through the third PMOS transistor 150 and the fourth PMOS transistor 160.

Hereinafter, the operation of the level shifter 10 when the voltage level of the input signal is converted downward will be described.

When the voltage of the input signal is converted from 'high' to 'low', the level shifter 10 (i) turns on the fifth PMOS transistor 240 by the voltage of the input signal, and at the same time, (ii) The fourth NMOS transistor 220 is turned on by the voltage of the butting signal, causing the second mirror node to fall to 'low', and the sixth PMOS transistor 250 and the seventh PMOS transistor 260 are turned on. The level shifter 10 (iii) outputs a control signal whose voltage is increased to 'high' through the sixth PMOS transistor 250 and the fifth PMOS transistor 240, and (iv) is controlled by the voltage of the input signal. 2 The NMOS transistor 120 is turned on and outputs an output signal whose voltage is lowered to 'low' to the output node.

The level shifter 10 of the present invention can solve problems such as static current, full swing, and floating that occur in various other existing level shifters.

Additionally, the level shifter 10 of the present invention is energy efficient and allows level shifting even at low voltage. Accordingly, the structure of the level shifter 10 of the present invention can be applied to blocks that use low voltage, which can increase the energy efficiency of the integrated circuit and improve operating speed.

Figure 2 is a diagram for explaining the upward switching operation of the level shifter according to an embodiment of the present invention.

In Figure 2, the operation of the level shifter 10 when the voltage of the input signal changes upward from '0' to '1' will be explained.

In the level shifter 10, when the voltage of the input signal is converted upward from 'low' to 'high' (①), the first NMOS transistor 110 and the third NMOS transistor 210 are switched by the voltage of the input signal. It turns on.

In the level shifter 10, the first NMOS transistor 110 is turned on by the voltage of the input signal and the first mirror node falls to 'low' (②), and the second PMOS transistor 140 and the third PMOS transistor ( 150) is turned on, and at the same time, the third NMOS transistor 210 is turned on by the voltage of the input signal, the voltage of the control signal falls to 'low' (②), and the fourth PMOS transistor 160 is turned on.

In the level shifter 10, the level shifter 10 outputs an output signal whose voltage is increased to 'high' to the output node through the third PMOS transistor 150 and the fourth PMOS transistor 160 (③). In other words, the current supplied from the second power voltage VDDH through the third PMOS transistor 150 and the fourth PMOS transistor 160 increases the output signal OUT to '1' (VDDH).

Figure 3 is a diagram for explaining a downward transition operation of a level shifter according to an embodiment of the present invention.

In Figure 3, the operation of the level shifter 10 when the voltage of the input signal changes upward from '1' to '0' will be explained.

In the level shifter 10, when the voltage of the input signal is converted down from 'high' to 'low' (①), the fifth PMOS transistor 240 is turned on by the voltage of the input signal, and the voltage of the inverting signal is turned on. The fourth NMOS transistor 220 is turned on.

In the level shifter 10, the fourth NMOS transistor 220 is turned on by the voltage of the inverting signal and the second mirror node falls to 'low', and the sixth PMOS transistor 250 and the seventh PMOS transistor 260 turns on (②).

The level shifter 10 outputs a control signal whose voltage is increased to 'high' through the sixth PMOS transistor 250 and the fifth PMOS transistor 240 (③).

In the level shifter 10, the second NMOS transistor 120 is turned on by the voltage of the control signal and outputs an output signal whose voltage is lowered to 'low' to the output node (④).

FIG. 4 is a diagram showing a level shifter with the fourth PMOS transistor removed to explain the operation of the control signal generator according to an embodiment of the present invention, and FIG. 5 is a diagram showing the operation of the level shifter by a control signal according to an embodiment of the present invention. This is a drawing to explain.

The level shifting unit 100 is composed of at least four PMOS transistors and at least two NPMOS transistors. The level shifting unit 100 switches the output voltage (OUT) upward or downward based on the input voltage.

The control signal generator 200 is composed of at least three PMOS transistors and at least three NMOS transistors. The control signal generator 200 generates a control signal inverted to the input voltage and transmits the control signal to at least one transistor of the specific PMOS transistor and the NPMOS transistor of the level shifting unit 100.

Hereinafter, the level shifting unit 100 will be described.

The level shifting unit 100 is composed of a circuit that raises OUT to '1' (VDDH) and lowers it to '0' (GND).

The reason why the level shifter 10 according to this embodiment does not operate with only the level shifting unit 100 without the control signal generating unit 200 is as follows. As shown in FIG. 4, when there is no control signal generator 200 and the fourth PMOS transistor is not present in the level shifting unit 100, the output voltage (OUT) is '1' when the input voltage switches to falling. ', the first PMOS transistor is turned off, so the first mirror node (X node) cannot be pulled up, so it maintains the '0' state. Therefore, there is a problem in that the output voltage (OUT) is fixed to '1' by the third PMOS transistor and the output voltage (OUT) cannot be lowered to '0'. Therefore, a fourth PMOS transistor is needed to block the pull-up current flowing from the third PMOS transistor.

To block the current caused by P pull-up flowing from the third PMOS transistor using the fourth PMOS transistor, the fourth PMOS transistor must be turned off when the input signal (IN) is '0', so the control signal is '1'. It should be this. Additionally, when the input voltage changes to rising, if the input voltage is '1', the fourth PMOS transistor must be turned on, so the control signal must be '0'. Therefore, it is desirable that the control signal is an inverted signal of the input voltage (IN).

Hereinafter, the control signal generator 200 will be described.

The control signal generator 200 generates a control signal whose phase is inverted to IN for operating the fourth PMOS transistor in order to operate the level shifting unit 100.

Referring to FIG. 5, the control signal generator 200 connects the gates of the third NMOS transistor and the fifth PMOS transistor to the input voltage IN to generate an inverted signal. Additionally, the control signal generator 200 must generate a signal amplified by the input voltage IN, which is the first power supply voltage, in order to reliably turn on and off the fourth PMOS transistor and the second NMOS transistor.

To generate a control signal, the control signal generator 200 uses a fourth NMOS transistor and a fifth NMOS transistor to create a LECC (Logic Error Correction Circuit) that operates only when the input voltage (IN) and output voltage (OUT) are different. You can use it. The control signal generator 200 uses the LECC to generate the fifth PMOS transistor to make the control signal (Y signal) to '1', which is close to the second power voltage (VDDH) when the input voltage (IN) is '0'. 6 Connect to the second power voltage (VDDH) through a PMOS transistor.

As shown in FIG. 5, when the input voltage (IN) of the level shifter 10 is '0', the control signal (Y signal) becomes '1', and the fourth PMOS transistor is in pull-up. It is possible to block the current caused by Additionally, the output voltage OUT is pulled down to '0' by the second NMOS transistor that receives the control signal from the level shifter 10.

Figure 6 is a diagram for explaining the advantages of a level shifter according to an embodiment of the present invention.

The level shifter 10 according to this embodiment performs an operation to block static current.

Specifically, when the voltage of the input signal is in a 'high' state, the level shifting unit 100 of the level shifter 10 operates in an off state so that the first PMOS transistor, which receives feedback from the voltage of the output signal, is turned off. And it is possible to block static current flowing through the first NMOS transistor.

Additionally, the level shifter 10 according to this embodiment performs a floating prevention operation. In other words, the level shifting unit 100 of the level shifter 10 prevents the floating high state from occurring.

Specifically, the level shifting unit 100 of the level shifter 10 has the first mirror node fixed to '0' by the first NMOS transistor after the voltage of the input signal is converted to 'high'. Pull-up current is supplied from the second power supply voltage through the third PMOS transistor and the fourth PMOS transistor, so that the output signal is maintained at the second power supply voltage, and the output signal is floating high. It can be prevented from becoming in a state.

Additionally, the level shifter 10 according to this embodiment performs full swing switching according to the voltage of the input signal.

Specifically, when the voltage of the input signal is switched upward to the 'high' state, the level shifter 10 causes the voltage of the output signal to rise to the second power supply voltage and keeps the voltage of the input signal in the 'high' state. After the rising transition is completed, the voltage of the output signal operates to maintain the second power supply voltage. In addition, when the voltage of the input signal is switched to a 'low' state, the level shifter 10 blocks the current due to pull-up through the fourth PMOS transistor and outputs the output due to the second NMOS transistor. The voltage of the signal is pulled down to 'low' so that the voltage of the output signal changes from ground to the second power supply voltage.

7A and 7B are diagrams showing the transistor stack and FinFET size in the level shifter according to an embodiment of the present invention.

FIG. 7A is a diagram showing a MOS transistor stack in the level shifter 10 according to an embodiment of the present invention, and FIG. 7B is a diagram showing the FinFET size in the level shifter 10 according to an embodiment of the present invention. am.

As shown in FIG. 7A, the level considering the order of the NMOS transistor stack (NFET stack, 700) of the pull-down path for the fourth NMOS transistor 220 - the fifth NMOS transistor 230. The circuit of the shifter 10 can be designed. For example, the level shifter 10 according to this embodiment can be sized using 4nm to 7nm FinFET. Each transistor included in the level shifter 10 may have a different number of Fins depending on the purpose, as shown in FIG. 7B.

Figure 8 is a diagram showing the operation of a level shifter according to an embodiment of the present invention.

Figure 8(a) shows the upward switching operation of the level shifter 10, and Figure 10(b) shows the downward switching operation of the level shifter 10.

Figure 9 is a diagram showing the results of comparing energy consumption between a level shifter according to an embodiment of the present invention and a conventional level shifter.

Figure 9 shows the results of comparing energy consumption between the level shifter 10, CPLS, and CMLS according to this embodiment. Referring to FIG. 9, it can be seen that the level shifter 10 according to an embodiment of the present invention has energy efficiency improved by 48.4% compared to CPLS at 0.6 v and energy efficiency improved by 79.69% compared to CMLS. .

Figure 10 is a diagram showing the results of Monte Carlo simulation according to an embodiment of the present invention.

Figure 10 shows the results of processing Monte Carlo simulation number 2000. As shown in Figure 10, it can be seen that CPLS produces unstable level shifting results as a result of Monte Carlo simulation when the voltage is 0.4 v.

On the other hand, it can be confirmed that the level shifter 10 of the present invention performs stable level shifting at 0.4 v. Therefore, it can be confirmed that the level shifter 10 structure of the present invention has a wider input range than CPLS.

Figure 11 is a diagram showing the results of comparing the degree of delay between a level shifter according to an embodiment of the present invention and a number of conventional level shifters.

Referring to the graph in FIG. 11, the circuit with the fastest operation speed due to low delay is CMLS (⑤), but CMLS is difficult to use in practice due to the static current problem. Therefore, it can be confirmed that the level shifter (⑧) of the present invention has a faster operating speed than the structure of other level shifters.

The above description is merely an exemplary explanation of the technical idea of the embodiments of the present invention, and those skilled in the art can make various modifications and modifications without departing from the essential characteristics of the embodiments of the present invention. Transformation will be possible. Accordingly, the embodiments of the present invention are not intended to limit but to explain the technical idea of the embodiment of the present invention, and the scope of the technical idea of the embodiment of the present invention is not limited by these embodiments. The scope of protection of the embodiments of the present invention should be interpreted in accordance with the claims below, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of rights of the embodiments of the present invention.

10: Level shifter
100: level shifting unit
200: Control signal generator

Claims (13)

In the level shifter that converts and outputs the voltage level of the output signal (OUT) according to the voltage level of the input signal (IN),
a level shifting unit that receives an input signal (IN) connected to a first power supply voltage, adjusts the voltage level to correspond to the voltage level of the input signal, and outputs the output signal (OUT); and
A control signal generator that generates and transmits a control signal that controls the operation of some transistors included in the level shifting unit to convert the voltage level of the output signal (OUT) when converting the voltage level of the input signal (IN), ,
The level shifting unit includes at least two NMOS transistors and at least four PMOS transistors, wherein the level shifting unit includes at least two NMOS transistors including a first NMOS transistor and a second NMOS transistor, and a first PMOS transistor, Consisting of at least four PMOS transistors including a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor,
In the level shifting unit, a second power voltage, a first connection line, and a second connection line are connected in parallel, and a second PMOS transistor, a first PMOS transistor, and a first NMOS transistor are connected in series to the first connection line. , A level shifter, characterized in that a third PMOS transistor, a fourth PMOS transistor, and a second NMOS transistor are connected in series to the second connection line. delete delete According to paragraph 1,
In the level shifting unit,
The gate of the first NMOS transistor is connected to the input node that receives the input signal, the contact point between the fourth PMOS transistor and the second NMOS transistor is connected to the output node that outputs the output signal, and the gate of the first PMOS transistor is Connected to the output node to receive output signal feedback,
The second PMOS transistor and the third PMOS transistor have a current mirror structure, and the first mirror node between the gate of the second PMOS transistor and the third PMOS transistor is between the first PMOS transistor and the first NMOS transistor. A level shifter characterized by being connected to a node. According to paragraph 1,
The control signal generator,
Connected to the gate of the fourth PMOS transistor and the second NMOS transistor, and applying the control signal for controlling the operation of the fourth PMOS transistor and the second NMOS transistor,
The level shifter, wherein the control signal is an inverting signal obtained by inverting the input signal. According to clause 4,
The control signal generator,
Comprising at least 3 NMOS transistors and at least 3 PMOS transistors,
The control signal generator includes at least three NMOS transistors including a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, and at least three PMOS transistors including a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor. A level shifter characterized by being composed of a transistor. According to clause 6,
The control signal generator,
The second power voltage, the third connection line, and the fourth connection line are connected in parallel,
A sixth PMOS transistor, a fifth PMOS transistor, and a third NMOS transistor are connected in series to the third connection line, and a seventh PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor are connected in series to the fourth connection line. Features a level shifter. In clause 7,
In the control signal generator,
The gates of the fifth PMOS transistor and the third NMOS transistor are connected to the input node that receives the input signal, and the contact point between the fifth PMOS transistor and the third NMOS transistor is connected to the control node that outputs the control signal, and the control node is connected to the gate of the fourth PMOS transistor and the second NMOS transistor to apply a control signal to the level shifting unit, and the gate of the fourth NMOS transistor is connected to an inverting input node that receives an inverting signal for the input signal. , the gate of the fifth NMOS transistor is connected to the output node to receive output signal feedback,
The sixth PMOS transistor and the seventh PMOS transistor have a current mirror structure, and the second mirror node between the gate of the sixth PMOS transistor and the seventh PMOS transistor is between the seventh PMOS transistor and the fourth NMOS transistor. A level shifter characterized by being connected to a node. According to clause 6,
The level shifter is,
When the voltage of the input signal is converted upward from 'low' to 'high', (i) the first NMOS transistor is turned on by the voltage of the input signal, the first mirror node falls to 'low', and the second PMOS transistor And the third PMOS transistor is turned on, and at the same time, (ii) the third NMOS transistor is turned on by the voltage of the input signal, the voltage of the control signal falls to 'low', and the fourth PMOS transistor is turned on, (iii) the third NMOS transistor is turned on by the voltage of the input signal. A level shifter characterized in that the output signal whose voltage is raised to 'high' is output to the output node through the 3 PMOS transistor and the 4th PMOS transistor. According to clause 9,
The level shifting unit,
When the voltage of the input signal is in a 'high' state, the first PMOS transistor that receives the voltage of the output signal as feedback operates in an off state, causing static current to flow through the second PMOS transistor and the first NMOS transistor. A level shifter characterized by blocking. According to clause 9,
The level shifting unit,
After the voltage of the input signal is converted to 'high', the first mirror node is fixed to '0' by the first NMOS transistor, so it is connected to the second power supply voltage through the third and fourth PMOS transistors. A level shifter that receives current through pull-up to maintain the output signal at the second power supply voltage and prevents the output signal from being in a floating high state. According to clause 6,
The level shifting unit,
Full swing conversion is performed depending on the voltage of the input signal,
When the voltage of the input signal is converted to a 'high' state, the voltage of the output signal is raised to the second power supply voltage, and after the upward transition is completed with the voltage of the input signal to be 'high', the voltage of the output signal is raised. This second power supply voltage is maintained,
When the voltage of the input signal transitions to 'low', the current due to pull-up is blocked through the fourth PMOS transistor, and the voltage of the output signal is changed to 'low' due to the second NMOS transistor. A level shifter characterized in that the voltage of the output signal changes from ground to the second power supply voltage by pulling down. According to clause 8,
The level shifter is,
When the voltage of the input signal is converted down from 'high' to 'low', (i) the fifth PMOS transistor is turned on by the voltage of the input signal, and at the same time, (ii) the fourth NMOS transistor is turned on by the voltage of the inverting signal. The transistor is turned on, causing the second mirror node to go 'low', the sixth PMOS transistor and the seventh PMOS transistor are turned on, and (iii) the voltage through the sixth PMOS transistor and the fifth PMOS transistor rises to 'high'. (iv) a level shifter characterized in that the second NMOS transistor is turned on by the voltage of the control signal and the output signal whose voltage is lowered to 'low' is output to the output node.