WO2023038314A1 - Level shifter for improving energy efficiency and input voltage range - Google Patents

Level shifter for improving energy efficiency and input voltage range Download PDF

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Publication number
WO2023038314A1
WO2023038314A1 PCT/KR2022/012201 KR2022012201W WO2023038314A1 WO 2023038314 A1 WO2023038314 A1 WO 2023038314A1 KR 2022012201 W KR2022012201 W KR 2022012201W WO 2023038314 A1 WO2023038314 A1 WO 2023038314A1
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WIPO (PCT)
Prior art keywords
voltage
pmos transistor
transistor
level shifter
level
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PCT/KR2022/012201
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French (fr)
Korean (ko)
Inventor
정한울
박지환
이문현
김경인
하현수
이석희
Original Assignee
광운대학교 산학협력단
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Priority claimed from KR1020220048367A external-priority patent/KR102648236B1/en
Application filed by 광운대학교 산학협력단 filed Critical 광운대학교 산학협력단
Publication of WO2023038314A1 publication Critical patent/WO2023038314A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present invention relates to a level shifter with improved energy efficiency and input voltage range.
  • the research of the present invention is related to the 'development of a computation in-memory compiler for low-power, high-speed implementation of machine learning algorithms (No. 2020R1G1A1009777)', the first research project of life carried out with the support of the National Research Foundation with funding from the Ministry of Science and ICT. do.
  • a level shifter is one of the important components used for connection between internal blocks of an integrated circuit, and is a major component enabling various voltages of internal blocks of an integrated circuit to be used.
  • a general level shifter has problems such as a static current flowing, a full swing impossible problem, a floating high state, and the like.
  • a general level shifter has a problem in that it does not normally operate at a low voltage where the input voltage range is below a certain level.
  • the present invention solves the problems of existing level shifters, uses energy only when changing a low voltage input voltage to a high voltage, and provides a level shifter with improved energy efficiency and range of input voltage capable of switching to a high voltage even at a low voltage input. has a main purpose.
  • the level shifter for achieving the above object is a level shifter for converting and outputting the voltage level of the output signal (OUT) according to the voltage level of the input signal (IN), the first power supply voltage a level shifting unit receiving an input signal (IN) connected to and outputting the output signal (OUT) by adjusting a voltage level to correspond to the voltage level of the input signal; and a control signal generation unit generating and transmitting a control signal for controlling the operation of some transistors included in the level shifting unit in order to convert the voltage level of the output signal OUT when the voltage level of the input signal IN is converted.
  • a control signal generation unit generating and transmitting a control signal for controlling the operation of some transistors included in the level shifting unit in order to convert the voltage level of the output signal OUT when the voltage level of the input signal IN is converted.
  • the level shifter of the present invention has an effect of solving problems such as static current, full swing, and floating occurring in other existing level shifters.
  • the level shifter of the present invention is energy efficient and has an effect of enabling level shifting even at low voltage. Therefore, the level shifter structure of the present invention can be used in a block using a low voltage, which can increase the energy efficiency of the integrated circuit and improve the operating speed.
  • FIG. 1 is a circuit diagram showing a level shifter according to an embodiment of the present invention.
  • FIG. 2 is a diagram for explaining an up conversion operation of a level shifter according to an embodiment of the present invention.
  • FIG. 3 is a diagram for explaining a descending transition operation of a level shifter according to an embodiment of the present invention.
  • FIG. 4 is a diagram showing a level shifter from which a fourth PMOS transistor is removed to explain the operation of a control signal generator according to an embodiment of the present invention.
  • FIG. 5 is a diagram for explaining an operation of a level shifter according to a control signal according to an embodiment of the present invention.
  • FIG. 6 is a diagram for explaining the advantages of a level shifter according to an embodiment of the present invention.
  • FIGS. 7A and 7B are diagrams illustrating a size of a transistor stack and a FinFET in a level shifter according to an embodiment of the present invention.
  • FIG. 8 is a diagram illustrating the operation of a level shifter according to an embodiment of the present invention.
  • FIG. 9 is a diagram showing a result of comparing energy consumption between a level shifter according to an embodiment of the present invention and a conventional level shifter.
  • FIG. 10 is a diagram showing the results of Monte Carlo simulation according to an embodiment of the present invention.
  • FIG. 11 is a diagram showing a result of comparing delay between a level shifter according to an embodiment of the present invention and a plurality of conventional level shifters.
  • the level shifter according to the present invention can be applied to products such as a central processing unit (CPU), static random access memory (SRAM), and dynamic random access memory (DRAM).
  • the level shifter according to the present invention can be partially applied to products such as mobile phones, wireless earphones, IoT home appliances, computers, and self-driving cars.
  • FIG. 1 is a circuit diagram showing a level shifter according to an embodiment of the present invention.
  • the level shifter 10 blocks static current from a current mirror based level shifter (CMLS), consumes energy only during level shifting, and level shifting even at low voltage (Level Shifting) This is a circuit about a possible structure.
  • CMLS current mirror based level shifter
  • the level shifter 10 blocks static current and includes a level shifter 100 and a control signal generator 200 to solve various level shifter problems.
  • the level shifting unit 100 is a circuit that performs level shifting
  • the control signal generating unit 200 is a circuit that generates a control signal (Y signal) transmitted to the level shifting unit 100 .
  • the level shifting unit 100 receives the input signal IN connected to the first power supply voltage VDDL, adjusts the voltage level of the output signal OUT to correspond to the voltage level of the input signal, and It outputs the level-adjusted output signal (OUT).
  • the level shifting unit 100 includes at least two NMOS transistors and at least four PMOS transistors. Specifically, the level shifting unit 100 includes at least two NMOS transistors including the first NMOS transistor 110 and the second NMOS transistor 120, the first PMOS transistor 130, the second PMOS transistor 140, It may be composed of at least four PMOS transistors including the third PMOS transistor 150 and the fourth PMOS transistor 160 .
  • the second power supply voltage VDDH and the first connection line and the second connection line are connected in parallel.
  • the second PMOS transistor 140 , the first PMOS transistor 130 , and the first NMOS transistor 110 are connected in series to the first connection line.
  • the third PMOS transistor 150, the fourth PMOS transistor 160, and the second NMOS transistor 120 are connected in series to the second connection line.
  • the gate of the first NMOS transistor 110 is connected to the input node receiving the input signal, and the contact between the fourth PMOS transistor 160 and the drain of the second NMOS transistor 120. is connected to an output node that outputs an output signal.
  • the gate of the first PMOS transistor 130 is connected to the output node to receive feedback of the output signal.
  • the second PMOS transistor 140 and the third PMOS transistor 150 have a current mirror structure, and the second PMOS transistor 140 and the third PMOS transistor 150
  • the first mirror node (X node) between the gates is connected to a node between the first PMOS transistor 130 and the first NMOS transistor 110 .
  • the control signal generation unit 200 controls the operation of some transistors included in the level shifting unit 100 to convert the voltage level of the output signal OUT when the voltage level of the input signal IN is converted. Generates and transmits control signals.
  • the control signal generator 200 is connected to the gates of the fourth PMOS transistor 160 and the second NMOS transistor 120 of the level shifter 100, and the fourth PMOS transistor 160 and the second NMOS transistor 120 ) transmits a control signal for operation control.
  • the control signal is preferably an inverting signal obtained by inverting an input signal.
  • the control signal generator 200 includes at least three NMOS transistors and at least three PMOS transistors. Specifically, the control signal generator 200 includes at least three NMOS transistors including the third NMOS transistor 210, the fourth NMOS transistor 220, and the fifth NMOS transistor 230 and the fifth PMOS transistor 240. , at least three PMOS transistors including the sixth PMOS transistor 250 and the seventh PMOS transistor 260 .
  • the second power supply voltage, the third connection line, and the fourth connection line are connected in parallel.
  • the sixth PMOS transistor 250 , the fifth PMOS transistor 240 , and the third NMOS transistor 210 are connected in series to the third connection line.
  • the seventh PMOS transistor 260, the fourth NMOS transistor 220, and the fifth NMOS transistor 230 are connected in series to the fourth connection line.
  • the gates of the fifth PMOS transistor 240 and the third NMOS transistor 210 are connected to an input node receiving an input signal, and the fifth PMOS transistor 240 and the third NMOS transistor The contact between the drains of 210 is connected to a control node that outputs a control signal, and the control node is connected to the fourth PMOS transistor 160 and the second NMOS transistor 120 to apply a control signal to the level shifting unit 100. ) is connected to the gate of In addition, the gate of the fourth NMOS transistor 220 is connected to the inverting input node receiving the inverting signal for the input signal, and the gate of the fifth NMOS transistor 230 is connected to the output node to receive the output signal as feedback. do.
  • the sixth PMOS transistor 250 and the seventh PMOS transistor 260 have a current mirror structure, and the sixth PMOS transistor 250 and the seventh PMOS transistor 260 The second mirror node between the gates is connected to a node between the seventh PMOS transistor 260 and the fourth NMOS transistor 220 .
  • the level shifter 10 performs full swing conversion according to the voltage of the input signal.
  • the level shifter 10 causes the voltage of the output signal to rise to the second power supply voltage when the voltage of the input signal is increased to a 'high' state, and the voltage of the input signal is increased to a 'high' state. After completion, the voltage of the output signal maintains the second power supply voltage.
  • the level shifter 10 blocks the current due to the pull-up through the fourth PMOS transistor 160 when the voltage of the input signal is lowered to a 'low' state, and the second NMOS transistor 120 causes the voltage of the output signal to be pulled down to 'low' so that the voltage of the output signal changes from the ground to the second power supply voltage.
  • level shifter 10 when the voltage level of the input signal is up-converted will be described.
  • the level shifter 10 When the level shifter 10 up-converts the voltage of the input signal from 'low' to 'high', (i) the first NMOS transistor 110 is turned on by the voltage of the input signal so that the first mirror node becomes 'low'. , the second PMOS transistor 140 and the third PMOS transistor 150 are turned on, and at the same time, (ii) the third NMOS transistor 210 is turned on by the voltage of the input signal and the voltage of the control signal is 'low'. ', and the fourth PMOS transistor 160 is turned on.
  • the level shifter 10 outputs (iii) an output signal whose voltage is raised to 'high' through the third PMOS transistor 150 and the fourth PMOS transistor 160 to an output node.
  • level shifter 10 when the voltage level of the input signal is down-converted will be described.
  • the level shifter 10 converts the voltage of the input signal down from 'high' to 'low', (i) the fifth PMOS transistor 240 is turned on by the voltage of the input signal, and (ii) The fourth NMOS transistor 220 is turned on by the voltage of the butting signal, the second mirror node drops to 'low', and the sixth PMOS transistor 250 and the seventh PMOS transistor 260 are turned on.
  • the level shifter 10 outputs a control signal whose voltage is raised to 'high' through (iii) the sixth PMOS transistor 250 and the fifth PMOS transistor 240, and (iv) controlled by the voltage of the input signal. 2
  • the NMOS transistor 120 is turned on and outputs an output signal whose voltage drops to 'low' to the output node.
  • the level shifter 10 of the present invention can solve problems such as static current, full swing, and floating occurring in other existing level shifters.
  • the level shifter 10 of the present invention is energy efficient and can perform level shifting even at low voltage. Therefore, the structure of the level shifter 10 of the present invention can be applied to a block using a low voltage, which can increase the energy efficiency of the integrated circuit and improve the operating speed.
  • FIG. 2 is a diagram for explaining an up conversion operation of a level shifter according to an embodiment of the present invention.
  • the first NMOS transistor 110 and the third NMOS transistor 210 are moved by the voltage of the input signal turns on
  • the first NMOS transistor 110 is turned on by the voltage of the input signal, and the first mirror node drops to 'low' (2), and the second PMOS transistor 140 and the third PMOS transistor ( 150) is turned on, and at the same time, the third NMOS transistor 210 is turned on by the voltage of the input signal, the voltage of the control signal drops to 'low' (2), and the fourth PMOS transistor 160 is turned on.
  • the level shifter 10 outputs an output signal whose voltage is raised to 'high' through the third PMOS transistor 150 and the fourth PMOS transistor 160 to an output node (3).
  • the current supplied from the second power voltage VDDH through the third PMOS transistor 150 and the fourth PMOS transistor 160 raises the output signal OUT to '1' (VDDH).
  • FIG. 3 is a diagram for explaining a descending transition operation of a level shifter according to an embodiment of the present invention.
  • the fifth PMOS transistor 240 is turned on by the voltage of the input signal, and the voltage of the inverting signal
  • the fourth NMOS transistor 220 is turned on by
  • the fourth NMOS transistor 220 is turned on by the voltage of the inverting signal so that the second mirror node goes low, and the sixth PMOS transistor 250 and the seventh PMOS transistor 260 turns on (2).
  • the level shifter 10 outputs a control signal whose voltage is raised to 'high' through the sixth PMOS transistor 250 and the fifth PMOS transistor 240 (3).
  • the second NMOS transistor 120 is turned on by the voltage of the control signal and outputs an output signal whose voltage has dropped to 'low' to an output node (4).
  • FIG. 4 is a diagram showing a level shifter from which a fourth PMOS transistor is removed for explaining the operation of a control signal generator according to an embodiment of the present invention
  • FIG. 5 is an operation of the level shifter according to a control signal according to an embodiment of the present invention. It is a drawing for explaining.
  • the level shifting unit 100 includes at least 4 PMOS transistors and at least 2 NPMOS transistors.
  • the level shifting unit 100 converts the output voltage OUT up or down based on the input voltage.
  • the control signal generator 200 includes at least three PMOS transistors and at least three NMOS transistors.
  • the control signal generating unit 200 generates a control signal inverted from an input voltage and transfers the control signal to at least one of a specific PMOS transistor and an NPMOS transistor of the level shifting unit 100 .
  • level shifting unit 100 will be described.
  • the level shifting unit 100 is composed of a circuit that raises OUT to '1' (VDDH) and lowers it to '0' (GND).
  • the level shifter 10 does not operate only with the level shifting unit 100 without the control signal generator 200 is as follows. As shown in FIG. 4 , when the control signal generating unit 200 is not present and the level shifting unit 100 does not have a fourth PMOS transistor, the output voltage OUT is '1' when the input voltage is turned to fall. Since the first PMOS transistor is turned off by ', the first mirror node (X node) cannot be pulled up, so the '0' state is maintained. Therefore, there is a problem in that the output voltage OUT cannot be lowered to '0' by fixing the output voltage OUT to '1' by the third PMOS transistor. Therefore, the fourth PMOS transistor is required to block the current due to the pull-up flowing in the third PMOS transistor.
  • the fourth PMOS transistor To block the current by P pull-up flowing from the third PMOS transistor using the fourth PMOS transistor, the fourth PMOS transistor must be turned off when the input signal (IN) is '0', so the control signal is '1'. It should be. In addition, when the input voltage rises, if the input voltage is '1', the fourth PMOS transistor must be turned on, so the control signal must be '0'. Therefore, the control signal is preferably a signal inverted to the input voltage (IN).
  • control signal generator 200 will be described.
  • the control signal generating unit 200 generates a control signal whose phase is inverted to IN for operating the fourth PMOS transistor for the operation of the level shifting unit 100 .
  • the control signal generating unit 200 connects the gates of the third NMOS transistor and the fifth PMOS transistor to the input voltage IN to generate an inverted signal.
  • the control signal generator 200 needs to generate a signal amplified from the input voltage IN, which is the first power supply voltage, in order to reliably turn on/off the fourth PMOS transistor and the second NMOS transistor.
  • the control signal generator 200 uses a fourth NMOS transistor and a fifth NMOS transistor to generate a control signal, and uses a logic error correction circuit (LECC) that operates only when the input voltage IN and the output voltage OUT are different. can be used
  • LECC logic error correction circuit
  • the control signal generator 200 uses LECC to generate a fifth PMOS transistor to make the control signal Y signal '1' close to the second power supply voltage VDDH when the input voltage IN is '0'. 6 Connect to the second power supply voltage (VDDH) through a PMOS transistor.
  • the control signal (Y signal) becomes '1', and the fourth PMOS transistor is pulled-up. current can be interrupted.
  • the output voltage OUT is pulled down to '0' by the second NMOS transistor receiving the control signal from the level shifter 10 as an input.
  • FIG. 6 is a diagram for explaining the advantages of a level shifter according to an embodiment of the present invention.
  • the level shifter 10 performs an operation of blocking static current.
  • the level shifting unit 100 of the level shifter 10 operates with the first PMOS transistor receiving feedback of the voltage of the output signal turned off, and the second PMOS transistor and blocking static current flowing through the first NMOS transistor.
  • the level shifter 10 performs a floating prevention operation.
  • the level shifting unit 100 of the level shifter 10 prevents a floating high state.
  • the level shifting unit 100 of the level shifter 10 since the level shifting unit 100 of the level shifter 10 has the first mirror node fixed at '0' by the first NMOS transistor after the voltage of the input signal is converted to 'high', A pull-up current is supplied from the second power supply voltage through the third PMOS transistor and the fourth PMOS transistor so that the output signal maintains the second power supply voltage state, and the output signal is floating high. can be prevented from becoming
  • the level shifter 10 performs full swing conversion according to the voltage of the input signal.
  • the level shifter 10 causes the voltage of the output signal to rise to the second power supply voltage when the voltage of the input signal is raised to a 'high' state, and the voltage of the input signal is raised to a 'high' state. After the rising transition is completed, the voltage of the output signal is operated to maintain the second power supply voltage.
  • the level shifter 10 cuts off the current by the pull-up through the fourth PMOS transistor and outputs the current through the second NMOS transistor. The voltage of the output signal is operated so that the voltage of the output signal is changed from the ground to the second power supply voltage by causing the voltage of the signal to be pulled down to 'low'.
  • FIGS. 7A and 7B are diagrams illustrating a size of a transistor stack and a FinFET in a level shifter according to an embodiment of the present invention.
  • FIG. 7A is a diagram showing a MOS transistor stack in the level shifter 10 according to an embodiment of the present invention
  • FIG. 7B is a diagram showing the FinFET size in the level shifter 10 according to an embodiment of the present invention. am.
  • the level The circuit of the shifter 10 can be designed.
  • the level shifter 10 according to the present embodiment can be sized using a 4nm to 7nm FinFET.
  • Each transistor included in the level shifter 10 may have a different number of Fins according to a purpose, as shown in FIG. 7B.
  • FIG. 8 is a diagram illustrating the operation of a level shifter according to an embodiment of the present invention.
  • FIG. 8 (a) shows an upward conversion operation of the level shifter 10
  • FIG. 10 (b) shows a downward conversion operation of the level shifter 10.
  • FIG. 9 is a diagram showing a result of comparing energy consumption between a level shifter according to an embodiment of the present invention and a conventional level shifter.
  • the level shifter 10 according to an embodiment of the present invention has energy efficiency improved by 48.4% compared to CPLS at 0.6 v and energy efficiency improved by 79.69% compared to CMLS. .
  • FIG. 10 is a diagram showing the results of Monte Carlo simulation according to an embodiment of the present invention.
  • FIG. 10 shows the result of processing 2000 Monte Carlo simulations. As shown in FIG. 10, it can be seen that when CPLS is 0.4 v, Monte Carlo simulation results and unstable level shifting results are obtained.
  • the level shifter 10 of the present invention performs stable level shifting at 0.4 v. Therefore, it can be confirmed that the structure of the level shifter 10 of the present invention has a wider input range than CPLS.
  • FIG. 11 is a diagram showing a result of comparing delay between a level shifter according to an embodiment of the present invention and a plurality of conventional level shifters.
  • the circuit with the fastest operating speed due to its low delay is the CMLS (5), but it is difficult to use the CMLS in practice due to the problem of static current. Therefore, it can be confirmed that the level shifter (8) of the present invention has a higher operating speed than the structures of other level shifters.

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  • Computer Hardware Design (AREA)
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Abstract

A level shifter for improving energy efficiency and input voltage range is disclosed. A level shifter, according to an embodiment of the present invention, for converting the voltage level of an output signal (OUT) according to the voltage level of an input signal (IN) and outputting same may comprise: a level shifting unit, which receives an IN connected to first power source voltage, and adjusts the voltage level to correspond to the voltage level of the IN, so that an OUT is output; and a control signal generation unit, which generates and transmits a control signal for controlling the operation of some transistors, included in the level shifting unit, in order to convert the voltage level of the OUT during voltage level conversion of the IN.

Description

에너지 효율 및 입력전압의 범위를 개선한 레벨 시프터Level shifter with improved energy efficiency and range of input voltage
본 발명은 에너지 효율 및 입력전압의 범위를 개선한 레벨 시프터에 관한 것이다. 본 발명의 연구는 과학기술정보통신부의 재원으로 한국연구재단의 지원을 받아 수행된 생애 첫 연구사업인 '기계학습 알고리즘의 저전력 고속 구현을 위한 컴퓨테이션 인 메모리 컴파일러 개발(No. 2020R1G1A1009777)'와 관련된다.The present invention relates to a level shifter with improved energy efficiency and input voltage range. The research of the present invention is related to the 'development of a computation in-memory compiler for low-power, high-speed implementation of machine learning algorithms (No. 2020R1G1A1009777)', the first research project of life carried out with the support of the National Research Foundation with funding from the Ministry of Science and ICT. do.
이 부분에 기술된 내용은 단순히 본 발명의 실시예에 대한 배경 정보를 제공할 뿐 종래기술을 구성하는 것은 아니다.The contents described in this section simply provide background information on the embodiments of the present invention and do not constitute prior art.
휴대폰, 컴퓨터, 자율주행 자동차 등 최첨단 시스템의 사용 증가로 집적회로의 사용이 늘어나고 있다. 레벨 시프터(Level Shifter)는 집적회로 내부 블록(block) 간의 연결에 사용되는 중요 부품 중 하나이며, 집적 회로 내부 블록들의 다양한 전압을 사용 가능하게 해주는 주요 부품이다.BACKGROUND OF THE INVENTION The increasing use of advanced systems such as mobile phones, computers, and autonomous vehicles is driving the use of integrated circuits. A level shifter is one of the important components used for connection between internal blocks of an integrated circuit, and is a major component enabling various voltages of internal blocks of an integrated circuit to be used.
일반적인 레벨 시프터는 스태틱 전류(Static current)가 흐르게 되는 문제, 풀 스윙(Full swing)이 불가능한 문제, 플로팅 하이(Floating High)인 상태가 되는 문제 등이 발생한다. 또한, 일반적인 레벨 시프터는 입력전압의 범위가 일정 수준 이하인 저전압에서는 정상적으로 동작하지 않는 문제점이 있다.A general level shifter has problems such as a static current flowing, a full swing impossible problem, a floating high state, and the like. In addition, a general level shifter has a problem in that it does not normally operate at a low voltage where the input voltage range is below a certain level.
본 발명은 기존 레벨 시프터들의 문제점을 해결하여 저전압인 입력 전압을 고전압으로 바꿀 때만 에너지를 사용하고, 낮은 전압의 입력에서도 고전압으로 전환이 가능한 에너지 효율 및 입력전압의 범위를 개선한 레벨 시프터를 제공하는 데 주된 목적이 있다.The present invention solves the problems of existing level shifters, uses energy only when changing a low voltage input voltage to a high voltage, and provides a level shifter with improved energy efficiency and range of input voltage capable of switching to a high voltage even at a low voltage input. has a main purpose.
본 발명의 일 측면에 의하면, 상기 목적을 달성하기 위한 레벨 시프터는, 입력신호(IN)의 전압 레벨에 따라 출력신호(OUT)의 전압 레벨을 변환하여 출력하는 레벨 시프터에 있어서, 제1 전원전압에 연결된 입력신호(IN)를 입력 받고, 상기 입력신호의 전압 레벨에 대응되도록 전압 레벨을 조정하여 상기 출력신호(OUT)를 출력하는 레벨 시프팅부; 및 상기 입력신호(IN)의 전압 레벨 변환 시 상기 출력신호(OUT)의 전압 레벨 변환을 위하여 상기 레벨 시프팅부에 포함된 일부 트랜지스터의 동작을 제어하는 제어신호를 생성하여 전달하는 제어신호 생성부를 포함할 수 있다. According to one aspect of the present invention, the level shifter for achieving the above object is a level shifter for converting and outputting the voltage level of the output signal (OUT) according to the voltage level of the input signal (IN), the first power supply voltage a level shifting unit receiving an input signal (IN) connected to and outputting the output signal (OUT) by adjusting a voltage level to correspond to the voltage level of the input signal; and a control signal generation unit generating and transmitting a control signal for controlling the operation of some transistors included in the level shifting unit in order to convert the voltage level of the output signal OUT when the voltage level of the input signal IN is converted. can do.
이상에서 설명한 바와 같이, 본 발명의 레벨 시프터는 기존의 다른 여러 레벨 시프터에서 발생하는 스태틱 전류(Static current), 풀 스윙(Full swing), 플로팅(Floating) 등의 문제를 해결할 수 있는 효과가 있다. As described above, the level shifter of the present invention has an effect of solving problems such as static current, full swing, and floating occurring in other existing level shifters.
또한, 본 발명의 레벨 시프터는 에너지 효율적이며 저전압에서도 레벨 시프팅(Level Shifting)이 가능한 효과가 있다. 이에, 본 발명의 레벨 시프터 구조를 저전압을 사용하는 블록(block)에 사용 가능하고, 이는 집적회로의 에너지 효율성을 증가 시켜줄 수 있으며 동작 속도를 향상 시킬 수 있는 효과가 있다.In addition, the level shifter of the present invention is energy efficient and has an effect of enabling level shifting even at low voltage. Therefore, the level shifter structure of the present invention can be used in a block using a low voltage, which can increase the energy efficiency of the integrated circuit and improve the operating speed.
도 1은 본 발명의 실시예에 따른 레벨 시프터를 나타낸 회로도이다.1 is a circuit diagram showing a level shifter according to an embodiment of the present invention.
도 2는 본 발명의 실시예에 따른 레벨 시프터의 상승 전환 동작을 설명하기 위한 도면이다. 2 is a diagram for explaining an up conversion operation of a level shifter according to an embodiment of the present invention.
도 3은 본 발명의 실시예에 따른 레벨 시프터의 하강 전환 동작을 설명하기 위한 도면이다. 3 is a diagram for explaining a descending transition operation of a level shifter according to an embodiment of the present invention.
도 4는 본 발명의 실시예에 따른 제어신호 생성부의 동작을 설명하기 위한 제4 PMOS 트랜지스터를 제거한 레벨 시프터를 나타낸 도면이다.4 is a diagram showing a level shifter from which a fourth PMOS transistor is removed to explain the operation of a control signal generator according to an embodiment of the present invention.
도 5는 본 발명의 실시예에 따른 제어신호에 의한 레벨 시프터의 동작을 설명하기 위한 도면이다. 5 is a diagram for explaining an operation of a level shifter according to a control signal according to an embodiment of the present invention.
도 6은 본 발명의 실시예에 따른 레벨 시프터의 장점을 설명하기 위한 도면이다. 6 is a diagram for explaining the advantages of a level shifter according to an embodiment of the present invention.
도 7a 및 도 7b는 본 발명의 실시예에 따른 레벨 시프터에서의 트랜지스터 스택 및 FinFET 사이즈를 나타낸 도면이다. 7A and 7B are diagrams illustrating a size of a transistor stack and a FinFET in a level shifter according to an embodiment of the present invention.
도 8은 본 발명의 실시예에 따른 레벨 시프터의 동작을 나타낸 도면이다. 8 is a diagram illustrating the operation of a level shifter according to an embodiment of the present invention.
도 9는 본 발명의 실시예에 따른 레벨 시프터와 종래의 레벨 시프터 간의 에너지 소모를 비교한 결과를 나타낸 도면이다. 9 is a diagram showing a result of comparing energy consumption between a level shifter according to an embodiment of the present invention and a conventional level shifter.
도 10은 본 발명의 실시예에 따른 몬테 카를로 시뮬레이션의 결과를 나타낸 도면이다. 10 is a diagram showing the results of Monte Carlo simulation according to an embodiment of the present invention.
도 11은 본 발명의 실시예에 따른 레벨 시프터와 종래의 다수의 레벨 시프터와의 지연 정도를 비교 결과를 나타낸 도면이다.11 is a diagram showing a result of comparing delay between a level shifter according to an embodiment of the present invention and a plurality of conventional level shifters.
이하, 본 발명의 바람직한 실시예를 첨부된 도면들을 참조하여 상세히 설명한다. 본 발명을 설명함에 있어, 관련된 공지 구성 또는 기능에 대한 구체적인 설명이 본 발명의 요지를 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명은 생략한다. 또한, 이하에서 본 발명의 바람직한 실시예를 설명할 것이나, 본 발명의 기술적 사상은 이에 한정하거나 제한되지 않고 당업자에 의해 변형되어 다양하게 실시될 수 있음은 물론이다. 이하에서는 도면들을 참조하여 본 발명에서 제안하는 에너지 효율 및 입력전압의 범위를 개선한 레벨 시프터에 대해 자세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description will be omitted. In addition, although preferred embodiments of the present invention will be described below, the technical idea of the present invention is not limited or limited thereto and can be modified and implemented in various ways by those skilled in the art. Hereinafter, a level shifter with improved energy efficiency and input voltage range proposed by the present invention will be described in detail with reference to drawings.
본 발명에 따른 레벨 시프터(Level Shifter)는 CPU(Central Processing Unit), SRAM(Static Random Access Memory), DRAM(Dynamic Random Access Memory) 등의 제품에 적용 가능하다. 또한, 본 발명에 따른 레벨 시프터는 휴대폰, 무선 이어폰, IoT 가전제품, 컴퓨터, 자율주행 자동차 등의 제품에 일부 응용될 수 있다.The level shifter according to the present invention can be applied to products such as a central processing unit (CPU), static random access memory (SRAM), and dynamic random access memory (DRAM). In addition, the level shifter according to the present invention can be partially applied to products such as mobile phones, wireless earphones, IoT home appliances, computers, and self-driving cars.
도 1은 본 발명의 실시예에 따른 레벨 시프터를 나타낸 회로도이다.1 is a circuit diagram showing a level shifter according to an embodiment of the present invention.
본 발명의 실시예에 따른 레벨 시프터(10)는 CMLS(Current Mirror Based Level Shifter)에서 스태틱 전류(Static current)를 차단하여 레벨 시프팅(Level Shifting) 동작 시에만 에너지를 소모하며 저전압에서도 레벨 시프팅(Level Shifting) 가능한 구조에 관한 회로이다. The level shifter 10 according to an embodiment of the present invention blocks static current from a current mirror based level shifter (CMLS), consumes energy only during level shifting, and level shifting even at low voltage (Level Shifting) This is a circuit about a possible structure.
본 발명에 따른 레벨 시프터(10)는 스태틱 전류(Static current)를 차단하며 다양한 레벨 시프터(Level Shifter) 문제를 해결하기 위해, 레벨 시프팅부(100) 및 제어신호 생성부(200)를 포함한다. 레벨 시프팅부(100)는 레벨 시프팅을 수행하는 회로이고, 제어신호 생성부(200)는 레벨 시프팅부(100)로 전달하는 제어신호(Y 신호)를 생성하는 회로이다. The level shifter 10 according to the present invention blocks static current and includes a level shifter 100 and a control signal generator 200 to solve various level shifter problems. The level shifting unit 100 is a circuit that performs level shifting, and the control signal generating unit 200 is a circuit that generates a control signal (Y signal) transmitted to the level shifting unit 100 .
본 실시예에 따른 레벨 시프팅부(100)는 제1 전원전압(VDDL)에 연결된 입력신호(IN)를 입력 받고, 입력신호의 전압 레벨에 대응되도록 출력신호(OUT)의 전압 레벨을 조정하여 전압 레벨이 조정된 출력신호(OUT)를 출력한다. The level shifting unit 100 according to the present embodiment receives the input signal IN connected to the first power supply voltage VDDL, adjusts the voltage level of the output signal OUT to correspond to the voltage level of the input signal, and It outputs the level-adjusted output signal (OUT).
레벨 시프팅부(100)는 적어도 2 개의 NMOS 트랜지스터 및 적어도 4 개의 PMOS 트랜지스터를 포함한다. 구체적으로, 레벨 시프팅부(100)는 제1 NMOS 트랜지스터(110) 및 제2 NMOS 트랜지스터(120)를 포함하는 적어도 2 개의 NMOS 트랜지스터와 제1 PMOS 트랜지스터(130), 제2 PMOS 트랜지스터(140), 제3 PMOS 트랜지스터(150) 및 제4 PMOS 트랜지스터(160)를 포함하는 적어도 4 개의 PMOS 트랜지스터로 구성될 수 있다. The level shifting unit 100 includes at least two NMOS transistors and at least four PMOS transistors. Specifically, the level shifting unit 100 includes at least two NMOS transistors including the first NMOS transistor 110 and the second NMOS transistor 120, the first PMOS transistor 130, the second PMOS transistor 140, It may be composed of at least four PMOS transistors including the third PMOS transistor 150 and the fourth PMOS transistor 160 .
레벨 시프팅부(100)는 제2 전원전압(VDDH)과 제1 연결 라인 및 제2 연결 라인이 병렬로 연결된다. 제1 연결 라인에는 제2 PMOS 트랜지스터(140), 제1 PMOS 트랜지스터(130) 및 제1 NMOS 트랜지스터(110)가 직렬 연결된다. 또한, 제2 연결 라인에는 제3 PMOS 트랜지스터(150), 제4 PMOS 트랜지스터(160) 및 제2 NMOS 트랜지스터(120)가 직렬 연결된다. In the level shifting unit 100, the second power supply voltage VDDH and the first connection line and the second connection line are connected in parallel. The second PMOS transistor 140 , the first PMOS transistor 130 , and the first NMOS transistor 110 are connected in series to the first connection line. Also, the third PMOS transistor 150, the fourth PMOS transistor 160, and the second NMOS transistor 120 are connected in series to the second connection line.
레벨 시프팅부(100)에서, 제1 NMOS 트랜지스터(110)의 게이트는 상기 입력신호를 입력받는 입력노드와 연결되고, 제4 PMOS 트랜지스터(160) 및 제2 NMOS 트랜지스터(120)의 드레인 사이의 접점은 출력신호를 출력하는 출력노드와 연결된다. 또한, 제1 PMOS 트랜지스터(130)의 게이트는 출력신호를 피드백 받기 위하여 출력노드와 연결된다. In the level shifting unit 100, the gate of the first NMOS transistor 110 is connected to the input node receiving the input signal, and the contact between the fourth PMOS transistor 160 and the drain of the second NMOS transistor 120. is connected to an output node that outputs an output signal. In addition, the gate of the first PMOS transistor 130 is connected to the output node to receive feedback of the output signal.
레벨 시프팅부(100)에서, 제2 PMOS 트랜지스터(140) 및 제3 PMOS 트랜지스터(150)는 커런트 미러(Current Mirror) 구조를 가지며, 제2 PMOS 트랜지스터(140) 및 제3 PMOS 트랜지스터(150)의 게이트 사이의 제1 미러 노드(X 노드)는 제1 PMOS 트랜지스터(130) 및 제1 NMOS 트랜지스터(110) 사이의 노드와 연결된다. In the level shifting unit 100, the second PMOS transistor 140 and the third PMOS transistor 150 have a current mirror structure, and the second PMOS transistor 140 and the third PMOS transistor 150 The first mirror node (X node) between the gates is connected to a node between the first PMOS transistor 130 and the first NMOS transistor 110 .
본 실시예에 따른 제어신호 생성부(200)는 입력신호(IN)의 전압 레벨 변환 시 출력신호(OUT)의 전압 레벨 변환을 위하여 레벨 시프팅부(100)에 포함된 일부 트랜지스터의 동작을 제어하는 제어신호를 생성하여 전달한다. The control signal generation unit 200 according to the present embodiment controls the operation of some transistors included in the level shifting unit 100 to convert the voltage level of the output signal OUT when the voltage level of the input signal IN is converted. Generates and transmits control signals.
제어신호 생성부(200)는 레벨 시프팅부(100)의 제4 PMOS 트랜지스터(160) 및 제2 NMOS 트랜지스터(120)의 게이트와 연결되고, 제4 PMOS 트랜지스터(160) 및 제2 NMOS 트랜지스터(120)의 동작 제어를 위한 제어신호를 전달한다. 여기서, 제어신호는 입력신호가 인버팅된 인버팅 신호인 것이 바람직하다. The control signal generator 200 is connected to the gates of the fourth PMOS transistor 160 and the second NMOS transistor 120 of the level shifter 100, and the fourth PMOS transistor 160 and the second NMOS transistor 120 ) transmits a control signal for operation control. Here, the control signal is preferably an inverting signal obtained by inverting an input signal.
제어신호 생성부(200)는 적어도 3 개의 NMOS 트랜지스터 및 적어도 3 개의 PMOS 트랜지스터를 포함한다. 구체적으로, 제어신호 생성부(200)는 제3 NMOS 트랜지스터(210), 제4 NMOS 트랜지스터(220) 및 제5 NMOS 트랜지스터(230)를 포함하는 적어도 3 개의 NMOS 트랜지스터와 제5 PMOS 트랜지스터(240), 제6 PMOS 트랜지스터(250) 및 제7 PMOS 트랜지스터(260)를 포함하는 적어도 3 개의 PMOS 트랜지스터로 구성될 수 있다.The control signal generator 200 includes at least three NMOS transistors and at least three PMOS transistors. Specifically, the control signal generator 200 includes at least three NMOS transistors including the third NMOS transistor 210, the fourth NMOS transistor 220, and the fifth NMOS transistor 230 and the fifth PMOS transistor 240. , at least three PMOS transistors including the sixth PMOS transistor 250 and the seventh PMOS transistor 260 .
제어신호 생성부(200)는 제2 전원전압과 제3 연결 라인 및 제4 연결 라인이 병렬로 연결된다. 제3 연결 라인에는 제6 PMOS 트랜지스터(250), 제5 PMOS 트랜지스터(240) 및 제3 NMOS 트랜지스터(210)가 직렬 연결된다. 또한, 제4 연결 라인에는 제7 PMOS 트랜지스터(260), 제4 NMOS 트랜지스터(220) 및 제5 NMOS 트랜지스터(230)가 직렬 연결된다.In the control signal generator 200, the second power supply voltage, the third connection line, and the fourth connection line are connected in parallel. The sixth PMOS transistor 250 , the fifth PMOS transistor 240 , and the third NMOS transistor 210 are connected in series to the third connection line. In addition, the seventh PMOS transistor 260, the fourth NMOS transistor 220, and the fifth NMOS transistor 230 are connected in series to the fourth connection line.
제어신호 생성부(200)에서, 제5 PMOS 트랜지스터(240) 및 제3 NMOS 트랜지스터(210)의 게이트는 입력신호를 입력받는 입력노드와 연결되고, 제5 PMOS 트랜지스터(240) 및 제3 NMOS 트랜지스터(210)의 드레인 사이의 접점은 제어신호를 출력하는 제어노드와 연결되며, 제어노드는 레벨 시프팅부(100)로 제어신호를 인가하기 위하여 제4 PMOS 트랜지스터(160) 및 제2 NMOS 트랜지스터(120)의 게이트와 연결된다. 또한, 제4 NMOS 트랜지스터(220)의 게이트는 입력신호에 대한 인버팅 신호를 입력받는 인버팅 입력 노드와 연결되며, 제5 NMOS 트랜지스터(230)의 게이트는 출력신호를 피드백 받기 위하여 출력노드와 연결된다. In the control signal generator 200, the gates of the fifth PMOS transistor 240 and the third NMOS transistor 210 are connected to an input node receiving an input signal, and the fifth PMOS transistor 240 and the third NMOS transistor The contact between the drains of 210 is connected to a control node that outputs a control signal, and the control node is connected to the fourth PMOS transistor 160 and the second NMOS transistor 120 to apply a control signal to the level shifting unit 100. ) is connected to the gate of In addition, the gate of the fourth NMOS transistor 220 is connected to the inverting input node receiving the inverting signal for the input signal, and the gate of the fifth NMOS transistor 230 is connected to the output node to receive the output signal as feedback. do.
레벨 시프팅부(100)에서, 제6 PMOS 트랜지스터(250) 및 제7 PMOS 트랜지스터(260)는 커런트 미러(Current Mirror) 구조를 가지며, 제6 PMOS 트랜지스터(250) 및 제7 PMOS 트랜지스터(260)의 게이트 사이의 제2 미러 노드는 제7 PMOS 트랜지스터(260) 및 제4 NMOS 트랜지스터(220) 사이의 노드와 연결된다.In the level shifting unit 100, the sixth PMOS transistor 250 and the seventh PMOS transistor 260 have a current mirror structure, and the sixth PMOS transistor 250 and the seventh PMOS transistor 260 The second mirror node between the gates is connected to a node between the seventh PMOS transistor 260 and the fourth NMOS transistor 220 .
이하, 본 실시예에 따른 레벨 시프터(10)의 동작에 대해 설명하도록 한다. Hereinafter, the operation of the level shifter 10 according to this embodiment will be described.
레벨 시프터(10)는 입력신호의 전압에 따라 풀 스윙(Full swing) 전환을 수행한다. The level shifter 10 performs full swing conversion according to the voltage of the input signal.
레벨 시프터(10)는 입력신호의 전압이 '하이'인 상태로 상승 전환될 때, 출력신호의 전압이 제2 전원전압까지 상승되도록 하고, 입력신호의 전압이 '하이'인 상태로 상승 전환이 완료된 후 출력신호의 전압이 제2 전원전압을 유지하도록 한다. The level shifter 10 causes the voltage of the output signal to rise to the second power supply voltage when the voltage of the input signal is increased to a 'high' state, and the voltage of the input signal is increased to a 'high' state. After completion, the voltage of the output signal maintains the second power supply voltage.
또한, 레벨 시프터(10)는 입력신호의 전압이 '로우'인 상태로 하강 전환될 때, 제4 PMOS 트랜지스터(160)를 통해 풀업(Pull-up)에 의한 전류를 차단하고, 제2 NMOS 트랜지스터(120)로 인해 출력신호의 전압이 '로우'로 풀다운(Pull-down)되도록 하여 출력신호의 전압은 그라운드(Ground)로부터 제2 전원전압까지 변하게 된다. In addition, the level shifter 10 blocks the current due to the pull-up through the fourth PMOS transistor 160 when the voltage of the input signal is lowered to a 'low' state, and the second NMOS transistor 120 causes the voltage of the output signal to be pulled down to 'low' so that the voltage of the output signal changes from the ground to the second power supply voltage.
이하, 입력신호의 전압 레벨이 상승 변환하는 경우 레벨 시프터(10)의 동작을 설명하도록 한다. Hereinafter, the operation of the level shifter 10 when the voltage level of the input signal is up-converted will be described.
레벨 시프터(10)는 입력신호의 전압이 '로우'에서 '하이'로 상승 변환한 경우, (i) 입력신호의 전압에 의해 제1 NMOS 트랜지스터(110)가 켜져 제1 미러 노드가 '로우'로 하강하고, 제2 PMOS 트랜지스터(140) 및 제3 PMOS 트랜지스터(150)가 켜지며, 동시에, (ii) 입력신호의 전압에 의해 제3 NMOS 트랜지스터(210)가 켜져 제어신호의 전압이 '로우'로 하강하고, 제4 PMOS 트랜지스터(160)가 켜진다. 레벨 시프터(10)는 (iii) 제3 PMOS 트랜지스터(150) 및 제4 PMOS 트랜지스터(160)를 통해 전압이 '하이'로 상승된 출력신호를 출력노드로 출력한다. When the level shifter 10 up-converts the voltage of the input signal from 'low' to 'high', (i) the first NMOS transistor 110 is turned on by the voltage of the input signal so that the first mirror node becomes 'low'. , the second PMOS transistor 140 and the third PMOS transistor 150 are turned on, and at the same time, (ii) the third NMOS transistor 210 is turned on by the voltage of the input signal and the voltage of the control signal is 'low'. ', and the fourth PMOS transistor 160 is turned on. The level shifter 10 outputs (iii) an output signal whose voltage is raised to 'high' through the third PMOS transistor 150 and the fourth PMOS transistor 160 to an output node.
이하, 입력신호의 전압 레벨이 하강 변환하는 경우 레벨 시프터(10)의 동작을 설명하도록 한다. Hereinafter, the operation of the level shifter 10 when the voltage level of the input signal is down-converted will be described.
레벨 시프터(10)는 입력신호의 전압이 '하이'에서 '로우'로 하강 변환한 경우, (i) 입력신호의 전압에 의해 제5 PMOS 트랜지스터(240)가 켜지며, 동시에, (ii) 인버팅 신호의 전압에 의해 제4 NMOS 트랜지스터(220)가 켜져 제2 미러 노드가 '로우'로 하강하고, 제6 PMOS 트랜지스터(250) 및 제7 PMOS 트랜지스터(260)가 켜진다. 레벨 시프터(10)는 (iii) 제6 PMOS 트랜지스터(250) 및 제5 PMOS 트랜지스터(240)를 통해 전압이 '하이'로 상승된 제어신호를 출력하며, (iv) 입력신호의 전압에 의해 제2 NMOS 트랜지스터(120)가 켜져 전압이 '로우'로 하강된 출력신호를 출력노드로 출력한다. When the level shifter 10 converts the voltage of the input signal down from 'high' to 'low', (i) the fifth PMOS transistor 240 is turned on by the voltage of the input signal, and (ii) The fourth NMOS transistor 220 is turned on by the voltage of the butting signal, the second mirror node drops to 'low', and the sixth PMOS transistor 250 and the seventh PMOS transistor 260 are turned on. The level shifter 10 outputs a control signal whose voltage is raised to 'high' through (iii) the sixth PMOS transistor 250 and the fifth PMOS transistor 240, and (iv) controlled by the voltage of the input signal. 2 The NMOS transistor 120 is turned on and outputs an output signal whose voltage drops to 'low' to the output node.
본 발명의 레벨 시프터(10)는 기존의 다른 여러 레벨 시프터에서 발생하는 스태틱 전류(Static current), 풀 스윙(Full swing), 플로팅(Floating) 등의 문제를 해결할 수 있다. The level shifter 10 of the present invention can solve problems such as static current, full swing, and floating occurring in other existing level shifters.
또한, 본 발명의 레벨 시프터(10)는 에너지 효율적이며 저전압에서도 레벨 시프팅(Level Shifting)이 가능하다. 이에, 본 발명의 레벨 시프터(10)의 구조를 저전압을 사용하는 블록(block)에 적용 가능하고, 이는 집적회로의 에너지 효율성을 증가 시켜줄 수 있으며, 동작 속도를 향상 시킬 수 있다. In addition, the level shifter 10 of the present invention is energy efficient and can perform level shifting even at low voltage. Therefore, the structure of the level shifter 10 of the present invention can be applied to a block using a low voltage, which can increase the energy efficiency of the integrated circuit and improve the operating speed.
도 2는 본 발명의 실시예에 따른 레벨 시프터의 상승 전환 동작을 설명하기 위한 도면이다. 2 is a diagram for explaining an up conversion operation of a level shifter according to an embodiment of the present invention.
도 2에서는 입력신호의 전압이 '0'에서 '1'로 상승 전환되는 경우 레벨 시프터(10)의 동작을 설명하도록 한다. In FIG. 2, the operation of the level shifter 10 when the voltage of the input signal rises from '0' to '1' will be described.
레벨 시프터(10)에서, 입력신호의 전압이 '로우'에서 '하이'로 상승 변환한 경우(①), 입력신호의 전압에 의해 제1 NMOS 트랜지스터(110) 및 제3 NMOS 트랜지스터(210)가 켜진다. In the level shifter 10, when the voltage of the input signal is up-converted from 'low' to 'high' (①), the first NMOS transistor 110 and the third NMOS transistor 210 are moved by the voltage of the input signal turns on
레벨 시프터(10)에서, 입력신호의 전압에 의해 제1 NMOS 트랜지스터(110)가 켜져 제1 미러 노드가 '로우'로 하강하고(②), 제2 PMOS 트랜지스터(140) 및 제3 PMOS 트랜지스터(150)가 켜지며, 동시에 입력신호의 전압에 의해 제3 NMOS 트랜지스터(210)가 켜져 제어신호의 전압이 '로우'로 하강하고(②), 제4 PMOS 트랜지스터(160)가 켜진다. In the level shifter 10, the first NMOS transistor 110 is turned on by the voltage of the input signal, and the first mirror node drops to 'low' (②), and the second PMOS transistor 140 and the third PMOS transistor ( 150) is turned on, and at the same time, the third NMOS transistor 210 is turned on by the voltage of the input signal, the voltage of the control signal drops to 'low' (②), and the fourth PMOS transistor 160 is turned on.
레벨 시프터(10)에서, 레벨 시프터(10)는 제3 PMOS 트랜지스터(150) 및 제4 PMOS 트랜지스터(160)를 통해 전압이 '하이'로 상승된 출력신호를 출력노드로 출력한다(③). 다시 말해, 제3 PMOS 트랜지스터(150) 및 제4 PMOS 트랜지스터(160)를 통해 제2 전원전압(VDDH)에서 공급되는 전류가 출력신호(OUT)를 '1'(VDDH)로 상승시킨다. In the level shifter 10, the level shifter 10 outputs an output signal whose voltage is raised to 'high' through the third PMOS transistor 150 and the fourth PMOS transistor 160 to an output node (③). In other words, the current supplied from the second power voltage VDDH through the third PMOS transistor 150 and the fourth PMOS transistor 160 raises the output signal OUT to '1' (VDDH).
도 3은 본 발명의 실시예에 따른 레벨 시프터의 하강 전환 동작을 설명하기 위한 도면이다. 3 is a diagram for explaining a descending transition operation of a level shifter according to an embodiment of the present invention.
도 3에서는 입력신호의 전압이 '1'에서 '0'로 상승 전환되는 경우 레벨 시프터(10)의 동작을 설명하도록 한다. In FIG. 3, the operation of the level shifter 10 when the voltage of the input signal rises from '1' to '0' will be described.
레벨 시프터(10)에서, 입력신호의 전압이 '하이'에서 '로우'로 하강 변환한 경우(①), 입력신호의 전압에 의해 제5 PMOS 트랜지스터(240)가 켜지고, 인버팅 신호의 전압에 의해 제4 NMOS 트랜지스터(220)가 켜진다. In the level shifter 10, when the voltage of the input signal is down-converted from 'high' to 'low' (①), the fifth PMOS transistor 240 is turned on by the voltage of the input signal, and the voltage of the inverting signal The fourth NMOS transistor 220 is turned on by
레벨 시프터(10)에서, 인버팅 신호의 전압에 의해 제4 NMOS 트랜지스터(220)가 켜져 제2 미러 노드가 '로우'로 하강하고, 제6 PMOS 트랜지스터(250) 및 제7 PMOS 트랜지스터(260)가 켜진다(②). In the level shifter 10, the fourth NMOS transistor 220 is turned on by the voltage of the inverting signal so that the second mirror node goes low, and the sixth PMOS transistor 250 and the seventh PMOS transistor 260 turns on (②).
레벨 시프터(10)에서, 제6 PMOS 트랜지스터(250) 및 제5 PMOS 트랜지스터(240)를 통해 전압이 '하이'로 상승된 제어신호를 출력한다(③).The level shifter 10 outputs a control signal whose voltage is raised to 'high' through the sixth PMOS transistor 250 and the fifth PMOS transistor 240 (③).
레벨 시프터(10)에서, 제어신호의 전압에 의해 제2 NMOS 트랜지스터(120)가 켜져 전압이 '로우'로 하강된 출력신호를 출력노드로 출력한다(④).In the level shifter 10, the second NMOS transistor 120 is turned on by the voltage of the control signal and outputs an output signal whose voltage has dropped to 'low' to an output node (④).
도 4는 본 발명의 실시예에 따른 제어신호 생성부의 동작을 설명하기 위한 제4 PMOS 트랜지스터를 제거한 레벨 시프터를 나타낸 도면이고, 도 5는 본 발명의 실시예에 따른 제어신호에 의한 레벨 시프터의 동작을 설명하기 위한 도면이다. 4 is a diagram showing a level shifter from which a fourth PMOS transistor is removed for explaining the operation of a control signal generator according to an embodiment of the present invention, and FIG. 5 is an operation of the level shifter according to a control signal according to an embodiment of the present invention. It is a drawing for explaining.
레벨 시프팅부(100)는 적어도 4 개의 PMOS 트랜지스터 및 적어도 2 개의 NPMOS 트랜지스터로 구성된다. 레벨 시프팅부(100)는 입력전압을 기반으로 출력전압(OUT)을 상승 또는 하강 전환한다. The level shifting unit 100 includes at least 4 PMOS transistors and at least 2 NPMOS transistors. The level shifting unit 100 converts the output voltage OUT up or down based on the input voltage.
제어신호 생성부(200)는 적어도 3 개의 PMOS 트랜지스터 및 적어도 3 개의 NMOS 트랜지스터로 구성된다. 제어신호 생성부(200)는 입력 전압에 반전된 제어신호를 생성하고, 레벨 시프팅부(100)의 특정 PMOS 트랜지스터 및 NPMOS 트랜지스터 중 적어도 하나의 트랜지스터로 제어신호를 전달한다. The control signal generator 200 includes at least three PMOS transistors and at least three NMOS transistors. The control signal generating unit 200 generates a control signal inverted from an input voltage and transfers the control signal to at least one of a specific PMOS transistor and an NPMOS transistor of the level shifting unit 100 .
이하, 레벨 시프팅부(100)에 대해 설명하도록 한다.Hereinafter, the level shifting unit 100 will be described.
레벨 시프팅부(100)는 OUT을 '1'(VDDH)로 올리고 '0'(GND)으로 내려주는 회로로 구성된다. The level shifting unit 100 is composed of a circuit that raises OUT to '1' (VDDH) and lowers it to '0' (GND).
본 실시예에 따른 레벨 시프터(10)가 제어신호 생성부(200) 없이 레벨 시프팅부(100)만으로 동작하지 않는 이유는 다음과 같다. 도 4에 도시된 같이, 제어신호 생성부(200)가 없고, 레벨 시프팅부(100)에 제4 PMOS 트랜지스터가 없을 경우, 입력전압이 하강(Falling) 전환할 때 출력전압(OUT)가 '1'에 의해 제1 PMOS 트랜지스터가 꺼져 있어 제1 미러 노드(X 노드)를 풀업(Pull-up)할 수 없어 '0'상태를 유지한다. 따라서, 제3 PMOS 트랜지스터에 의해 출력전압(OUT)를 '1'로 고정시켜 출력전압(OUT)을 '0'으로 내리지 못하는 문제가 있다. 따라서, 제3 PMOS 트랜지스터에서 흐르는 풀업(Pull-up)에 의한 전류를 차단하기 위해 제4 PMOS 트랜지스터가 필요하다. The reason why the level shifter 10 according to the present embodiment does not operate only with the level shifting unit 100 without the control signal generator 200 is as follows. As shown in FIG. 4 , when the control signal generating unit 200 is not present and the level shifting unit 100 does not have a fourth PMOS transistor, the output voltage OUT is '1' when the input voltage is turned to fall. Since the first PMOS transistor is turned off by ', the first mirror node (X node) cannot be pulled up, so the '0' state is maintained. Therefore, there is a problem in that the output voltage OUT cannot be lowered to '0' by fixing the output voltage OUT to '1' by the third PMOS transistor. Therefore, the fourth PMOS transistor is required to block the current due to the pull-up flowing in the third PMOS transistor.
제4 PMOS 트랜지스터를 사용해 제3 PMOS 트랜지스터에서 흐르는 P풀업(Pull-up)에 의한 전류를 차단하려면 입력신호(IN)가 '0'일 때 제4 PMOS 트랜지스터가 꺼져야 하므로 제어신호는 '1'이 되어야 한다. 또한, 입력전압이 상승(rising) 전환할 때, 입력전압이 '1'이면 제4 PMOS 트랜지스터를 켜야하므로 제어신호는 '0'이어야 한다. 따라서, 제어신호는 입력전압(IN)에 인버팅된 신호인 것이 바람직하다. To block the current by P pull-up flowing from the third PMOS transistor using the fourth PMOS transistor, the fourth PMOS transistor must be turned off when the input signal (IN) is '0', so the control signal is '1'. It should be. In addition, when the input voltage rises, if the input voltage is '1', the fourth PMOS transistor must be turned on, so the control signal must be '0'. Therefore, the control signal is preferably a signal inverted to the input voltage (IN).
이하, 제어신호 생성부(200)에 대해 설명하도록 한다.Hereinafter, the control signal generator 200 will be described.
제어신호 생성부(200)는 레벨 시프팅부(100)의 동작을 위하여 제4 PMOS 트랜지스터를 동작하기 위한 위상이 IN에 반전된 제어신호를 생성한다. The control signal generating unit 200 generates a control signal whose phase is inverted to IN for operating the fourth PMOS transistor for the operation of the level shifting unit 100 .
도 5를 참고하면, 제어신호 생성부(200)는 반전된 신호를 생성하기 위해 제3 NMOS 트랜지스터와 제5 PMOS 트랜지스터의 게이트가 입력전압(IN)과 연결되도록 한다. 또한, 제어신호 생성부(200)는 제4 PMOS 트랜지스터 및 제2 NMOS 트랜지스터를 확실하게 키고 끄기 위해서는 제1 전원전압인 입력전압(IN)보다 증폭된 신호를 생성해야 한다. Referring to FIG. 5 , the control signal generating unit 200 connects the gates of the third NMOS transistor and the fifth PMOS transistor to the input voltage IN to generate an inverted signal. In addition, the control signal generator 200 needs to generate a signal amplified from the input voltage IN, which is the first power supply voltage, in order to reliably turn on/off the fourth PMOS transistor and the second NMOS transistor.
제어신호 생성부(200)는 제어신호를 생성하기 위해, 제4 NMOS 트랜지스터와 제5 NMOS 트랜지스터를 사용해 입력전압(IN)과 출력전압(OUT)이 다를 때만 동작하는 LECC(Logic Error correction circuit)을 사용할 수 있다. 제어신호 생성부(200)는 LECC를 사용해 입력전압(IN)이 '0'일 때 제어신호(Y signal)를 제2 전원전압(VDDH)에 가까운 '1'로 만들기 위해 제5 PMOS 트랜지스터를 제6 PMOS 트랜지스터를 통해 제2 전원전압(VDDH)와 연결한다. The control signal generator 200 uses a fourth NMOS transistor and a fifth NMOS transistor to generate a control signal, and uses a logic error correction circuit (LECC) that operates only when the input voltage IN and the output voltage OUT are different. can be used The control signal generator 200 uses LECC to generate a fifth PMOS transistor to make the control signal Y signal '1' close to the second power supply voltage VDDH when the input voltage IN is '0'. 6 Connect to the second power supply voltage (VDDH) through a PMOS transistor.
도 5에 도시된 바와 같이, 레벨 시프터(10)는 입력전압(IN)이 '0'일 때 제어신호(Y signal)는 '1'이 되고, 제4 PMOS 트랜지스터가 풀업(Pull-up)에 의한 전류를 차단할 수 있다. 또한, 레벨 시프터(10)에서 제어신호를 입력으로 하는 제2 NMOS 트랜지스터에 의해 출력전압(OUT)은 '0'으로 풀다운(Pull-down) 된다.As shown in FIG. 5, in the level shifter 10, when the input voltage (IN) is '0', the control signal (Y signal) becomes '1', and the fourth PMOS transistor is pulled-up. current can be interrupted. In addition, the output voltage OUT is pulled down to '0' by the second NMOS transistor receiving the control signal from the level shifter 10 as an input.
도 6은 본 발명의 실시예에 따른 레벨 시프터의 장점을 설명하기 위한 도면이다. 6 is a diagram for explaining the advantages of a level shifter according to an embodiment of the present invention.
본 실시예에 따른 레벨 시프터(10)는 스태틱 전류(Static current)를 차단하는 동작을 수행한다. The level shifter 10 according to the present embodiment performs an operation of blocking static current.
구체적으로, 레벨 시프터(10)의 레벨 시프팅부(100)는 입력신호의 전압이 '하이'인 상태인 경우, 출력신호의 전압을 피드백 받는 제1 PMOS 트랜지스터가 꺼짐 상태로 동작하여 제2 PMOS 트랜지스터 및 제1 NMOS 트랜지스터를 통해 흐르게 되는 스태틱 전류(static current)를 차단할 수 있다. Specifically, when the voltage of the input signal is 'high', the level shifting unit 100 of the level shifter 10 operates with the first PMOS transistor receiving feedback of the voltage of the output signal turned off, and the second PMOS transistor and blocking static current flowing through the first NMOS transistor.
또한, 본 실시예에 따른 레벨 시프터(10)는 플로팅(Floating) 방지 동작을 수행한다. 다시 말해, 레벨 시프터(10)의 레벨 시프팅부(100)는 플로팅 하이(Floating High)인 상태가 되는 것을 방지한다. In addition, the level shifter 10 according to the present embodiment performs a floating prevention operation. In other words, the level shifting unit 100 of the level shifter 10 prevents a floating high state.
구체적으로, 레벨 시프터(10)의 레벨 시프팅부(100)는 입력신호의 전압이 '하이'로 상승 변환이 끝난 후, 제1 미러 노드가 제1 NMOS 트랜지스터에 의해 ‘0’으로 고정되어 있어 있으므로 제3 PMOS 트랜지스터와 제4 PMOS 트랜지스터를 통해 제2 전원전압에서 풀업(Pull-up)에 의한 전류를 공급받아 출력신호가 제2 전원전압 상태가 유지되도록 하고, 출력신호가 플로팅 하이(Floating High)인 상태가 되는 것을 방지할 수 있다. Specifically, since the level shifting unit 100 of the level shifter 10 has the first mirror node fixed at '0' by the first NMOS transistor after the voltage of the input signal is converted to 'high', A pull-up current is supplied from the second power supply voltage through the third PMOS transistor and the fourth PMOS transistor so that the output signal maintains the second power supply voltage state, and the output signal is floating high. can be prevented from becoming
또한, 본 실시예에 따른 레벨 시프터(10)는 입력신호의 전압에 따라 풀 스윙(Full swing) 전환을 수행한다. In addition, the level shifter 10 according to the present embodiment performs full swing conversion according to the voltage of the input signal.
구체적으로, 레벨 시프터(10)는 입력신호의 전압이 '하이'인 상태로 상승 전환될 때, 출력신호의 전압이 제2 전원전압까지 상승되도록 하고, 입력신호의 전압이 '하이'인 상태로 상승 전환이 완료된 후 출력신호의 전압이 제2 전원전압을 유지하도록 동작한다. 또한, 레벨 시프터(10)는 입력신호의 전압이 '로우'인 상태로 하강 전환될 때, 제4 PMOS 트랜지스터를 통해 풀업(Pull-up)에 의한 전류를 차단하고, 제2 NMOS 트랜지스터로 인해 출력신호의 전압이 '로우'로 풀다운(Pull-down)되도록 하여 출력신호의 전압은 그라운드(Ground)로부터 제2 전원전압까지 변하도록 동작한다. Specifically, the level shifter 10 causes the voltage of the output signal to rise to the second power supply voltage when the voltage of the input signal is raised to a 'high' state, and the voltage of the input signal is raised to a 'high' state. After the rising transition is completed, the voltage of the output signal is operated to maintain the second power supply voltage. In addition, when the voltage of the input signal is turned down to a 'low' state, the level shifter 10 cuts off the current by the pull-up through the fourth PMOS transistor and outputs the current through the second NMOS transistor. The voltage of the output signal is operated so that the voltage of the output signal is changed from the ground to the second power supply voltage by causing the voltage of the signal to be pulled down to 'low'.
도 7a 및 도 7b는 본 발명의 실시예에 따른 레벨 시프터에서의 트랜지스터 스택 및 FinFET 사이즈를 나타낸 도면이다. 7A and 7B are diagrams illustrating a size of a transistor stack and a FinFET in a level shifter according to an embodiment of the present invention.
도 7a은 본 발명의 실시예에 따른 레벨 시프터(10)에서의 MOS 트랜지스터 스택(stack)을 나타낸 도면이고, 도 7b는 본 발명의 실시예에 따른 레벨 시프터(10)에서의 FinFET 사이즈를 나타낸 도면이다. 7A is a diagram showing a MOS transistor stack in the level shifter 10 according to an embodiment of the present invention, and FIG. 7B is a diagram showing the FinFET size in the level shifter 10 according to an embodiment of the present invention. am.
도 7a에 도시된 바와 같이, 제4 NMOS 트랜지스터(220)- 제5 NMOS 트랜지스터(230)에 대한 풀 다운 경로(pull-down path)의 NMOS 트랜지스터 스택(NFET stack, 700)의 순서를 고려하여 레벨 시프터(10)의 회로를 설계할 수 있다. 예를 들어, 본 실시예에 따른 레벨 시프터(10)는 4nm ~ 7nm FinFET을 사용하여 사이징(sizing)할 수 있다. 레벨 시프터(10)에 포함된 각각의 트랜지스터는 목적에 따라 도 7b와 같이 Fin 개수를 다르게 설정할 수 있다. As shown in FIG. 7A, considering the order of the NMOS transistor stack (NFET stack, 700) of the pull-down path for the fourth NMOS transistor 220 to the fifth NMOS transistor 230, the level The circuit of the shifter 10 can be designed. For example, the level shifter 10 according to the present embodiment can be sized using a 4nm to 7nm FinFET. Each transistor included in the level shifter 10 may have a different number of Fins according to a purpose, as shown in FIG. 7B.
도 8은 본 발명의 실시예에 따른 레벨 시프터의 동작을 나타낸 도면이다. 8 is a diagram illustrating the operation of a level shifter according to an embodiment of the present invention.
도 8의 (a)는 레벨 시프터(10)의 상승 전환 동작을 나타내고, 도 10의 (b)는 레벨 시프터(10)의 하강 전환 동작을 나타낸다. FIG. 8 (a) shows an upward conversion operation of the level shifter 10, and FIG. 10 (b) shows a downward conversion operation of the level shifter 10.
도 9는 본 발명의 실시예에 따른 레벨 시프터와 종래의 레벨 시프터 간의 에너지 소모를 비교한 결과를 나타낸 도면이다.9 is a diagram showing a result of comparing energy consumption between a level shifter according to an embodiment of the present invention and a conventional level shifter.
도 9는 본 실시예에 따른 레벨 시프터(10), CPLS 및 CMLS 간의 에너지 소모를 비교한 결과를 나타낸다. 도 9를 참고하면, 본 발명의 실시예에 따른 레벨 시프터(10)는 0.6 v일 때 CPLS보다 48.4 % 만큼 개선된 에너지 효율을 가지고 있으며 CMLS보다 79.69 % 만큼 개선된 에너지 효율을 가지는 것을 확인할 수 있다. 9 shows a result of comparing energy consumption between the level shifter 10, CPLS, and CMLS according to the present embodiment. Referring to FIG. 9 , it can be seen that the level shifter 10 according to an embodiment of the present invention has energy efficiency improved by 48.4% compared to CPLS at 0.6 v and energy efficiency improved by 79.69% compared to CMLS. .
도 10은 본 발명의 실시예에 따른 몬테 카를로 시뮬레이션의 결과를 나타낸 도면이다. 10 is a diagram showing the results of Monte Carlo simulation according to an embodiment of the present invention.
도 10은 2000 번 몬테 카를로 시뮬레이션(Monte Carlo simulation)을 처리한 결과를 나타낸다. 도 10와 같이 CPLS는 0.4 v 일 때 몬테 카를로 시뮬레이션 결과, 불안정한 레벨 시프팅(Level Shifting) 결과를 가져오는 것을 확인할 수 있다. 10 shows the result of processing 2000 Monte Carlo simulations. As shown in FIG. 10, it can be seen that when CPLS is 0.4 v, Monte Carlo simulation results and unstable level shifting results are obtained.
반면, 본 발명의 레벨 시프터(10)는 0.4 v 때 안정적인 레벨 시프팅(Level Shifting)을 수행하는 것을 확인할 수 있다. 따라서, 본 발명의 레벨 시프터(10) 구조는 CPLS보다 넓은 범위의 입력 범위를 가지는 것을 확인할 수 있다.On the other hand, it can be confirmed that the level shifter 10 of the present invention performs stable level shifting at 0.4 v. Therefore, it can be confirmed that the structure of the level shifter 10 of the present invention has a wider input range than CPLS.
도 11은 본 발명의 실시예에 따른 레벨 시프터와 종래의 다수의 레벨 시프터와의 지연 정도를 비교 결과를 나타낸 도면이다.11 is a diagram showing a result of comparing delay between a level shifter according to an embodiment of the present invention and a plurality of conventional level shifters.
도 11의 그래프를 참고하면, 지연(Delay)이 적어 동작 속도가 가장 빠른 회로는 CMLS(⑤)이지만 CMLS는 스태틱 전류(Static current) 문제로 인해 실질적으로 사용하기 어렵다. 따라서, 본 발명의 레벨 시프터(⑧)가 다른 레벨 시프터의 구조에 비해 동작 속도가 빠른 것을 확인할 수 있다. Referring to the graph of FIG. 11 , the circuit with the fastest operating speed due to its low delay is the CMLS (⑤), but it is difficult to use the CMLS in practice due to the problem of static current. Therefore, it can be confirmed that the level shifter (⑧) of the present invention has a higher operating speed than the structures of other level shifters.
이상의 설명은 본 발명의 실시예의 기술 사상을 예시적으로 설명한 것에 불과한 것으로서, 본 발명의 실시예가 속하는 기술 분야에서 통상의 지식을 가진 자라면 본 발명의 실시예의 본질적인 특성에서 벗어나지 않는 범위에서 다양한 수정 및 변형이 가능할 것이다. 따라서, 본 발명의 실시예들은 본 발명의 실시예의 기술 사상을 한정하기 위한 것이 아니라 설명하기 위한 것이고, 이러한 실시예에 의하여 본 발명의 실시예의 기술 사상의 범위가 한정되는 것은 아니다. 본 발명의 실시예의 보호 범위는 아래의 청구범위에 의하여 해석되어야 하며, 그와 동등한 범위 내에 있는 모든 기술 사상은 본 발명의 실시예의 권리범위에 포함되는 것으로 해석되어야 할 것이다.The above description is only illustrative of the technical idea of the embodiment of the present invention, and those skilled in the art to which the embodiment of the present invention pertains may make various modifications and modifications within the scope not departing from the essential characteristics of the embodiment of the present invention. transformation will be possible. Therefore, the embodiments of the present invention are not intended to limit the technical idea of the embodiment of the present invention, but to explain, and the scope of the technical idea of the embodiment of the present invention is not limited by these examples. The protection scope of the embodiments of the present invention should be construed according to the claims below, and all technical ideas within the equivalent range should be construed as being included in the scope of the embodiments of the present invention.
<부호의 설명><Description of codes>
10: 레벨 시프터10: Level Shifter
100: 레벨 시프팅부100: level shifting unit
200: 제어신호 생성부200: control signal generator

Claims (13)

  1. 입력신호(IN)의 전압 레벨에 따라 출력신호(OUT)의 전압 레벨을 변환하여 출력하는 레벨 시프터에 있어서,In the level shifter for converting and outputting the voltage level of the output signal (OUT) according to the voltage level of the input signal (IN),
    제1 전원전압에 연결된 입력신호(IN)를 입력 받고, 상기 입력신호의 전압 레벨에 대응되도록 전압 레벨을 조정하여 상기 출력신호(OUT)를 출력하는 레벨 시프팅부; 및 a level shifting unit receiving an input signal (IN) connected to a first power supply voltage, adjusting a voltage level to correspond to the voltage level of the input signal, and outputting the output signal (OUT); and
    상기 입력신호(IN)의 전압 레벨 변환 시 상기 출력신호(OUT)의 전압 레벨 변환을 위하여 상기 레벨 시프팅부에 포함된 일부 트랜지스터의 동작을 제어하는 제어신호를 생성하여 전달하는 제어신호 생성부When the voltage level of the input signal (IN) is converted, a control signal generator generates and transfers a control signal for controlling the operation of some transistors included in the level shifting unit to convert the voltage level of the output signal (OUT).
    를 포함하는 것을 특징으로 하는 레벨 시프터.A level shifter comprising a.
  2. 제1항에 있어서,According to claim 1,
    상기 레벨 시프팅부는,The level shifting unit,
    적어도 2 개의 NMOS 트랜지스터 및 적어도 4 개의 PMOS 트랜지스터를 포함하되,at least 2 NMOS transistors and at least 4 PMOS transistors,
    상기 레벨 시프팅부는, 제1 NMOS 트랜지스터 및 제2 NMOS 트랜지스터를 포함하는 적어도 2 개의 NMOS 트랜지스터와 제1 PMOS 트랜지스터, 제2 PMOS 트랜지스터, 제3 PMOS 트랜지스터 및 제4 PMOS 트랜지스터를 포함하는 적어도 4 개의 PMOS 트랜지스터로 구성되는 것을 특징으로 하는 레벨 시프터.The level shifting unit may include at least two NMOS transistors including a first NMOS transistor and a second NMOS transistor and at least four PMOS transistors including a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor. A level shifter comprising a transistor.
  3. 제2항에 있어서,According to claim 2,
    상기 레벨 시프팅부는,The level shifting unit,
    제2 전원전압과 제1 연결 라인 및 제2 연결 라인이 병렬로 연결되며,The second power supply voltage and the first connection line and the second connection line are connected in parallel,
    상기 제1 연결 라인에는 제2 PMOS 트랜지스터, 제1 PMOS 트랜지스터 및 제1 NMOS 트랜지스터가 직렬 연결되고, 상기 제2 연결 라인에는 제3 PMOS 트랜지스터, 제4 PMOS 트랜지스터 및 제2 NMOS 트랜지스터가 직렬 연결되는 것을 특징으로 하는 레벨 시프터.A second PMOS transistor, a first PMOS transistor, and a first NMOS transistor are connected in series to the first connection line, and a third PMOS transistor, a fourth PMOS transistor, and a second NMOS transistor are connected in series to the second connection line. Featured level shifter.
  4. 제3항에 있어서,According to claim 3,
    상기 레벨 시프팅부에서, In the level shifting unit,
    제1 NMOS 트랜지스터의 게이트는 상기 입력신호를 입력받는 입력노드와 연결되고, 제4 PMOS 트랜지스터 및 제2 NMOS 트랜지스터 사이의 접점은 출력신호를 출력하는 출력노드와 연결되며, 제1 PMOS 트랜지스터의 게이트는 출력신호를 피드백 받기 위하여 출력노드와 연결되되,A gate of the first NMOS transistor is connected to an input node receiving the input signal, a contact point between the fourth PMOS transistor and the second NMOS transistor is connected to an output node outputting an output signal, and a gate of the first PMOS transistor is It is connected to the output node to receive feedback of the output signal,
    제2 PMOS 트랜지스터 및 제3 PMOS 트랜지스터는 커런트 미러(Current Mirror) 구조를 가지며, 상기 제2 PMOS 트랜지스터 및 상기 제3 PMOS 트랜지스터의 게이트 사이의 제1 미러 노드는 제1 PMOS 트랜지스터 및 제1 NMOS 트랜지스터 사이의 노드와 연결되는 것을 특징으로 하는 레벨 시프터.The second PMOS transistor and the third PMOS transistor have a current mirror structure, and the first mirror node between the gates of the second PMOS transistor and the third PMOS transistor is between the first PMOS transistor and the first NMOS transistor. Level shifter, characterized in that connected to the node of.
  5. 제2항에 있어서,According to claim 2,
    상기 제어신호 생성부는,The control signal generating unit,
    제4 PMOS 트랜지스터 및 제2 NMOS 트랜지스터의 게이트와 연결되고, 제4 PMOS 트랜지스터 및 제2 NMOS 트랜지스터의 동작 제어를 위한 상기 제어신호를 인가하되,It is connected to the gates of the fourth PMOS transistor and the second NMOS transistor and applies the control signal for controlling the operation of the fourth PMOS transistor and the second NMOS transistor,
    상기 제어신호는 상기 입력신호가 인버팅된 인버팅 신호인 것을 특징으로 하는 레벨 시프터.The level shifter, characterized in that the control signal is an inverting signal obtained by inverting the input signal.
  6. 제2항에 있어서,According to claim 2,
    상기 제어신호 생성부는,The control signal generating unit,
    적어도 3 개의 NMOS 트랜지스터 및 적어도 3 개의 PMOS 트랜지스터를 포함하되,at least 3 NMOS transistors and at least 3 PMOS transistors,
    상기 제어신호 생성부는, 제3 NMOS 트랜지스터, 제4 NMOS 트랜지스터 및 제5 NMOS 트랜지스터를 포함하는 적어도 3 개의 NMOS 트랜지스터와 제5 PMOS 트랜지스터, 제6 PMOS 트랜지스터 및 제7 PMOS 트랜지스터를 포함하는 적어도 3 개의 PMOS 트랜지스터로 구성되는 것을 특징으로 하는 레벨 시프터.The control signal generator may include at least three NMOS transistors including a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, and at least three PMOS transistors including a fifth PMOS transistor, a sixth PMOS transistor, and a seventh PMOS transistor. A level shifter comprising a transistor.
  7. 제6항에 있어서,According to claim 6,
    상기 제어신호 생성부는,The control signal generating unit,
    제2 전원전압과 제3 연결 라인 및 제4 연결 라인이 병렬로 연결되며,The second power supply voltage and the third connection line and the fourth connection line are connected in parallel,
    상기 제3 연결 라인에는 제6 PMOS 트랜지스터, 제5 PMOS 트랜지스터 및 제3 NMOS 트랜지스터가 직렬 연결되고, 상기 제4 연결 라인에는 제7 PMOS 트랜지스터, 제4 NMOS 트랜지스터 및 제5 NMOS 트랜지스터가 직렬 연결되는 것을 특징으로 하는 레벨 시프터.A sixth PMOS transistor, a fifth PMOS transistor, and a third NMOS transistor are connected in series to the third connection line, and a seventh PMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor are connected in series to the fourth connection line. Featured level shifter.
  8. 제7항에 있어서,According to claim 7,
    상기 제어신호 생성부에서,In the control signal generator,
    제5 PMOS 트랜지스터 및 제3 NMOS 트랜지스터의 게이트는 상기 입력신호를 입력받는 입력노드와 연결되고, 제5 PMOS 트랜지스터 및 제3 NMOS 트랜지스터 사이의 접점은 제어신호를 출력하는 제어노드와 연결되며, 제어노드는 레벨 시프팅부로 제어신호를 인가하기 위하여 제4 PMOS 트랜지스터 및 제2 NMOS 트랜지스터의 게이트와 연결되고, 제4 NMOS 트랜지스터의 게이트는 입력신호에 대한 인버팅 신호를 입력받는 인버팅 입력 노드와 연결되며, 제5 NMOS 트랜지스터의 게이트는 출력신호를 피드백 받기 위하여 출력노드와 연결되되,Gates of the fifth PMOS transistor and the third NMOS transistor are connected to an input node receiving the input signal, and a contact point between the fifth PMOS transistor and the third NMOS transistor is connected to a control node outputting a control signal, and a control node Is connected to the gates of the fourth PMOS transistor and the second NMOS transistor to apply a control signal to the level shifting unit, and the gate of the fourth NMOS transistor is connected to an inverting input node receiving an inverting signal for the input signal. , The gate of the fifth NMOS transistor is connected to the output node to receive feedback of the output signal,
    제6 PMOS 트랜지스터 및 제7 PMOS 트랜지스터는 커런트 미러(Current Mirror) 구조를 가지며, 상기 제6 PMOS 트랜지스터 및 상기 제7 PMOS 트랜지스터의 게이트 사이의 제2 미러 노드는 제7 PMOS 트랜지스터 및 제4 NMOS 트랜지스터 사이의 노드와 연결되는 것을 특징으로 하는 레벨 시프터.The sixth PMOS transistor and the seventh PMOS transistor have a current mirror structure, and the second mirror node between the gates of the sixth PMOS transistor and the seventh PMOS transistor is between the seventh PMOS transistor and the fourth NMOS transistor. Level shifter, characterized in that connected to the node of.
  9. 제6항에 있어서,According to claim 6,
    상기 레벨 시프터는,The level shifter,
    입력신호의 전압이 '로우'에서 '하이'로 상승 변환한 경우, (i) 입력신호의 전압에 의해 제1 NMOS 트랜지스터가 켜져 제1 미러 노드가 '로우'로 하강하고, 제2 PMOS 트랜지스터 및 제3 PMOS 트랜지스터가 켜지며, 동시에, (ii) 입력신호의 전압에 의해 제3 NMOS 트랜지스터가 켜져 제어신호의 전압이 '로우'로 하강하고, 제4 PMOS 트랜지스터가 켜지며, (iii) 제3 PMOS 트랜지스터 및 제4 PMOS 트랜지스터를 통해 전압이 '하이'로 상승된 상기 출력신호를 출력노드로 출력하는 것을 특징으로 하는 레벨 시프터.When the voltage of the input signal is up-converted from 'low' to 'high', (i) the first NMOS transistor is turned on by the voltage of the input signal, the first mirror node goes down to 'low', the second PMOS transistor and The third PMOS transistor is turned on, (ii) the third NMOS transistor is turned on by the voltage of the input signal, the voltage of the control signal drops to 'low', the fourth PMOS transistor is turned on, (iii) the third The level shifter, characterized in that for outputting the output signal whose voltage is raised to 'high' through the PMOS transistor and the fourth PMOS transistor to an output node.
  10. 제9항에 있어서,According to claim 9,
    상기 레벨 시프팅부는,The level shifting unit,
    입력신호의 전압이 '하이'인 상태인 경우, 출력신호의 전압을 피드백 받는 제1 PMOS 트랜지스터가 꺼짐 상태로 동작하여 제2 PMOS 트랜지스터 및 제1 NMOS 트랜지스터를 통해 흐르게 되는 스태틱 전류(static current)를 차단하는 것을 특징으로 하는 레벨 시프터.When the voltage of the input signal is in a 'high' state, the first PMOS transistor receiving feedback of the voltage of the output signal operates in an off state to reduce the static current flowing through the second PMOS transistor and the first NMOS transistor. A level shifter characterized in that for blocking.
  11. 제9항에 있어서,According to claim 9,
    상기 레벨 시프팅부는,The level shifting unit,
    입력신호의 전압이 '하이'로 상승 변환이 끝난 후, 제1 미러 노드가 제1 NMOS 트랜지스터에 의해 ‘0’으로 고정되어 있어 있으므로 제3 PMOS 트랜지스터와 제4 PMOS 트랜지스터를 통해 제2 전원전압에서 풀업(Pull-up)에 의한 전류를 공급받아 출력신호가 제2 전원전압 상태가 유지되도록 하고, 출력신호가 플로팅 하이(Floating High)인 상태가 되는 것을 방지하는 것을 특징으로 하는 레벨 시프터.After the voltage of the input signal is converted to 'high', since the first mirror node is fixed at '0' by the first NMOS transistor, the second power voltage is generated through the third and fourth PMOS transistors. A level shifter characterized by receiving current supplied by a pull-up, maintaining the output signal in the second power supply voltage state, and preventing the output signal from being in a floating high state.
  12. 제6항에 있어서,According to claim 6,
    상기 레벨 시프팅부는,The level shifting unit,
    입력신호의 전압에 따라 풀 스윙(Full swing) 전환을 수행하되, Full swing conversion is performed according to the voltage of the input signal,
    입력신호의 전압이 '하이'인 상태로 상승 전환될 때, 출력신호의 전압이 제2 전원전압까지 상승되도록 하고, 입력신호의 전압이 '하이'인 상태로 상승 전환이 완료된 후 출력신호의 전압이 제2 전원전압을 유지하도록 하며,When the voltage of the input signal is raised to a 'high' state, the voltage of the output signal is increased to the second power supply voltage, and the voltage of the output signal is completed after the rising transition is completed while the voltage of the input signal is 'high'. This second power supply voltage is maintained,
    입력신호의 전압이 '로우'인 상태로 하강 전환될 때, 제4 PMOS 트랜지스터를 통해 풀업(Pull-up)에 의한 전류를 차단하고, 제2 NMOS 트랜지스터로 인해 출력신호의 전압이 '로우'로 풀다운(Pull-down)되도록 하여 출력신호의 전압은 그라운드(Ground)로부터 제2 전원전압까지 변하게 되는 것을 특징으로 하는 레벨 시프터.When the voltage of the input signal is turned down to a 'low' state, the current by the pull-up is blocked through the 4th PMOS transistor, and the voltage of the output signal is reduced to 'low' by the 2nd NMOS transistor. A level shifter characterized in that the voltage of the output signal is changed from the ground to the second power supply voltage by being pulled down.
  13. 제6항에 있어서,According to claim 6,
    상기 레벨 시프터는, The level shifter,
    입력신호의 전압이 '하이'에서 '로우'로 하강 변환한 경우, (i) 입력신호의 전압에 의해 제5 PMOS 트랜지스터가 켜지며, 동시에, (ii) 인버팅 신호의 전압에 의해 제4 NMOS 트랜지스터가 켜져 제2 미러 노드가 '로우'로 하강하고, 제6 PMOS 트랜지스터 및 제7 PMOS 트랜지스터가 켜지며, (iii) 제6 PMOS 트랜지스터 및 제5 PMOS 트랜지스터를 통해 전압이 '하이'로 상승된 제어신호를 출력하며, (iv) 제어신호의 전압에 의해 제2 NMOS 트랜지스터가 켜져 전압이 '로우'로 하강된 상기 출력신호를 출력노드로 출력하는 것을 특징으로 하는 레벨 시프터.When the voltage of the input signal is down-converted from 'high' to 'low', (i) the 5th PMOS transistor is turned on by the voltage of the input signal, and at the same time (ii) the 4th NMOS transistor is turned on by the voltage of the inverting signal. The transistor is turned on, the second mirror node drops to 'low', the 6th PMOS transistor and the 7th PMOS transistor are turned on, (iii) the voltage is raised to 'high' through the 6th PMOS transistor and the 5th PMOS transistor. A level shifter that outputs a control signal, and (iv) outputs the output signal whose voltage has dropped to 'low' to an output node when the second NMOS transistor is turned on by the voltage of the control signal.
PCT/KR2022/012201 2021-09-09 2022-08-16 Level shifter for improving energy efficiency and input voltage range WO2023038314A1 (en)

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KR1020220048367A KR102648236B1 (en) 2021-09-09 2022-04-19 Level Shifter with Improved Power Efficiency and Input Voltage Range

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040155693A1 (en) * 2003-01-31 2004-08-12 Matsushita Electric Industrial Co., Ltd. Level shifter having automatic delay adjusting function
KR20100015946A (en) * 2007-04-27 2010-02-12 모사이드 테크놀로지스 인코퍼레이티드 A buffer comprising a voltage level shifting circuit
KR20180092804A (en) * 2017-02-09 2018-08-20 에이블릭 가부시키가이샤 Level shifter
KR20200092104A (en) * 2019-01-24 2020-08-03 삼성전자주식회사 Level shifter and operation method thereof
KR20200138655A (en) * 2019-05-31 2020-12-10 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Level shifter

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040155693A1 (en) * 2003-01-31 2004-08-12 Matsushita Electric Industrial Co., Ltd. Level shifter having automatic delay adjusting function
KR20100015946A (en) * 2007-04-27 2010-02-12 모사이드 테크놀로지스 인코퍼레이티드 A buffer comprising a voltage level shifting circuit
KR20180092804A (en) * 2017-02-09 2018-08-20 에이블릭 가부시키가이샤 Level shifter
KR20200092104A (en) * 2019-01-24 2020-08-03 삼성전자주식회사 Level shifter and operation method thereof
KR20200138655A (en) * 2019-05-31 2020-12-10 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Level shifter

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