CN217607797U - Level conversion circuit, integrated circuit, and electronic device - Google Patents

Abstract

The application discloses a level conversion circuit, an integrated circuit and an electronic device. The level shift circuit includes: the signal input module is used for generating an intermediate signal according to an input signal at a first end of the signal input module and transmitting the intermediate signal to a first intermediate node, the signal output module is used for generating an output signal according to the intermediate signal at the first intermediate node and transmitting the output signal to a second end of the signal output module, and the positive feedback module is used for adjusting a level value of the intermediate signal of the signal input module according to the output signal in a conversion process of converting the level value of the output signal from an initial level to a target level, so that the conversion speed is accelerated, and the transmission requirement of a high-speed signal is met.

Description

Level conversion circuit, integrated circuit, and electronic device

Technical Field

The present disclosure relates to the field of integrated circuit technologies, and more particularly, to a level shifter, an integrated circuit, and an electronic device.

Background

With the rapid development of technology, integrated circuits (e.g., SOC) have been widely used in various electronic devices, such as mobile phones, tablet computers, and notebook computers. To achieve energy saving and high efficiency in the operation of the integrated circuit, each module in the integrated circuit should operate at different and appropriate voltages according to different requirements. Therefore, the multi-power-supply voltage domain technology is widely applied to integrated circuits.

In an integrated circuit applying a multi-power-supply voltage domain technology, a level conversion circuit is an important module, and provides an interactive way for modules working under different voltage domains, so that correct transmission of signals among the voltage domains is ensured. However, the traditional level shift circuit has long delay of rising and falling of input and output signals, has large influence on high-speed signals, and is not suitable for high-speed and high-performance integrated circuits.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention provides a level shift circuit, an integrated circuit and an electronic device to improve the above problems.

In a first aspect, an embodiment of the present application provides a level shift circuit. The circuit comprises a signal input module, a signal output module and a positive feedback module. The first end of the signal input module is connected to a first reference voltage, the second end of the signal input module is grounded, the third end of the signal input module is connected to the first end of the signal input module, and the fourth end of the signal input module is connected to a first intermediate node; the signal input module is used for generating an intermediate signal according to an input signal of the first end of the signal input module and transmitting the intermediate signal to the first intermediate node. The first end of the signal output module is connected to the first intermediate node, the second end of the signal output module is used for transmitting an output signal, the third end of the signal output module is connected to a first reference voltage, and the fourth end of the signal output module is grounded; the signal output module is used for generating an output signal according to the intermediate signal of the first intermediate node and transmitting the output signal to the second end of the signal output module. The first end of the positive feedback module is connected to the first intermediate node, the second end of the positive feedback module is connected to the first reference voltage, and the third end of the positive feedback module is connected to the second end of the signal output module; the positive feedback module is used for adjusting the level value of the intermediate signal of the signal input module according to the output signal in the conversion process of converting the level value of the output signal from the initial level to the target level, so that the conversion speed is accelerated. The initial level is a high level or a low level, and when the initial level is the high level, the target level is the low level; when the initial level is low, the target level is high.

In a second aspect, an embodiment of the present application provides an integrated circuit including the above level shift circuit.

In a third aspect, an embodiment of the present application provides an electronic device, which includes the above level shift circuit or the above integrated circuit.

The utility model provides a level shift circuit includes: the signal input module is used for generating an intermediate signal according to an input signal at a first end of the signal input module and transmitting the intermediate signal to a first intermediate node, the signal output module is used for generating an output signal according to the intermediate signal at the first intermediate node and transmitting the output signal to a second end of the signal output module, and the positive feedback module is used for adjusting a level value of the intermediate signal of the signal input module according to the output signal in a conversion process of converting the level value of the output signal from an initial level to a target level, so that the conversion speed is accelerated, and the transmission requirement of a high-speed signal is met.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a schematic structural diagram of a level shift circuit according to an embodiment of the present invention.

Fig. 2 shows a schematic structural diagram of a signal input module according to an embodiment of the present invention.

Fig. 3 shows a schematic structural diagram of a first unit according to an embodiment of the present invention.

Fig. 4 shows a schematic structural diagram of a second unit according to an embodiment of the present invention.

Fig. 5 shows a schematic structural diagram of a second inverter according to an embodiment of the present invention.

Fig. 6 shows a schematic structural diagram of a third unit provided in an embodiment of the present invention.

Fig. 7 shows a schematic structural diagram of another third unit provided in the embodiment of the present invention.

Fig. 8 shows a schematic structural diagram of a signal output module according to an embodiment of the present invention.

Fig. 9 shows a schematic structural diagram of a second inverter according to an embodiment of the present invention.

Fig. 10 shows a schematic structural diagram of a positive feedback module according to an embodiment of the present invention.

Fig. 11 is a schematic structural diagram of another level shift circuit according to an embodiment of the present invention.

Fig. 12 shows a schematic structural diagram of a reset module according to an embodiment of the present invention.

Fig. 13 is a schematic structural diagram of another level shift circuit according to an embodiment of the present invention.

Fig. 14 shows a transient simulation waveform diagram of a level shift circuit according to an embodiment of the present invention.

Fig. 15 shows a schematic structural diagram of an integrated circuit according to an embodiment of the present invention.

Fig. 16 shows a schematic structural diagram of an electronic device according to an embodiment of the present invention.

Fig. 17 is a schematic structural diagram of another electronic device according to an embodiment of the present invention.

Description of the drawings: 100. the circuit comprises a level conversion circuit 110, a signal input module 110a and a first end of the signal input module; 110b, a second end of the signal input module; 110c, a third end of the signal input module; 111. a first unit 111a, a first end of the first unit 111b, a second end of the first unit 111c, a third end of the first unit; 1111. a second switch tube 1111a, a first end of the second switch tube 1111b, a second end of the second switch tube 1111c, a third end of the second switch tube; 112. a second cell, 112a, a first end of the second cell, 112b, a second end of the second cell, 112c, a third end of the second cell, 112d, a fourth end of the second cell; 1121. a first inverter, 1121a, a first terminal of the first inverter, 1121b, a second terminal of the first inverter; 11211. a fifth switching tube 11211a, a first end 11211b of the fifth switching tube, a second end 11211c of the fifth switching tube, and a third end of the fifth switching tube; 11212. a sixth switching tube 11212a, a first end of the sixth switching tube 11212b, a second end of the sixth switching tube 11212c, a third end of the sixth switching tube; 1122. a third switching tube 1122a, a first end of the third switching tube 1122b, a second end of the third switching tube 1122c, and a third end of the third switching tube; 1123. a fourth switching tube 1123a, a first end of the fourth switching tube 1123b, a second end of the fourth switching tube 1123c, and a third end of the fourth switching tube; 113. a third cell 113a, a first end of the third cell 113b, a second end of the third cell 113c, a third end of the third cell 113d, a fourth end of the third cell; 1131. a seventh switching tube 1131a, a first end of the seventh switching tube, 1131b, a second end of the seventh switching tube, 1131c, and a third end of the seventh switching tube; 1132. an eighth switching tube 1132a, a first end of the eighth switching tube, 1132b, a second end of the eighth switching tube, 1132c, and a third end of the eighth switching tube; 120. the signal output module 120a, the first end of the signal output module 120b, the second end of the signal output module 120c, the third end of the signal output module 120d and the fourth end of the signal output module; 121. a second inverter 121a, a first terminal of the second inverter, 121b, a second terminal of the second inverter; 1211. a ninth switching tube 1211a, a first end 1211b of the ninth switching tube, a second end 1211c of the ninth switching tube, and a third end of the ninth switching tube; 1212. a tenth switching tube 1212a, a first end of the tenth switching tube 1212b, a second end of the tenth switching tube 1212c, and a third end of the tenth switching tube; 130. the positive feedback module 130a, the first end of the positive feedback module 130b, the second end of the positive feedback module 130c, the third end of the positive feedback module 131, the eleventh switch tube 131a, the first end of the eleventh switch tube 131b, the second end of the eleventh switch tube 131c and the third end of the eleventh switch tube 131 c; 140. the reset module 140a, the first end of the reset module, 140b, the second end of the reset module, 140c and the third end of the reset module; 141. the first switch tube 141a, the first end 141b of the first switch tube, the second end 141c of the first switch tube, and the third end of the first switch tube; IN, an input signal, OUT, an output signal, RST, a reset signal, V1, a first reference voltage, V2, a second reference voltage, a first intermediate node, B, a second intermediate node, C, a third intermediate node; 200. an integrated circuit; 300. electronic device, 310, housing.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

With the rapid development of technology, integrated circuits (e.g., system on chip SOCs) have been widely used in various electronic devices, such as mobile phones, tablet computers, notebook computers, etc. To achieve energy saving and high efficiency in the operation of the integrated circuit, each module in the integrated circuit should operate at different and appropriate voltages according to different requirements. Generally, a module which is critical to a time sequence usually works under a higher power supply voltage so as to meet the speed performance index of a chip; modules with low timing requirements are generally operated at a lower power supply voltage to reduce the power consumption of the chip. Therefore, the multi-power-supply voltage domain technology is widely applied to integrated circuits. In an integrated circuit applying a multi-power-supply voltage domain technology, a level conversion circuit is an important module, and provides an interactive way for modules working under different voltage domains, so that correct transmission of signals among the voltage domains is ensured. When the signal is converted from the high-voltage domain to the low-voltage domain, the ordinary buffer can be used for realizing the trans-voltage domain transmission of the signal; when a signal is converted from a low voltage domain to a high voltage domain, a more complex level shift circuit is required.

However, the applicant has found in research that the conventional level shift circuit commonly used at present is not very suitable for high-speed data transmission. Specifically, the conventional level shift circuit has a long delay between the rise and the fall of the input and output signals, which is not favorable for maintaining the integrity of the high-speed signals, and thus causes signal distortion. The conventional level shift circuit commonly used at present comprises a cross-coupling level shift circuit and a level shift circuit based on a current mirror, and both of the circuits have the problem of long delay of rising and falling of input and output signals. Therefore, the conventional level shift circuit is not suitable for transmission of high-speed signals, and cannot be applied to high-speed and high-performance integrated circuits, and the limitation is too large.

In order to improve the above problem, the applicant proposes a level shift circuit, an integrated circuit, and an electronic device provided by the present application, wherein the level shift circuit includes: the signal input module is used for generating an intermediate signal according to an input signal at a first end of the signal input module and transmitting the intermediate signal to a first intermediate node, the signal output module is used for generating an output signal according to the intermediate signal at the first intermediate node and transmitting the output signal to a second end of the signal output module, and the positive feedback module is used for adjusting a level value of the intermediate signal of the signal input module according to the output signal in a conversion process of converting the level value of the output signal from an initial level to a target level, so that the conversion speed is accelerated, and the transmission requirement of a high-speed signal is met.

The level shift circuit provided in the embodiments of the present application will be described in detail by specific embodiments.

Referring to fig. 1, an embodiment of the present invention provides a level shift circuit 100, which includes a signal input module 110, a signal output module 120, and a positive feedback module 130.

IN the embodiment of the present application, the first terminal 110a of the signal input module 110 is connected to the first reference voltage V1, the second terminal 110b of the signal input module 110 is grounded, the third terminal 110c of the signal input module 110 is configured to receive the input signal IN, and the fourth terminal 110d of the signal input module 110 is connected to the first intermediate node a. The signal input module 110 is configured to generate an intermediate signal according to the input signal IN at the first end 110a of the signal input module 110, and transmit the intermediate signal to the first intermediate node a.

The input signal IN is a signal to be level-converted. The input signal IN has a plurality of different states according to the level variation of the input signal IN. For example, the input signal IN may be static, i.e. the level state of the input signal IN remains unchanged. Exemplarily, the input signal IN may be maintained IN a high state; the input signal IN may also be kept IN a low state. As another example, the input signal IN may be dynamic, i.e., the level state of the input signal IN changes dynamically. Exemplarily, the input signal IN may be converted from a low level state to a high level state; the input signal IN may also be switched from a high state to a low state.

IN some embodiments, when the voltage of the input signal IN is a preset voltage, the level state of the input signal IN is a high level state. When the voltage of the input signal IN is zero, the level state of the input signal IN is a low level state.

IN some embodiments, the level state of the intermediate signal follows the level state change of the input signal IN and is opposite to the change direction of the input signal.

For example, when the input signal IN is kept IN a high level state, the intermediate signal is kept IN a low level state. When the input signal IN is changed from the low state to the high state, the intermediate signal is changed from the high state to the low state.

In the embodiment of the present application, the first terminal 120a of the signal output module 120 is connected to the first intermediate node a, the second terminal 120b of the signal output module 120 is used for transmitting the output signal OUT, the third terminal 120c of the signal output module 120 is connected to the first reference voltage V2, and the fourth terminal 120d of the signal output module 120 is grounded. The signal output module 120 is configured to generate an output signal OUT according to the intermediate signal of the first intermediate node a.

IN the embodiment of the present application, the output signal OUT refers to a signal obtained by level-converting the input signal IN. Depending on the level variation of the output signal OUT, the output signal OUT may be static, i.e. the level state of the output signal OUT remains unchanged. Illustratively, the output signal OUT may be maintained in a high state; the output signal OUT may also be maintained in a low state. As another example, the output signal OUT may be dynamic, i.e., the level state of the output signal OUT changes dynamically. Illustratively, the output signal OUT may transition from a low state to a high state; the output signal OUT may also be converted from a high state to a low state.

In some embodiments, the level state of the output signal OUT follows the level state change of the intermediate signal and is opposite to the change direction of the intermediate signal.

For example, when the intermediate signal is kept in the high state, the output signal OUT is kept in the low state. When the intermediate signal is switched from the low state to the high state, the output signal OUT is switched from the high state to the low state.

That is, when the level state of the input signal IN changes, the level state of the intermediate signal changes following the level state of the input signal IN, and the direction of the change is opposite to the direction of the change of the input signal IN; the output signal OUT changes along with the level state of the intermediate signal, and the change direction is opposite to that of the intermediate signal; therefore, the level state of the output signal OUT is changed along with the level state of the input signal IN, and the change direction is the same as that of the input signal IN.

IN some embodiments, the first reference voltage V1 is greater than a preset voltage, that is, the voltage range of the output signal OUT is greater than the voltage range of the input signal IN, so that the level shift circuit 100 of the embodiment of the present application can convert the input signal IN the low voltage domain to the output signal OUT IN the high voltage domain.

In the embodiment of the present application, the first terminal 130a of the positive feedback module 130 is connected to the first intermediate node a, the second terminal 130b of the positive feedback module 130 is connected to the first reference voltage V1, and the third terminal 130c of the positive feedback module 130 is connected to the second terminal 120b of the signal output module 120. The positive feedback module 130 is configured to adjust a level value of the intermediate signal of the signal input module 110 according to the output signal OUT during a conversion process of the level value of the output signal OUT from an initial level to a target level, so as to accelerate a conversion speed of the conversion process.

The initial level refers to a level state of the output signal OUT before level conversion; the target level refers to a level state of the output signal OUT after completion of level conversion.

Illustratively, when the input signal IN is converted from a low level to a high level, the initial level of the output signal OUT is a low level and the target level is a high level, and during the level conversion, the level state of the intermediate signal is converted from a high level to a low level, and the positive feedback module 130 reduces the current flowing into the first intermediate node a according to the output signal OUT, thereby accelerating the speed of converting the level state of the intermediate signal from a high level to a low level.

When the input signal IN is converted from a high level to a low level, the initial level of the output signal OUT is a high level and the target level is a low level, and during the level conversion, the level state of the intermediate signal is converted from a low level to a high level, and the positive feedback module 130 increases the current flowing into the first intermediate node a according to the output signal OUT, thereby accelerating the speed at which the level state of the intermediate signal is converted from a low level to a high level.

In some embodiments, as shown in fig. 2, the signal input module 110 includes a first unit 111 and a second unit 112.

The first end 111a of the first unit 111 is connected to the first end 110a of the signal input module 110, the second end 111b of the first unit 111 is connected to the first intermediate node a, and the third end 111c of the first unit 111 is grounded; the first terminal 111a of the first unit 111 receives the input signal IN, and when the input signal IN is at a high level, the first unit 111 generates an intermediate signal from the input signal IN and outputs the intermediate signal through the second terminal 111b of the first unit 111.

In some embodiments, as shown in fig. 3, the first unit 111 includes a second switch tube 1111. The first end 1111a of the second switch 1111 is connected to the first end 110a of the signal input module 110, the second end 111b of the second switch 1111 is grounded, and the third end 1111c of the second switch 1111 is connected to the first intermediate node a.

When the input signal IN is at a high level, the second switch 1111 is turned on to connect the first intermediate node a to the ground, so as to change the level state of the intermediate signal flowing to the first intermediate node a. When the input signal IN is at a low level, the second switch 1111 is turned off, and the path between the first intermediate node a and the ground is disconnected.

Optionally, the second switch tube 1111 is an enhancement NMOS tube.

A first end 112a of the second unit 112 is connected to the first end 110a of the signal input module 110, a second end 112b of the second unit 112 is connected to the first intermediate node a, and a third end 112c of the second unit 112 is connected to the first reference voltage V1. The first terminal 112A of the second unit 112 receives the input signal IN, generates an intermediate signal according to the input signal IN when the input signal IN is at a low level, and outputs the intermediate signal through the second terminal 112b of the second unit 112.

In some embodiments, as shown in fig. 4, the second unit 112 includes a first inverter 1121, a third switching tube 1122, and a fourth switching tube 1123. A first end 1121a of the first inverter 1121 is connected to a first end 1122a of the third switching tube 1122, and a second end 1121b of the first inverter 1121 is connected to the first intermediate node a.

In some embodiments, as shown in fig. 5, the first inverter 1121 includes a fifth switching tube 11211 and a sixth switching tube 11212; a first end 11211a of the fifth switching tube 11211 is connected to the first intermediate node a, a second end 11211B of the fifth switching tube 11211 is connected to a second reference voltage V2, and a third end 11211c of the fifth switching tube 11211 is connected to the second intermediate node B; a first terminal 11212a of the sixth switching tube 11212 is connected to the first intermediate node a, a second terminal 11212B of the sixth switching tube 11212 is grounded, and a third terminal 11212c of the sixth switching tube 11212 is connected to the second intermediate node B.

When the input signal IN is at a low level, the intermediate signal is at a high level, the fifth switching tube 11211 is turned off, and the sixth switching tube 11212 is turned on.

When the input signal IN is at a high level, the intermediate signal is at a low level, the fifth switching tube 11211 is turned on, and the sixth switching tube 11212 is turned off.

Optionally, the fifth switch tube 11211 is an enhancement PMOS tube, and the sixth switch tube 11212 is an enhancement NMOS tube.

In some embodiments, the first end 1122a of the third switching tube 1122 is connected to the second intermediate node B, the second end 1122B of the third switching tube 1122 is connected to the first end 110B of the signal input module 110, and the third end 1122C of the third switching tube 1122 is connected to the third intermediate node C.

In some embodiments, first terminal 1123a of fourth switching tube 1123 is connected to third intermediate node C, second terminal 1123b of fourth switching tube 1123 is connected to first reference voltage V2, and third terminal 1123C of fourth switching tube 1123 is connected to first intermediate node a.

When the input signal IN is at a static low level, the intermediate signal is at a high level, the first inverter 1121 sets the level of the second intermediate node B to a low level according to the high-level intermediate signal, the third switching transistor 1122 is turned off, the fourth switching transistor 1123 is turned off, and the intermediate signal is at a high level.

When the input signal IN is at a static high level, the second unit 112 does not affect the change of the intermediate signal.

When the input signal IN is converted from a high level to a low level, the third switching tube 1122 is turned on, so that the fourth switching tube 1123 is turned on, and the intermediate signal is converted from a low level to a high level; further, the first inverter 1121 turns the second intermediate node B low in response to the high intermediate signal, thereby turning off the third switching tube 1122 and turning off the fourth switching tube 1123.

The second unit 112 does not affect the change of the intermediate signal when the input signal IN is transited from the low level to the high level.

Optionally, the third switch transistor 1122 is an enhancement NMOS transistor, and the fourth switch transistor 1123 is an enhancement PMOS transistor.

In some embodiments, as shown in fig. 6, the signal input module 110 further includes: and a third unit 113. The third unit 113 is configured to maintain the level of the third intermediate node C IN a high state when the input signal IN at the first end 110a of the signal input module 110 is static.

A first end 113a of the third unit 113 is connected to the first reference voltage V1, a second end 113b of the third unit 113 is connected to the first intermediate node a, a third end 113C of the third unit 113 is connected to the third intermediate node C, and a fourth end 113d of the third unit 113 is connected to the second end 120b of the signal output module 120.

In some embodiments, as shown in fig. 7, the third unit 113 includes a seventh switching tube 1131 and an eighth switching tube 1132. A first end 1131a of the seventh switching tube 1131 is connected to the second end 120b of the signal output module 120, a second end 1131b of the seventh switching tube 1131 is connected to the first reference voltage V1, and a third end 1131C of the seventh switching tube 1132 is connected to the third intermediate node C; a first end 1132a of the eighth switch tube 1132 is connected to the first intermediate node a, a second end 1132b of the eighth switch tube 1132 is connected to the first reference voltage V1, and a third end 1132C of the eighth switch tube 1132 is connected to the third intermediate node C.

When the input signal IN is at a static low level, the intermediate signal is at a high level, the seventh switching tube 1131 is turned on, the eighth switching tube 1132 is turned off, and the level of the third intermediate node C remains at a high level.

When the input signal IN is at a static high level, the intermediate signal is at a low level, the seventh switching tube 1131 is turned off, the eighth switching tube 1132 is turned on, and the level of the third intermediate node C remains at a high level.

When the input signal IN is converted from the high level to the low level, the intermediate signal level rises, the seventh switching tube 1131 is turned on, the eighth switching tube 1132 is turned off, and the level of the third intermediate node C is set to the low level.

The third unit 113 does not affect the intermediate signal variation when the input signal IN is transitioned from the low level to the high level.

Optionally, the seventh switch tube 1131 is an enhancement PMOS tube, and the eighth switch tube 1132 is an enhancement PMOS tube.

In some embodiments, the first reference voltage V1 is higher than the second reference voltage V2. If the first reference voltage V1 is lower than the second reference voltage V2, the level of the third terminal 1122c of the third switching tube 1122 may be higher than the second reference voltage V2, and the high voltage may damage the low voltage device providing the input signal IN, thereby reducing the reliability of the front stage circuit. IN the embodiment of the present application, the first inverter 1121 is powered by the second reference voltage V2, and the first end 1121a of the first inverter 1121 outputs a high level signal to control the level of the third end 1122c of the third switching tube 1122 to be less than or equal to the second reference voltage V2, so that the low voltage device providing the input signal IN is effectively prevented from being damaged by the high voltage.

In some embodiments, as shown in fig. 8, the signal output module 120 includes a second inverter 121. The first terminal 121a of the second inverter 121 is connected to the first intermediate node a, and the second terminal 121b of the second inverter 121 is connected to the second terminal 120b of the signal output module 120.

In some embodiments, as shown in fig. 9, the second inverter 121 includes a ninth switching tube 1211 and a tenth switching tube 1212. A first end 1211a of the ninth switching tube 1211 is connected to the first intermediate node a, a second end 1211b of the ninth switching tube 1211 is grounded, and a third end 1211c of the ninth switching tube 1211 is connected to the second end 120b of the signal output module 120; a first end 1212a of the tenth switching tube 1212 is connected to the first intermediate node a, a second end 1212b of the tenth switching tube 1212 is connected to the first reference voltage V1, and a third end 1212c of the tenth switching tube 1212 is connected to the second end 120b of the signal output module 120. Optionally, the ninth switch 1211 is an enhancement NMOS transistor, and the tenth switch 1212 is an enhancement PMOS transistor.

When the input signal IN is at the low static level, the intermediate signal is at the high level, the tenth switching tube 1212 is turned off, the eleventh switching tube 131 is turned on, and the output signal OUT remains at the low level.

When the input signal IN is at the static high level, the intermediate signal is at the low level, the tenth switching tube 1212 is turned on, the eleventh switching tube 131 is turned off, and the output signal OUT remains at the high level.

When the output signal OUT is switched from the high level to the low level, the tenth switching tube 1212 is turned off, the eleventh switching tube 131 is turned on, and the output signal OUT is switched from the high level to the low level.

When the output signal OUT is changed from the low level to the high level, the intermediate signal level is decreased, the tenth switching tube 1212 is turned on, the eleventh switching tube 131 is turned off, and the output signal OUT is changed from the low level to the high level.

The utility model discloses a level conversion circuit need not wait for the pull-up switch tube to turn off at the IN-process that input signal IN was converted into the low level by the high level, can directly switch on ninth switch tube 1211 to the route between intercommunication and the ground makes the level of output signal OUT descend fast, improves the falling speed of output signal OUT level.

The utility model discloses a level shift circuit need not wait for the pull-up switch tube to turn off at the IN-process that input signal IN was converted into the high level by the low level to directly switch on tenth switch tube 1212 to the route between intercommunication and the first reference voltage V1 makes the level of output signal OUT rise fast, improves the rising speed of the level of output signal OUT.

In some embodiments, as shown in fig. 10, the positive feedback module 130 includes an eleventh switching tube 131. The first end 131a of the eleventh switching tube 131 is connected to the second end 120b of the signal output module 120, the second end 131b of the eleventh switching tube 131 is connected to the first reference voltage V1, and the third end 131c of the eleventh switching tube 131 is connected to the first intermediate node a.

When the input signal IN is at a static low level, the eleventh switch tube 131 does not affect the change of the intermediate signal.

When the input signal IN is at a static high level, the eleventh switch tube 131 does not affect the change of the intermediate signal.

When the input signal IN is changed from the high level to the low level, the level of the output signal OUT is decreased, and the eleventh switching tube 131 is turned on to increase the current flowing to the first intermediate node a, thereby increasing the level rising speed of the intermediate signal.

When the input signal IN is changed from the low level to the high level, the level of the output signal OUT rises, and the eleventh switching tube 131 is turned off to reduce the current flowing to the first intermediate node a, so that the speed of the level drop of the intermediate signal is increased.

Optionally, the eleventh switch tube 131 is an enhancement PMOS tube.

IN some embodiments, the size of the second switch tube 1111 is much larger than that of the eleventh switch tube 131, when the level of the input signal IN rises, the second switch tube 1111 is turned on to pull the level of the intermediate signal down to a low level immediately, and the output signal OUT rises to a high level, so that the latency of turning off the pull-up switch tube IN the conventional cross-coupled level shifter circuit is not required, and the response of the output signal OUT is faster.

In some embodiments, in the signal holding state of the level shifter circuit, the seventh switching tube 1131, the eighth switching tube 1132 and the eleventh switching tube 131 function to hold the level of the third intermediate node C and the high level state of the intermediate signal, and the seventh switching tube 1131, the eighth switching tube 1132 and the eleventh switching tube 131 have small sizes, and only need to provide a weak pull-up current in the on state; in the signal change process of the level shift circuit, the pull-down current of the third intermediate node C is provided by the third switching tube 1122 when being turned on, the pull-up current and the pull-down current of the intermediate signal are mainly provided by the fourth switching tube 1123 and the second switching tube 1111 when being turned on, and the second switching tube 1111, the third switching tube 1122 and the fourth switching tube 1123 have larger sizes, so that the response time of the signal can be shortened.

In some embodiments, as shown in fig. 11, the level shift circuit according to the embodiment of the present application may further include: the module 140 is reset.

The first end 140a of the reset module 140 is configured to receive a reset signal RST, the second end 140b of the reset module 140 is connected to the second end 120b of the signal output module 120, the third end 140c of the reset module 140 is grounded, and the reset module 140 is configured to set the second end 120b of the output module 120 to a reset level after receiving the reset signal RST.

In some embodiments, as shown in fig. 12, the reset module 140 includes a first switching tube 141. The first end 141a of the first switch tube 141 is used for receiving the reset signal RST, the second end 141b of the first switch tube 141 is grounded, and the third end 141c of the first switch tube 141 is connected to the second end 120b of the signal output module 120.

When the reset signal RST is not at a high level, the first switching tube 141 does not affect signal changes in the circuit. Optionally, the first switch tube 141 is an enhancement NMOS tube.

As shown in fig. 13, the embodiment of the present application provides a schematic structural diagram of another level shifter 100. In this embodiment, the level shift circuit 100 includes: a signal input module 110, a signal output module 120, a positive feedback module 130 and a reset module 140.

In an embodiment of the present application, the signal input module 110 includes a first unit 111, a second unit 112, and a third unit 113.

The first unit 111 includes a second switch tube 1111. The second switch 1111 is an enhancement NMOS.

The second unit 112 includes a third switching tube 1122, a fourth switching tube 1123, a fifth switching tube 11211 and a sixth switching tube 11212. The third switch tube 1122 is an enhancement type NMOS tube, the fourth switch tube 1123 is an enhancement type PMOS tube, the fifth switch tube 11211 is an enhancement type PMOS tube, and the sixth switch tube 11212 is an enhancement type NMOS tube.

The third unit 113 includes a seventh switching tube 1131 and an eighth switching tube 1132. The seventh switch tube 1131 is an enhanced PMOS tube, and the eighth switch tube 1132 is an enhanced PMOS tube.

The signal output module 120 includes a ninth switching tube 1211 and a tenth switching tube 1212. The ninth switch tube 1211 is an enhancement NMOS tube, and the tenth switch tube 1212 is an enhancement PMOS tube.

The positive feedback module 130 includes an eleventh switching tube 131. The eleventh switch tube 131 is an enhancement PMOS tube.

The reset module 140 includes a first switching tube 141. The first switch tube 141 is an enhancement NMOS tube.

In the embodiment of the present application, the first reference voltage V1 is 1.8V, and the second reference voltage V2 is 1V. When the input signal IN is high, the corresponding voltage is 1V, and when the input signal IN is low, the corresponding voltage is 0V. When the output signal OUT is at a high level, the corresponding voltage is 1.8V, and when the output signal OUT is at a low level, the corresponding voltage is 0V.

The operation of the level shifter 100 according to the embodiment of the present application will be described in detail below.

When the reset signal RST is at a high level, the circuit is in a reset state, the eleventh switch tube 131 is turned on, and the third terminal (drain) of the first switch tube 141 is set to a low level, so the output signal OUT is reset to a low level. At this time, the seventh switch 1131 is conducted with the eleventh switch 131, so the third terminal (drain) of the seventh switch 1131 is set to high level. The level shift circuit 100 of the embodiment of the present application has no quiescent current in the reset state.

When the reset signal RST is at a low level, the level shift circuit 100 of the embodiment of the present application operates normally.

When the input signal IN is static and remains low, the second switch 1111 is turned off, the eleventh switch 131 is turned on, so the intermediate signal is set to high, the fifth switch 11211 is turned off, the sixth switch 11212 is turned on, so the third terminal (drain) of the sixth switch 11212 is set to low, and the third switch 1122 is turned off. Since the seventh switching tube 1131 is turned on, the third intermediate node C is set to a high level, so that the tenth switching tube 1212 is turned off, and the ninth switching tube 1211 is turned on. Since the second terminal (source) of the ninth switching tube 1211 is grounded, the output signal OUT is maintained at a low level.

When the input signal IN is static and the input signal IN is kept at a high level, the second switching tube 1111 is turned on, so the middle signal is set to a low level, then the ninth switching tube 1211 is turned off and the tenth switching tube 1212 is turned on, so the third terminal (drain) of the ninth switching tube 1211 is set to a high level, i.e. the output signal OUT is kept at a high level.

When the input signal IN is static, the seventh switching tube 1131, the eighth switching tube 1132 and the eleventh switching tube 131 function to maintain the high level state of the intermediate signal and the third intermediate node C, and the seventh switching tube 1131, the eighth switching tube 1132 and the eleventh switching tube 131 have small sizes, so that only a weak pull-up current needs to be provided IN the on state.

When the input signal IN is dynamic, the second switch tube 1111 is turned on from off to provide a pull-down path for the first intermediate node a while the eleventh switch tube 131 is initially IN an on state but only provides a weak pull-up current, so that the level of the intermediate signal is lowered from high to low. Since the first intermediate node a goes low, the ninth switching tube 1211 turns off and the tenth switching tube 1212 turns on, so that the output signal OUT rises in level.

And the first end (gate) of the eleventh switch tube 131 is connected to the second end 120b of the signal output module 120, and the eleventh switch tube 131 is gradually turned off under the action of the output signal OUT, so that the current flowing to the first intermediate node a by the eleventh switch tube 131 gradually decreases, which also accelerates the level decrease of the intermediate signal, and the level rising speed of the output signal OUT is also accelerated until the output signal OUT transitions to a high level.

When the input signal IN is dynamic, the second switch tube 1111 is turned off from the on state IN the process of the input signal IN decreasing from the high level to the low level. In some embodiments, the size of the third switching tube 1122 may be set to be much larger than that of the eighth switching tube 1132, and when the third switching tube 1122 is turned from off to on, the level of the third intermediate node C rapidly drops to a low level, so that the fourth switching tube 1123 is turned on. The fourth switch tube 1123 is turned on to connect the first intermediate node a to the path of the first reference voltage V1, so that the level of the intermediate signal rises, and the level of the output signal OUT falls.

Since the first end (gate) of the eleventh switch tube 131 is connected to the second end 120b of the signal output module 120, under the action of the output signal OUT, the eleventh switch tube 131 is turned from off to on, so as to increase the current flowing from the eleventh switch tube 131 to the first intermediate node a, thereby increasing the level-up speed of the intermediate signal, and increasing the level-down speed of the output signal OUT until the output signal OUT is converted to a low level.

And since the level of the intermediate signal rises, the fifth switching tube 11211 is turned off and the sixth switching tube 11212 is turned on, so that the level of the second intermediate node B falls to a low level, and the third switching tube 1122 is finally turned off.

Fig. 14 shows a transient simulation waveform of the level shift circuit 100 IN the embodiment of the present application, a frequency of an input signal IN is 1GHz, and as can be seen from fig. 14, a delay time of level shift is less than 90ps (picoseconds), so that the level shift circuit 100 IN the embodiment of the present application can effectively shorten a response time of a change of an output signal OUT, and improve a speed of level shift.

As shown in fig. 15, an integrated circuit 200 is further provided in the present embodiment, where the integrated circuit 200 includes the level shift circuit 100.

The embodiment of the present application further provides an electronic device 300, as shown in fig. 16, the electronic device 300 includes a housing 310 and the level shift circuit 100 described above. Alternatively, as shown in fig. 17, the electronic device 300 includes the housing 310 and the integrated circuit 200 described above.

Alternatively, the electronic device may be a mobile phone, a notebook computer, a tablet computer, or the like.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims (15)

1. A level shift circuit, comprising:

a first end of the signal input module is connected to a first reference voltage, a second end of the signal input module is grounded, a third end of the signal input module is used for receiving an input signal, and a fourth end of the signal input module is connected to a first intermediate node; the signal input module is used for generating an intermediate signal according to the input signal and transmitting the intermediate signal to a first intermediate node;

a first end of the signal output module is connected to the first intermediate node, a second end of the signal output module is used for transmitting an output signal, a third end of the signal output module is connected to the first reference voltage, and a fourth end of the signal output module is grounded; the signal output module is configured to generate the output signal according to the intermediate signal of the first intermediate node;

a first end of the positive feedback module is connected to the first intermediate node, a second end of the positive feedback module is connected to the first reference voltage, and a third end of the positive feedback module is connected to the second end of the signal output module; the positive feedback module is used for adjusting the level value of the intermediate signal of the signal input module according to the output signal in the conversion process of converting the level value of the output signal from an initial level to a target level, so that the conversion speed in the conversion process is accelerated;

wherein the initial level is a high level or a low level, and when the initial level is the high level, the target level is the low level; when the initial level is a low level, the target level is a high level.

2. The level shift circuit of claim 1, further comprising: the reset module, the first end of reset module is used for receiving reset signal, the second end of reset module connect in the second end of signal output module, the third end ground connection of reset module, reset module is used for receiving behind the reset signal with the second end of output module is reset level.

3. The level shift circuit of claim 2, wherein the reset module comprises: the first end of the first switch tube is used for receiving the reset signal, the second end of the first switch tube is grounded, and the third end of the first switch tube is connected to the output signal end.

4. The level shift circuit according to claim 1, wherein the signal input module comprises a first unit and a second unit;

the first end of the first unit is connected to the first end of the signal input module, the second end of the first unit is connected to the first intermediate node, and the third end of the first unit is grounded; the first end of the first unit receives the input signal, generates the intermediate signal according to the input signal and outputs the intermediate signal through the second end of the first unit when the input signal is at a high level;

a first end of the second unit is connected to a first end of the signal input module, a second end of the second unit is connected to the first intermediate node, and a third end of the second unit is connected to the first reference voltage; the first end of the second unit receives the input signal, generates the intermediate signal according to the input signal and outputs the intermediate signal through the second end of the second unit when the input signal is at a low level.

5. The circuit of claim 4, wherein the first unit comprises a second switch tube, a first end of the second switch tube is connected to the first end of the signal input module, a second end of the second switch tube is grounded, and a third end of the second switch tube is connected to the first intermediate node.

6. The level shift circuit of claim 4, wherein:

the second unit comprises a first phase inverter, a third switching tube and a fourth switching tube;

a first end of the first inverter is connected to a second intermediate node, and a second end of the first inverter is connected to the first intermediate node;

the first end of the third switching tube is connected to the second middle node, the second end of the third switching tube is connected to the first end of the signal input module, and the third end of the third switching tube is connected to the third middle node;

the first end of the fourth switch tube is connected to the third middle node, the second end of the fourth switch tube is connected to the first reference voltage, and the third end of the fourth switch tube is connected to the first middle node.

7. The level shift circuit of claim 6, wherein:

the first phase inverter comprises a fifth switching tube and a sixth switching tube;

a first end of the fifth switching tube is connected to the first intermediate node, a second end of the fifth switching tube is connected to a second reference voltage, and a third end of the fifth switching tube is connected to the second intermediate node;

the first end of the sixth switching tube is connected to the first intermediate node, the second end of the sixth switching tube is grounded, and the third end of the sixth switching tube is connected to the second intermediate node.

8. The level shift circuit of claim 7,

the first reference voltage is higher than the second reference voltage.

9. The circuit of claim 4, wherein the signal input module further comprises a third unit, a first terminal of the third unit is connected to the first reference voltage, a second terminal of the third unit is connected to the first intermediate node, a third terminal of the third unit is connected to the third intermediate node, and a fourth terminal of the third unit is connected to the second terminal of the signal output module; the third unit is configured to maintain the level of the third intermediate node in a high level state when the input signal of the first end of the signal input module is static.

10. The level shift circuit of claim 9, wherein:

the third unit comprises a seventh switching tube and an eighth switching tube;

a first end of the seventh switching tube is connected to the second end of the signal output module, a second end of the seventh switching tube is connected to the first reference voltage, and a third end of the seventh switching tube is connected to the third intermediate node;

a first end of the eighth switching tube is connected to the first intermediate node, a second end of the eighth switching tube is connected to the first reference voltage, and a third end of the eighth switching tube is connected to the third intermediate node.

11. The circuit according to any of claims 1 to 10, wherein the signal output module comprises a second inverter, a first terminal of the second inverter is connected to the first intermediate node, and a second terminal of the second inverter is connected to the second terminal of the signal output module.

12. The circuit of claim 11, wherein the second inverter comprises a ninth switch and a tenth switch;

a first end of the ninth switching tube is connected to the first intermediate node, a second end of the ninth switching tube is grounded, and a third end of the ninth switching tube is connected to the second end of the signal output module;

a first end of the tenth switching tube is connected to the first intermediate node, a second end of the tenth switching tube is connected to the first reference voltage, and a third end of the tenth switching tube is connected to the second end of the signal output module.

13. The circuit according to claim 1, wherein the positive feedback module comprises an eleventh switch tube;

a first end of the eleventh switching tube is connected to the second end of the signal output module, a second end of the eleventh switching tube is connected to a first reference voltage, and a third end of the eleventh switching tube is connected to the first intermediate node.

14. An integrated circuit comprising the level shifter circuit of any one of claims 1 to 13.

15. An electronic device comprising a housing and the level shifter circuit of any one of claims 1-13 or the integrated circuit of claim 14 disposed within the housing.

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