CN117748955B - High-speed low-power consumption CMOS voltage conversion circuit - Google Patents
High-speed low-power consumption CMOS voltage conversion circuit Download PDFInfo
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- CN117748955B CN117748955B CN202410187085.2A CN202410187085A CN117748955B CN 117748955 B CN117748955 B CN 117748955B CN 202410187085 A CN202410187085 A CN 202410187085A CN 117748955 B CN117748955 B CN 117748955B
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Abstract
The invention discloses a high-speed low-power consumption CMOS voltage conversion circuit, which belongs to the field of integrated circuits and comprises PMOS (P-channel metal oxide semiconductor) transistors MP 1-MP 4, NMOS (N-channel metal oxide semiconductor) transistors MN 1-MN 6, an inverter INV and a capacitor C; the PMOS transistors MP 1-MP 2 and the NMOS transistors MN 1-MN 2 are IO MOS devices; the PMOS transistors MP 3-MP 4 and the NMOS transistors MN 3-MN 6 are core MOS devices. Simulations based on T22ULP show that the circuit of the invention can reach a clock frequency of 12.5G even with a voltage core=0.8v, io=1.8v, which is far from achievable with conventional circuits. And the power consumption at the same speed also shows that the invention is far lower than the existing circuit. The circuit is completely compatible with the CMOS process, does not increase any MASK or area, and therefore, the circuit perfectly combines high speed, low power consumption and low cost. The voltage and IO voltage difference of the core in the prior process is larger and larger, and the requirements on speed and power consumption are higher and higher, so that the scheme of the invention has great use value.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-speed low-power consumption CMOS voltage conversion circuit.
Background
The CMOS circuit always has low voltage and high voltage power domains, and signal communication between different power domains involves voltage conversion, so the voltage conversion circuit is a basic circuit. As shown in FIG. 1, the conventional voltage conversion circuit has a core circuit in which two IO PMOS are connected to form a latch structure, and driven by two IO NMOS. The circuit is driven entirely by the upper PMOS when the output is 1, and by the lower NMOS when the output is 0.
The traditional circuit has the defects of high power consumption and low speed, and the reasons are as follows: when the circuit is turned over, the competition between NMOS and PMOS exists, namely the pull-down capability of the NMOS is far greater than that of the PMOS. Because the core voltage is far lower than the IO voltage, and the core voltage faces the IO NMOS, the overdrive voltage of the NMOS is far lower than that of the PMOS, and the IO NMOS must be designed to be particularly large in size to compete for the PMOS; while an excessively large NMOS size is a large load for the previous circuits, thus severely affecting speed while increasing power consumption.
The core voltage and IO voltage in the prior process are more and more different, and the speed of the current circuit is higher and higher. Therefore, the speed and power consumption bottlenecks faced by the conventional circuit are larger and larger, and cannot meet the requirements. Therefore, a new circuit is urgently needed to provide high-speed conversion and reduce power consumption while achieving high speed, so as to adapt to more practical application scenes.
Disclosure of Invention
The invention aims to provide a high-speed low-power consumption CMOS voltage conversion circuit to solve the problems in the background technology.
In order to solve the technical problems, the invention provides a high-speed low-power consumption CMOS voltage conversion circuit, which comprises PMOS transistors MP 1-MP 4 and NMOS transistors MN 1-MN 6;
The source end of the PMOS tube MP1 and the source end of the PMOS tube MP2 are both connected with the MVDDQ, the drain end of the PMOS tube MP1 is simultaneously connected with the gate end of the PMOS tube MP2 and the drain end of the NMOS tube MN1, and the drain end of the PMOS tube MP2 is simultaneously connected with the gate end of the PMOS tube MP1 and the drain end of the NMOS tube MN 2;
The gate end of the NMOS tube MN1 and the gate end of the NMOS tube MN2 are both connected with the MVDDQ, the source end of the NMOS tube MN1 is connected with the drain end of the NMOS tube MN3, the source end of the NMOS tube MN3 is simultaneously connected with the drain end of the PMOS tube MP3 and the drain end of the NMOS tube MN5, the source end of the PMOS tube MP3 is connected with the VDD, the gate end of the NMOS tube MN5 is connected with the signal DPL, the source end of the NMOS tube MN5 is connected with the MVSS, and the gate end of the NMOS tube MN3 is connected with the DPL;
the source end of the NMOS tube MN2 is connected with the drain end of the NMOS tube MN4, the source end of the NMOS tube MN4 is connected with the drain end of the PMOS tube MP4 and the drain end of the NMOS tube MN6 at the same time, the source end of the PMOS tube MP4 is connected with the VDD, the gate is connected with the signal DNL, the source end of the NMOS tube MN6 is connected with the MVSS, and the gate is connected with the DNL; the gate end of the NMOS transistor MN3 and the gate end of the NMOS transistor MN4 are both connected with VDD.
In one embodiment, the device further comprises an inverter INV and a capacitor C, wherein the input end of the inverter INV is connected with the drain end of the PMOS transistor MP2, and the output end of the inverter INV is connected between the source end of the NMOS transistor MN1 and the drain end of the NMOS transistor MN3 by the capacitor C.
In one embodiment, the PMOS transistors MP 1-MP 2 and the NMOS transistors MN 1-MN 2 are IO MOS devices; the PMOS transistors MP 3-MP 4 and the NMOS transistors MN 3-MN 6 are core MOS devices; wherein MVDDQ and VDD represent the IO voltage and core voltage, respectively.
In one embodiment, the NMOS transistors MN3 and MN4 are pull-down transistors.
In one embodiment, the capacitor C is a feedforward capacitor, and the capacitance is 50fF.
In one embodiment, the capacitance C is implemented with MOM.
The simulation based on T22ULP shows that the circuit can reach 12.5G clock frequency even under the conditions of voltage core=0.8V and IO=1.8V, which is far from the traditional circuit. And the power consumption at the same speed also shows that the invention is far lower than the existing circuit. The circuit is completely compatible with the CMOS process, does not increase any MASK or area, and therefore, the circuit perfectly combines high speed, low power consumption and low cost. The voltage and IO voltage difference of the core in the prior process is larger and larger, and the requirements on speed and power consumption are higher and higher, so that the scheme of the invention has great use value.
Drawings
Fig. 1 is a schematic diagram of a conventional voltage conversion circuit.
Fig. 2 is a schematic diagram of a high-speed low-power consumption CMOS voltage conversion circuit according to the present invention.
Fig. 3 is a voltage schematic diagram of the input signal period 80p, detect point.
Fig. 4 is a voltage schematic diagram of input signal periods 80p, drive points.
Fig. 5 is a voltage waveform diagram of the input signal period 80p, detect2 and drive2 points of the conventional circuit.
Fig. 6 is a schematic diagram of the current waveform when the signal 400p is input.
Detailed Description
The following describes the high-speed low-power consumption CMOS voltage conversion circuit according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a high-speed low-power consumption CMOS voltage conversion circuit, which has a structure shown in figure 2 and comprises PMOS (P-channel metal oxide semiconductor) transistors MP 1-MP 4, NMOS (N-channel metal oxide semiconductor) transistors MN 1-MN 6, an inverter INV and a capacitor C; the source end of the PMOS tube MP1 and the source end of the PMOS tube MP2 are both connected with the MVDDQ, the drain end of the PMOS tube MP1 is simultaneously connected with the gate end of the PMOS tube MP2 and the drain end of the NMOS tube MN1, and the drain end of the PMOS tube MP2 is simultaneously connected with the gate end of the PMOS tube MP1 and the drain end of the NMOS tube MN 2; the gate end of the NMOS tube MN1 and the gate end of the NMOS tube MN2 are both connected with the MVDDQ, the source end of the NMOS tube MN1 is connected with the drain end of the NMOS tube MN3, the source end of the NMOS tube MN3 is simultaneously connected with the drain end of the PMOS tube MP3 and the drain end of the NMOS tube MN5, the source end of the PMOS tube MP3 is connected with the VDD, the gate end of the NMOS tube MN5 is connected with the signal DPL, the source end of the NMOS tube MN5 is connected with the MVSS, and the gate end of the NMOS tube MN3 is connected with the DPL; the source end of the NMOS tube MN2 is connected with the drain end of the NMOS tube MN4, the source end of the NMOS tube MN4 is connected with the drain end of the PMOS tube MP4 and the drain end of the NMOS tube MN6 at the same time, the source end of the PMOS tube MP4 is connected with the VDD, the gate is connected with the signal DNL, the source end of the NMOS tube MN6 is connected with the MVSS, and the gate is connected with the DNL; the gate end of the NMOS tube MN3 and the gate end of the NMOS tube MN4 are connected with VDD; the input end of the inverter INV is connected with the drain end of the PMOS tube MP2, and the output end of the inverter INV is connected between the source end of the NMOS tube MN1 and the drain end of the NMOS tube MN3 by a capacitor C.
PMOS transistors MP 1-MP 2 and NMOS transistors MN 1-MN 2 are IO MOS devices, and PMOS transistors MP 3-MP 4 and NMOS transistors MN 3-MN 6 are core MOS devices. MVDDQ and VDD represent the IO voltage and core voltage, respectively; the signal DPL and the signal DNL are opposite input signals from the core MOS device. The upper part of the circuit is connected into a latch structure by two IO PMOS as the traditional circuit, and the difference is that each IO PMOS is connected with one IO NMOS and core NMOS in series, namely a PMOS tube MP1 is connected with an NMOS tube MN1 and an NMOS tube MN3 in series, and a PMOS tube MP2 is connected with an NMOS tube MN2 and an NMOS tube MN4 in series. The gate terminals of the IO NMOS and the core NMOS in series are connected to IO voltage MVDDQ and core voltage VDD, respectively, as shown in FIG. 2. The inverter INV of the core device provides a differential input signal, and on the non-IO PMOS driving transistor side, the output of the inverter INV is connected to N point with a capacitor, that is, the N point is located between the source end of the NMOS transistor MN1 and the drain end of the NMOS transistor MN 3.
In order to increase the speed and reduce the power consumption, the IO NMOS (NMOS transistors MN1 and MN 2) cannot be used as the pull-down driving transistor, but the core NMOS (NMOS transistors MN3 and MN 4) is used as the pull-down driving transistor. However, the core NMOS cannot bear IO voltage and needs to be isolated, so that an IO NMOS and a core NMOS are connected in series under the IO PMOS in the circuit, and the gate ends of the IO NMOS and the core NMOS are respectively connected to the IO voltage MVDDQ and the core voltage VDD, so that the maximum voltage transmitted to the core inverter INV by the high voltage is VDD-vth, wherein vth is the threshold voltage of the core MOS device, and the reliability problem is eliminated.
The circuit is switched quickly, and in fact, the drive point in fig. 2 is switched quickly; wherein the drive point is the point of the IO PMOS drive inverter INV. The drive point changes from 1 to 0, which on the one hand requires an increase in the pull-down capability of the core NMOS, and on the other hand it is desirable that the detect point changes rapidly to 1, thus reducing the pull-up effect on pull-down. The drive point changes from 0 to 1, requiring the detect point to change rapidly to 0. The detect point and drive point can change rapidly depending on two points: the core signal can be driven by an inverter INV instead of just NMOS, and a small capacitor C as shown in fig. 2 is added to the detect point side.
With coreMOS devices MN3 and MN4 as NMOS isolation tubes, the core signal can now be driven with inverter INV instead of just NMOS. Then in the process of the detect point and the drive point becoming 1, the voltage can be pulled up directly to the voltage of VDD-vth in the start stage corePMOS (PMOS transistors MP3 and MP 4). However, due to the limitation of the core NMOS threshold voltage, the detect point can only be quickly raised to the voltage of VDD-vth, so that after the capacitor shown in FIG. 2 is added in the circuit, the voltage of the detect point can be quickly raised to VDD, and the speed of changing the driver point to 0 is greatly accelerated. The capacitance has two points to be noted: one end of the capacitor cannot be connected to the detect point, otherwise, the capacitor becomes a load in the process that the detect point rises from the core voltage to the IO voltage, so that the PMOS tubes MP1 and MP2 are turned off too slowly, and power consumption is increased. The highest voltage of the point is IO voltage minus the threshold voltage of the IO NMOS, and the difference between the voltage and core voltage is small because the substrate effect threshold voltage is very high, so the influence on turning off the PMOS transistors MP1 and MP2 is very small. Secondly, the side of the drive point cannot put a similar feed-forward capacitor because this affects the time that the drive point rises from VDD to MVDDQ. Since the capacitance of the MOS is very small, the feedforward capacitor C only needs 50fF, and can be realized by MOM.
Only one side of the voltage conversion circuit needs to drive the following inverter INV, so that two sides of the circuit can be asymmetrically designed, and the non-driving side can use a small IO PMOS, so that the size of the inverter INV can be reduced, and the power consumption is reduced. However, the asymmetric design space of the traditional circuit is much smaller, because the pull-up is completely from 0 to IO voltage by the IO PMOS, and the existing IO PMOS only needs from core voltage to IO voltage, the space is much smaller, so that the corresponding IO PMOS is smaller in size, and more space is reserved for asymmetric design.
Simulation results of the present invention
The invention takes the simulation waveform of the circuit of the T22ULP technology as the data support. The core voltage is 0.8V, the IO voltage is 1.8V, the pch_mac/nch_mac is used as the core device, and the pch_18_mac/nch_18_mac is used as the IO device. The simulation was performed at TT/25 ℃. The output load of the circuit was 30fF.
FIG. 3 shows the voltage at the detect point of the input signal period 80p, yellow with capacitance, and red without capacitance; FIG. 4 is a plot of the input signal period 80p, drive point voltage, yellow with capacitance, and red without capacitance; FIG. 5 is a voltage waveform diagram of the detect2 and drive2 points of the conventional circuit during an input signal period 80 p; fig. 6 shows a current waveform of an input signal 400p, yellow is the present invention, and red is a conventional circuit. As can be seen from the simulation waveforms of FIGS. 3-6, the speed of the circuit of the present invention is much higher than that of the conventional circuit, while the power consumption of the circuit of the present invention is much lower than that of the conventional circuit at the same speed.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (5)
1. A high-speed low-power consumption CMOS voltage conversion circuit is characterized by comprising PMOS transistors MP 1-MP 4 and NMOS transistors MN 1-MN 6;
The source end of the PMOS tube MP1 and the source end of the PMOS tube MP2 are both connected with the MVDDQ, the drain end of the PMOS tube MP1 is simultaneously connected with the gate end of the PMOS tube MP2 and the drain end of the NMOS tube MN1, and the drain end of the PMOS tube MP2 is simultaneously connected with the gate end of the PMOS tube MP1 and the drain end of the NMOS tube MN 2;
The gate end of the NMOS tube MN1 and the gate end of the NMOS tube MN2 are both connected with the MVDDQ, the source end of the NMOS tube MN1 is connected with the drain end of the NMOS tube MN3, the source end of the NMOS tube MN3 is simultaneously connected with the drain end of the PMOS tube MP3 and the drain end of the NMOS tube MN5, the source end of the PMOS tube MP3 is connected with the VDD, the gate end of the NMOS tube MN5 is connected with the signal DPL, the source end of the NMOS tube MN5 is connected with the MVSS, and the gate end of the NMOS tube MN3 is connected with the DPL;
The source end of the NMOS tube MN2 is connected with the drain end of the NMOS tube MN4, the source end of the NMOS tube MN4 is connected with the drain end of the PMOS tube MP4 and the drain end of the NMOS tube MN6 at the same time, the source end of the PMOS tube MP4 is connected with the VDD, the gate is connected with the signal DNL, the source end of the NMOS tube MN6 is connected with the MVSS, and the gate is connected with the DNL; the gate end of the NMOS tube MN3 and the gate end of the NMOS tube MN4 are connected with VDD; wherein, the PMOS transistors MP 1-MP 2 and the NMOS transistors MN 1-MN 2 are IO MOS devices; PMOS transistors MP 3-MP 4 and NMOS transistors MN 3-MN 6 are core MOS devices, MVDDQ and VDD respectively represent IO voltage and core voltage; the signal DPL and the signal DNL are opposite input signals from the core MOS device.
2. The high-speed low-power consumption CMOS voltage converting circuit according to claim 1, further comprising an inverter INV and a capacitor C, wherein the input end of the inverter INV is connected to the drain end of the PMOS transistor MP2, and the output end is connected between the source end of the NMOS transistor MN1 and the drain end of the NMOS transistor MN3 by the capacitor C.
3. The high-speed low-power CMOS voltage converter circuit according to claim 1, wherein said NMOS transistors MN3 and MN4 are pull-down transistors.
4. The high-speed low-power consumption CMOS voltage converting circuit according to claim 2, wherein said capacitor C is a feedforward capacitor having a capacitance of 50fF.
5. The high-speed low-power consumption CMOS voltage converter circuit according to claim 4, wherein said capacitor C is implemented with MOM.
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| CN107528579A (en) * | 2017-08-28 | 2017-12-29 | 天津大学 | At a high speed, low-power consumption level shift circuit |
| US10164524B1 (en) * | 2016-05-31 | 2018-12-25 | Cadence Design Systems, Inc. | Methods and devices for charge pump level translation in high-speed memory drivers |
| WO2019114031A1 (en) * | 2017-12-12 | 2019-06-20 | 清华四川能源互联网研究院 | Low-power-consumption constant on-time timing circuit design method and timing circuit |
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| US7250795B2 (en) * | 2005-03-29 | 2007-07-31 | Promos Technologies Pte. Ltd. | High-speed, low-power input buffer for integrated circuit devices |
| WO2013095649A1 (en) * | 2011-12-23 | 2013-06-27 | Intel Corporation | Apparatus and system for generating a signal with phase angle configuration |
| US11658572B2 (en) * | 2020-06-11 | 2023-05-23 | Intel Corporation | Power field effect transistor topology and bootstrap circuit for inverting buck-boost DC-DC converter |
| US11632101B1 (en) * | 2021-09-30 | 2023-04-18 | Bitmain Development Inc. | Voltage level shifter applicable to very-low voltages |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10164524B1 (en) * | 2016-05-31 | 2018-12-25 | Cadence Design Systems, Inc. | Methods and devices for charge pump level translation in high-speed memory drivers |
| CN107528579A (en) * | 2017-08-28 | 2017-12-29 | 天津大学 | At a high speed, low-power consumption level shift circuit |
| WO2019114031A1 (en) * | 2017-12-12 | 2019-06-20 | 清华四川能源互联网研究院 | Low-power-consumption constant on-time timing circuit design method and timing circuit |
| CN109921769A (en) * | 2019-03-12 | 2019-06-21 | 中国电子科技集团公司第五十八研究所 | A kind of high-speed low-power-consumption level displacement circuit |
| EP3907866A1 (en) * | 2020-05-09 | 2021-11-10 | INTEL Corporation | Accurate load current sensing apparatus and method |
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