TW202002516A - Dynamic flip flop and electronic device - Google Patents

Abstract

A dynamic flip flop is provided. The dynamic flip flop comprises a transmission gate, a first inverter, a second inverter, a pull-up transistor and a pull-down transistor. The pull-up transistor and the pull-down transistor constitute a feedback inverter, and compared to the first inverter that is a tri-state inverter, the feedback inverter is configured as a week keeper circuit. Therefore, the dynamic flip flop can use the tri-state inverter to capture data to reduce the leakage currents. In addition, The dynamic flip flop can also use the week keeper circuit to store data to avoid floating node to drive output.

Description

Dynamic flip-flop and electronic equipment

The present invention relates to a flip flop (FF), and particularly to a dynamic flip flop and electronic equipment.

Generally, dynamic flip-flops can achieve the logic function function with a smaller number of transistors. Therefore, compared with static flip flops, the circuit layout area of dynamic flip-flops is smaller, and the production is reduced jointly. cost. For example, please refer to FIG. 1, which is a circuit schematic diagram of a conventional dynamic flip-flop. The dynamic flip-flop 1 includes a transmission gate 101, an inverter 102, a transmission gate 103, and an inverter 104. First, the transmission gate 101 is used to receive the data signal D, and output the data signal D to the inverter 102 according to the clock signal CLKB and its inverted clock signal CP. The inverter 102 is used to invert the data signal D and output the inverted data signal D.

Next, the transmission gate 103 is used to receive the inverted data signal D, and output the inverted data signal D to the inverter 104 according to the clock signal CP and the clock signal CLKB. The inverter 104 is used to invert the inverted data signal D and output the data signal Q. It can be seen from the above that because the input signal load is reduced, the dynamic flip-flop 1 of this type of architecture is more suitable for high-speed operating environments, but its disadvantage is that there will be glitch and leakage currents The problem is that the wrong data signal Q is output, or even storage loss occurs. Therefore, it is necessary to design a dynamic flip-flop that can solve the above-mentioned conventional problems while retaining the advantages of the original area efficiency.

The embodiment of the invention provides a dynamic flip-flop. The dynamic flip-flop has an input end and an output end, and it includes a transmission gate, a first inverter, a second inverter, a pull-up transistor and a pull-down transistor ). The transmission gate is coupled to the input terminal and used to receive the first data signal and output the first data signal to the first node according to the first clock signal and its inverted second clock signal. The first inverter is coupled to the transmission gate via the first node, and is used to invert the first data signal and output the inverted first data signal to the second node. The second inverter is coupled between the second node and the output terminal, and is used to invert the inverted first data signal to generate a second data signal, and output the second data signal to the output terminal. The pull-up transistor is coupled between the second node and the power supply voltage, and is used to pull up the voltage of the second node to the power supply voltage. The pull-down transistor is coupled between the second node and the ground voltage, and is used to pull down the voltage of the second node to the ground voltage.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and drawings of the present invention, but these descriptions and the drawings are only used to illustrate the present invention, not the rights of the present invention Any restrictions on the scope.

In the following, the invention will be described in detail by illustrating various embodiments of the invention. However, the inventive concept may be embodied in many different forms and should not be interpreted as being limited to the exemplary embodiments set forth herein. In addition, the same reference numerals may be used to represent similar elements in the drawings.

In detail, the dynamic flip-flop provided by the embodiments of the present invention may be applicable to any electronic device with a computing function, such as a smart phone, game machine, router, or tablet computer. In a word, the present invention does not limit the specific implementation of the dynamic flip-flop included in the embodiment of the electronic device. Those with ordinary knowledge in the technical field should be able to carry out related designs based on actual needs or applications. Please refer to FIG. 2, which is a circuit schematic diagram of a dynamic flip-flop provided by an embodiment of the present invention. The dynamic flip-flop 2 mainly has an input terminal IN and an output terminal OUT, and it includes a transmission gate 201, an inverter 202, an inverter 203, a pull-up transistor 204 and a pull-down transistor 205. In this embodiment, the transmission gate 201 is coupled to the input terminal IN, and is used to receive the data signal D, and output the data signal D to the node T1 according to the clock signal CLKB and its inverted clock signal CP. The inverter 202 is coupled to the transmission gate 201 via the node T1, and is used to invert the data signal D and output the inverted data signal D to the node T2. It can be understood that the "node T1" in this embodiment can refer to the node where the transmission gate 201 and the inverter 202 are connected, and the "node T2" refers to the inverter 202 and the inverter 203 Connected nodes.

In addition, the inverter 202 is a first inverter, and the inverter 203 is a second inverter. In this embodiment, the inverter 203 is coupled between the node T2 and the output terminal OUT, and is used to invert the inverted data signal D to generate the data signal Q and output the data signal Q to the output terminal OUT. The pull-up transistor 204 is coupled between the node T2 and the power supply voltage VDD, and is used to pull up the voltage of the node T2 to the power supply voltage VDD and latch the data signal Q. The pull-down transistor 205 is coupled between the node T2 and the ground voltage VSS, and is used to pull down the voltage of the node T2 to the ground voltage VSS and the latch data signal Q. According to the teaching of the above content, those with ordinary knowledge in the technical field should understand that the dynamic flip-flop 2 provided by the embodiment of the present invention adopts a circuit design architecture that is completely different from the conventional dynamic flip-flop 1.

It must be understood that the so-called "clock signal CLKB" refers to the clock signal generated by inverting the original clock signal CLK (not shown), and the so-called "clock signal CP" That is, the clock signal generated by the clock signal CLKB is inverted again. In short, "clock signal CP" is equivalent to the original clock signal CLK. However, the present invention does not limit the specific implementation manners of the clock signal CLKB and the clock signal CP, and those with ordinary knowledge in the technical field should be able to make relevant designs based on actual needs or applications. However, since the principles of the clock signal CLKB and the clock signal CP used in the dynamic flip-flop 2 are already known to those of ordinary skill in the art, the details of the clock signal CLKB and the clock signal CP are described in This will not be repeated here.

Specifically, as shown in FIG. 2, the transmission gate 201 includes an N-type metal-oxide half-field transistor (NMOSFET) N1 and a P-type metal-oxide half-field transistor (PMOSFET) P1 connected in parallel, but the present invention does not The connection relationship and transistor type are limited. In this embodiment, the drain of the N-type MOSFET N1 and the drain of the P-type MOSFET P1 are coupled to the input IN of the dynamic flip-flop 2 via the node T3, N-type The source of the MOS transistor N1 and the source of the P-type MOS transistor P1 are coupled to the node T1 via the node T4, and the gate of the N-type MOS transistor N1 is used for receiving The pulse signal CLKB and the gate of the P-type metal-oxide half field effect transistor P1 are used to receive the clock signal CP. It can be understood that the "node T3" in this embodiment can refer to the node where the drain of the N-type metal-oxide half-field transistor N1 is connected to the drain of the P-type metal-oxide half-field transistor P1, and " The "node T4" refers to a node where the source of the N-type metal-oxide half-field transistor N1 is connected to the source of the P-type metal-oxide half-field transistor P1.

In addition, the inverter 202 includes two P-type metal oxide field effect transistors P2, P3 and two N-type metal oxide field effect transistors N2, N3 connected in series. In this embodiment, the source of the P-type metal oxide semiconductor field P2 is coupled to the power supply voltage VDD, the source of the N-type metal oxide semiconductor field N3 is coupled to the ground voltage VSS, and the P-type metal oxide semiconductor field effect The gate of the transistor P2 and the gate of the N-type MOS transistor N3 are respectively coupled to the node T1 for receiving the data signal D, and the source of the P-type MOS transistor P3 is coupled to The drain of P-type metal-oxide half-field transistor P2, the source of N-type metal-oxide half-field transistor N2 is coupled to the drain of N-type metal-oxide half-field transistor N3, P-type metal-oxide half-field transistor P3 And the drain of N-type MOSFET half N2 are coupled to node T2 via node T5, the gate of P-type MOSFET half P3 is used to receive the clock signal CLKB, N-type gold The gate electrode of the oxygen half field effect transistor N2 is used to receive the clock signal CP. It can be understood that the "node T5" in this embodiment refers to a node where the drain of the P-type metal-oxide-half field-effect transistor P3 is connected to the drain of the N-type metal-oxide-half field-effect transistor N2.

Therefore, compared with the inverter 102 of FIG. 1, the inverter 202 of FIG. 2 increases the circuit design of the P-type metal oxide half-field transistor P3 and the N-type metal oxide half-field transistor N2, and in this embodiment In this case, the inverter 202 can be regarded as a tri-state inverter. In addition, the transmission gate 201 and the inverter 202 of FIG. 2 can also be regarded as a master latch as a whole. According to the teaching of the above, those with ordinary knowledge in the technical field should understand that one of the main spirits of the present invention is to enable the main latch to use the three-state inverter for data extraction to avoid being affected by The impact when the input terminal changes its appearance. In addition, the present invention can use the three-state inverter to replace the output terminal as the main latch, thereby reducing the leakage current problem and keeping the application in a high-speed operating environment.

For example, assuming that the inverter 202 does not have the P-type metal-oxide half-field effect transistor P3 and the N-type metal-oxide half-field effect transistor N2, the inverter 202 is likely to have the power supply voltage VDD to The leakage current between the ground voltage VSS is such that the node T2 is subjected to a leakage attack. Therefore, in this embodiment, the inverter 202 is turned on or off by adding a P-type metal oxide half-field transistor P3 and an N-type metal oxide half-field transistor N2 controlled by the clock signal CLKB and the clock signal CP The current path from the power supply voltage VDD to the ground voltage VSS reduces the leakage impact of the node T2.

It is worth mentioning that, under such a circuit design architecture, the main latch is correspondingly an edge triggered latch (edge triggered latch). However, since the operating principles of P-type metal-oxide half-field transistors P1, P2, P3 and N-type metal-oxide half-field transistors N1, N2, N3 are all well-known to those with ordinary knowledge in the technical field, the relevant The details of the main latch, that is, the transmission gate 201 and the inverter 202 will not be repeated here. It should be noted that the specific implementation of the inverter 202 in FIG. 2 is only an example here, and it is not intended to limit the present invention. For example, please refer to FIG. 3, which is a circuit schematic diagram of a dynamic flip-flop provided by another embodiment of the present invention. Among them, some components in FIG. 3 that are the same as or similar to those in FIG. 2 are marked with the same or similar drawing numbers, so the details will not be detailed here.

In other embodiments, as shown in FIG. 3, the P-type metal-oxide half field effect transistor P3 may be coupled to be close to the power supply voltage VDD, and the N-type metal-oxide half field effect transistor N2 may be coupled to be close to ground. Voltage VSS. That is to say, in the embodiment of FIG. 3, the source of the P-type metal-oxide half field effect transistor P3 is coupled to the power supply voltage VDD, and the source of the N-type metal-oxide half field effect transistor N2 is coupled to the ground voltage VSS, The drain of P-type metal-oxide half-field transistor P3 is coupled to the source of P-type metal-oxide half-field transistor P2, and the drain of N-type metal-oxide half-field transistor N2 is coupled to N-type metal-oxide half-field transistor The source of the crystal N3, the drain of the P-type MOS transistor P2 and the drain of the N-type MOS transistor N3 are coupled to the node T2 via the node T5. It can be understood that the "node T5" in the embodiment of FIG. 3 also refers to the node where the drain of the P-type metal-oxide half-field transistor P2 and the drain of the N-type metal-oxide half-field transistor N3 are connected. In a word, the present invention does not limit the specific implementation of the inverter 202. Those with ordinary knowledge in the technical field should be able to carry out related designs according to actual needs or applications.

In addition, referring back to FIG. 2, the inverter 203 includes a P-type metal-oxide half-field transistor P4 and an N-type metal-oxide half-field transistor N4 connected in series, but the present invention does not use this connection relationship and transistor type Limited. In this embodiment, the source of the P-type metal oxide semiconductor field P4 is coupled to the power supply voltage VDD, the source of the N-type metal oxide semiconductor field N4 is coupled to the ground voltage VSS, and the P-type metal oxide semiconductor field effect The drain of the transistor P4 and the drain of the N-type metal-oxide half-field transistor N4 are coupled to the output terminal OUT via the node T6, the gate of the P-type metal-oxide half-field transistor P4 and the N-type metal-oxide half-field effect The gate of the crystal N4 is coupled to the node T2 via the node T7 for receiving the inverted data signal D. It can be understood that the "node T6" in this embodiment can refer to the node where the drain of the P-type metal-oxide half-field transistor P4 and the drain of the N-type metal-oxide half-field transistor N4 are connected, and " The node T7" refers to the node where the gate of the P-type metal-oxide half-field transistor P4 is connected to the gate of the N-type metal-oxide half-field transistor N4. Since the operation principle of the inverter 203 is also known to those skilled in the art, the details of the inverter 203 will not be repeated here.

On the other hand, as shown in FIG. 2, the pull-up transistor 204 may be a P-type metal-oxide half-field transistor P5, and the pull-down transistor 205 may be an N-type metal-oxide half-field transistor N5, but the present invention does not This transistor type is limited. In this embodiment, the source of the P-type metal oxide semiconductor field P5 is coupled to the power supply voltage VDD, the source of the N-type metal oxide semiconductor field N5 is coupled to the ground voltage VSS, and the P-type metal oxide semiconductor field effect The drain of the transistor P5 and the drain of the N-type metal-oxide half-field transistor N5 are respectively coupled to the node T2, the gate of the P-type metal-oxide half-field transistor P5 and the N-type metal-oxide half-field transistor N5 The gates are respectively coupled to the output terminal OUT for receiving the data signal Q.

That is to say, in this embodiment, the pull-up transistor 204 and the pull-down transistor 205 can be combined to form a feedback inverter 206. It can be understood that the feedback inverter 206 and the inverter 203 of FIG. 2 can also be regarded as a slave latch as a whole, and in this embodiment, compared to the inverter 202, The feedback inverter 206 must be configured as a weak keeper circuit. Specifically, when the next piece of new data is to be written, the inverter 202 and the inverter 206 are prone to data collision at the node T2, so the signal output capability of the inverter 202 must be higher than that of the inverter 206 The signal output capability is relatively strong, so that the data on node T2 can be forcibly updated. Therefore, compared to the inverter 202, the inverter 206 must be configured as a weak hold circuit.

Generally speaking, it is common to design strong threshold circuits and channel lengths to distinguish between strong holding circuits and weak holding circuits. Therefore, if the inverter 202 is a short channel device (short channel device), the feedback inverter 206 of this embodiment should be relatively designed as a long channel device (long channel device); or If the inverter 202 is a low threshold voltage element, the feedback inverter 206 of this embodiment should be relatively designed as a high threshold voltage element. In a word, the present invention does not limit the specific implementation of the strong/weak holding circuit. Those with ordinary knowledge in the technical field should be able to carry out related designs according to actual needs or applications.

Obviously, according to the teachings above, those with ordinary knowledge in this technical field should also understand that the second spirit of the present invention is to make the slave latch use the weak holding circuit to store data to avoid floating Click to drive the output, and ensure that the slave latch can work at a low frequency. In addition, the present invention uses the weak holding circuit to maintain the state of the node T2. For example, if the voltage at the output terminal OUT is at a logic low level, the P-type metal-oxide half-effect transistor P5 (ie, the pull-up transistor 204) is also turned on to pull the voltage of the node T2 to the power supply voltage VDD.

On the contrary, if the voltage at the output terminal OUT is at a logic high level, the N-type metal-oxide half-effect transistor N5 (ie, the pull-down transistor 205) is also turned on to pull the voltage of the node T2 to the ground voltage VSS. However, since the operating principles of the P-type metal-oxide half-field transistors P4, P5 and the N-type metal-oxide half-field transistors N4, N5 are already known to those skilled in the art, the related subordinate latches The details of the inverter, that is, the inverter 203, the pull-up transistor 204, and the pull-down transistor 205 will not be repeated here.

It should be noted that if it is considered to extend the design concept of the strong hold circuit directly to the output terminal OUT, therefore, in other embodiments (not shown in the figure), the slave latch may not need to use feedback The inverter 206 utilizes the tri-state characteristic of the inverter 202, and the integrated inverter 203 is configured as a strong holding circuit. This design method can also help to maintain the state of the node T2. Since the detailed details are also as described in the foregoing embodiment, they will not be repeated here. In addition, please refer to FIG. 4, which is a circuit schematic diagram of a dynamic flip-flop provided by another embodiment of the present invention. Among them, some elements in FIG. 4 that are the same as or similar to those in FIG. 2 are marked with the same or similar drawing numbers, so details will not be detailed here.

Compared with the dynamic flip-flop 2 of FIG. 2, the dynamic flip-flop 4 of FIG. 4 further includes a P-type metal oxide half-field connected in series between the P-type metal oxide half-field effect transistor P5 and the N-type metal oxide half-field effect transistor N5 Effect transistor P6 and N-type metal oxide half field effect transistor N6. In this embodiment, the source of the P-type metal-oxide half-field transistor P6 is coupled to the drain of the P-type metal-oxide half-field transistor P5, and the source of the N-type metal-oxide half-field transistor N6 is coupled to N The drain of the NMOS transistor N5, the drain of the PMOS transistor P6 and the drain of the NMOS transistor N6 are respectively coupled to the node T2, the PMOS transistor The gate of the effect transistor P6 is used to receive the clock signal CP, and the gate of the N-type metal oxide half field effect transistor N6 is used to receive the clock signal CLKB.

In other words, in this embodiment, the P-type metal-oxide half-field transistors P5, P6 and the N-type metal-oxide half-field transistors N5, N6 can be regarded as a feedback latch 406 as a whole . Since the feedback latch 406 adopts a design similar to that of the inverter 202, this embodiment will make the layout structure of the dynamic flip-flop 4 more friendly, thereby reducing process variation. In addition, in this embodiment, the P-type metal-oxide half-field transistor P6 and the N-type metal-oxide half-field transistor N6 in the feedback latch are used to prevent the node T2 from being impacted by leakage current again. Since the detailed details are also as described in the foregoing embodiment, they will not be repeated here.

On the other hand, if it is considered that the dynamic flip-flop 2 in FIG. 2 can also have a hold time function, and there is no need to increase the number of transistors additionally, the present invention allows the transmission gate 201 to be configured as A weak holding circuit, and compared to the transmission gate 201, the generation path of the clock signal should be configured as a strong holding circuit. For example, the clock signal CLKB here can be directly generated by the clock signal CP passing through another inverter (not shown), and the other inverter will be compared to the transmission gate. 201 is configured as a strong hold circuit. Since the operating principles of the strong holding circuit and the weak holding circuit are already known to those with ordinary knowledge in the technical field, the details of the above details will not be repeated here.

Furthermore, if it is considered to make the dynamic flip-flop 2 more capable of having a scan function (scan function), please refer to FIG. 5 together, which is a dynamic flip-flop provided by another embodiment of the present invention. Circuit diagram. Among them, some elements in FIG. 5 that are the same as or similar to those in FIG. 2 are marked with the same or similar drawing numbers, so the details will not be detailed here.

As shown in FIG. 5, the dynamic flip-flop 5 may further include a transistor string 501 and a transistor string 502 coupled between the input terminal IN and the node T3. In this embodiment, the transistor string 501 includes a P-type metal oxide half-field transistor P7 and an N-type metal oxide half-field transistor N7 connected in series with each other. The source of the P-type MOS transistor P7 and the source of the N-type MOS transistor N7 are respectively coupled to the input terminal IN to receive the data signal D, and the P-type MOS transistor The drain of the transistor P7 and the drain of the N-type MOS transistor N7 are coupled to the node T3 via the sub-node A1. The gate of the P-type MOS transistor P7 is used to receive the scan enable signal SE, the gate electrode of the N-type metal-oxide half field effect transistor N7 is used to receive the scan enable signal SEB which is opposite to the scan enable signal SE.

In addition, in this embodiment, the transistor string 502 includes a P-type metal oxide half-field transistor P8 and an N-type metal oxide half-field transistor N8 connected in series. Among them, the source of the P-type metal oxide half field effect transistor P8 and the source of the N-type metal oxide half field effect transistor N8 are respectively coupled to the scanning terminal SCAN, for receiving the scanning signal SI, and the P-type metal oxide half field effect The drain of the transistor P8 and the drain of the N-type MOS transistor N8 are coupled to the node T3 via the sub-node A2. The gate of the P-type MOS transistor P8 is used to receive the scan enable signal SEB, the gate electrode of N-type metal oxide half field effect transistor N8 is used to receive the scan enable signal SE. It can be understood that the "child node A1" and "child node A2" in this embodiment can refer to the same child node, and the child node refers to the node where the input terminal IN is connected to the node T3.

That is to say, in this embodiment, the transistor strings 501, 502 and the transmission gate 201 can be regarded as a data multiplexer (MUX) 503 as a whole, and it should be understood that this embodiment uses transmission The gate 201 serves as the control end of the data multiplexer 503, so that the data multiplexer 503 can selectively output the data signal D or the scan signal SI to the inverter 202. According to the teaching of the above, those with ordinary knowledge in the art should understand that the dynamic flip-flop 5 in FIG. 5 can have a power consumption that is better than that of the conventional dynamic flip-flop 1. Since the operating principle of the flip-flop with scanning function is already known by those with ordinary knowledge in the technical field, the details of the above details will not be repeated here.

Or, if it is considered to make the dynamic flip-flop 2 more capable of having a reset function, please refer to FIG. 6 together. FIG. 6 is a circuit of a dynamic flip-flop provided by another embodiment of the present invention. Schematic. Among them, some elements in FIG. 6 that are the same as or similar to those in FIG. 2 are marked with the same or similar drawing numbers, so the details will not be detailed here. As shown in FIG. 6, the dynamic flip-flop 6 may further include a P-type metal oxide half-field transistor P9 and an N-type metal oxide half-field transistor N9. In this embodiment, the P-type metal-oxide half field effect transistor P9 is coupled between the node T2 and the node T7. The source of the P-type MOSFET P9 is coupled to the power supply voltage VDD, the drain of the P-type MOSFET P9 is coupled to the sub-node A3 between the node T2 and the node T7, the P-type gold The gate of the oxygen half field effect transistor P9 is used to receive the reset signal RB.

In addition, in this embodiment, the N-type metal-oxide-semiconductor field effect transistor N9 is connected in series between the N-type metal-oxide-semiconductor field effect transistor N3 and the ground voltage VSS. Wherein, the source of the N-type MOSFET N9 is coupled to the ground voltage VSS, and the drain of the N-type MOSFET N9 is coupled to the source of the N-type MOSFET N3, N The gate of the NMOS transistor N9 is used to receive the reset signal RB. In other words, compared with the conventional dynamic flip-flop 1, the dynamic flip-flop 6 of FIG. 6 only needs to add a small number of transistors to achieve the reset function, and the dynamic flip-flop 6 of FIG. 6 is still A circuit design that solves the aforementioned leakage current problem can be used. Since the operating principle of the flip-flop with reset function is also well known by those with ordinary knowledge in the technical field, the details above will not be repeated here.

Similarly, if it is considered to make the dynamic flip-flop 2 more capable of having a set function, please refer to FIG. 7 together. FIG. 7 is a circuit schematic diagram of a dynamic flip-flop provided by another embodiment of the present invention. . Among them, some elements in FIG. 7 that are the same as or similar to those in FIG. 2 are marked with the same or similar drawing numbers, so the details will not be detailed here. As shown in FIG. 7, the dynamic flip-flop 7 may further include a P-type metal oxide half-field effect transistor P10 and an N-type metal oxide half-field effect transistor N10. In this embodiment, the P-type metal-oxide half field effect transistor P10 is connected in series between the power supply voltage VDD and the P-type metal-oxide half field effect transistor P2. Wherein, the source of the P-type metal-oxide-half field-effect transistor P10 is coupled to the power supply voltage VDD, and the drain of the P-type metal-oxide-half field-effect transistor P10 is coupled to the source of the P-type metal-oxide half-field transistor P2, P The gate of the PMOS transistor P10 is used to receive the setting signal S.

In addition, in this embodiment, the N-type metal oxide half field effect transistor N10 is coupled between the node T2 and the node T7. The source of the N-type MOSFET N10 is coupled to the ground voltage VSS, the drain of the N-type MOSFET N10 is coupled to the sub-node A3 between the node T2 and the node T7, and the N-type gold The gate of the oxygen half field effect transistor N10 is used to receive the setting signal S. However, due to the advantages of the dynamic flip-flop 7 and the operating principle of the flip-flop with a setting function are also well known to those with ordinary knowledge in the technical field, so the details above will not be repeated here.

On the other hand, if it is considered to make the dynamic flip-flop 2 more capable of data retention, please refer to FIG. 8 together. FIG. 8 is a dynamic flip-flop provided by another embodiment of the present invention. Schematic of the circuit. Among them, some elements in FIG. 8 that are the same as or similar to those in FIG. 2 are marked with the same or similar drawing numbers, so the details will not be detailed here. As shown in FIG. 8, the dynamic flip-flop 8 may further include P-type metal oxide half-field transistors P11-P13 and N-type metal oxide half-field transistors N11-N13.

In this embodiment, the P-type metal-oxide-half field-effect transistor P11 is connected in series between the power supply voltage VDD and the P-type metal-oxide-half field-effect transistor P2. Wherein, the source of the P-type metal-oxide-half field-effect transistor P11 is coupled to the power supply voltage VDD, and the drain of the P-type metal-oxide-half field-effect transistor P11 is coupled to the source of the P-type metal-oxide half-field transistor P2, P The gate of the PMOS transistor P11 is used to receive the control signal SL. The N-type metal-oxide half-effect transistor N11 is connected in series between the N-type metal-oxide half-effect transistor N3 and the ground voltage VSS. Wherein, the source of the N-type MOSFET N11 is coupled to the ground voltage VSS, the drain of the N-type MOSFET N11 is coupled to the source of the N-type MOSFET N3, N The gate electrode of the NMOS transistor N11 is used to receive the control signal SLB which is inverse to the control signal SL.

In addition, in this embodiment, the P-type metal-oxide half-field transistor P12 is connected in series between the P-type metal-oxide half-field transistor P5 and the node T2. Among them, the source of the P-type metal-oxide half-field transistor P12 is coupled to the drain of the P-type metal-oxide half-field transistor P5, and the drain of the P-type metal-oxide half-field transistor P12 is coupled to the node T2, P-type The gate of the PMOS transistor P12 is used to receive the control signal SLB. The N-type metal-oxide half field effect transistor N12 is connected in series between the N-type metal-oxide half field effect transistor N5 and the node T2. Among them, the source of the N-type metal-oxide half-field transistor N12 is coupled to the drain of the N-type metal-oxide half-field transistor N5, and the drain of the N-type metal-oxide half-field transistor N12 is coupled to the node T2, N-type The gate electrode of the metal oxide half field effect transistor N12 is used to receive the control signal SL.

Similarly, in this embodiment, the source of the P-type metal-oxide half-field transistor P13 is coupled between the drain of the P-type metal-oxide half-field transistor P5 and the source of the P-type metal-oxide half-field transistor P12 The sub-node A4, the drain of the P-type MOS transistor P13 is coupled to the sub-node A5 between the node T2 and the node T5, and the gate of the P-type MOS transistor P13 is used to receive the clock signal CP. In addition, the source of the N-type metal-oxide half-field transistor N13 is coupled to the sub-node A6 between the drain of the N-type metal-oxide half-field transistor N5 and the source of the N-type metal-oxide half-field transistor N12, N-type The drain of the NMOS transistor N13 is coupled to the sub-node A5, and the gate of the N-type NMOS transistor N13 is used to receive the clock signal CLKB. Since the operation principle of the flip-flop with data retention is also known by those with ordinary knowledge in the technical field, the details of the above details will not be repeated here.

In summary, the dynamic flip-flop provided by the embodiments of the present invention will adopt a circuit design architecture that is completely different from the conventional dynamic flip-flop. Specifically, the dynamic flip-flop of this embodiment may be such that the main latch utilizes a three-state inverter to capture data to reduce the leakage current problem. In addition, the dynamic flip-flop of this embodiment may be such that the slave latch uses a weak holding circuit to store data to avoid floating points to drive the output.

The above is only an embodiment of the present invention, and it is not intended to limit the patent scope of the present invention.

1, 2, 4, 5, 6, 7, 8 ‧‧‧ dynamic flip-flop IN‧‧‧ input terminal OUT‧‧‧ output terminal 101, 103, 201‧‧‧ transmission gate 102, 104, 202, 203‧ ‧‧Inverter 204‧‧‧Pull-up transistor 205‧‧‧ Pull-down transistor 206‧‧‧Feedback inverter 406‧‧‧Feedback latch 501, 502‧‧‧‧Transistor string 503‧‧ ‧Data multiplexers P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13 ‧‧‧P-type metal oxide semi-field effect transistors N1, N2, N3, N4, N5 , N6, N7, N8, N9, N10, N11, N12, N13 ‧‧‧N-type metal oxide half field effect transistor D, Q‧‧‧ data signal CLKB, CP‧‧‧ clock signal VDD‧‧‧ supply voltage VSS‧‧‧ground voltage SE, SEB‧‧‧scan enable signal SCAN‧‧‧scan terminal SI‧‧‧scan signal RB‧‧‧reset signal SL, SLB‧‧‧control signal T1, T2, T3, T4 , T5, T6, T7 ‧‧‧ nodes A1, A2, A3, A4, A5, A6 ‧‧‧ child nodes

1 is a circuit schematic diagram of a conventional dynamic flip-flop; FIG. 2 is a circuit schematic diagram of a dynamic flip-flop provided by an embodiment of the present invention; FIG. 3 is a circuit schematic diagram of a dynamic flip-flop provided by another embodiment of the present invention Figure 4 is a circuit schematic diagram of a dynamic flip-flop provided by another embodiment of the present invention; Figure 5 is a circuit schematic diagram of a dynamic flip-flop provided by another embodiment of the present invention; Figure 6 is another embodiment of the present invention; The schematic circuit diagram of the provided dynamic flip-flop; FIG. 7 is the schematic circuit diagram of the dynamic flip-flop provided by another embodiment of the invention; FIG. 8 is the schematic circuit diagram of the dynamic flip-flop provided by another embodiment of the invention .

2‧‧‧Dynamic flip-flop

IN‧‧‧input

OUT‧‧‧Output

201‧‧‧Transmission gate

202、203‧‧‧Inverter

204‧‧‧Pull-up transistor

205‧‧‧pull-down transistor

206‧‧‧Feedback inverter

P1, P2, P3, P4, P5 ‧‧‧P type metal oxide half field effect transistor

N1, N2, N3, N4, N5 ‧‧‧N type metal oxide half field effect transistor

D, Q‧‧‧ data signal

CLKB, CP‧‧‧clock signal

VDD‧‧‧Power supply voltage

VSS‧‧‧Ground voltage

T1, T2, T3, T4, T5, T6, T7

Claims (14)

A dynamic flip flop (FF) has an input terminal and an output terminal, and includes: a transmission gate coupled to the input terminal and used to receive a first data signal, And outputting the first data signal to a first node according to a first clock signal and its inverted second clock signal; a first inverter is coupled to the first node via the first node The transmission gate is used to invert the first data signal and output the inverted first data signal to a second node; a second inverter is coupled between the second node and the output terminal , And used to invert the inverted first data signal to generate a second data signal, and output the second data signal to the output terminal; a pull-up transistor (pull-up transistor), coupled to Between the second node and a power supply voltage, and used to pull up the voltage of the two nodes to the power supply voltage; and a pull-down transistor, coupled between the second node and a ground voltage, And used to pull down the voltage of the two nodes to the ground voltage. The dynamic flip-flop of claim 1, wherein the transmission gate includes a first N-type metal-oxide half-field transistor and a first P-type metal-oxide half-field transistor connected in parallel, the first N The drain of the MOSFET and the drain of the first P-type MOSFET are coupled to the input terminal of the dynamic flip-flop through a third node, the first N-type gold The source of the oxygen half-field transistor and the source of the first P-type metal oxide half-field transistor are coupled to the first node via a fourth node, and the gate of the first N-type metal oxide half-field transistor The pole is used to receive the first clock signal, and the gate of the first P-type metal oxide half field effect transistor is used to receive the second clock signal. The dynamic flip-flop of claim 2, wherein the first inverter is a tri-state inverter (tri-state inverter), and it includes a second P-type metal oxide half field effect connected in series Transistor, a third P-type metal oxide half-field transistor, a second N-type metal oxide half-field transistor, and a third N-type metal oxide half-field transistor, the second P-type metal oxide half-field transistor The source of the is coupled to the power supply voltage, the source of the third N-type metal-oxide half field effect transistor is coupled to the ground voltage, the gate of the second P-type metal-oxide half field effect transistor and the third N The gates of the MOSFETs are respectively coupled to the first node to receive the first data signal, and the source of the third P-type MOSFETs is coupled to the second The drain of the P-type metal-oxide half-field transistor, the source of the second N-type metal-oxide half-field transistor is coupled to the drain of the third N-type metal-oxide half-field transistor, the third P-type gold The drain of the oxygen half field effect transistor and the drain of the second N-type metal oxide half field effect transistor are coupled to the second node via a fifth node, and the gate of the third P-type metal oxide half field effect transistor The pole is used to receive the first clock signal, and the gate electrode of the second N-type metal oxide half field effect transistor is used to receive the second clock signal. The dynamic flip-flop as claimed in claim 3, wherein the second inverter includes a fourth P-type metal oxide half-field transistor and a fourth N-type metal oxide half-field transistor connected in series, the The source of the fourth P-type MOSFET is coupled to the power supply voltage, the source of the fourth N-type MOSFET is coupled to the ground voltage, and the fourth P-type MOSFET is coupled to the ground voltage The drain of the transistor and the drain of the fourth N-type metal oxide half-field effect transistor are coupled to the output terminal of the dynamic flip-flop through a sixth node. The fourth P-type metal oxide half-field effect transistor And the gate of the fourth N-type metal-oxide-half field effect transistor are coupled to the second node via a seventh node for receiving the inverted first data signal. The dynamic flip-flop of claim 4, wherein the pull-up transistor is a fifth P-type metal oxide half field effect transistor, and the pull-down transistor is a fifth N-type metal oxide half field effect transistor, The source of the fifth P-type MOSFET is coupled to the power supply voltage, the source of the fifth N-type MOSFET is coupled to the ground voltage, and the fifth P-type MOSFET The drain of the effect transistor and the drain of the fifth N-type metal-oxide half-field effect transistor are respectively coupled to the second node, the gate of the fifth P-type metal-oxide half-field effect transistor and the fifth N The gates of the MOSFETs are respectively coupled to the output end of the dynamic flip-flop to receive the second data signal. The dynamic flip-flop of claim 5, wherein the pull-up transistor and the pull-down transistor constitute a feedback inverter, and compared to the first inverter, the The feedback inverter is configured as a weak keeper circuit. The dynamic flip-flop as described in claim 5 further includes a sixth P-type metal oxide connected in series between the fifth P-type metal oxide half-field transistor and the fifth N-type metal oxide half-field transistor A half field effect transistor and a sixth N-type metal oxide half field effect transistor, the source of the sixth P type metal oxide half field effect transistor is coupled to the drain of the fifth P type metal oxide half field effect transistor, the The source of the sixth N-type MOSFET is coupled to the drain of the fifth N-type MOSFET, the drain of the sixth P-type MOSFET and the sixth N The drains of the MOSFETs are respectively coupled to the second node, the gate of the sixth P-type MOSFET is used to receive the second clock signal, and the sixth N-type transistor The gate electrode of the metal-oxide half-effect transistor is used to receive the first clock signal. The dynamic flip-flop of claim 5 further includes a first transistor string and a second transistor string coupled between the input terminal and the third node. The dynamic flip-flop as claimed in claim 8, wherein the first transistor string includes a seventh P-type metal oxide half-field transistor and a seventh N-type metal oxide half-field transistor connected in series, the The source of the seventh P-type metal oxide half-field effect transistor and the source of the seventh N-type metal oxide half-field effect transistor are respectively coupled to the input terminal for receiving the first data signal, the seventh The drain of the P-type MOS transistor and the drain of the seventh N-type MOSFET are coupled to the third node via a first sub-node, the seventh P-type MOSFET The gate electrode of the effect transistor is used to receive a first scan enable signal, and the gate electrode of the seventh N-type metal oxide half field effect transistor is used to receive a second scan inverse to the first scan enable signal Enable signal. The dynamic flip-flop of claim 9, wherein the second transistor string includes an eighth P-type metal oxide half-field transistor and an eighth N-type metal oxide half-field transistor connected in series, the The source of the eighth P-type metal-oxide half-field effect transistor and the source of the eighth N-type metal-oxide half-field effect transistor are respectively coupled to a scanning terminal for receiving a scanning signal. The drain of the metal-oxygen half-field transistor and the drain of the eighth N-type metal-oxide half-field transistor are commonly coupled to the third node via a second sub-node, and the eighth P-type metal-oxide half-field effect The gate of the crystal is used to receive the second scan enable signal, and the gate of the eighth N-type metal oxide half field effect transistor is used to receive the first scan enable signal. The dynamic flip-flop as recited in claim 5 further includes: a ninth P-type gold-oxygen half-field effect transistor, coupled between the second node and the seventh node, wherein the ninth P-type gold The source of the oxygen half field effect transistor is coupled to the power supply voltage, and the drain of the ninth P-type gold oxide half field effect transistor is coupled to a third sub-node between the second node and the seventh node. The gate of the ninth P-type metal-oxide half-field transistor is used to receive a reset signal; and a ninth N-type metal-oxide half-field transistor, connected in series to the third N-type metal-oxide half-field transistor and the Between ground voltages, the source of the ninth N-type metal oxide half-field transistor is coupled to the ground voltage, and the drain of the ninth N-type metal oxide half-field transistor is coupled to the third N-type metal oxide The source of the half field effect transistor, and the gate of the ninth N-type metal oxide half field effect transistor are used to receive the reset signal. The dynamic flip-flop as claimed in claim 5 further includes: a tenth P-type metal-oxide half-field transistor connected in series between the power supply voltage and the second P-type metal-oxide half-field transistor, wherein the The source of the tenth P-type MOSFET is coupled to the power supply voltage, and the drain of the tenth P-type MOSFET is coupled to the source of the second P-type MOSFET Electrode, the gate of the tenth P-type metal oxide semi-field effect transistor is used to receive a setting signal; and a tenth N-type metal oxide semi-field effect transistor is coupled between the second node and the seventh node , Wherein the source of the tenth N-type metal oxide semi-field effect transistor is coupled to the ground voltage, and the drain of the tenth N-type metal oxide semi-field transistor is coupled between the second node and the seventh node A third sub-node, the gate of the tenth N-type metal oxide half-field effect transistor is used to receive the setting signal. The dynamic flip-flop as recited in claim 5 further includes: an eleventh P-type metal oxide semi-field effect transistor connected in series between the power supply voltage and the second P-type metal oxide semi-field effect transistor, wherein The source of the eleventh P-type MOSFET is coupled to the power supply voltage, and the drain of the eleventh P-type MOSFET is coupled to the second P-type MOSFET The source of the crystal, the gate of the eleventh P-type metal oxide half field effect transistor is used to receive a first control signal; an eleventh N-type metal oxide half field effect transistor is connected in series with the third N type Between the metal oxide semiconductor field effect transistor and the ground voltage, wherein the source of the eleventh N-type metal oxide semiconductor field effect transistor is coupled to the ground voltage, and the drain electrode of the eleventh N-type metal oxide semiconductor field effect transistor It is coupled to the source of the third N-type MOSFET, and the gate of the eleventh N-type MOSFET is used to receive a second control that is inverse to the first control signal. A signal; a twelfth P-type metal-oxide half-field effect transistor connected in series between the fifth P-type metal-oxide half-field effect transistor and the second node, wherein the source of the twelfth P-type metal-oxide half-field effect transistor The pole is coupled to the drain of the fifth P-type metal oxide half-field transistor, the drain of the twelfth P-type metal oxide half-field transistor is coupled to the second node, and the twelfth P-type metal oxide The gate of the half field effect transistor is used to receive the second control signal; a twelfth N-type metal oxide half field effect transistor is connected in series between the fifth N-type metal oxide half field effect transistor and the second node, The source electrode of the twelfth N-type metal oxide semi-field effect transistor is coupled to the drain electrode of the fifth N-type metal oxide semi-field effect transistor, and the drain electrode of the twelfth N-type metal oxide semi-field effect transistor is coupled. Connected to the second node, the gate of the twelfth N-type metal oxide half field effect transistor is used to receive the first control signal; a thirteenth P-type metal oxide half field effect transistor, of which the thirteenth The source of the P-type metal-oxide-half field-effect transistor is coupled to a fourth element between the drain of the fifth P-type metal-oxide-half field-effect transistor and the source of the twelfth P-type metal-oxide-half field effect transistor. Node, the drain of the thirteenth P-type metal oxide semi-field effect transistor is coupled to a fifth sub-node between the second node and the fifth node, the The gate is used to receive the second clock signal; and a thirteenth N-type metal oxide half field effect transistor, wherein the source of the thirteenth N-type metal oxide half field effect transistor is coupled to the fifth N A sixth sub-node between the drain of the metal oxide semiconductor field-effect transistor and the source of the twelfth N-type metal oxide semiconductor field effect transistor, the drain coupling of the thirteenth N-type metal oxide semiconductor field effect transistor Connected to the fifth sub-node, the gate of the thirteenth N-type metal oxide half field effect transistor is used to receive the first clock signal. An electronic device, including the dynamic flip-flop according to any one of the items 1 to 13 of the request item.

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