WO2023141906A1

WO2023141906A1 - Conjugate logic gate circuit, integrated circuit and electronic device

Info

Publication number: WO2023141906A1
Application number: PCT/CN2022/074437
Authority: WO
Inventors: 詹士杰; 吴颖; 廖恒; 许俊豪
Original assignee: 华为技术有限公司
Priority date: 2022-01-27
Filing date: 2022-01-27
Publication date: 2023-08-03
Also published as: CN117083805A

Abstract

The embodiments of the present application relate to the technical field of circuits. Provided are a conjugate logic gate circuit, an integrated circuit and an electronic device. The embodiments of the present application are mainly used for providing a conjugate logic gate circuit capable of realizing conjugate input and conjugate output. The conjugate logic gate circuit comprises an inverter, a buffer, a first voltage end and a second voltage end, wherein the inverter and the buffer are connected in parallel between the first voltage end and the second voltage end; an input port of the inverter is electrically connected to an input port of the buffer, so as to form a first input port of the conjugate logic gate circuit; a conjugate input port of the inverter is electrically connected to a conjugate input port of the buffer, so as to form a first conjugate input port of the conjugate logic gate circuit; and one of an output port of the inverter and an output port of the buffer forms an output port of the conjugate logic gate circuit, and the other one forms a conjugate output port of the conjugate logic gate circuit. The conjugate logic gate circuit can realize cascade connection.

Description

Conjugate logic gates, integrated circuits, electronic devices

technical field

The present application relates to the field of circuit technology, and in particular to a conjugate logic gate circuit, an integrated circuit including the conjugate logic gate circuit, and electronic equipment including the integrated circuit.

Background technique

Logic gates are the basic components on an integrated circuit. Logic gates can be composed of transistors, and the combination of these transistors can make a high or low level representing two signals pass through them to generate a high or low level signal. It can also be said that a logic gate circuit refers to a circuit that can realize basic logic operations such as "NOR", "NAND", "OR", and "AND".

At present, there is a logic gate circuit, which is a circuit structure with a conjugate input and a single output. That is, in this circuit, a conjugated input signal can be received, but the conjugated signal cannot be output. Then, this kind of circuit structure cannot be cascaded to form a more complex multi-level logic circuit, so that the application scenarios of this kind of circuit are very limited. In addition, if this kind of logic gate circuit is applied to an integrated circuit, some additional circuits may need to be added, making the integrated circuit relatively complex and high in complexity.

Contents of the invention

The present application provides a conjugate logic gate circuit, an integrated circuit including the conjugate logic gate circuit, and electronic equipment including the integrated circuit. The main purpose is to provide a conjugate logic gate circuit capable of realizing conjugate input and conjugate output, so that the logic gate circuit can be cascaded.

In order to achieve the above object, the embodiments of the present application adopt the following technical solutions:

On the one hand, the present application provides a conjugate logic gate circuit, and the conjugate logic gate circuit may be a unipolar logic gate circuit.

The conjugate logic gate circuit includes a unipolar inverter and a unipolar buffer, for example, the inverter is an N-type inverter, and the buffer is an N-type buffer; the inverter and the buffer are connected in parallel to the first Between the DC voltage terminal and the second DC voltage terminal; both the inverter and the buffer have an input port, a conjugate input port, and an output port; wherein, the input port of the inverter is electrically connected to the input port of the buffer, to Forming the first input port of the conjugate logic gate circuit; the conjugate input port of the inverter is electrically connected with the conjugate input port of the buffer to form the first conjugate input port of the conjugate logic gate circuit; the inverter's One of the output port and the output port of the buffer forms an output port of the conjugate logic gate, and the other forms a conjugate output port of the conjugate logic gate.

Based on the above description of the circuit structure of the conjugate logic gate circuit, it can be seen that the logic gate circuit is controlled by a conjugated input signal (that is, it includes the first input port receiving the inverse signal and the first conjugate input port) And, it is also a conjugated output, that is, it includes an output port that can output an inverted signal and a conjugated output port to form a conjugated logic gate circuit with conjugated input and conjugated output.

For example, in some more complex logic gate circuits, the above-mentioned conjugate logic gate circuits can be cascaded, that is, the conjugate output of the first-stage conjugate logic gate circuit can be used as the second-stage conjugate logic gate circuit Conjugate input to form a complex circuit.

In addition, since both the inverter and the buffer are unipolar circuits, for example, when the transistor controlled by the input signal is turned on, the transistor controlled by the conjugate input signal is turned off, so that the first DC voltage terminal and the The leakage current between the second DC voltage terminals can reduce the static power consumption of the conjugate logic gate circuit.

In a possible implementation manner, the inverter includes a first transistor and a third transistor, and both the first transistor and the third transistor include a first gate; the first transistor and the third transistor are connected in series between the first DC voltage terminal and the Between the second DC voltage terminals; the gate of the first transistor is the first conjugate input port; the gate of the third transistor is the first input port; a point at the electrical connection between the first transistor and the third transistor is a conjugate logic gate circuit output port.

For example, when the first transistor and the second transistor both use N-type transistors, or both use P-type transistors, the inverter formed in this way is a unipolar inverter, and in this inverter, the static hold state, the first transistor and the third transistor are not turned on at the same time, but when one transistor is turned on, the other transistor is turned off, so that the static leakage phenomenon can be reduced.

In addition, the number of transistors of this type of inverter is small, which can improve the integration level of the conjugate logic gate circuit.

In a possible implementation manner, the buffer includes a second transistor and a fourth transistor, and both the second transistor and the fourth transistor include a first gate; the second transistor and the fourth transistor are connected in series between the first DC voltage terminal and the first gate. Between the two DC voltage terminals; the gate of the second transistor is the first input port; the gate of the fourth transistor is the first conjugate input port; a point at the electrical connection between the second transistor and the fourth transistor is the conjugate logic gate circuit Conjugated output port.

Like the transistors in the above-mentioned inverter, all N-type transistors or P-type transistors can be used. In this case, in the buffer, when the state is held statically, the second transistor and the fourth transistor are not turned on at the same time, but when one transistor is turned on, the other transistor is turned off, thereby reducing the Static leakage phenomenon.

In addition, when the first transistor, the second transistor, the third transistor and the fourth transistor are all electronic type field effect transistors, when the first transistor and the second transistor are depletion type, compared with the enhancement type, the opening can be greatly increased. The on-state current (On Current), thereby speeding up the pull-up speed, increasing the response frequency of the conjugate logic gate, and at the same time achieving a high output potential without potential loss.

In addition, in the conjugated logic gate circuit of the present application, no additional feedback structure and capacitance structure are needed, and high-speed response can be realized. In addition, the number of transistors in the conjugate logic gate circuit is small, and if the conjugate logic gate circuit is applied to an integrated circuit, the integration density of the integrated circuit can be increased.

In a possible implementation manner, at least one of the first transistor and the third transistor further includes a second gate; the second gate is electrically connected to the bias voltage.

That is to say, the threshold voltage of the transistor can be adjusted through the bias voltage, so as to realize zero potential loss of the conjugate logic gate circuit.

Moreover, when a double-gate (first gate and second gate) transistor is used, the transistor can better control the channel switch in the case of a short channel, and has a lower sub-threshold swing, so that the In the case of a certain threshold voltage, it has a larger on-state current and response speed.

In a possible implementation manner, the first transistor further includes a second gate; the second gate is electrically connected to the output port of the conjugate logic gate circuit.

In this implementation, the threshold voltage of the transistor is adjusted by electrically connecting a gate to the output port, so as to realize zero potential loss of the conjugate logic gate circuit.

In a possible implementation manner, the first transistor further includes a second gate; the second gate is electrically connected to the first DC voltage terminal.

In this embodiment, the threshold voltage of the transistor is adjusted by connecting one gate of the transistor to the voltage terminal, thereby realizing zero potential loss of the conjugate logic gate circuit.

In a possible implementation, the conjugate logic gate circuit further includes a voltage regulating transistor; the first electrode of the voltage regulating transistor is electrically connected to the second gate, and the second electrode is electrically connected to the first DC voltage terminal; The gate is electrically connected to the output port of the conjugate logic gate circuit.

That is to say, the threshold voltage of the first transistor is adjusted through the voltage regulating transistor to realize zero potential loss.

In a possible implementation manner, the conjugate logic gate circuit further includes a feedback circuit; the feedback circuit is electrically connected to the second gate, and the feedback circuit is also electrically connected to the first DC voltage terminal and the output port of the conjugate logic gate circuit.

That is, a feedback circuit is used to adjust the threshold voltage of the first transistor to realize zero potential loss.

In a possible implementation manner, by adjusting the voltage of the second gate of the first transistor, the threshold voltage of the first transistor is less than or equal to zero when the first transistor is turned on, and the threshold voltage of the third transistor is greater than zero. The zero potential loss of the conjugate logic gate circuit is realized.

In a possible implementation manner, the first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors, or all are P-type transistors.

When an N-type transistor is used, the formed logic gate circuit may be called an N-type conjugate logic gate circuit, or, when a P-type transistor is used, the formed logic gate circuit may be called a P-type conjugate logic gate circuit.

In a possible implementation manner, the conjugate logic gate circuit further includes: a first gate transistor and a second gate transistor; wherein, the gate of the first gate transistor and the gate of the second gate transistor are both used is electrically connected to the clock signal; the first electrode of the first gate is electrically connected to the first input port, and the second electrode is electrically connected to the input signal; the first electrode of the second gate is electrically connected to the first conjugate input port connected, and the second electrode is electrically connected to the inverted input signal, so that the conjugate logic gate circuit forms a latch.

Using the latch circuit formed by the circuit including the inverter and the buffer in the embodiment of the present application, the number of transistors is small, and the integration degree of the latch can be improved.

In a possible implementation manner, there are multiple latches, and the multiple latches include a first latch and a second latch; in the second latch, the gate of the first gate and the gate of the second gate are used to be electrically connected to the anti-clock signal; the second electrode of the first gate of the second latch is electrically connected to the output port of the first latch; the second latch The second electrode of the second gate transistor of the device is electrically connected to the conjugate output port of the first latch, so that the electrically connected first latch and the second latch form a flip-flop.

A flip-flop can be formed by cascading the above-mentioned latches.

In a possible implementation manner, the conjugate logic gate circuit further includes another inverter and another buffer; wherein, the inverter and the buffer form a first sub-circuit, and the other inverter and another buffer The device forms the second sub-circuit; the conjugated logic gate circuit also includes: a first gating tube and a second gating tube; a third gating tube and a fourth gating tube; the first gating tube is electrically connected to the first sub-circuit between the first input port of the circuit and the output port of the second sub-circuit; the second gating tube is electrically connected between the first conjugate input port of the first sub-circuit and the conjugate output port of the second sub-circuit; the second The gate of the first gate transistor and the gate of the second gate transistor are both used to electrically connect with the anti-clock signal; the first electrode of the third gate transistor is electrically connected to the first input port of the first sub-circuit, and the second The electrodes are used to electrically connect the input signal; the first electrode of the fourth gating tube is electrically connected to the first conjugate input port of the first sub-circuit, and the second electrode is used to electrically connect the reverse input signal; the gate of the third gating tube Both the pole and the gate of the fourth gating transistor are used to be electrically connected to the clock signal to form a latch; the output port of the first sub-circuit is electrically connected to the first input port of the second sub-circuit to form the output of the latch port, the conjugated output port of the first subcircuit is electrically connected to the first conjugated input port of the second subcircuit to form a conjugated output port of the latch.

In a possible implementation manner, there are multiple latches, and the multiple latches include a first latch and a second latch; the output port of the first latch and the second latch of the second latch The second electrodes of the three gate transistors are connected, and the conjugate output port of the first latch is connected with the second electrode of the fourth gate transistor of the second latch, so that the electrically connected first latch and the second gate Two latches form a flip-flop.

In a possible implementation manner, the conjugate logic gate circuit further includes a clock signal control circuit; the clock control circuit is used to control the turning on or off of the inverter and the buffer according to the clock signal.

That is, the switching on and off of the inverter and the buffer is controlled by a clock signal.

In a possible implementation manner, the clock control circuit includes: a third transistor and a fourth transistor; the third transistor, the inverter, and the fourth transistor are connected in series between the first DC voltage terminal and the second DC voltage terminal; and Both the gate of the third transistor and the gate of the fourth transistor are electrically connected to the clock signal.

This is only a circuit structure controlled by a clock signal, and of course, other circuit structures can also be used.

In a possible implementation manner, the conjugate logic gate circuit is a NOR gate circuit including a first input port, a first conjugate input port, a second input port, and a second conjugate input port.

In a possible implementation manner, the conjugate logic gate circuit further includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the seventh transistor and the first transistor are connected in series to the first DC voltage terminal and the conjugate Between the output ports of the logic gate circuit; the eighth transistor and the second transistor are connected in parallel between the first DC voltage terminal and the conjugate output port of the conjugate logic gate circuit; the ninth transistor and the third transistor are connected in parallel with the second DC voltage terminal and the output port of the conjugate logic gate circuit; the tenth transistor and the fourth transistor are connected in series between the second DC voltage terminal and the conjugate output port of the conjugate logic gate circuit; wherein, the gate of the eighth transistor and The gate of the ninth transistor is electrically connected, and forms the second input port of the NOR gate circuit; the gate of the seventh transistor is electrically connected with the gate of the tenth transistor, and forms the second conjugate of the NOR gate circuit input port.

In a possible implementation manner, the conjugate logic gate circuit is a NAND gate circuit including a first input port, a first conjugate input port, a second input port, and a second conjugate input port.

In a possible implementation manner, the conjugate logic gate circuit further includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; the seventh transistor and the first transistor are connected in parallel to the first DC voltage terminal and the conjugate Between the output ports of the logic gate circuit; the eighth transistor and the second transistor are connected in series between the first DC voltage terminal and the conjugate output port of the conjugate logic gate circuit; the ninth transistor and the third transistor are connected in series with the second DC voltage terminal and the output port of the conjugate logic gate circuit; the tenth transistor and the fourth transistor are connected in parallel between the second DC voltage terminal and the conjugate output port of the conjugate logic gate circuit; wherein, the gate of the eighth transistor and The gate of the ninth transistor is electrically connected, and forms a second input port of the NAND gate circuit; the gate of the seventh transistor is electrically connected with the gate of the tenth transistor, and forms a second conjugate of the NAND gate circuit input port.

On the other hand, the present application also provides an integrated circuit, which includes an interface and a logic gate circuit, where the logic gate is a conjugate logic gate circuit in any of the above possible implementation manners.

In the integrated circuit, since the conjugate logic gate circuit in any of the above-mentioned implementation modes is included, and because the conjugate logic gate circuit has a conjugate input and conjugate output structure, furthermore, in the integrated circuit Among them, cascading can be realized, the integrated circuit can be simplified, paving the way for increasing the integration density of the integrated circuit, and low leakage and low power consumption can also be achieved.

In another aspect, the present application also provides an electronic device, the electronic device includes a circuit board and an integrated circuit, and the integrated circuit is the integrated circuit in the above embodiment, and the integrated circuit is formed on the circuit board.

Since the above-mentioned conjugate logic gate circuit is included in the integrated circuit in the electronic equipment, it can solve the same technical problem and achieve the same technical effect as the above-mentioned conjugate logic gate circuit.

Description of drawings

FIG. 1 is a partial circuit diagram of an electronic device provided in an embodiment of the present application;

FIG. 2 is a circuit diagram of a conjugate logic gate circuit provided by an embodiment of the present application;

FIG. 3 is a circuit symbol of a conjugate logic gate circuit provided in an embodiment of the present application;

FIG. 4 is a circuit diagram of a storage unit in a SRAM memory provided by an embodiment of the present application;

Fig. 5 is a circuit diagram of a logic gate circuit in the related art;

FIG. 6 is a circuit diagram of a conjugate logic gate circuit provided by an embodiment of the present application;

Fig. 7a is a circuit diagram of a conjugate logic gate circuit provided by the embodiment of the present application;

Fig. 7b is a circuit diagram of a conjugate logic gate circuit provided by the embodiment of the present application;

FIG. 8 is a process structure diagram of a transistor provided in an embodiment of the present application;

FIG. 9 is a circuit diagram of a conjugate logic gate circuit provided by an embodiment of the present application;

FIG. 10 is a process structure diagram of a transistor provided in an embodiment of the present application;

FIG. 11 is a circuit diagram of a conjugate logic gate circuit provided by an embodiment of the present application;

FIG. 12 is a process structure diagram of a transistor provided in an embodiment of the present application;

FIG. 13 is a circuit diagram of a conjugate logic gate circuit provided by an embodiment of the present application;

FIG. 14 is a circuit diagram of a conjugate logic gate circuit provided by an embodiment of the present application;

FIG. 15 is a circuit diagram of a conjugate logic gate circuit provided by an embodiment of the present application;

FIG. 16 is a timing diagram of a conjugate logic gate circuit provided by the embodiment of the present application;

Fig. 17a is a circuit diagram of a conjugate logic gate circuit provided by the embodiment of the present application;

Fig. 17b is a circuit symbol of a conjugate logic gate circuit provided by the embodiment of the present application;

Fig. 17c is a circuit diagram of a conjugate logic gate circuit provided by the embodiment of the present application;

FIG. 18 is a circuit diagram of a conjugate logic gate circuit provided by an embodiment of the present application;

FIG. 19 is a circuit diagram of a NOR gate provided in the embodiment of the present application;

FIG. 20 is a circuit symbol of a NOR gate provided in the embodiment of the present application;

FIG. 21 is a circuit diagram of a NAND gate provided in the embodiment of the present application;

FIG. 22 is a circuit symbol of a NAND gate provided in the embodiment of the present application;

FIG. 23 is a circuit diagram of a latch provided in an embodiment of the present application;

FIG. 24 is a circuit diagram of a flip-flop provided in an embodiment of the present application;

FIG. 25 is a timing diagram of a conjugate logic gate circuit provided by the embodiment of the present application;

FIG. 26 is a circuit diagram of a latch provided in an embodiment of the present application;

FIG. 27 is a circuit diagram of a latch provided in an embodiment of the present application;

FIG. 28 is a circuit diagram of a flip-flop provided by an embodiment of the present application;

FIG. 29 is a circuit diagram of a flip-flop provided by an embodiment of the present application;

FIG. 30 is a circuit diagram of a latch provided in an embodiment of the present application;

FIG. 31 is a circuit diagram of a latch provided in an embodiment of the present application;

FIG. 32 is a circuit diagram of a flip-flop provided in an embodiment of the present application;

FIG. 33 is a circuit diagram of a latch provided in an embodiment of the present application;

FIG. 34 is a circuit diagram of a flip-flop provided by the embodiment of the present application.

Reference signs:

100 - electronic equipment;

200-CPU;

300 - memory;

400-conjugate logic gate circuit;

401 - inverter;

402-buffer;

400a-the first conjugate logic gate circuit;

400b-the second conjugate logic gate circuit;

500 - latch;

500a - first latch;

500b - second latch;

600 - trigger;

700-NAND gate circuit;

700a-the first NAND gate circuit;

700b-the second NAND gate circuit;

700c-the third NAND gate circuit;

700d-the fourth NAND gate circuit;

800-CLKINV;

800a - first CLKINV; 800b - second CLKINV;

900-NOR gate circuit;

01-channel;

02 - the first electrode;

03 - the second electrode;

04-the first gate dielectric layer;

05-the second gate dielectric layer;

061-the first grid; 062-the second grid.

Detailed ways

Before introducing the embodiments involved in this application, first introduce the technical terms involved in this application, specifically as follows:

Pull-up refers to clamping the signal at a high level.

Pull-down refers to clamping the signal at a low level.

Logic level, the level of voltage in digital circuits is represented by logic level, including high level and low level. Among them, high level is represented by "1" and low level is represented by "0". Digital circuits formed by different components have different logic levels corresponding to voltages.

An amorphous oxide semiconductor transistor is also called an amorphous (noncrystalline) oxide semiconductor transistor, or a transistor using an amorphous oxide as a channel layer.

Short-channel effect (short-channel effect): It is some effects that appear in the transistor when the conductive channel length of the metal oxide semiconductor field effect transistor is reduced to a certain level (such as tens of nanometers, or even a few nanometers). These effects mainly include threshold voltage decrease with channel length decrease, drain-induced barrier decrease, carrier surface scattering, velocity saturation, ionization and hot electron effects, etc.

Static holding stage: refers to the state in which the input and output remain unchanged. It can also be interpreted as: in a static logic circuit, a stable input signal keeps the MOS transistor on or off, thereby maintaining a stable output state, that is static hold phase.

The following embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

The technical solution of the present application can be applied to various devices including integrated circuits. For example, FIG. 1 is a circuit block diagram of an electronic device 100 provided in the embodiment of the present application, and the electronic device 100 can be a terminal device , such as mobile phones, tablet computers, smart bracelets, and various types of computing devices such as personal computers (personal computers, PCs), servers, and workstations.

Exemplarily, as shown in FIG. 1 again, the electronic device 100 may include a memory 300, a central processing unit (central processing unit, CPU) 200, and the like. Wherein, the CPU 200 may be electrically connected to the memory 300 through a bus.

In the above-mentioned devices such as the CPU 200 and the memory 300, there are integrated circuits including logic gates. Logic gates can include "AND gates", "OR gates", "NOT gates", "NAND gates", "NOR gates", "XOR gates" and so on. These logic gates can also be used in combination to implement more complex logic operations.

The embodiment of the present application provides a logic gate circuit, the logic gate circuit is a conjugate logic gate circuit, the conjugate logic gate circuit can be cascaded, in addition, it also overcomes the existing unipolar logic gate circuit technology has the problem of large static power consumption. See the following for specific implementation methods.

FIG. 2 is a circuit diagram of a conjugate logic gate circuit 400 provided in an embodiment of the present application. As shown in FIG. 2 , the conjugate logic gate circuit 400 includes an inverter 401 and a buffer 402 , and the inverter 401 and the buffer 402 are connected in parallel to the first DC voltage terminal and the second DC voltage terminal. For example, the inverter 401 and the buffer 402 are connected in parallel between the power supply voltage VDD and the ground.

Wherein, the inverter 401 has an input port IN, a conjugate input port IN', and an output port. Buffer 402 also has an input port IN and a conjugate input port IN', and an output port.

The input port of the inverter 401 is coupled to the input port of the buffer 402 to form the input port IN of the conjugate logic gate circuit 400, and the conjugate input port of the inverter 401 is coupled to the conjugate input port of the buffer 402. , forming the conjugate input port IN′ of the conjugate logic gate circuit 400 . One of the output port of the inverter 401 and the output port of the buffer 402 forms the output port OUT of the conjugate logic gate circuit 400, and the other forms the conjugate output port OUT' of the conjugate logic gate circuit 400.

Based on the above description of the circuit diagram of the conjugate logic gate circuit 400 involved in the present application, it can be seen that, as shown in Figure 3, Figure 3 provides the circuit symbol of the conjugate logic gate circuit 400 of the present application, wherein the black dotted line Represents the signal line conjugated with black. It can be understood that the conjugated logic gate circuit 400 provided in this application is an inverter (Inverter) including a conjugated input port and a conjugated output port as shown in FIG. 3 , wherein the input and the conjugated The conjugated inputs (IN and IN') can come from the output of the previous stage and the conjugated outputs (OUT and OUT').

Therefore, if the conjugate logic gate circuit 400 is applied in a more complex circuit, cascade connection can be realized. For example, in some scenarios, when the conjugate logic gate circuit 400 shown in FIG. 2 can be applied to an SRAM memory, FIG. 4 is a circuit diagram of one of the storage units in the SRAM memory. In this storage unit, the first conjugate logic gate circuit 400a and the second conjugate logic gate circuit 400b formed by the logic gate circuit shown in Fig. 2 are included, the first conjugate logic gate circuit 400a and the second conjugate logic gate circuit 400a are Gate circuit 400b is electrically connected to form the core structure of the memory cell.

4, the input port IN of the first conjugate logic gate circuit 400a is connected to the output port OUT of the second conjugate logic gate circuit 400b, and the output port OUT of the first conjugate logic gate circuit 400a is connected to the second conjugate logic gate circuit 400b. The input port IN in the logic gate circuit 400b is connected, the conjugate input port IN' of the first conjugate logic gate circuit 400a is connected to the conjugate output port OUT' of the second conjugate logic gate circuit 400b, the first conjugate logic gate circuit The conjugated output port OUT' of the circuit 400a is connected to the conjugated input port IN' of the second conjugated logic gate circuit 400b. In this way, the cascade connection of the first conjugate logic gate circuit 400a and the second conjugate logic gate circuit 400b is realized.

Figure 5 shows a logic gate circuit in the related art that can also be cascaded. In this logic gate circuit, the gate and drain of the transistor T1 are short-circuited and used as a pull-up transistor, and the transistor T2 is a pull-down transistor. .

In the logic gate circuit shown in FIG. 5 , when the transistor T2 is turned on, since the gate and the drain of the transistor T1 are short-circuited, the transistor T1 is also turned on. In this case, it will result in a large high quiescent leakage current and a large power consumption.

Based on the logic gate circuit of the related art above, the conjugate logic gate circuit 400 of the present application can also achieve low static power consumption, and the specific circuit structure and function are described as follows.

As shown in FIG. 2 , one of the circuit structures that can be realized by the inverter 401 and the buffer 402 is shown. In this implementation structure, the inverter 401 includes a first transistor T1 and a third transistor T3, the first transistor T1 and the third transistor T3 are connected in series, and are electrically connected between the first DC voltage terminal and the second DC voltage terminal; The buffer 402 includes a second transistor T2 and a fourth transistor T4, the second transistor T2 and the fourth transistor T4 are connected in series and electrically connected between the first DC voltage terminal and the second DC voltage terminal.

Realizable circuit structures of the inverter 401 and the buffer 402 include those shown in FIG. 2 , but are not limited to those shown in FIG. 2 . For example, transistors can also be added on the basis of FIG. 2 , and the added transistors can be connected in series with the first transistor T1 and the third transistor T3 , or in parallel, or a combination of series and parallel. The structure of the inverter 401 and the buffer 402 shown in FIG. 2 is taken as an example for introduction below.

Wherein, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may all be electronic field effect transistors (N-type field effect transistors, NFETs), and may also be called N-channel field effect transistors; or These transistors are all hole-type field effect transistors (P-type field effect transistors, PFETs), and can also be called P-channel field effect transistors. For example, FIG. 2 illustrates that all transistors in the conjugate logic gate circuit 400 are NFET transistors, and FIG. 6 illustrates that all transistors in the conjugate logic gate circuit 400 are PFET transistors. That is to say, the conjugate logic gate circuit given in this application is a unipolar conjugate logic gate.

Taking the NFET conjugate logic gate circuit 400 shown in FIG. 2 as an example, the first electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2, and is used to electrically connect the first DC voltage terminal, for example, as The first electrode of the first transistor T1 and the first electrode of the second transistor T2 shown in FIG. 2 and FIG. 6 are both connected to the power supply voltage VDD.

The second electrode of the first transistor T1 is electrically connected to the first electrode of the third transistor T3 , that is, the first transistor T1 and the third transistor T3 are connected in series to form an output port OUT of the conjugate logic gate circuit 400 .

The gate of the second transistor T2 is electrically connected to the gate of the third transistor T3 to form an input port IN of the conjugate logic gate circuit 400 .

The second electrode of the third transistor T3 is electrically connected to the second electrode of the fourth transistor T4, and is used to electrically connect to the second DC voltage terminal, such as Vss or ground (Ground, GND).

The first electrode of the fourth transistor T4 is electrically connected to the second electrode of the second transistor T2, that is, the second transistor T2 and the fourth transistor T4 are connected in series, and form a conjugate output port OUT' of the conjugate logic gate circuit 400.

The gate of the fourth transistor T4 is electrically connected to the gate of the first transistor T1, and forms a conjugate input port IN' of the conjugate logic gate circuit 400 .

As shown in Figure 2 and Figure 6, since both the first transistor T1 and the second transistor T2 are connected to the power supply voltage VDD, the first transistor T1 and the second transistor T2 can be considered as pull-up transistors, except that the third transistor Both T3 and the fourth transistor T4 can be grounded, then the third transistor T3 and the fourth transistor T4 can be regarded as pull-down transistors.

It should be noted that: the first electrode of the transistor referred to in this application refers to one of the source and the drain, and the second electrode of the transistor refers to the other of the source and the drain. For example, in the conjugate logic gate circuit 400 formed by NFET transistors shown in FIG. 2 , the first electrode of the first transistor T1 refers to the drain connected to the power supply voltage VDD, and the second electrode is the source. Similarly, in the conjugate logic gate circuit 400 formed by PFET transistors shown in FIG. 5 , for the PFET transistors, the source connected to the power supply voltage VDD and the other electrode is the drain.

In addition, it needs to be explained that: the input port IN and the conjugated input port IN' refer to: the conjugated and inverted phase of the signal transmitted by the input port IN and the signal transmitted by the conjugated input port IN'. The output port OUT and the conjugated output port OUT' refer to: the conjugated and inverted phase of the signal transmitted by the output port OUT and the signal transmitted by the conjugated output port OUT'. For example, the inversion or conjugate signal of a high level "1" is a low level "0". In implementation, the initial conjugate input IN' can be specifically realized by IN passing through a single-input and single-output inverter (such as a single-input and single-output CMOS inverter), and the subsequent conjugate input IN' can be generated by The last conjugate output OUT' is generated.

The NFET-type conjugate logic gate circuit 400 shown in FIG. 2 is taken as an example, and its working principle can be understood as: when the input port IN is at a low potential (0V), the conjugate input port IN' is at a high potential (VDD), and the first Both the transistor T1 and the fourth transistor T4 are in the on state, while the second transistor T2 and the third transistor T3 are in the off state, so that VDD charges the next stage load connected to the output port OUT through the first transistor T1 until the output The port OUT terminal reaches VDD or the gate-source voltage (Vgs) of the first transistor T1 is equal to 0V. And the conjugated output port OUT' is connected to the ground through the fourth transistor T4 until 0V. Therefore, the final output port OUT and the conjugate output port OUT' are high potential (VDD or VDD-Vth) and low potential (0V) respectively. Wherein, if the threshold voltages Vth of the pull-up first transistor T1 and the second transistor T2 are both greater than 0, the output port OUT is finally stable at VDD-Vth, otherwise it is stable at VDD.

The conjugate logic gate circuit 400 of the present application can also be understood in this way. The conjugate logic gate circuit 400 of the present application is controlled by a conjugated input signal. In this way, in the static hold phase, the first transistor T1 and The third transistor T3 is turned on at the same time, and the second transistor T2 and the fourth transistor T4 are not turned on at the same time, so that low static leakage can be achieved.

The "leakage current" mentioned in this application refers to: the leakage current between the first voltage source and the second voltage source as shown in Figure 2 and Figure 6, that is, between the first electrode and the second electrode of the transistor leakage current between them.

The following describes how to achieve low static power consumption by using the conjugate logic gate circuit of the present application in conjunction with the memory shown in FIG. 4 .

As shown in FIG. 4 , in the writing operation of the memory cell: the word line WL receives a high-level signal, and both the gate transistor Ts1 and the gate transistor Ts2 are turned on. If the high level is written, the bit line BL receives a high level signal, and the conjugate bit line BL' receives a low level signal. If the input port Q is high level and the output port Q' is low level, that is, the input port When the original signal of Q and output port Q' is the same as the signal of bit line BL and conjugate bit line BL', the signal remains unchanged. If the input port Q is low level and the output port Q' is high level, the bit line The line BL and the conjugated bit line BL' reverse the signals of the input port Q and the output port Q' through two gate transistors, so that the input port Q is at a high level and the output port Q' is at a low level, and then the word line WL receives The low-level signal turns off the gate transistor Ts1 and the gate transistor Ts2, and the levels of the Q and Q' ports that have been written into the signal are held by the positive feedback of the latch structure to complete the write operation. When writing a low level, it is the same as the above-mentioned high level writing process, and will not be repeated here.

After the write operation is complete, a signal static hold phase is included. Then, in the signal static holding phase, in any parallel path of the first conjugated logic gate circuit 400a and the second conjugated logic gate circuit 400b, only one transistor is in the on state, and the other is in the off state. For example, when the transistors in the logic gate circuit are all NFETs, after writing a high level (Q is high level, Q' is low level), the transistor T3a, transistor T2a, transistor T1b and transistor T4b are all in the conduction state. The transistor T1a, the transistor T4a, the transistor T3b and the transistor T2b are all in the off state.

It can also be seen from the memory cells formed above that when the conjugate logic gate circuit 400 provided in the present application is used, low static power consumption can be achieved during the static signal holding phase, thereby reducing the power consumption of the entire SRAM memory.

In addition to realizing low static power consumption, the conjugate logic gate circuit 400 provided in this application has a relatively small number of transistors. As shown in FIG. 6, a conjugate logic gate circuit 400 only includes four transistors. An inverter with conjugate input and conjugate output can be obtained. The structure is simple and the number of transistors is small, which can increase the integration density of the integrated circuit including the logic gate circuit.

In addition, in the conjugate logic gate circuit 400 of the present application, no additional feedback structure and capacitor structure may be needed, and further, high-speed response may be achieved.

In the conjugate logic gate circuit 400 given in this application, there is no special limitation on the structure of the transistor, for example, a single-gate transistor or a double-gate transistor can be used, for example, a single-gate transistor is used in Figure 2 and Figure 6 , as shown in Figure 7a and Figure 7b, a double-gate transistor is used, wherein, in the conjugate logic gate circuit 400 shown in Figure 7a, the double-gate transistor is an NFET type double-gate transistor, and that shown in Figure 7b is a PFET type Conjugate logic gate circuit 400 formed by double-gate transistors.

FIG. 8 exemplarily shows a process structure diagram of a double-gate transistor. Specifically, as shown in FIG. 8, the double-gate transistor includes a first electrode 02 and a second electrode 03, and a The channel 01 between the second electrodes 03. Moreover, the gate of the double-gate transistor includes a first gate 061 and a second gate 062, the first gate 061 is formed on one side of the channel 01 through the first gate dielectric layer 04, and the second gate 062 is formed through the second The gate dielectric layer 05 is formed on the other side of the channel 01 . The first grid 061 may also be called a top gate (Top Gate), and the second grid 062 is called a bottom gate (Bottom Gate).

When the transistors in the conjugate logic gate circuit 400 are double-gate transistors, as shown in FIG. 8 , the first gate 061 and the second gate 062 are connected to the input port or the conjugate input port. For example, when the first transistor T1 is a double-gate transistor, then the connected first gate 061 and the second gate 062 are connected to the conjugate input port IN'.

In some realizable circuit diagrams, all of the first transistor T1 to the fourth transistor T4 can be double-gate transistors as shown in FIG. 7a and FIG. 7b. In other circuit diagrams that can be implemented, some of the first transistor T1 to the fourth transistor T4 use double-gate transistors, and some use transistors with other structures, for example, some use single-gate transistors, and other parts use double-gate transistors.

In the conjugate logic gate circuit 400 using a double-gate transistor, it can better control the channel switch in the case of a short channel, and has a lower sub-threshold swing, so that at a certain threshold voltage (threshold voltage) In the case of a larger on-state current (On Current) and response speed.

In addition, the gate structure of the transistor can be arranged in different ways, for example, it can be a fin field effect transistor, a ring gate transistor, a vertical structure nanowire field effect transistor, and the like.

In addition, the conjugate logic gate circuit 400 of the present application can adjust the threshold voltage (threshold voltage) of the pull-up transistor (the first transistor T1 and the second transistor T2) and the pull-down transistor (the third transistor T3 and the fourth transistor T4). ) are different, so that the threshold voltage Vth of the pull-up transistor is less than or equal to 0, and the threshold voltage Vth of the pull-down transistor is greater than 0, so as to realize zero potential loss of the output of the logic gate circuit.

For example, the different threshold voltage Vth of the pull-up transistor and the pull-down transistor can be realized by adjusting the channel material of the transistor, adjusting the gate work function, adjusting the dipole, and adjusting the back gate voltage.

Several methods for realizing different threshold voltages Vth of the pull-up transistor and the pull-down transistor from the perspective of changing the circuit connection relationship are given below. Moreover, the following adjustment of the threshold voltage of the pull-up transistor and the pull-down transistor is realized on the basis of the double-gate transistor, and the threshold voltage of the transistor when it is turned on is adjusted by adjusting the voltage of one gate of the double-gate.

FIG. 9 is a circuit diagram of a conjugate logic gate circuit 400 of the present application. Specifically, one of the top gate and bottom gate of the double-gate pull-up first transistor T1 can be connected to the output port OUT. Similarly, the top gate and bottom gate of the double-gate pull-up second transistor T2 can be connected One of the gates is connected to the conjugate output port OUT'. This is equivalent to applying an additional gate voltage constant to 0V to the pull-up transistor. By adjusting the gate dielectric thickness corresponding to the gate during manufacture, the threshold voltage Vth of the pull-up transistor can be adjusted equivalently. Similarly, this method can also adjust the threshold voltage of the pull-down transistor, which will not be repeated here.

FIG. 10 shows a process structure diagram of one of the pull-up transistors in FIG. 9 that can adjust the threshold voltage Vth. As shown in Fig. 10, the second gate (bottom gate) 062 is connected to the first electrode 02 of the transistor, because the first electrode 02 is connected to the output port, thereby realizing the electrical connection between the bottom gate and the output port OUT . Besides, the first gate (top gate) 061 is electrically connected to the input port IN.

In some other possible manners, the top gate may also be electrically connected to the output port OUT, and the bottom gate may be electrically connected to the input port IN.

FIG. 11 is a circuit diagram of another conjugate logic gate circuit 400 of the present application. Specifically, one of the top gate and the bottom gate of the double-gate transistor may be connected to the bias voltage Vbias. The threshold voltage of the transistor can be individually adjusted through the Vbias bias, so as to realize different threshold voltages in the pull-up transistor and the pull-down transistor. The bias voltages to which the four transistors are connected can be different.

As shown in FIG. 11 , the gate (top gate or bottom gate) of each transistor in the conjugate logic gate circuit 400 can be connected with the bias voltage Vbias; or, only the gate of the pull-up transistor (top gate or bottom gate) is connected to the bias voltage Vbias, and the pull-down transistor is not connected to the bias voltage Vbias; or, only the gate (top gate or bottom gate) of the pull-down transistor can be connected to the bias voltage Vbias, and the pull-up transistor is not connected to the bias voltage Voltage Vbias. When some transistors are not connected to the bias voltage Vbias, the top gate and bottom gate of the transistors not connected to the bias voltage Vbias can be connected, or connected to the output port.

FIG. 12 shows a process structure diagram of one of the pull-up or pull-down transistors in FIG. 11 that can be realized by adjusting the threshold voltage Vth. Referring to FIG. 12 , the second gate (bottom gate) 062 is connected to the bias voltage Vbias. Adopting this method can be understood as adjusting the threshold voltage Vth through the back gate (bottom gate) voltage.

Certainly, in some other implementable manners, the first gate 061 (top gate) may also be connected to the bias voltage Vbias.

The possible Vth shift of the transistors of the conjugate logic gate circuit 400 given in the present application after long-term operation will lead to the shift of the operating point of the logic circuit, resulting in chaotic logic and timing states. The additional Vbias applied to the back gate can regulate the Vth of the transistor through an external control circuit, and adjust the Vth back to the initial state as needed. The performance of using this logic gate circuit is better.

FIG. 13 is a circuit diagram of another conjugate logic gate circuit 400 of the present application. Specifically, one of the top gate and the bottom gate of the double-gate pull-up first transistor T1 can be connected to the first DC voltage terminal (such as VDD). Similarly, the double-gate pull-up second transistor T1 can be connected to One of the top gate and the bottom gate of T2 is connected to the first DC voltage terminal (such as VDD). The threshold voltage Vth of the pull-up transistor is adjusted by adjusting the thickness of the gate dielectric corresponding to the gate during manufacture.

In some other possible ways, the top gate of the pull-up transistor may also be electrically connected to VDD, and the bottom gate of the pull-up transistor may be electrically connected to the input port IN. Alternatively, the bottom gate of the pull-up transistor may be electrically connected to VDD, and the top gate may be electrically connected to the input port IN.

FIG. 14 is a circuit diagram of another conjugate logic gate circuit 400 of the present application. Specifically, one of the top gate and bottom gate of the double-gate pull-up first transistor T1 can be electrically connected to the output port OUT and VDD through the transistor (also called a voltage regulating transistor) T5. Similarly, the One of the top gate and the bottom gate of the double-gate pull-up second transistor T2 is electrically connected to the conjugated output port OUT′ and VDD through the transistor T6.

Specifically, as shown in Figure 14, the first electrode of the transistor T5 is electrically connected to the gate (first gate or second gate) of the first transistor T1, the second electrode of the transistor T5 is electrically connected to VDD, and the gate of the transistor T5 pole is electrically connected with the output port OUT. The first electrode of the transistor T6 is electrically connected to the gate of the second transistor T2 (the first gate or the second gate), the second electrode of the transistor T6 is electrically connected to VDD, and the gate of the transistor T6 is connected to the conjugate output port OUT' electrical connection. That is to say, by adding an additional transistor structure, the threshold voltage Vth of the pull-up transistor can also be adjusted.

When the threshold voltage adjustment method shown in FIG. 14 is adopted, when the output port Out is at a high potential, that is, when the pull-up transistor is turned on, the output port Out potential control transistor T5 is turned on, and VDD is connected to the gate of the first transistor T1, so that The threshold voltage of the first transistor T1 decreases to be less than or equal to zero.

FIG. 15 is a circuit diagram of another conjugate logic gate circuit 400 of the present application. Specifically, one of the top gate and the bottom gate of the double-gate pull-up first transistor T1 can be electrically connected to the output port OUT and VDD through a feedback circuit (Feedback Circuit). Pulling one of the top gate and the bottom gate of the second transistor T2 is electrically connected to the conjugated output port OUT' and VDD through a feedback circuit (Feedback Circuit). Compared with FIG. 14 above, that is, the transistor can be replaced by a feedback circuit. This feedback circuit can reduce the threshold voltage of the pull-up transistor in real time by increasing the voltage of the gate connected to the feedback circuit when the pull-up transistor is turned on. That is, the threshold voltage of the pull-up transistor itself can be greater than zero, and a real-time threshold voltage less than or equal to zero can be obtained only when it is turned on. This method can further reduce the static power consumption of the logic gate 400 .

In the above-mentioned FIGS. 9 to 15 , the adjustment of the threshold voltage is realized by changing the connection relationship of the electronic components in the logic gate circuit. Compared with changing the internal structure of the transistor, such as changing the channel material and changing the gate material, it is easier to implement from the perspective of technology. Furthermore, the method of adjusting the threshold voltage in Figures 9 to 15 given in this application will not give Craft brings additional complexity. In addition, a better threshold voltage Vth can also be provided. Of course, the threshold voltage can also be adjusted in combination with the adjustment means in the process, such as the adjustment of the gate work function, the adjustment of the dipole, the adjustment of the channel material, and the circuit connection method.

The effect of reducing power consumption and zero potential loss of the above-mentioned conjugate logic gate circuit 400 will be verified in combination with simulation results.

FIG. 16 shows a simulation structure of a conjugate logic gate circuit 400 formed by NFET type transistors. Specifically, in the case of a conjugate input (IN/IN') at 2.5GHz, the conjugate inverter (that is, the conjugate logic gate circuit 400) can realize a conjugate output (OUT/OUT') with zero potential loss . At the same time, under static working conditions, the leakage current (Leakage Current) of the conjugate inverter can be controlled in the order of nA/μm. This result reflects the advantages of the conjugated logic gate structure with small leakage, no potential loss, and fast response.

With the development of semiconductor technology, the three-dimensional stacking of chips is the trend of process development. In the three-dimensional stacking technology of chips, monolithic integration has the advantages of low cost and high interconnection density, and is gradually being widely used. For example, part of the digital logic circuit including the above-mentioned conjugate logic gate circuit 400 can be integrated into one chip with other integrated circuit modules, and the other integrated circuit modules can be processed through the front end of line (FEOL) process. To be integrated in the processor, the digital logic circuit including the above-mentioned conjugate logic gate circuit 400 is integrated in the processor through a back end of line (BEOL) process.

Then, since the digital logic circuit adopts the back end BEOL process, furthermore, the transistor forming the conjugate logic gate circuit 400 not only needs to have high mobility, but also needs to have the characteristics of low temperature growth. For example, in the process means that can be realized, the above-mentioned logic gate circuit can be fabricated by using an electronic amorphous oxide semiconductor (amorphous oxide semiconductor, AOS) field effect transistor.

When the above-mentioned conjugate logic gate circuit 400 is manufactured by adopting the back-end BEOL process, because the conjugate logic gate circuit 400 has the advantages of low static leakage and zero potential loss, it can avoid high power consumption and timing confusion of the back-end logic circuit. Phenomenon.

Based on the above-mentioned conjugate logic gate circuits 400 with various structures, FIG. 17a and FIG. 17b can be derived, as well as the conjugate inverter (CLKINV) controlled by the clock signal CLK shown in FIG. 17c.

As shown in FIG. 17a, the conjugate inverter (CLKINV) 800 controlled by the clock signal CLK includes a transistor Tr1 and a transistor Tr2 in addition to the above-mentioned conjugate logic gate circuit 400 .

Wherein, the second electrode of the transistor Tr1 is electrically connected with the first electrode of the first transistor T1 and the first electrode of the second transistor T2, and the first electrode of the transistor Tr1 is electrically connected with the first voltage source (such as VDD); The first electrode is electrically connected to the second electrode of the third transistor T3 and the second electrode of the fourth transistor T4, and the second electrode of the transistor Tr2 is electrically connected to the second voltage source (such as ground).

Also, the gate of the transistor Tr1 is electrically connected to the gate of the transistor Tr2, and is also electrically connected to the clock signal CLK.

That is to say, the conjugate logic gate circuit 400 provided in this application is electrically connected to the high and low voltage sources respectively through two transistors, and the gates of the two connected transistors are controlled by the clock signal CLK. In this case, the conjugate logic gate circuit 400 can work normally only when CLK is at a high level.

Fig. 17b is the circuit symbol of the conjugated inverter (CLKINV) 800 shown in Fig. 17a, that is, in the conjugated inverter (CLKINV) 800, the input port IN, the conjugated input port IN', the clock signal CLK port, as well as output port OUT and conjugate output port OUT'.

Figure 17c is another conjugate inverter (CLKINV) controlled by the clock signal CLK, and Figure 17b can also be the circuit symbol of the conjugate inverter (CLKINV) formed in Figure 17c. As shown in Fig. 17c, in this circuit structure, in addition to the above-mentioned conjugate logic gate circuit 400, it also includes a transistor Tr1 and a transistor Tr2, and a transistor Tr3 and a transistor Tr4. Wherein, the first transistor T1, the third transistor T3, the transistor Tr1 and the transistor Tr3 are connected in series to form a path, and the second transistor T2, the fourth transistor T4, the transistor Tr2 and the transistor Tr4 are connected in series to form another path.

Also, the gates of the transistor Tr1 and the transistor Tr2, and the transistor Tr3 and the transistor Tr4 are all connected to the clock signal CLK.

Compared with the conjugate inverter (CLKINV) 800 with two different structures shown in Fig. 17a and Fig. 17c, the number of transistors in Fig. 17a is less and the integration level will be higher.

Based on the above-mentioned conjugate logic gate circuits 400 with different structures, various more complex logic operations can be derived, such as "NAND gate", "NOR gate", "XOR gate" etc.

FIG. 18 is a conjugate exclusive OR gate (XOR) logic circuit or an exclusive NOR gate (XNOR) logic circuit derived based on the above conjugate logic gate circuit 400 . Specifically, as shown in Figure 18, the logic gate can output the XOR and XNOR results of A and B by conjugating input A and A', and conjugating B and B'.

In the logic gate circuit shown in FIG. 18, double-gate transistors are used. Of course, single-gate transistors or the above-mentioned transistor structure or connection method with threshold voltage adjustment function can also be used.

FIG. 19 shows yet another conjugate NOR gate (NOR) circuit derived from the above-mentioned conjugate logic gate circuit 400 . As shown in FIG. 19, the conjugate NOR gate (NOR) circuit includes the above-mentioned first transistor T1, second transistor T2, third transistor T3 and fourth transistor T4. In addition, the conjugate NOR gate The (NOR) circuit also includes transistor T7, transistor T8, transistor T9 and transistor T10. The connection relationship of the first transistor T1 , the second transistor T2 , the third transistor T3 and the fourth transistor T4 has been described above, and will not be repeated here.

The first electrode of the transistor T7 is electrically connected to the first DC voltage terminal (such as VDD), and the second electrode of the transistor T7 is electrically connected to the first electrode of the first transistor T1. That is, the transistor T7 and the first transistor T1 are connected in series.

The first electrode of the transistor T8 is electrically connected to VDD, and the second electrode of the transistor T8 is electrically connected to the second electrode of the second transistor T2. That is, the transistor T8 and the second transistor T2 are connected in parallel.

The first electrode of the transistor T9 is electrically connected to the first electrode of the third transistor T3, and the second electrode of the transistor T9 is electrically connected to the second DC voltage terminal (such as ground). That is, the transistor T9 and the third transistor T3 are connected in parallel.

The first electrode of the transistor T10 is electrically connected to the second electrode of the fourth transistor T4, and the second electrode of the transistor T10 is electrically connected to the second DC voltage terminal (such as ground). That is, the transistor T10 and the fourth transistor T4 are connected in series.

It should be explained that, in the NOR circuit shown in FIG. 19 , the connection relationship of the gates of each transistor is not shown. Specifically, the gate of the first transistor T1 is electrically connected to the gate of the fourth transistor T4 to form a conjugate input port A'; the gate of the second transistor T2 is electrically connected to the gate of the third transistor T3 to form an input Port A; the gate of transistor T7 is electrically connected to the gate of transistor T10 to form a conjugate input port B'; the gate of transistor T8 is electrically connected to the gate of transistor T9 to form input port B. Thus, the NOR gate output port (A+B)' shown in FIG. 19 and the NOR gate conjugate output port A+B are formed.

What Fig. 20 shows is the circuit symbol of the circuit diagram of Fig. 19, combined with Fig. 19 and Fig. 20, it can be seen that the NOR gate (NOR) includes two sets of conjugated input ports (including A/A' and B/B'), and two conjugated output ports (including (A+B)'/A+B).

In the NOR gate circuit shown in FIG. 19, for example, the first transistor T1 is turned on, the third transistor T3 is turned off, the transistor T7 is turned on, and the transistor T9 is turned off. That is to say, the transistors on the path between the first DC voltage terminal and the second DC voltage terminal will not be turned on at the same time, so that the static power consumption of the NOR gate (NOR) circuit can be reduced.

As another example, FIG. 21 shows a conjugate NAND gate (NAND) circuit based on the above-mentioned logic gate circuit. As shown in FIG. 21, the conjugate NAND gate (NAND) circuit includes the above-mentioned first transistor T1, second transistor T2, third transistor T3 and fourth transistor T4, the conjugate NAND gate (NAND ) circuit also includes a transistor T7, a transistor T8, a transistor T9 and a transistor T10. The connection relationship of the first transistor T1 , the second transistor T2 , the third transistor T3 and the fourth transistor T4 has been described above, and will not be repeated here.

The first electrode of the transistor T7 is electrically connected to the first DC voltage terminal (such as VDD), and the second electrode of the transistor T7 is electrically connected to the second electrode of the first transistor T1. That is, the transistor T7 and the first transistor T1 are connected in parallel.

The first electrode of the transistor T8 is electrically connected to VDD, and the second electrode of the transistor T8 is electrically connected to the first electrode of the second transistor T2. That is, the transistor T8 and the second transistor T2 are connected in series.

The first electrode of the transistor T9 is electrically connected to the second electrode of the third transistor T3, and the second electrode of the transistor T9 is electrically connected to the second DC voltage terminal (such as ground). That is, the transistor T9 and the third transistor T3 are connected in series.

The first electrode of the transistor T10 is electrically connected to the first electrode of the fourth transistor T4, and the second electrode of the transistor T10 is electrically connected to the second DC voltage terminal (such as ground). That is, the transistor T10 and the fourth transistor T4 are connected in parallel.

In the NAND gate circuit shown in FIG. 21 , the connection relationship of the gates of the respective transistors is not shown. Specifically, the gate of the first transistor T1 is electrically connected to the gate of the fourth transistor T4 to form a conjugate input port A'; the gate of the second transistor T2 is electrically connected to the gate of the third transistor T3 to form an input Port A; the gate of transistor T7 is electrically connected to the gate of transistor T10 to form a conjugate input port B'; the gate of transistor T8 is electrically connected to the gate of transistor T9 to form input port B. Thus, the NAND gate output port (AB)' shown in Fig. 21, and the NAND gate conjugate output port AB are formed.

What Fig. 22 shows is the circuit symbol of the circuit of Fig. 21, in combination with Fig. 21 and Fig. 22, it can be seen that the NAND gate (NAND) includes two sets of conjugated input ports (including A/A' and B/B'), and two conjugated output ports (including (AB)'/AB).

Similarly, in the NAND gate circuit shown in FIG. 21 , for example, the first transistor T1 is turned on, the third transistor T3 is turned off, the transistor T7 is turned on, and the transistor T9 is turned off. That is, the transistors on the path between the first DC voltage terminal and the second DC voltage terminal will not be turned on at the same time, so that the static power consumption of the NAND gate (NAND) circuit can also be reduced.

In addition, due to the existence of the conjugate output, the above-mentioned NAND gate (NAND) and NOR gate (NOR) can also be used as an AND gate (AND) and an OR gate (OR) at the same time.

The pole type of transistor T7, transistor T8, transistor T9 and transistor T10 in the above-mentioned NAND gate (NAND) circuit or NOR gate (NOR) circuit, and the first transistor T1, the second transistor T2, the third transistor T3 It is the same as the pole type of the fourth transistor T4. For example, in FIG. 19, the NOR gate (NOR) formed when the first transistors T1 to T10 are all NFET transistors can be called a unipolar N-type conjugate NOR gate; similarly, if the first transistors T1 to The logic gate formed when the transistors T10 are all PFET transistors can be called a unipolar P-type conjugate NOR gate.

19 to 22 are only exemplary partial logic gates formed based on the above-mentioned conjugate logic gate circuit 400. In other implementations, more complex logic gate circuits can also be formed, such as NOR gates (And- Or-Inverter, AOI) Adder (Full-Adder), Decoder (Decoder), etc., will not be exhaustive here.

The latches and flip-flops formed based on the NAND gates (NAND) of FIG. 21 and FIG. 22 are also given below. For example, FIG. 23 shows a circuit diagram of a D latch (Latch) 500, and FIG. 24 shows a circuit diagram of a D flip-flop (Flip Flop) 600. The two circuit structures are introduced respectively below.

See the latch 500 shown in FIG. 23 , which includes a first NAND gate circuit 700a, a second NAND gate circuit 700b, a third NAND gate circuit 700c and a fourth NAND gate circuit 700d. The first NAND gate circuit 700a, the second NAND gate circuit 700b, the third NAND gate circuit 700c and the fourth NAND gate circuit 700d all adopt the NAND gate circuit structure shown in FIG. 21 .

The latch 500 shown in FIG. 23 can be simply understood in this way, each NAND gate circuit in the latch 500 includes a first group of conjugated input ports and a second group of conjugated input ports, and the output port and the conjugate output port. As shown in Figure 23, the input ports of the first group of conjugates are A and A', and the input ports of the second group of conjugates are B and B'.

Wherein, the port A of the first NAND gate circuit 700a is electrically connected to the port B' of the second NAND gate circuit 700b, and is used for electrically connecting the input signal D.

The port A' of the first NAND gate circuit 700a is electrically connected to the port B of the second NAND gate circuit 700b, and is used for electrically connecting the inverted input signal D'.

The port B of the first NAND gate circuit 700a is electrically connected to the port A of the second NAND gate circuit 700b, and is used for electrically connecting the clock signal CLK.

The port B' of the first NAND gate circuit 700a is electrically connected to the port A' of the second NAND gate circuit 700b, and is used for electrically connecting the inverse clock signal CLK'.

The output port of the first NAND gate circuit 700a is electrically connected to the port A of the third NAND gate circuit 700c, and the conjugate output port of the first NAND gate circuit 700a is connected to the port A' of the third NAND gate circuit 700c. electrical connection.

The output port of the second NAND gate circuit 700b is electrically connected with the port B of the fourth NAND gate circuit 700d, and the conjugate output port of the second NAND gate circuit 700b is connected with the port B' of the fourth NAND gate circuit 700d. electrical connection.

Port B of the third NAND gate circuit 700c is electrically connected to the conjugate output port of the fourth NAND gate circuit 700d, and the conjugate output port of the fourth NAND gate circuit 700d forms the conjugate output of the latch Port Q'.

The port B' of the third NAND gate circuit 700c is electrically connected to the output port of the fourth NAND gate circuit 700d.

Port A of the fourth NAND gate circuit 700d is electrically connected to the conjugate output port of the third NAND gate circuit 700c, and the conjugate output port of the third NAND gate circuit 700c forms the output port Q of the latch .

The port A' of the fourth NAND gate circuit 700d is electrically connected to the output port of the third NAND gate circuit 700c.

It can be seen from the latch 500 shown in FIG. 23 that it does not contain other logic gate structures except four NAND gate circuits.

FIG. 24 is a circuit diagram of a flip-flop 600 based on the latch structure described in FIG. 23 . Specifically, the flip-flop 600 includes a first latch 500a and a second latch 500b. Moreover, the output port Q of the first latch 500a is electrically connected to the input signal D of the second latch 500b, and the output port Q' of the first latch 500a is connected to the inverted input signal D' of the second latch 500b. electrical connection.

FIG. 25 shows the timing simulation results of the three-level cascaded D flip-flop composed of unipolar (N-type) conjugate NAND logic gates shown in FIG. 24 . From Figure 25, it can be concluded that when CLK is on the falling edge (from 1 to 0), the Data signal can be transmitted to the Q output of the flip-flop (DFF1-3 in Figure 25 refers to the first stage to the Q output corresponding to the third stage flip-flop). It can be seen that the output Q of DFF1 flips according to the Data input at the falling edge of CLK, and remains unchanged at other times. However, because DFF2 and DFF3 are cascaded in the second and third stages, it is necessary to wait for the output Q of DFF1 to flip on the first CLK falling edge, and then wait until the second and third CLK falling edges to flip. This means that D is transferred to the output of DFF1 on the first falling edge of CLK, transferred from the output of DFF1 to the output of DFF2 on the second falling edge of CLK, and so on. That is to say, the conjugate logic structure of the logic gate circuit presented in this application can meet the requirement of cascading complex logic circuits.

In some other realizable digital circuits, on the basis of those shown in FIG. 23 and FIG. 24 , more logic gate circuits provided by the embodiments of the present application may be included to form more complex logic combinations and sequential circuits.

Except, the D latch shown in FIG. 23 and the D flip-flop shown in FIG. 24 are both formed by using the NAND gate circuits shown in FIG. 21 and FIG. 22 . Of course, it can also be formed by the NOR gate circuit shown in FIG. 19 and FIG. 20 , or formed by a combination of NAND gate and NOR gate circuit.

Based on the above-mentioned conjugate logic gate circuits 400 with various structures, more latch and flip-flop circuits can be derived. Several latch and flip-flop circuits are also given below, and the specific structure is shown below.

FIG. 26 is a circuit diagram of a D latch (Latch), and FIG. 27 is a circuit structure that can be realized in FIG. 26 . Specifically, in combination with FIG. 26 and FIG. 27 , the D latch 500 includes any one of the above-mentioned conjugate logic gate circuits 400 , and the gate transistor Ts1 and the gate transistor Ts2 . Wherein, the gate of the gate transistor Ts1 is connected with the gate gate of the gate transistor Ts2, and is electrically connected with the clock signal CLK, and the first electrode of the gate transistor Ts1 is electrically connected with the input port IN of the conjugated logic gate circuit 400, and gate The second electrode of the transistor Ts1 is electrically connected to the input signal D, the first electrode of the gate transistor Ts2 is electrically connected to the conjugate input port IN' of the conjugate logic gate circuit 400, and the second electrode of the gate transistor Ts2 is electrically connected to the reverse input signal D 'Electrically connected. In this case, for example, when the clock signal CLK is at a high potential, the input signal D is output as an inverted signal through the conjugate logic gate circuit 400 .

Moreover, in the exemplary D-latch shown in FIG. 27 , the transistors in the conjugate logic gate circuit 400 are double-gate transistors, and the top gate and the bottom gate of the double-gate transistors are electrically connected. Certainly, the conjugate logic gate circuit 400 may be one or a mixture of the different gate connection methods shown above.

As shown in Figure 28 is a circuit diagram of a D flip-flop (Flip Flop), and Figure 29 is a circuit structure that can be realized in Figure 28. 26 and FIG. 28, it can be seen that a plurality of (at least two) latches 500 shown in FIG. 26 are connected in series to obtain a flip-flop 600, for example, the first latch 500a of FIG. By connecting with the second latch 500b, the flip-flop 600 shown in FIG. 28 can be obtained.

The circuit structure of the D flip-flop 600 is described in detail in combination with FIG. 28 and FIG. 29. In the D flip-flop 600, a first conjugate logic gate circuit 400a, a second conjugate logic gate circuit 400b, and a gate transistor Ts11 are included. , the gate tube Ts12, the gate tube Ts12 and the gate tube Ts22.

Wherein, the gate of the gate transistor Ts11 is connected to the gate gate of the gate transistor Ts21, and is electrically connected to the clock signal CLK, and the first electrode of the gate transistor Ts11 is connected to the input port IN1 of the first conjugate logic gate circuit 400a, The second electrode of the gate transistor Ts11 is connected to the input signal D, the first electrode of the gate transistor Ts21 is connected to the conjugate input port IN1' of the first conjugate logic gate circuit 400a, and the second electrode of the gate transistor Ts21 is connected to the reverse The input signal D' is connected; the gate of the gate of the gate of the gate Ts12 is connected with the gate of the gate of the gate Ts22, and is electrically connected with the anti-clock signal CLK', and the first electrode of the gate of the gate Ts12 is connected with the second conjugate logic gate circuit 400b The input port IN2 of the gating transistor Ts12 is connected to the output port OUT of the first conjugate logic gate circuit 400a, the first electrode of the gating transistor Ts22 is connected to the conjugate input of the second conjugate logic gate circuit 400b port IN2', the second electrode of the gate transistor Ts22 is connected to the conjugated output port OUT' of the first conjugated logic gate circuit 400a, and the output port of the second conjugated logic gate circuit 400b forms the output port of the flip-flop 600 Q, the conjugated output port of the second conjugated logic gate circuit 400 b forms the conjugated output port Q′ of the flip-flop 600 .

In the latch 500 shown in FIG. 26 and the flip-flop 600 shown in FIG. 28, the gate transistor can be of the same pole type as the transistor in the logic gate circuit, for example, both use NFET transistors, or both use PFET transistors .

In the D flip-flop shown in Figure 28 and Figure 29, the voltage is input through the gates at IN1 and IN1'. When the clock signal CLK is a high voltage, the input signals D and D' charge the gate capacitance of IN1 and IN1' to CLK-Vth (Vth is the threshold voltage of the gate transistor Ts11/Ts21); when the clock signal is a low voltage, The voltage at the IN1 terminal will be maintained for a certain period of time according to the leakage of the gate tube and the gate capacitance; after a certain period of time, it is necessary to raise the CLK to a high level for refreshing to prevent IN1 from powering down.

In addition, in the D flip-flop shown in Fig. 28 and Fig. 29, the number of transistors is 12. In this case, the number of transistors is less than that of the traditional CMOS D flip-flop. For example, the flip-flop is applied to process In the processor, high-density integration of the processor can be realized. In addition, when these transistors are all made of amorphous oxide semiconductor transistors, the digital logic circuit can be manufactured by subsequent processes to realize three-dimensional and high-density integration of semiconductor devices.

Based on the above-mentioned conjugate logic gate circuit 400 of different structures, as shown in Figure 30 is a circuit diagram of another D latch (Latch) comprising the above-mentioned conjugate logic gate circuit 400, Figure 31 is a kind of Figure 30 possible circuit configurations. 30 and 31 together, in the latch 500, it includes a first conjugate logic gate circuit 400a, a second conjugate logic gate circuit 400b, and a gate transistor T1+, a gate transistor T1-, a selector Through tube T2+ and gate tube T2-.

Wherein, the input port IN of the first conjugate logic gate circuit 400a is connected to the output port OUT of the second conjugate logic gate circuit 400b through the gate transistor T2+, and the conjugate input port IN of the first conjugate logic gate circuit 400a 'Connect to the conjugate output port OUT of the second conjugate logic gate circuit 400b through the gate transistor T2-, that is, the first electrode of the gate transistor T2+ is connected to the input port IN of the first conjugate logic gate circuit 400a connection, the second electrode of the gate transistor T2+ is connected to the output port OUT in the second conjugate logic gate circuit 400b; the first electrode of the gate transistor T2- is connected to the conjugate input port in the first conjugate logic gate circuit 400a IN' connection, the second electrode of the gate transistor T2- is connected to the conjugate output port OUT' in the second conjugate logic gate circuit 400b; and, the gate of the gate transistor T2+ and the gate of the gate transistor T2- Both are electrically connected to the inverse clock signal CLK'.

Also, in combination with Fig. 30 and Fig. 31, the output port OUT of the first conjugate logic gate circuit 400a is connected to the input port IN of the second conjugate logic gate circuit 400b, and the conjugate output of the first conjugate logic gate circuit 400a The port OUT' is connected to the conjugated input port IN' of the second conjugated logic gate circuit 400b. That is to say, the first conjugate logic gate circuit 400a and the second conjugate logic gate circuit 400b shown in FIG. 30 and FIG. 31 are connected to form a ring structure.

Continuing with Fig. 30 and Fig. 31, in the latch 500, the first electrode of the gate transistor T1+ is connected to the input port IN of the first conjugate logic gate circuit 400a, and the second electrode of the gate transistor T1+ is connected to the input signal D is connected; the first electrode of the gate transistor T1- is connected to the conjugate input port IN' of the first conjugate logic gate circuit 400a, and the second electrode of the gate transistor T1- is connected to the inverting input signal D'. Both the gate of the gate transistor T1+ and the gate of the gate transistor T1 − are electrically connected to the clock signal CLK.

The output port of the first conjugate logic gate circuit 400a is connected to the input port of the second conjugate logic gate circuit 400b, and forms the output port OUT of the latch 500, the conjugate output of the first conjugate logic gate circuit 400a port is connected to the conjugate input port of the second conjugate logic gate circuit 400b and forms the conjugate output port OUT′ of the latch 500 .

Such as the latch structure shown in FIG. 30, FIG. 31 exemplarily shows that the transistors in the first conjugated logic gate circuit 400a and the second conjugated logic gate circuit 400b are all NFET transistors, and the gate transistors T1+ to The gate tube T2- also adopts NFET transistor. Of course, in some other possible circuit structures, transistors with other structures can also be used for the gate transistor T1+ to the gate transistor T2 −.

Based on the above description of the circuit structure of the latch 500 shown in FIG. 30 and FIG. 31, it can be analyzed that a latch 500 structure includes 12 transistors, and the number of transistors is relatively small. When the latch is applied in When used in integrated circuits, it can pave the way for the high integration of integrated circuits.

Continuing to combine Figure 30 and Figure 31 together, in this D latch structure, when the clock signal CLK is at a high level, both the gate transistor T1+ and the gate transistor T1- are turned on, and the gate transistor T2+ and the gate transistor T2 - Both are closed, the input signal D and the inverted input signal D' are written into the first conjugate logic gate circuit 400a, and output to the output port Out and the conjugate output port Out'; when the clock signal CLK is low level, the gate Both the transistor T1+ and the gate transistor T1- are turned off, and the gate transistor T2+ and the gate transistor T2- are both turned on. The ring latch starts to form a stable closed-loop feedback and stores the input signal when the clock signal is at a high level.

As shown in FIG. 32 is a circuit diagram of a D flip-flop (Flip Flop). Comparing FIG. 30 and FIG. 32 , it can be seen that a flip-flop 600 can be obtained by connecting at least two latches 500 shown in FIG. 30 in series. For example, the flip-flop 600 shown in FIG. 32 can be obtained by connecting the first latch 500a and the second latch 500b in FIG. 30 .

Specifically, as shown in FIG. 32 , the second electrode of the gate transistor T1+ of the second latch 500b is connected to the output port OUT of the first latch 500a, and the gate transistor T1- of the second latch 500b The second electrode is connected to the conjugate output port OUT' of the first latch 500a.

In addition, the output port of the second latch 500b forms the output port Q of the flip-flop 600, and the conjugate output port of the second latch 500b forms the conjugate output port Q' of the flip-flop 600.

That is to say, by cascading two ring-structured D-latches, and adopting a clock signal and an inverted clock signal in the first and second-level D-latches respectively, a falling clock signal-triggered D flip-flop can be realized.

In the flip-flop 600 shown in FIG. 32, not only the number of transistors is small, but also the advantage of having a long data retention time (no need for refresh operation) can be realized.

FIG. 33 is a circuit diagram of another latch 500 provided in the embodiment of the present application, and FIG. 34 is a realizable circuit structure of FIG. 33 . Combined with FIG. 33 and FIG. 34 , the latch 500 includes the first CLKINV 800 a and the second CLKINV 800 b belonging to CLKINV described above, and the NAND gate circuit 700 described above.

Specifically, the output port of the first CLKINV800a is electrically connected to the port A of the NAND circuit 700, and the conjugate output port of the first CLKINV800a is electrically connected to the port A' of the NAND circuit 700.

The port B of the NAND gate circuit 700 is used for electrically connecting the set signal SET, and the port B' of the NAND gate circuit 700 is used for electrically connecting the inverted set signal SET'.

A point where the output port of the first CLKINV 800 a is electrically connected to the port A of the NAND circuit 700 is electrically connected to the output port of the second CLKINV 800 b.

A point where the conjugate output port of the first CLKINV800a is electrically connected to the port A' of the NAND circuit 700 is electrically connected to the conjugate output port of the second CLKINV800b.

And, the output port of the NAND gate circuit 700 is electrically connected with the input port IN of the second CLKINV800b, and forms the output port OUT of the latch 500, and the conjugate output port of the NAND gate circuit 700 is the conjugate of the second CLKINV800b The input port IN' is electrically connected to form a conjugate output port OUT' of the latch 500; another input port of the second CLKINV 800b is electrically connected to the inverse clock signal CLK'.

In addition, the input port IN of the first CLKINV800a is used for electrically connecting the input signal D, the conjugate input port IN' is used for electrically connecting the inverted input signal D', and another input port is used for electrically connecting the clock signal CLK.

In the structural diagram that can be realized shown in FIG. 34 , the transistors in CLKINV and the transistors in the NAND circuit both use N-type single-gate transistors. Of course, the latch 500 includes, but is not limited to, the single-gate transistor shown in FIG. 34 .

The above is only a part of the logic operation circuit including the conjugate logic gate circuit 400 shown in FIG. 3 provided in this application. Of course, there may be more logic operation circuit structures, which will not be exhausted here.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

The above is only the specific implementation of the application, but the scope of protection of the application is not limited thereto. Anyone familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the application, and should cover Within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

A conjugate logic gate circuit, characterized in that it comprises:

Unipolar inverters and unipolar buffers;

The inverter and the buffer are connected in parallel between the first DC voltage terminal and the second DC voltage terminal;

Both the inverter and the buffer have an input port and a conjugate input port, and an output port;

Wherein, the input port of the inverter is electrically connected to the input port of the buffer to form a first input port of the conjugate logic gate circuit;

The conjugate input port of the inverter is electrically connected to the conjugate input port of the buffer to form a first conjugate input port of the conjugate logic gate circuit;

One of the output port of the inverter and the output port of the buffer forms the output port of the conjugate logic gate circuit, and the other forms the conjugate output port of the conjugate logic gate circuit.
The conjugate logic gate circuit according to claim 1, wherein the inverter comprises a first transistor and a third transistor, and both the first transistor and the third transistor comprise a first gate;

The first transistor and the third transistor are connected in series between the first DC voltage terminal and the second DC voltage terminal;

The first gate of the first transistor is the first conjugate input port;

The first gate of the third transistor is the first input port;

A point where the first transistor and the third transistor are electrically connected is an output port of the conjugate logic gate circuit.
The conjugate logic gate circuit according to claim 2, wherein the buffer comprises a second transistor and a fourth transistor, and both the second transistor and the fourth transistor comprise a first gate;

The second transistor and the fourth transistor are connected in series between the first DC voltage terminal and the second DC voltage terminal;

The first gate of the second transistor is the first input port;

The first gate of the fourth transistor is the first conjugate input port;

A point where the second transistor and the fourth transistor are electrically connected is a conjugate output port of the conjugate logic gate circuit.
The conjugate logic gate circuit according to claim 2 or 3, characterized in that,

The first transistor also includes a second gate;

The second gate is electrically connected to the output port of the conjugate logic gate circuit.
The conjugate logic gate circuit according to claim 2 or 3, wherein at least one of the first transistor and the third transistor further includes a second gate;

The second grid is electrically connected to a bias voltage.
The conjugate logic gate circuit according to claim 2 or 3, characterized in that,

The first transistor also includes a second gate;

The second grid is electrically connected to the first DC voltage terminal.
The conjugate logic gate circuit according to claim 5 or 6, wherein the conjugate logic gate circuit further comprises a voltage regulating transistor;

The first electrode of the voltage regulating transistor is electrically connected to the second gate, and the second electrode is electrically connected to the first DC voltage terminal;

The gate of the voltage regulating transistor is electrically connected to the output port of the conjugate logic gate circuit.
The conjugate logic gate circuit according to claim 5 or 6, wherein the conjugate logic gate circuit further comprises a feedback circuit;

The feedback circuit is electrically connected to the second gate, and the feedback circuit is also electrically connected to the first DC voltage terminal and the output port of the conjugate logic gate circuit respectively.
The conjugate logic gate circuit according to any one of claims 4-8, characterized in that, by adjusting the voltage of the second gate of the first transistor, the threshold value of the first transistor when it is turned on The voltage is less than or equal to zero.
The conjugate logic gate circuit according to any one of claims 3-9, characterized in that,

The first transistor, the second transistor, the third transistor and the fourth transistor are all N-type transistors, or all are P-type transistors.
The conjugate logic gate circuit according to any one of claims 1-10, wherein the conjugate logic gate circuit further comprises:

a first gating tube and a second gating tube;

Wherein, the gate of the first gate transistor and the gate of the second gate transistor are both used to be electrically connected to a clock signal;

The first electrode of the first gating tube is electrically connected to the first input port, and the second electrode is electrically connected to the input signal;

The first electrode of the second gating transistor is electrically connected to the first conjugated input port, and the second electrode is electrically connected to the inverted input signal, so that the conjugated logic gate circuit forms a latch.
The conjugate logic gate circuit according to claim 11, wherein there are multiple latches, and the multiple latches include a first latch and a second latch;

In the second latch, both the gate of the first gate and the gate of the second gate are electrically connected to an inverse clock signal;

The second electrode of the first gate transistor of the second latch is electrically connected to the output port of the first latch;

The second electrode of the second gate transistor of the second latch is electrically connected to the conjugate output port of the first latch, so that the electrically connected first latch and the second Latches form flip-flops.
The conjugate logic gate circuit according to any one of claims 1-10, wherein the conjugate logic gate circuit further comprises another inverter and another buffer;

Wherein, the electrically connected inverter and the buffer form a first subcircuit, and the electrically connected another inverter and the other buffer form a second subcircuit;

The conjugate logic gate circuit also includes:

a first gating tube and a second gating tube;

a third gating tube and a fourth gating tube;

The first gating tube is electrically connected between the first input port of the first sub-circuit and the output port of the second sub-circuit;

The second gating tube is electrically connected between the first conjugate input port of the first sub-circuit and the conjugate output port of the second sub-circuit;

Both the grid of the first gating transistor and the grid of the second gating transistor are electrically connected to an inverse clock signal;

The first electrode of the third gating tube is electrically connected to the first input port of the first sub-circuit, and the second electrode is used to electrically connect the input signal;

The first electrode of the fourth gating tube is electrically connected to the first conjugate input port of the first sub-circuit, and the second electrode is used to electrically connect the reverse input signal;

Both the gate of the third gate and the gate of the fourth gate are electrically connected to a clock signal to form a latch;

The output port of the first subcircuit is electrically connected to the first input port of the second subcircuit to form the output port of the latch, and the conjugate output port of the first subcircuit is connected to the second The first conjugate input ports of the sub-circuits are electrically connected to form the conjugate output ports of the latch.
The conjugate logic gate circuit according to claim 13, wherein there are multiple latches, and the multiple latches include a first latch and a second latch;

The output port of the first latch is connected to the second electrode of the third gate transistor of the second latch, and the conjugate output port of the first latch is connected to the second electrode of the second latch The second electrode of the fourth gate transistor of the latch is connected, so that the electrically connected first latch and the second latch form a flip-flop.
The conjugate logic gate circuit according to any one of claims 1-10, wherein the conjugate logic gate circuit further comprises a clock signal control circuit;

The clock control circuit is used to control the on or off of the inverter and the buffer according to the clock signal.
The conjugate logic gate circuit according to claim 15, wherein the clock control circuit comprises: a third transistor and a fourth transistor;

The third transistor, the inverter and the fourth transistor are connected in series between the first DC voltage terminal and the second DC voltage terminal;

And the gate of the third transistor and the gate of the fourth transistor are both used to be electrically connected to a clock signal.
The conjugate logic gate circuit according to any one of claims 1-10, wherein the conjugate logic gate circuit further comprises: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

The seventh transistor and the first transistor are connected in series between the first DC voltage terminal and the output port of the conjugate logic gate circuit;

The eighth transistor and the second transistor are connected in parallel between the first DC voltage terminal and the conjugate output port of the conjugate logic gate circuit;

The ninth transistor and the third transistor are connected in parallel between the second DC voltage terminal and the output port of the conjugate logic gate circuit;

The tenth transistor and the fourth transistor are connected in series between the second DC voltage terminal and the conjugate output port of the conjugate logic gate circuit;

Wherein, the gate of the eighth transistor is electrically connected to the gate of the ninth transistor, and a second input port is formed;

The gate of the seventh transistor is electrically connected to the gate of the tenth transistor, and forms a second conjugate input port.
The conjugate logic gate circuit according to any one of claims 1-10, wherein the conjugate logic gate circuit further comprises: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

The seventh transistor and the first transistor are connected in parallel between the first DC voltage terminal and the output port of the conjugate logic gate circuit;

The eighth transistor and the second transistor are connected in series between the first DC voltage terminal and the conjugate output port of the conjugate logic gate circuit;

The ninth transistor and the third transistor are connected in series between the second DC voltage terminal and the output port of the conjugate logic gate circuit;

The tenth transistor and the fourth transistor are connected in parallel between the second DC voltage terminal and the conjugate output port of the conjugate logic gate circuit;

Wherein, the gate of the eighth transistor is electrically connected to the gate of the ninth transistor, and a second input port is formed;

The gate of the seventh transistor is electrically connected to the gate of the tenth transistor, and forms a second conjugate input port.
An integrated circuit, characterized in that it comprises:

logic gate circuit;

an interface, the logic gate circuit is electrically connected to the interface;

Wherein, the logic gate circuit comprises the conjugate logic gate circuit described in any one of claims 1-18.
An electronic device, characterized in that it comprises:

circuit board;

The integrated circuit of claim 19;

The integrated circuit is formed on the circuit board.