TWI662793B - Multi-bit flip flop and electronic device - Google Patents

Abstract

An embodiment of the present invention provides a multi-bit flip-flop. The multi-bit flip-flop includes a clock input pin, a clock buffer circuit, and a plurality of flip-flops. The clock buffer circuit is used for receiving a first clock signal received from a clock input pin, and providing a second clock signal and a third clock signal according to the first clock signal. Each flip-flop is used to receive the second clock signal and the third clock signal, and store data according to the second clock signal and the third clock signal. Therefore, the multi-bit flip-flop is designed so that each flip-flop can share the same clock.

Description

Multi-bit flip-flop and electronic equipment

The invention relates to a flip flop (FF), and in particular to a multi-bit flip-flop and electronic equipment capable of sharing a clock.

The flip-flop can only store one bit of data. When you want to store multi-bit data, you must combine and use multiple flip-flops, which are collectively called multi-bit flip-flops. In the existing multi-bit flip-flops, the clock path is one of the most complicated parts of the overall circuit design. Therefore, how to improve the clock path of the multi-bit flip-flops while effectively reducing the time Pulse swing is an important subject in this technical field.

An embodiment of the present invention provides a multi-bit flip-flop. The multi-bit flip-flop includes a clock input pin, a clock buffer circuit, and a plurality of flip-flops. The clock input pin is configured to receive a first clock signal. The clock buffer circuit is coupled to the clock input pin for receiving a first clock signal, and provides a second clock signal and a third clock signal according to the first clock signal. The clock buffer circuit includes a first clock signal. An inverter (inverter) and a second inverter. The first inverter is coupled to the clock input pin via the first node, and is used to receive and invert the first clock signal, and output the inverted first clock signal as the second clock via the second node. signal. The second inverter is coupled to the second node via the third node, and is configured to receive and invert the second clock signal, and output the inverted second clock signal as the third clock signal via the fourth node. Each flip-flop has a corresponding data input terminal and data output terminal, and each flip-flop is coupled to the third node and the fourth node for receiving the second clock signal and the third clock signal. And store data according to the second clock signal and the third clock signal.

An embodiment of the present invention further provides a multi-bit flip-flop. The multi-bit flip-flop includes a clock input pin, a clock buffer circuit, and a plurality of flip-flops. The clock input pin is configured to receive a first clock signal. The clock buffer circuit is coupled to the clock input pin for receiving a first clock signal, and provides a second clock signal and a third clock signal according to the first clock signal. The clock buffer circuit includes a first clock signal. An inverter, a second inverter and a transistor string. The first inverter is coupled to the clock input pin via the first node, and is used to receive and invert the first clock signal, and output the inverted first clock signal as the fourth clock via the second node. signal. The second inverter is coupled to the second node via the third node, and is configured to receive and invert the fourth clock signal, and output the inverted fourth clock signal as the fifth clock signal via the fourth node. The transistor string is coupled to the third node and the fourth node for receiving the fourth clock signal and the fifth clock signal, and according to the fourth clock signal and the fifth clock signal, the fifth node and the sixth clock The node provides a second clock signal and a third clock signal. Each of these flip-flops has a corresponding data input terminal and a data output terminal, and each flip-flop is coupled to the fifth node and the sixth node for receiving the second clock signal and the third clock. Clock signal, and stores data according to the second clock signal and the third clock signal.

In order to further understand the features and technical contents of the present invention, please refer to the following detailed description and accompanying drawings of the present invention, but these descriptions and attached drawings are only used to illustrate the present invention, not the right to the present invention No limitation on scope.

Hereinafter, the present invention will be described in detail by explaining various embodiments of the present invention with drawings. However, the inventive concept may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Moreover, the same reference numbers may be used in the drawings to indicate similar elements.

In detail, the multi-bit flip-flop provided in the embodiment of the present invention may be applicable to any electronic device having a computing function, such as a smart phone, a game console, a router, or a tablet computer. In summary, the present invention does not limit the specific implementation of the multi-bit flip-flop included in the embodiment of the electronic device, and those with ordinary knowledge in the technical field should be able to carry out related designs based on actual needs or applications. Please refer to FIG. 1, which is a schematic circuit diagram of a multi-bit flip-flop provided by an embodiment of the present invention. The multi-bit flip-flop 1 includes a clock input pin PIN1, a clock buffer circuit 110, and a plurality of flip-flops, such as the flip-flop 121 to the flip-flop 128. It is worth mentioning that in order to facilitate the following description, the multiple flip-flops shown in FIG. 1 are only described by using an example of eight, but the number is not intended to limit the present invention. In this embodiment, the clock input pin PIN1 is configured to receive the clock signal CP. The clock buffer circuit 110 is coupled to the clock input pin PIN1 to receive the clock signal CP, and provides the clock signal CKB and the clock signal CKD according to the clock signal CP.

As shown in FIG. 1, the clock buffer circuit 110 may include a first inverter 111 and a second inverter 112. The first inverter 111 is coupled to the clock input pin PIN1 via a node T11 to receive and invert the clock signal CP, and outputs the inverted clock signal CP as a clock signal CKB via a node T12. The second inverter 112 is coupled to the node T12 via the node T13, and is configured to receive and invert the clock signal CKB, and output the inverted clock signal CKB as the clock signal CCK via the node T14. In addition, each of the flip-flops 121 to 128 has a corresponding data input terminal and data output terminal. For example, the flip-flop 121 has a data input terminal D1 and a data output terminal Q1, and the flip-flop 122 has a data input terminal D2 and a data output. Terminal Q2, and so on, the flip-flop 127 has a data input D7 and a data output Q7, and the flip-flop 128 has a data input D8 and a data output Q8, and each of the flip-flops 121-128 is coupled The nodes T13 and T14 are used to receive the clock signal CKB and the clock signal CKD, and store data according to the clock signal CKB and the clock signal CCK.

It can be understood that, in this embodiment, the nodes T11 and T12 can refer to the input and output terminals of the first inverter 111, respectively, and the nodes T13 and T14 also refer to the second inverters, respectively. An input terminal and an output terminal of the phaser 112. In addition, according to the teachings of the above content, those with ordinary knowledge in the technical field should understand that the multi-bit flip-flop 1 provided in this embodiment is designed so that each of the flip-flops 121 to 128 is coupled to a node T13 and node T14, so that each of the flip-flops 121 to 128 can share the same clock signal CKB and the same clock signal CCK. It should be noted that each of the flip-flops 121 to 128 in this embodiment may be a static flip-flop, a dynamic flip-flop, or any type of flip-flop. In short, the present invention does not limit the specific implementation of each of the flip-flops 121 to 128, and those with ordinary knowledge in the technical field should be able to carry out related designs according to actual needs or applications. However, since the operation principle of storing data according to the clock signal CKB and the clock signal CKD of each of the flip-flops 121 to 128 is already known to those having ordinary knowledge in the technical field, the above-mentioned Details of 121-128 will not be repeated here.

Further, the first inverter 111 may include a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) P11 and an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) N11 connected in series with each other, but the present invention is not in this connection relationship. And transistor types are restricted. In this embodiment, the source of the P-type metal-oxide-semiconductor field-effect transistor P11 is coupled to the power supply voltage VDD, the source of the N-type metal-oxide-semiconductor field-effect transistor N11 is coupled to the ground voltage VSS, and the P-type metal-oxide-semiconductor field-effect transistor N11 is coupled to the ground voltage VSS. The drain of transistor P11 and the drain of N-type metal-oxide-semiconductor half-field-effect transistor N11 are coupled to node T12. The gate of P-type metal-oxide-semiconductor half-field-effect transistor P11 and the N-type metal-oxide-semiconductor half-field-effect transistor N11 The gate is commonly coupled to node T11. Similarly, the second inverter 112 may include a P-type metal-oxide-semiconductor half-effect transistor P12 and an N-type metal-oxide-semiconductor half-effect transistor N12 connected in series with each other, but the present invention is not limited by this connection relationship and transistor type. In this embodiment, the source of the P-type metal-oxide-semiconductor field-effect transistor P12 is coupled to the power supply voltage VDD, and the source of the N-type metal-oxide-semiconductor field-effect transistor N12 is coupled to the ground voltage VSS. The drain of the transistor P12 and the drain of the N-type MOS half-effect transistor N12 are coupled to the node T14. The gate of the P-type MOSFET and the N-type MOSFET The gate is commonly coupled to node T13.

More specifically, please refer to FIG. 2 together. FIG. 2 is a timing diagram of the multi-bit flip-flop of FIG. 1. As shown in FIG. 2, since at the first rising edge of the clock signal CCK (that is, at the first rising edge of the clock signal CKB), the i-th flip-flop 12i (where i is 1 to The data signal input by the data input terminal Di of the 8) has a logic "high" level, so the data signal output by the data output terminal Qi of the i-th flip-flop 12i can be switched from the logic "low" level Change to a logic "high" level. Next, since at the second rising edge of the clock signal CKD (that is, at the second rising edge of the clock signal CKB), the data signal input from the data input terminal Di of the i-th flip-flop 12i With the logic "low" level, the data signal output from the data output terminal Qi of the i-th flip-flop 12i can be changed from the logic "high" level to the logic "low" level.

That is to say, in this embodiment, the i-th flip-flop 12i can latch its data input terminal Di only by the rising edge of the clock signal CKD (or the falling edge of the clock signal CKD). The input data signal. Since the principle of the data signal latched by the flip-flop 12i is also known to those having ordinary knowledge in the technical field, the details of the above-mentioned details will not be repeated here. It must be understood that the P-type metal-oxide-semiconductor half-effect transistors P11, P12, and N-type metal-oxide-semiconductor half-effect transistors N11, N12 can be ultra-low voltage trigger (uLVT) metal-oxide half-effect transistors The transistor is used for implementation, but the present invention is not limited to this type of transistor. Therefore, when the uLVT metal-oxide half field effect transistor is used in this embodiment, the i-th flip-flop 12i only needs to perform the above lock according to the relatively small level change on the clock signal CKB and the clock signal CKD. Save action.

On the other hand, if the amplitudes of the clock signal CKB and the clock signal CKD are reduced, please refer to FIG. 3. FIG. 3 is a schematic circuit diagram of a multi-bit flip-flop provided by another embodiment of the present invention. . Among them, some elements in FIG. 3 that are the same as or similar to those in FIG. 1 are marked with the same or similar drawing numbers, and therefore no further details are given here. As shown in FIG. 3, the clock buffer circuit 310 of the multi-bit flip-flop 3 may include a first inverter 111, a second inverter 112, a P-type MOSFET and an N-type MOSFET Effective transistor N33. In this embodiment, the P-type metal-oxide-semiconductor half-effect transistor P33 is connected in series between the P-type metal-oxide-semiconductor half-effect transistor P11 and the power supply voltage VDD, and the source of the P-type metal-oxide-semiconductor half-effect transistor P33 is coupled to the power supply voltage. The drain and gate of the VDD, P-type MOSFET half-effect transistor P33 are coupled to the source of the P-type MOSFET half-effect transistor P11. In addition, in this embodiment, the N-type metal-oxide-semiconductor FET N33 is connected in series between the N-type metal-oxide-semiconductor FET N12 and the ground voltage VSS, and the source of the N-type metal-oxide-semiconductor FET N33 is coupled to The ground voltage VSS, the drain and gate of the N-type metal-oxide-semiconductor half-effect transistor N33 is coupled to the source of the N-type metal-oxide-semiconductor half-effect transistor N12. Therefore, compared with the clock signal CKB and the clock signal CKD in FIG. 1, the clock signal CKB and the clock signal CCK in FIG. 3 can both reduce their amplitudes by 1Vt. For example, the logic “high” bit of the clock signal CKB The quasi-reduction is 1Vt, and the logic “low” bit criterion of the clock signal CKD is increased by 1Vt, but the present invention does not limit the specific implementation of Vt. Since the detailed details are also described in the foregoing embodiment, they will not be described in detail here.

Similarly, please refer to FIG. 4, which is a schematic circuit diagram of a multi-bit flip-flop according to another embodiment of the present invention. Among them, some components in FIG. 4 that are the same as or similar to those in FIG. 1 are marked with the same or similar drawing numbers, and therefore no further details are given here. As shown in FIG. 4, compared with the clock buffer circuits 110 and 310 of FIGS. 1 and 3, the clock buffer circuit 410 of FIG. 4 is used to receive the clock signal CP, and provides the clock signal according to the clock signal CP. CKN and clock signal CKP. In addition, each of the flip-flops 121 to 128 in FIG. 4 is coupled to the node T45 and the node T46, and is used to receive the clock signal CKN and the clock signal CKP, and according to the clock signal CKN and the clock signal CKP, Save data. In this embodiment, the clock buffer circuit 410 may include a first inverter 111, a second inverter 112, and a transistor string 313. The transistor string 313 is coupled to the nodes T13 and T14, and is used to receive the clock signal CKB and the clock signal CKD, and according to the clock signal CKB and the clock signal CCK, the clock signal CKN and Clock signal CKP.

Further, the transistor string 313 may include a P-type metal-oxide-semiconductor field-effect transistor P43 and an N-type metal-oxide-semiconductor field-effect transistor N43, N44 connected in series with each other. In this embodiment, the source of the P-type metal-oxide-semiconductor field-effect transistor P43 is coupled to the power supply voltage VDD, the drain of the P-type metal-oxide-semiconductor field-effect transistor P43 and the drain of the N-type metal-oxide-semiconductor field-effect transistor N43. Commonly coupled to node T45, the source of N-type MOSFET half-effect transistor N43 and the drain of N-type MOSFET half-effect transistor N44 are commonly coupled to node T46, source of N-type MOSFET half-effect transistor N44 The electrode is coupled to the ground voltage VSS, and the gate of the P-type metal-oxide-semiconductor half-effect transistor P43 is coupled to the node T13 and the N-type metal-oxide-semiconductor half-effect transistor N43 is coupled to the node T13. The gate is coupled to the node T14. It can be understood that, in this embodiment, the nodes T45 and T46 can also refer to the two output ends of the clock buffer circuit 410, and the node T45 is used to provide the clock signal CKN, and the node T46 is used to Provides clock signal CKP.

In addition, as shown in FIG. 4, the clock buffer circuit 410 may further include a P-type metal-oxide-semiconductor field-effect transistor P44 and capacitors C1 and C2. In this embodiment, the source of the P-type metal-oxide-semiconductor field-effect transistor P44 is coupled to the node T45, and the drain of the P-type metal-oxide-semiconductor field-effect transistor P44 is coupled to the node T46. The gate of P44 is coupled to the node T14 together with the gate of N-type metal-oxide-semiconductor field-effect transistor N44. The first terminal of the capacitor C1 is coupled to the power supply voltage VDD, and the second terminal of the capacitor C1 is coupled to the node T45. The first terminal of the capacitor C2 is coupled to the ground voltage VSS, and the second terminal of the capacitor C2 is coupled to the node T46. Next, please refer to FIG. 5 together. FIG. 5 is a timing diagram of the multi-bit flip-flop of FIG. 4. According to the teachings of the above content, those with ordinary knowledge in the technical field should understand that compared to the embodiments of FIG. 1 and FIG. 3, the i-th flip-flop 12i of FIG. 4 will only be able to use the clock signal. The rising edge of CKN (or the falling edge of the clock signal CKP) is used to latch the data signal input from its data input terminal Di. It must be understood that, since P-type MOSFETs P43 and P44 and N-type MOSFETs N43 and N44 are used in this embodiment, compared with the clock signal CKB and the clock in FIG. 1 Both the signal CKD, the clock signal CKN and the clock signal CKP in FIG. 4 can reduce their amplitudes to half of the high level, as shown in FIG. 5. Since the detailed details are also described in the foregoing embodiment, they will not be described in detail here.

On the other hand, if it is considered that the multi-bit flip-flop 1 in FIG. 1 can also have a clock-controlled power switch function, please refer to FIG. 6 together, which is the present invention A schematic circuit diagram of a multi-bit flip-flop provided in another embodiment. Among them, some elements in FIG. 6 that are the same as or similar to those in FIG. 1 are marked with the same or similar drawing numbers, and therefore no further details are given here. As shown in FIG. 6, the clock buffer circuit 610 is further configured to provide the power conversion signal SW1 and the power conversion signal SW2 through the node T65 and the node T66 according to the clock signal CKB and the clock signal CKD, and each of the flip-flops 121˜ 128 is further coupled to node T65 and node T66, and is used to receive power conversion signal SW1 and power conversion signal SW2. It can be understood that, in this embodiment, the node T65 is used to provide the power conversion signal SW1, and the node T66 is used to provide the power conversion signal SW2.

Further, the clock buffer circuit 610 of FIG. 6 may include a first inverter 111, a second inverter 112, P-type MOSFETs P63, P64, and N-type MOSFETs N63, N64. In this embodiment, the source of the P-type metal-oxide-semiconductor field-effect transistor P63 is coupled to the power supply voltage VDD, and the drain of the P-type metal-oxide-semiconductor field-effect transistor P63 is coupled to the node T65. The gate of the crystal P63 is coupled to the node T13 together with the flip-flops 121-128. In addition, the source of the N-type metal-oxide-semiconductor field-effect transistor N63 is coupled to the node T65, the drain of the N-type metal-oxide-semiconductor field-effect transistor N63 is coupled to the power supply voltage VDD, and the gate of the N-type metal-oxide-semiconductor field-effect transistor N63 is coupled to the gate The pole is coupled to the node T13 together with the gate of the P-type metal-oxide-semiconductor field-effect transistor P63. Similarly, the source of the P-type metal-oxide-semiconductor field-effect transistor P64 is coupled to the node T66, the drain of the P-type metal-oxide-semiconductor field-effect transistor P64 is coupled to the ground voltage VSS, and the The gate is coupled to the node T14 together with the flip-flops 121-128. In addition, the source of the N-type metal-oxide-semiconductor field-effect transistor N64 is coupled to the ground voltage VSS, the drain of the N-type metal-oxide-semiconductor field-effect transistor N64 is coupled to the node T66, and the gate of the N-type metal-oxide-semiconductor field-effect transistor N64 is connected to the gate. The pole is coupled to the node T14 with the gate of the P-type metal-oxide-semiconductor field-effect transistor P64.

Next, please refer to FIG. 7 together. FIG. 7 is a timing diagram of the multi-bit flip-flop of FIG. 6. According to the teachings of the above content, those with ordinary knowledge in the technical field should understand that the P-type metal-oxide-semiconductor half-effect transistors P63, P64 and N-type metal-oxide-semiconductor half-effect transistors N63, N64 can be regarded as a whole. Weak keeper circuit. That is, the multi-bit flip-flop 6 provided in this embodiment is designed to use this weak hold circuit as a power conversion when the clock signal CP is at a logic low level. Generally speaking, strong hold circuits and weak hold circuits are usually distinguished by designing different threshold voltages or channel lengths. All in all, the present invention does not limit the specific implementation of this weak holding circuit. Those with ordinary knowledge in the technical field should be able to make related designs based on actual needs or applications. It should be noted that, because the operation principle of a flip-flop with a power conversion function is also known to those having ordinary knowledge in the technical field, the details of the above details will not be repeated here.

On the other hand, in addition to considering that the multi-bit flip-flop 1 in FIG. 1 can also have a clock-controlled power conversion function, consider also reducing the power conversion signal SW1 and the power conversion signal SW2 as shown in FIG. 6. In terms of amplitude, please refer to FIG. 8. FIG. 8 is a schematic circuit diagram of a multi-bit flip-flop provided by another embodiment of the present invention. Among them, some elements in FIG. 8 that are the same as or similar to those in FIG. 6 are marked with the same or similar drawing numbers, and therefore no further details are given here. As shown in FIG. 8, compared to the clock buffer circuit 610 of FIG. 6, the clock buffer circuit 810 of FIG. 8 may include a first inverter 111, a second inverter 112, and a P-type MOSFET. P83, P84, P85 and N-type metal-oxide half field effect transistors N83, N84, N85. In this embodiment, the source of the P-type metal-oxide-semiconductor field-effect transistor P83 is coupled to the power supply voltage VDD, and the drain of the P-type metal-oxide-semiconductor field-effect transistor P83 is coupled to the node T65. The gate of the crystal P83 is coupled to the node T13 together with the flip-flops 121-128. In addition, the source of the P-type metal-oxide-semiconductor field-effect transistor P84 is coupled to the power supply voltage VDD, and the drain and gate of the P-type metal-oxide-semiconductor field-effect transistor P84 are coupled to the P-type metal-oxide-semiconductor half-effect transistor P85. At the source, the drain of the P-type metal-oxide-semiconductor field-effect transistor P85 is coupled to node T65, and the gate of the P-type metal-oxide-semiconductor field-effect transistor P85 is coupled to the node T14 with the flip-flops 121-128.

Similarly, the source of the N-type metal-oxide-semiconductor field-effect transistor N83 is coupled to the ground voltage VSS, and the drain of the N-type metal-oxide-semiconductor field-effect transistor N83 is coupled to the node T66. The gate is coupled to the node T14 together with the flip-flops 121-128. The source of the N-type metal-oxide-semiconductor field-effect transistor N84 is coupled to the ground voltage VSS, and the drain and gate of the N-type metal-oxide-semiconductor field-effect transistor N84 are coupled to the source of the N-type metal-oxide-semiconductor FET N85. The drain of the N-type metal-oxide-semiconductor half field-effect transistor N85 is coupled to the node T66, and the gate of the N-type metal-oxide-semiconductor half field-effect transistor N85 is coupled to the node T13 with the flip-flops 121-128. Therefore, compared to the power conversion signal SW1 and the power conversion signal SW2 in FIG. 6, the power conversion signal SW1 and the power conversion signal SW2 in FIG. 8 can both reduce their amplitudes by 1 Vt, for example, the logic “high” bit of the power conversion signal SW1 1Vt has been reduced, and the logic "low" bit criterion of the power conversion signal SW2 has been increased by 1Vt, but the present invention does not limit the specific implementation of Vt. Since the operation details are also as described in the previous embodiment, they will not be repeated here.

Finally, as described above, each of the flip-flops 121 to 128 can be a dynamic flip-flop. Therefore, please refer to FIG. 9, which is a schematic circuit diagram of the flip-flop in the multi-bit flip-flop of FIG. 1. . Among them, some elements in FIG. 9 that are the same as or similar to those in FIG. 1 are marked with the same or similar drawing numbers, so details are not described in detail here. It is worth mentioning that, in order to facilitate the following description, this embodiment will be described by using only an example of the flip-flop 121. As shown in FIG. 9, the flip-flop 121 includes a transmission gate 901, a third inverter 902, a fourth inverter 903, a pull-up transistor 904, and a pull-down transistor 905. The transmission gate 901 is coupled to the data input terminal D1 of the flip-flop 121, and is configured to receive a first data signal (not shown), and output the first data signal to the child node A1 according to the clock signal CKB and the clock signal CKD. The third inverter 902 is coupled to the transmission gate 901 via the child node A1, and is used for inverting the first data signal, and outputs the inverted first data signal to the child node A2. The fourth inverter 903 is coupled between the child node A2 and the data output terminal Q1 of the flip-flop 121, and is used to invert the inverted first data signal to generate a second data signal (not shown), and output The second data signal is sent to the data output terminal Q1 of the flip-flop 121. The pull-up transistor 904 is coupled between the child node A2 and the power supply voltage VDD, and is used to pull up the voltage of the child node A2 to the power supply voltage VDD. The pull-down transistor 905 is coupled between the child node A2 and the ground voltage VSS, and is used to pull down the voltage of the child node A2 to the ground voltage VSS. It can be understood that the "child node A1" in this embodiment can refer to a node where the transmission gate 901 is connected to the third inverter 902, and the "child node A2" also refers to the third inverter 902 is a node connected to the fourth inverter 903.

In this embodiment, the transmission gate 901 includes an N-type metal-oxide-semiconductor half-field-effect transistor N93 and a P-type metal-oxide semi-field-effect transistor P93, a drain of the N-type metal-oxide-semiconductor half-field-effect transistor N93, and a P-type metal oxide. The drain of the half field effect transistor P93 is coupled to the data input terminal D1 of the flip-flop 121 via the node A3. The source of the N-type metal-oxide-semiconductor half field-effect transistor N93 and the source of the P-type metal-oxide-semiconductor half field-effect transistor P93. The common pole is coupled to the sub-node A1 through the sub-node A4. The gate of the N-type metal-oxide-semiconductor half-effect transistor N93 is used to receive the clock signal CKB, and the gate of the P-type metal-oxygen half-effect transistor P93 is used to receive the clock. Pulse signal CKD. It can be understood that the "child node A3" in this embodiment can refer to a node where the drain of the N-type metal-oxide-semiconductor field-effect transistor N93 and the drain of the P-type metal-oxide-semiconductor field-effect transistor P93 are connected, and The “child node A4” also refers to a node where the source of the N-type metal-oxide-semiconductor field-effect transistor N93 is connected to the source of the P-type metal-oxide-semiconductor field-effect transistor P93.

In addition, the third inverter 902 is a tri-state inverter, and includes P-type metal-oxide-semiconductor half-effect transistors P94 and P95 and N-type metal-oxide-semiconductor half-effect transistors N94 and N95 connected in series with each other. The source of the P-type metal-oxide-semiconductor field-effect transistor P94 is coupled to the power supply voltage VDD, the source of the N-type metal-oxide-semiconductor field-effect transistor N95 is coupled to the ground voltage VSS, and the gate of the P-type metal-oxide-semiconductor half-effect transistor P94 is connected to the ground voltage VSS. The gates of the N-type metal-oxide-semiconductor half-effect transistor N95 are coupled to the sub-node A1 to receive the first data signal, and the source of the P-type metal-oxide semi-effect transistor P95 is coupled to the P-metal oxide. The drain of the half field-effect transistor P94, the source of the N-type metal-oxide-semiconductor field-effect transistor N94 is coupled to the drain of the N-type metal-oxide-semiconductor field-effect transistor N95, the drain of the P-type metal-oxide-semiconductor half-field-effect transistor P95, and The drain of the N-type metal-oxide-semiconductor half field-effect transistor N94 is coupled to the child node A2 via the node A5. The gate of the P-type metal-oxide semi-effect transistor P95 is used to receive the clock signal CKB. The gate of transistor N94 is used to receive the clock signal CKD.

The fourth inverter 903 includes a P-type metal-oxide-semiconductor field-effect transistor P96 and an N-type metal-oxide-semiconductor field-effect transistor N96 connected in series. The source of the P-type metal-oxide-semiconductor field-effect transistor P96 is coupled to the power supply voltage VDD, N. The source of the metal-oxide-semiconductor MOSFET N96 is coupled to the ground voltage VSS. The drain of the P-type metal-oxide-semiconductor MOSFET P96 and the drain of the N-type metal-oxide-semiconductor MOSFET N96 are coupled via the sub-node A6. At the data output terminal Q1 of the flip-flop 121, the gate of the P-type metal-oxide-semiconductor half-effect transistor P96 and the gate of the N-type metal-oxide-semiconductor half-effect transistor N96 are coupled to the child node A2 through the child node A7, To receive the inverted first data signal. In addition, the pull-up transistor 904 is a P-type metal-oxide-semiconductor field-effect transistor P97, the pull-down transistor 905 is an N-type metal-oxide-semiconductor field-effect transistor N97, and the source of the P-type metal-oxide-semiconductor half-field-effect transistor P97 is coupled to the power source. Voltage VDD, the source of N-type MOSFET half-effect transistor N97 is coupled to ground voltage VSS, the drain of P-type MOSFET half-effect transistor P97 and the drain of N-type MOSFET half-effect transistor N97 are respectively coupled Connected to sub-node A2, the gate of P-type metal-oxide-semiconductor half-effect transistor P97 and the gate of N-type metal-oxide-semiconductor half-effect transistor N97 are respectively coupled to the data output terminal Q1 of the flip-flop 121 for Receive a second data signal.

It should be noted that, in this embodiment, the pull-up transistor 904 and the pull-down transistor 905 constitute a feedback inverter 906, and compared to the third inverter 902, the feedback inverter is Configured as a weak hold circuit. That is, when the next new data is to be written, the third inverter 902 and the feedback inverter 906 will easily collide with each other on the child node A2, so the signal output capability of the third inverter 902 must be It must be stronger than the signal output capability of the feedback inverter 906, so that the data on the child node A2 can be forcibly updated. Therefore, compared to the third inverter 902, the feedback inverter 906 must be configured as a weak holding circuit. Due to the operating principles of P-type metal-oxide-semiconductor FETs P93, P94, P95, P96, P97, and N-type metal-oxide-semiconductor MOSFETs N93, N94, N95, N96, and N97, those who have ordinary knowledge in the technical field have also It is known, therefore, the details of the above-mentioned flip-flop 121 will not be repeated here.

In summary, the multi-bit flip-flop provided in the embodiment of the present invention is designed so that each flip-flop can share the same clock, thereby improving the clock path of the multi-bit flip-flop. In addition, the multi-bit flip-flop provided in the embodiment of the present invention is also designed to be capable of reducing the clock amplitude and having the advantages of clock control power conversion function.

The above description is only an embodiment of the present invention, and is not intended to limit the patent scope of the present invention.

1, 3, 4, 6, 8‧‧‧ multi-bit flip-flops

121 ～ 128‧‧‧Positive and negative

PIN1‧‧‧ clock input pin

110, 310, 410, 610, 810‧‧‧ clock buffer circuit

CP, CKB, CKD, CKN, CKP‧‧‧ Clock signal

111‧‧‧first inverter

112‧‧‧Second Inverter

313‧‧‧Transistor String

D1 ～ D8, Di‧‧‧ data input terminal

Q1 ～ Q8, Qi‧‧‧ data output terminal

T11, T12, T13, T14, T45, T46, T65, T66‧‧‧ nodes

P11, P12, P33, P43, P44, P63, P64, P83, P84, P85, P93, P94, P95, P96, P97‧‧‧P type metal oxide half field effect transistor

N11, N12, N33, N43, N44, N63, N64, N83, N84, N85, N93, N94, N95, N96, N97‧‧‧N N-type MOSFETs

VDD‧‧‧ supply voltage

VSS‧‧‧ ground voltage

C1, C2‧‧‧capacitor

SW1‧‧‧Power Conversion Signal

SW2‧‧‧ Power Conversion Signal

A1, A2, A3, A4, A5, A6, A7‧‧‧ child nodes

901‧‧‧Transmission gate

902‧‧‧third inverter

903‧‧‧Fourth inverter

904‧‧‧Pull-up transistor

905‧‧‧Pull down transistor

906‧‧‧Feedback Inverter

FIG. 1 is a schematic circuit diagram of a multi-bit flip-flop provided by an embodiment of the present invention; FIG. 2 is a timing diagram of the multi-bit flip-flop of FIG. 1; FIG. 3 is a multi-bit flip-flop provided by another embodiment of the present invention Figure 4 is a circuit diagram of a multi-bit flip-flop provided by another embodiment of the present invention; Figure 5 is a timing diagram of the multi-bit flip-flop of FIG. 4; A schematic circuit diagram of a multi-bit flip-flop provided by another embodiment of the invention; FIG. 7 is a timing diagram of the multi-bit flip-flop of FIG. 6; FIG. 8 is a multi-bit flip-flop provided by another embodiment of the present invention A schematic circuit diagram of the inverter; FIG. 9 is a schematic circuit diagram of the flip-flop in the multi-bit flip-flop of FIG. 1.

Claims (18)

A multi-bit flip flop includes: a clock input pin configured to receive a first clock signal; and a clock buffer circuit coupled to the clock input pin. Receiving the first clock signal, and providing a second clock signal and a third clock signal according to the first clock signal, wherein the clock buffer circuit includes a first inverter through a first A node is coupled to the clock input pin for receiving and inverting the first clock signal, and outputting the inverted first clock signal as a second clock signal through a second node; A second inverter is coupled to the second node via a third node for receiving and inverting the second clock signal, and outputs the second clock signal which has been inverted through a fourth node. As the third clock signal; and a clock-controlled power converter, according to the second clock signal and the third clock signal, a first power conversion signal and a first power conversion signal are provided via a fifth node and a sixth node. A second power conversion signal; and a plurality of flip-flops, each of which Each of the flip-flops has a corresponding data input terminal and a data output terminal, and each of the flip-flops is coupled to the third node and the fourth node for receiving the second clock signal and The third clock signal, and storing data according to the second clock signal and the third clock signal, wherein each of the flip-flops is coupled to the fifth node and the sixth node, and To receive the first power conversion signal and the second power conversion signal. The multi-bit flip-flop according to claim 1, wherein the first inverter comprises a first P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) and a first N-type metal-oxide-semiconductor half-field connected in series with each other. NMOSFET, wherein the source of the first P-type metal-oxide-semiconductor field-effect transistor is coupled to a power supply voltage, and the source of the first N-type metal-oxide-semiconductor field-effect transistor is coupled to a ground voltage, The drain of the first P-type MOSFET and the drain of the first N-type MOSFET are coupled to the second node, and the first P-type MOSFET And the gate of the first N-type metal-oxide-semiconductor field-effect transistor are coupled to the first node in common. The multi-bit flip-flop as described in claim 2, wherein the second inverter includes a second P-type metal-oxide-semiconductor and a second N-type metal-oxide-semiconductor. Wherein the source of the second P-type metal-oxide-semiconductor field-effect transistor is coupled to the power supply voltage, the source of the second N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, and the second P-type metal-oxide semiconductor field-effect transistor is coupled to the ground voltage. The drain of the oxygen half field effect transistor and the drain of the second N-type metal oxide half field effect transistor are coupled to the fourth node, the gate of the second P type metal oxide half field effect transistor and the first The gates of the two N-type metal-oxide-semiconductor half-field-effect transistors are commonly coupled to the third node. The multi-bit flip-flop as described in claim 3, wherein the clock buffer circuit further comprises: a third P-type metal-oxide-semiconductor half-effect transistor, connected in series to the first P-type metal-oxide-semiconductor half-effect transistor And the power supply voltage, wherein the source of the third P-type metal-oxide-semiconductor field-effect transistor is coupled to the power-supply voltage, and the drain and gate of the third P-type metal-oxide-semiconductor field-effect transistor are coupled to the source A source of a first P-type MOSFET and a third N-type MOSFET; connected in series between the second N-type MOSFET and the ground voltage, wherein the three N The source of the metal oxide semiconductor field effect transistor is coupled to the ground voltage, and the drain and gate of the third N type metal oxide semiconductor field effect transistor are coupled to the second N type metal oxide semiconductor field effect transistor. Source. The multi-bit flip-flop according to claim 3, wherein the clock-controlled power converter includes: a third P-type metal-oxide-semiconductor field-effect transistor, The source is coupled to the power supply voltage, the drain of the third P-type MOSFET is connected to the fifth node, and the gate of the third P-type MOSFET is connected to the positive An inverter is commonly coupled to the third node; a third N-type metal-oxide-semiconductor field-effect transistor, and a source of the three N-type metal-oxide-semiconductor half-field-effect transistor is coupled to the fifth node and the third N-type metal The drain of the oxygen half field effect transistor is coupled to the power supply voltage, and the gate of the third N-type metal oxide half field effect transistor is coupled to the gate of the third P type metal oxide half field effect transistor. The third node; a fourth P-type metal-oxide-semiconductor field-effect transistor, the source of the fourth P-type metal-oxide-semiconductor field-effect transistor is coupled to the sixth node, The drain is coupled to the ground voltage, and the gate of the fourth P-type MOSFET is coupled to the fourth node together with the flip-flops; and a fourth N-type The source of the four N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, and the drain of the fourth N-type metal-oxide-semiconductor field-effect transistor is coupled to the sixth node. The gate of the four N-type metal-oxide-semiconductor half-field-effect transistor is coupled to the fourth node together with the gate of the fourth P-type metal-oxide-semiconductor half-field-effect transistor. The multi-bit flip-flop as described in claim 5, wherein the clock buffer circuit further includes: a third P-type metal-oxide-semiconductor half-effect transistor, and a source of the third P-type metal-oxide-semiconductor half-effect transistor. And the drain of the third P-type metal-oxide-semiconductor field-effect transistor is coupled to the fifth node, and the gate of the third P-type metal-oxide-semiconductor field-effect transistor is opposite to the positive and negative electrodes. A fourth to a fifth P-type metal-oxide-semiconductor half-field-effect transistor, the source of the fourth P-type metal-oxide-semiconductor half-field-effect transistor is coupled to the power supply voltage, and the fourth The drain and gate of the P-type MOSFET are coupled to the source of the fifth P-type MOSFET, and the drain of the fifth P-type MOSFET is coupled to The fifth node, the gate of the fifth P-type metal-oxide-semiconductor field-effect transistor is coupled to the fourth node with the flip-flops; a third N-type metal-oxide-semiconductor field-effect transistor, and the three N The source of the MOS half-effect transistor is coupled to the ground voltage, and the drain of the third N-type MOSFET is coupled to the sixth node, and the third N-type MOSFET is connected to the sixth node. The gate of the transistor is coupled to the fourth node with the flip-flops; and a fourth to a fifth N-type metal-oxide-semiconductor field-effect transistor, the source of the four N-type metal-oxide-semiconductor half-field effect transistor And the gate is coupled to the ground voltage, and the drain and gate of the fourth N-type metal-oxide-semiconductor field-effect transistor are coupled to the source of the fifth N-type metal-oxide-semiconductor field-effect transistor, and the fifth N-type metal-oxide-semiconductor field-effect transistor The drain of the oxygen half field effect transistor is coupled to the sixth node, and the gate of the fifth N-type metal oxide half field effect transistor is coupled to the third node together with the flip-flops. The multi-bit flip-flop as described in claim 3, wherein each of the flip-flops is a dynamic flip-flop, and includes a transmission gate coupled to the data of the flip-flop. The input terminal is used to receive a first data signal, and output the first data signal to a first child node according to the second clock signal and the third clock signal; a third inverter passes through the first A child node is coupled to the transmission gate for inverting the first data signal and outputs the inverted first data signal to a second child node; a fourth inverter is coupled to the first The two child nodes and the data output terminal of the flip-flop are used to invert the inverted first data signal to generate a second data signal, and output the second data signal to the flip-flop. Data output terminal; a pull-up transistor is coupled between the second sub-node and the power voltage for pulling up the voltage of the two sub-nodes to the power voltage; and a pull-down transistor is coupled to the second The sub-node and the ground voltage are used to pull down the voltage of the two sub-nodes to the ground voltage. The multi-bit flip-flop as described in claim 7, wherein the transmission gate includes a third N-type metal-oxide-semiconductor and a third P-type metal-oxide-semiconductor. The drain of the three N-type MOSFET and the drain of the third P-type MOSFET are coupled to the data input terminal of the flip-flop through a third sub-node, and the third The source of the N-type metal-oxide-semiconductor field-effect transistor and the source of the third P-type metal-oxide-semiconductor half-field-effect transistor are coupled to the first child node through a fourth child node, and the third N-type metal-oxide semiconductor half-field The gate of the effect transistor is used to receive the second clock signal, and the gate of the third P-type metal-oxide-semiconductor half field effect transistor is used to receive the third clock signal. The multi-bit flip-flop according to claim 8, wherein the third inverter is a three-state inverter, and includes a fourth P-type metal-oxide-semiconductor half-effect transistor, a A fifth P-type metal-oxide-semiconductor field-effect transistor, a fourth N-type metal-oxide-semiconductor field-effect transistor, and a fifth N-type metal-oxide-semiconductor half-field-effect transistor, the source coupling of the fourth P-type metal-oxide-semiconductor half-field-effect transistor Connected to the power voltage, the source of the fifth N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, the gate of the fourth P-type metal-oxide-semiconductor field-effect transistor and the fifth N-type metal-oxide-semiconductor half-field transistor. The gates of the effect transistor are respectively coupled to the first sub-node to receive the first data signal, and the source of the fifth P-type metal-oxide-semiconductor field-effect transistor is coupled to the fourth P-type metal. The drain of an oxygen half field effect transistor, the source of the fourth N-type metal oxide half field effect transistor is coupled to the drain of the fifth N type metal oxide half field effect transistor, and the fifth P type metal oxide half field effect The drain of the transistor and the drain of the fourth N-type metal-oxide-semiconductor field-effect transistor are coupled to the second child node through a fifth child node. The fifth P-type metal-oxide-semiconductor half-field-effect transistor The gate of the body is used to receive the second clock signal, and the gate of the fourth N-type metal-oxide-semiconductor field-effect transistor is used to receive the third clock signal. The multi-bit flip-flop according to item 9, wherein the fourth inverter includes a sixth P-type metal-oxide-semiconductor and a sixth N-type metal-oxide-semiconductor. The source of the sixth P-type metal-oxide-semiconductor half-field-effect transistor is coupled to the power supply voltage, the source of the sixth N-type metal-oxide-semiconductor half-field-effect transistor is coupled to the ground voltage, and the sixth P-type metal-oxide-semiconductor half-effect transistor is coupled to the ground voltage. The drain of the half field effect transistor and the drain of the sixth N-type metal oxide half field effect transistor are coupled to the data output terminal of the flip-flop through a sixth child node, and the sixth P type metal oxide half field The gate of the effect transistor and the gate of the sixth N-type metal-oxide-semiconductor half field effect transistor are coupled to the second sub-node through a seventh sub-node for receiving the first data that has been inverted. signal. The multi-bit flip-flop as described in claim 10, wherein the pull-up transistor is a seventh P-type metal-oxide half-field effect transistor, and the pull-down transistor is a seventh N-type metal-oxide half-field effect transistor. Crystal, the source of the seventh P-type metal-oxide-semiconductor field-effect transistor is coupled to the supply voltage, the source of the seventh N-type metal-oxide-semiconductor field-effect transistor is coupled to the ground voltage, and the seventh P-type metal The drain of the oxygen half field effect transistor and the drain of the seventh N-type metal oxide half field effect transistor are respectively coupled to the second child node, the gate of the seventh P type metal oxide half field effect transistor and the The gates of the seventh N-type metal-oxide-semiconductor half-effect transistor are respectively coupled to the data output terminal of the flip-flop for receiving the second data signal. The multi-bit flip-flop according to claim 11, wherein the pull-up transistor and the pull-down transistor group constitute a feedback inverter, and compared to the third inverter, the feedback The inverter is configured as a weak hold circuit. A multi-bit flip-flop includes: a clock input pin configured to receive a first clock signal; and a clock buffer circuit coupled to the clock input pin to receive the first clock Signal, and a second clock signal and a third clock signal are provided according to the first clock signal, wherein the clock buffer circuit includes a first inverter coupled to the clock via a first node A clock input pin is used to receive and invert the first clock signal, and output the first clock signal that has been inverted through a second node as a fourth clock signal; a second inverter, A third node is coupled to the second node to receive and invert the fourth clock signal, and a fourth node outputs the inverted fourth clock signal as a fifth clock signal. And a transistor string, coupled to the third node and the fourth node, for receiving the fourth clock signal and the fifth clock signal, and according to the fourth clock signal and the fifth clock Pulse signal, the second clock signal is provided via a fifth node and a sixth node The third clock signal; and a plurality of flip-flops, each of which has a corresponding data input terminal and a data output terminal, and each of the flip-flops is coupled to the first flip-flop The five nodes and the sixth node are used to receive the second clock signal and the third clock signal, and store data according to the second clock signal and the third clock signal. The multi-bit flip-flop according to claim 13, wherein the first inverter includes a first P-type MOSFET and a first N-type MOSFET The source of the first P-type metal-oxide-semiconductor half-field-effect transistor is coupled to a power supply voltage, the source of the first N-type metal-oxide-semiconductor half-field-effect transistor is coupled to a ground voltage, and the first P-type metal-oxide semiconductor field-effect transistor is coupled to a ground voltage. The drain of the half field-effect transistor and the drain of the first N-type metal-oxide-semiconductor half field-effect transistor are coupled to the second node, the gate of the first P-type metal-oxide-semiconductor half-field effect transistor and the first The gates of the N-type metal-oxide-semiconductor field-effect transistor are commonly coupled to the first node. The multi-bit flip-flop according to claim 14, wherein the second inverter includes a second P-type MOSFET and a second N-type MOSFET The source of the second P-type metal-oxide-semiconductor half-field-effect transistor is coupled to the power supply voltage, the source of the second N-type metal-oxide-semiconductor half-field-effect transistor is coupled to the ground voltage, and the second P-type metal-oxide-semiconductor half-effect transistor is coupled to the ground voltage. The drain of the half field-effect transistor and the drain of the second N-type metal-oxide-semiconductor half-field-effect transistor are coupled to the fourth node in common, and the gate of the second P-type metal-oxide-semiconductor half-field-effect transistor and the second The gate of the N-type metal-oxide-semiconductor field-effect transistor is commonly coupled to the third node. The multi-bit flip-flop as described in claim 15, wherein the transistor string includes a third P-type MOSFET and a third N-type MOSFET and a A fourth N-type metal-oxide-semiconductor field-effect transistor, wherein a source of the third P-type metal-oxide-semiconductor field-effect transistor is coupled to the power supply voltage, and a drain of the third P-type metal-oxide-semiconductor half-effect transistor is connected to the first The drain of the three N-type metal-oxide-semiconductor field-effect transistor is coupled to the fifth node in common. The source of the third N-type metal-oxide-semiconductor field-effect transistor and the drain of the fourth N-type metal-oxide-semiconductor field-effect transistor are coupled together. Commonly coupled to the sixth node, the source of the fourth N-type MOSFET is coupled to the ground voltage, and the gate of the third P-type MOSFET is connected to the third N The gates of the MOSFETs are coupled to the third node, and the gates of the fourth N-type MOSFETs are coupled to the fourth node. The multi-bit flip-flop as described in claim 16, wherein the clock buffer circuit further includes: a fourth P-type metal-oxide-semiconductor half-effect transistor, and a source of the fourth P-type metal-oxide-semiconductor half-effect transistor. And a drain electrode of the fourth P-type metal-oxide-semiconductor half-field-effect transistor is coupled to the sixth node, and a gate of the fourth P-type metal-oxide-semiconductor half-field-effect transistor is connected to the fourth node. The gate of the N-type metal-oxide-semiconductor field-effect transistor is commonly coupled to the fourth node; a first capacitor, a first terminal of the first capacitor is coupled to the power supply voltage, and a second terminal of the first capacitor is coupled At the fifth node; and a second capacitor, a first terminal of the second capacitor is coupled to the ground voltage, and a second terminal of the second capacitor is coupled to the sixth node. An electronic device includes the multi-bit flip-flop according to any one of claims 1 to 17.