CN103716014A - Neuron MOS tube-based differential double-edged flip-flop design - Google Patents

Abstract

The invention discloses a neuron MOS tube-based differential double-edged flip-flop design, comprising principal triggers 1 and 2 and a subordinate trigger, which are all have differential structures. The principal trigger 1 is composed of a PMOS tube m3 and a PMOS tube m4 which constitute the differential structure, and a three-input n-type floating gate MOS tube m1 and a three-input n-type floating gate MOS tube m2. The principal trigger 2 is composed of a PMOS tube m7 and a PMOS tube m8 which constitute the differential structure, and a three-input n-type floating gate MOS tube m5 and a three-input n-type floating gate MOS tube m6. The subordinate trigger is composed of a PMOS tube m9 and a PMOS tube m10 which constitute the differential structure, and a three-input n-type floating gate MOS tube m11, a three-input n-type floating gate MOS tube m12, a three-input n-type floating gate MOS tube m13, a three-input n-type floating gate MOS tube m14, a phase inverter INV1, and a phase inverter INV2. The beneficial effects of the invention are that the double-edged flip-flop design is advantaged by complementary output, low power consumption, simple structure, and the like; the pull-down network structure is simplified; and the circuit power consumption is further decreased.

Description

A kind of difference type dual-edge trigger design based on neuron mos pipe

Technical field

The present invention relates to a kind of difference type dual-edge trigger design, more specifically, it relates to a kind of difference type dual-edge trigger design based on neuron mos pipe.

Background technology

Trigger is member basic in digital integrated circuit, and they are determining to comprise the performance of the circuit such as power consumption, delay, area, reliability.In all triggers, the trigger of differential configuration is owing to having the advantages such as complementary output, low-power consumption, simple structure, and therefore application is more extensive.Differential flip-flops can play the effect of amplifier, so they can well work under low amplitude of oscillation voltage signal.They can also set up various logic functions and reduce order-checking expense in trigger.

Dual-edge trigger can both sample input signal on clock signal rising edge edge and trailing edge edge, thereby upgrades output state.Therefore,, keeping legacy data to process under the condition of frequency, use dual-edge trigger can make the frequency halving of clock signal, thereby reduced the dynamic power consumption of clock network.But the dual-edge trigger circuit structure of prior art is complicated, and power consumption is undesirable, and function is dumb.

Summary of the invention

The object of the invention is to overcome deficiency of the prior art, provide a kind of rational in infrastructure, low in energy consumption, control the design of the difference type dual-edge trigger based on neuron mos pipe flexibly.

This difference type dual-edge trigger based on neuron mos pipe designs, and comprises the slave flipflop of master flip-flop 1, master flip-flop 2 and a differential configuration of differential configuration; Described master flip-flop 1 is by the PMOS pipe m3 and the PMOS pipe m4 that form differential configuration, and three input N-shaped floating-gate MOS tube m1 and three input N-shaped floating-gate MOS tube m2 form; Described master flip-flop 2 is by the PMOS pipe m7 and the PMOS pipe m8 that form differential configuration, and three input N-shaped floating-gate MOS tube m5 and three input N-shaped floating-gate MOS tube m6 form; Described slave flipflop is by the PMOS pipe m9 and the PMOS pipe m10 that form differential configuration, three input N-shaped floating-gate MOS tube m11, three input N-shaped floating-gate MOS tube m12, three input N-shaped floating-gate MOS tube m13 and three input N-shaped floating-gate MOS tube m14, inverter INV1 and inverter INV2 form;

The source class of described PMOS pipe m3, m4, m7, m8, m9 and m10 meets operating voltage VDD, the source class of described three input N-shaped floating-gate MOS tube m1, m2, m5, m6 and input be ground connection all, the source class ground connection of described three input N-shaped floating-gate MOS tube m11, m12, m13, m14;

In described master flip-flop 1, form two PMOS pipe m3 of differential configuration and the drain electrode of m4 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m1 and m2 respectively, and the output of generation master flip-flop 1

and x1; In described master flip-flop 2, form two PMOS pipe m7 of differential configuration and the drain electrode of m8 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m5 and m6 respectively, and the output of generation master flip-flop 2

and x2;

The output x1 of described master flip-flop 1 and an input that connects respectively three in slave flipflop input N-shaped floating-gate MOS tube m11 and m14, the output x2 of described master flip-flop 2 and an input that connects respectively the input N-shaped floating-gate MOS tube m12 of three in slave flipflop and m13;

In described slave flipflop, form two PMOS pipe m9 of differential configuration and the drain electrode of m10 and be connected with the drain electrode of m12, m13 and m14 with two three input N-shaped floating-gate MOS tube m11 respectively, and be connected to output by two inverter INV1 and INV2;

When clk rising edge, the output x1 of described master flip-flop 1 and by m11 and m14, be transferred to output, the output x2 of described master flip-flop 2 and being inputted D determines; When clk trailing edge, the output x2 of described master flip-flop 2 and

by m12 and m13, be transferred to output, the output x1 of described master flip-flop 1 and

being inputted D determines.S and R realize respectively asynchronous set and the asynchronous resetting function of trigger.

The invention has the beneficial effects as follows: the threshold value that circuit has utilized neuron mos pipe to have is easy to control this natural quality, without increasing special circuit, only need by increase the just switch of control circuit easily of an input in N-shaped floating-gate MOS tube.The trigger of differential configuration is owing to having the advantages such as complementary output, low-power consumption, simple structure, and use N-shaped floating-gate MOS tube pulldown network to replace the nMOS logical circuit in traditional difference type trigger, simplify pulldown network structure, thereby further reduced the power consumption of circuit.And by the utilization of floating-gate MOS tube, set end and reset terminal in trigger can be realized very easily.Dual-edge trigger can both sample input signal on clock signal rising edge edge and trailing edge edge, has improved the efficiency of clock signal, has reduced the dynamic power consumption of clock network.Adding of asynchronous set and asynchronous resetting end makes the function of trigger more flexible.

Accompanying drawing explanation

Fig. 1 is that N-shaped and p-type are inputted floating-gate MOS tube symbol and capacitor model more;

Fig. 2 is circuit theory diagrams of the present invention;

Fig. 3 is a kind of encapsulation connecting circuit of the embodiment of the present invention;

Fig. 4 is the transient state functional simulation performance plot of circuit shown in Fig. 3 under 25MHz clock frequency, and abscissa is the time, and unit is ns, and ordinate is voltage, and unit is V.

Embodiment

Below in conjunction with drawings and Examples, the present invention is described further.Although the present invention is described in connection with preferred embodiment, should know, do not represent to limit the invention in described embodiment.On the contrary, the present invention is by alternative, modified model and the equivalent contained in the scope of the present invention that can be included in attached claims restriction.

Many input floating-gate MOS tubes are that propose in recent years a kind of has the new device that functional strong, threshold value is controlled the feature such as flexible, and people have carried out further investigation in a plurality of fields such as simulation, numeral and neural nets to its application.The double level polysilicon CMOS technique of the processing technology of this device and standard is completely compatible, its symbol represent and capacitor model as shown in Figure 1.It has a plurality of input grids and a floating boom utmost point, and wherein floating boom is formed by ground floor polysilicon, and a plurality of input control grid are formed by second layer polysilicon.Between input and floating boom, by electric capacity, realize coupling.V in Fig. 1 _frepresent the voltage on floating boom, V ₀for underlayer voltage, V ₁, V ₂..., V _nfor applied signal voltage.C ₀be the coupling capacitance between floating boom and substrate, it is mainly by gate oxide capacitor C _oxform C ₁, C ₂..., C _nfor the coupling capacitance between each input grid and floating boom.In Fig. 1, D and S represent respectively drain electrode and source electrode.Net charge Q on floating boom _fby following formula, provided:

$Q_F=\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i(V_F-V_i)=V_F\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i-\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i{V}_i;---\left(1\right)$

For n raceway groove floating-gate MOS tube, substrate ground connection, so V ₀=0.Suppose that the initial charge on floating boom is zero, according to law of conservation of charge, can be obtained fom the above equation:

$V_F=\underset{i=1}{\overset{n}{\mathrm{\Σ}}}{w}_i{V}_i;---\left(2\right)$

$w_i=\frac{C_i}{C_0+\underset{j=1}{\overset{n}{\mathrm{\Σ}}}{C}_j};---\left(3\right)$

If V _tfor the threshold voltage of the pipe seen into by floating boom end, work as V _f>V _tshi Guanzi conducting.By formula (2) and (3), can be found out, input floating-gate MOS tube more and can, to each grid input signal weighted sum, by the summed result calculating, go to control " opening " and " pass " of metal-oxide-semiconductor.The weighted sum computing of noticing all input signals that it carries out on floating boom utilizes capacitance coupling effect to carry out with voltage mode, and this has shown that it has the low-power consumption characteristic more outstanding than current-mode summation technology.If with V ₁as input, other inputs, as control end, have:

$V_1>\frac{\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i}{C_1}{V}_T-\frac{C_2}{C_1}{V}_2-...-\frac{C_n}{C_1}{V}_n;---\left(4\right)$

Like this, by V ₁the threshold voltage V of the pipe that end is seen into ^* _t1can be expressed as:

${V^{*}}_{t1}=\frac{\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i}{C_1}{V}_T-\frac{C_2}{C_1}{V}_2-...-\frac{C_n}{C_1}{V}_n;---\left(5\right)$

Above formula shows, without adjusting V _t, as long as by changing the proportionate relationship between coupling capacitance or changing control end voltage V _ijust can change floating-gate MOS tube with respect to input signal V ₁threshold voltage, thereby control conducting and the cut-off of metal-oxide-semiconductor.For p raceway groove floating-gate MOS tube, the common connection circuit maximum voltage sources of substrate is (as V _dD), so V in formula (1) ₀=V _dD, corresponding correction need be done in formula (2)-(5).

The structure of a kind of difference type dual-edge trigger circuit based on neuron mos pipe of the present invention as shown in Figure 2, comprising: the master flip-flop circuit (1,2) of two differential configurations and the slave flipflop circuit of a differential configuration.

Described master flip-flop 1 forms by forming two PMOS pipe m3 of differential configuration and m4, two three input N-shaped floating-gate MOS tube m1 and m2; Described master flip-flop 2 forms by forming two PMOS pipe m7 of differential configuration and m8, two three input N-shaped floating-gate MOS tube m5 and m6; Described slave flipflop forms by forming two PMOS pipe m9 of differential configuration and m10, two three input N-shaped floating-gate MOS tube m11, m12, m13 and m14, two inverter INV1 and INV2.

The source class of described PMOS pipe m3, m4, m7, m8, m9 and m10 meets operating voltage VDD, the source class of described three input N-shaped floating-gate MOS tube m1, m2, m5, m6 and input be ground connection all, the source class ground connection of described three input N-shaped floating-gate MOS tube m11, m12, m13, m14.

In described master flip-flop 1, form two PMOS pipe m3 of differential configuration and the drain electrode of m4 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m1 and m2 respectively, and the output of generation master flip-flop 1 and x1; In described master flip-flop 2, form two PMOS pipe m7 of differential configuration and the drain electrode of m8 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m5 and m6 respectively, and the output of generation master flip-flop 2

and x2.

The output x1 of described master flip-flop 1 and

an input that connects respectively three in slave flipflop input N-shaped floating-gate MOS tube m11 and m14, the output x2 of described master flip-flop 2 and

an input that connects respectively the input N-shaped floating-gate MOS tube m12 of three in slave flipflop and m13.

In described slave flipflop, form two PMOS pipe m9 of differential configuration and the drain electrode of m10 and be connected with the drain electrode of m12, m13 and m14 with two three input N-shaped floating-gate MOS tube m11 respectively, and be connected to output by two inverter INV1 and INV2.

When clk rising edge, the output x1 of described master flip-flop 1 and

by m11 and m14, be transferred to output, the output x2 of described master flip-flop 2 and being inputted D determines; When clk trailing edge, the output x2 of described master flip-flop 2 and

by m12 and m13, be transferred to output, the output x1 of described master flip-flop 1 and

being inputted D determines.S and R realize respectively asynchronous set and the asynchronous resetting function of trigger.

Input (V1, V2, the V3) weight of the three input floating-gate MOS tubes that adopt in the design is identical, i.e. C1=C2=C3.According to formula (4), only need $\frac{V1*C1+V2*C2+V3*C3}{C1+C2+C3}\≥V_T=\frac{V_H}{2};$ ? $\frac{V1+V2+V3}{3}\≥V_T=\frac{V_H}{2}.$ V _hit is high level.

Described m1(V1=D, V2=clk, V3=0) and m2(V1=

v2=clk, V3=0), when clk is high level, because V2=V3=0, so

m1 and m2 end, output

with x1 in hold mode; When clk is low level, V2=V _h, V3=0, works as V1=V _htime, pipe conducting, when V1=0, pipe cut-off, the at this moment output of m1 and m2

determine by inputting D with x1; Therefore master flip-flop 1 is operated in clk low level state.

In like manner, master flip-flop 2 is operated in clk high level state to the course of work of M5 and m6.

Described m11(V1=x1, V2=clk, V3=S) and m14(V1=

v2=clk, V3=R), when clear terminal and set end are not made used time, i.e. S=R=0; When clk is low level, because V2=V3=0, so

m11 and m14 cut-off,

transmit less than output with x1; When clk is high level, V2=V _h, V3=0, works as V1=V _htime, pipe conducting, when V1=0, pipe cut-off,

with x1 determine current trigger output Q and

therefore during clk rising edge the output x1 of master flip-flop 1 and

determine the output of described a kind of difference type dual-edge trigger based on neuron mos pipe.

The course of work of m12 and m13 in like manner, during clk trailing edge the output x2 of master flip-flop 2 and

determine the output of described a kind of difference type dual-edge trigger based on neuron mos pipe.

Adopt TSMC0.35 μ m double level polysilicon CMOS technological parameter, and the voltage VDD=1.5V of power taking source VDD, when clock frequency is 25MHz frequency, Fig. 4 has provided the voltage transmission curve obtaining through HSPICE simulation.Analog result has shown the functional characteristic that it is correct, has shown a kind of practicality of the difference type dual-edge trigger circuit based on neuron mos pipe.

Claims (1)

1. the difference type dual-edge trigger design based on neuron mos pipe, is characterized in that: the slave flipflop that comprises master flip-flop 1, master flip-flop 2 and a differential configuration of differential configuration; Described master flip-flop 1 is by the PMOS pipe m3 and the PMOS pipe m4 that form differential configuration, and three input N-shaped floating-gate MOS tube m1 and three input N-shaped floating-gate MOS tube m2 form; Described master flip-flop 2 is by the PMOS pipe m7 and the PMOS pipe m8 that form differential configuration, and three input N-shaped floating-gate MOS tube m5 and three input N-shaped floating-gate MOS tube m6 form; Described slave flipflop is by the PMOS pipe m9 and the PMOS pipe m10 that form differential configuration, three input N-shaped floating-gate MOS tube m11, three input N-shaped floating-gate MOS tube m12, three input N-shaped floating-gate MOS tube m13 and three input N-shaped floating-gate MOS tube m14, inverter INV1 and inverter INV2 form;

The source class of described PMOS pipe m3, m4, m7, m8, m9 and m10 meets operating voltage VDD, the source class of described three input N-shaped floating-gate MOS tube m1, m2, m5, m6 and input be ground connection all, the source class ground connection of described three input N-shaped floating-gate MOS tube m11, m12, m13, m14;

In described master flip-flop 1, form two PMOS pipe m3 of differential configuration and the drain electrode of m4 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m1 and m2 respectively, and the output of generation master flip-flop 1

and x1; In described master flip-flop 2, form two PMOS pipe m7 of differential configuration and the drain electrode of m8 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m5 and m6 respectively, and the output of generation master flip-flop 2

and x2;

The output x1 of described master flip-flop 1 and

an input that connects respectively three in slave flipflop input N-shaped floating-gate MOS tube m11 and m14, the output x2 of described master flip-flop 2 and

an input that connects respectively the input N-shaped floating-gate MOS tube m12 of three in slave flipflop and m13;

In described slave flipflop, form two PMOS pipe m9 of differential configuration and the drain electrode of m10 and be connected with the drain electrode of m12, m13 and m14 with two three input N-shaped floating-gate MOS tube m11 respectively, and be connected to output by two inverter INV1 and INV2;

When clk rising edge, the output x1 of described master flip-flop 1 and

by m11 and m14, be transferred to output, the output x2 of described master flip-flop 2 and

being inputted D determines; When clk trailing edge, the output x2 of described master flip-flop 2 and

by m12 and m13, be transferred to output, the output x1 of described master flip-flop 1 and

being inputted D determines.S and R realize respectively asynchronous set and the asynchronous resetting function of trigger.

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