CN203675067U - Difference-type single-edge D trigger based on neuron MOS transistor - Google Patents

Abstract

The utility model discloses a difference-type single-edge D trigger based on a neuron MOS transistor. The difference-type single-edge D trigger based on the neuron MOS transistor comprises a master trigger of a difference structure and a slave trigger of a difference structure, the master trigger is composed of two PMOS transistors m3 and m4 which form the difference structure and two three-input n-type floating gate MOS transistors m1 and m2, and the slave trigger is composed of two PMOS transistors m7 and m8 which form the difference structure, two three-input n-type floating gate MOS transistors m5 and m6, and two inverters INV1 and INV2. The beneficial effects of the utility model are that: by adding an input end in the n-type floating gate MOS transistors, the on-off of a circuit can be controlled conveniently; the triggers of the difference structures have the advantages of complementary output, low power consumption and simple structure, so that an n-type floating gate MOS transistor pull-down network is applied to substitute for an nMOS logic circuit in a conventional difference-type trigger, and the structure of the pull-down network is simplified, and accordingly, the power consumption of the circuit is reduced further; by the application of the floating gate MOS transistors, the setting ends and the reset ends in the triggers can be realized very conveniently.

Description

Difference type list edge D flip-flop based on neuron mos pipe

Technical field

The utility model relates to a kind of difference type list edge triggered flip flop, and more specifically, it relates to a kind of difference type list edge D flip-flop based on neuron mos pipe.

Background technology

Trigger is member basic in digital integrated circuit, and they are determining to comprise the performance of the circuit such as power consumption, delay, area, reliability.In all triggers, the trigger of differential configuration is owing to having the advantages such as complementary output, low-power consumption, simple structure, and therefore application is more extensive.Differential flip-flops can play the effect of amplifier, and therefore they can well work under low amplitude of oscillation voltage signal.They can also set up various logic functions and reduce order-checking expense in trigger.

Summary of the invention

The purpose of this utility model is to overcome deficiency of the prior art, provide a kind of except having low-power consumption and feature simple in structure, can also and reset by asynchronous input set end and bring in the difference type list edge D flip-flop based on neuron mos pipe of controlling flexibly output state.

This difference type list edge D flip-flop based on neuron mos pipe, comprises the master flip-flop of differential configuration and the slave flipflop of differential configuration;

Described master flip-flop is managed m3 and m4 by two PMOS that form differential configuration, inputs N-shaped floating-gate MOS tube m1 and m2 formation for two three; Described slave flipflop forms by forming two PMOS pipe m7 of differential configuration and m8, two three input N-shaped floating-gate MOS tube m5 and m6, two inverter INV1 and INV2;

Described PMOS pipe m3, m4, m7 and m8 source class meet operating voltage VDD, the source class ground connection of described three input N-shaped floating-gate MOS tube m1, m2, m5 and m6;

In described master flip-flop, form two PMOS pipe m3 of differential configuration and the drain electrode of m4 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m1 and m2 respectively, and the output of generation master flip-flop

and x; In described slave flipflop, form two PMOS pipe m7 of differential configuration and the drain electrode of m8 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m5 and m6 respectively, and by two inverter INV1 and INV2 be connected to output Q with

In the time of clk low level, described master flip-flop receives input signal, determine master flip-flop output x and

now described slave flipflop cuts out, the output Q of slave flipflop and

remain unchanged; In the time of clk rising edge, master flip-flop cuts out, slave flipflop open, determine master flip-flop output x and

determine the output of slave flipflop, the output Q of whole trigger and

s and R realize respectively asynchronous set and the asynchronous resetting function of trigger simultaneously.

The beneficial effects of the utility model are: the threshold value that circuit has utilized neuron mos pipe to have is easy to control this natural quality, without increasing special circuit, only need by increase the just switch of control circuit easily of an input in N-shaped floating-gate MOS tube.The trigger of differential configuration is owing to having the advantages such as complementary output, low-power consumption, simple structure, and use N-shaped floating-gate MOS tube pulldown network to replace the nMOS logical circuit in traditional difference type trigger, simplify pulldown network structure, thereby further reduced the power consumption of circuit.And by the utilization of floating-gate MOS tube, set end and reset terminal in trigger can be realized very easily.

Brief description of the drawings

Fig. 1 is that N-shaped and p-type are inputted floating-gate MOS tube symbol and capacitor model more;

Fig. 2 is the utility model circuit theory diagrams.

Embodiment

Below in conjunction with drawings and Examples, the utility model is described further.Although the utility model is described in connection with preferred embodiment, should know, do not represent that the utility model is limited in described embodiment.On the contrary, the utility model is by alternative, modified model and the equivalent contained in the scope of the present utility model that can be included in attached claims restriction.

Many input floating-gate MOS tubes are new devices that propose in recent years a kind of has functional strong, the feature such as threshold value control is flexible, and people have carried out further investigation in multiple fields such as simulation, numeral and neural nets to its application.The double level polysilicon CMOS technique of the processing technology of this device and standard is completely compatible, its symbol represent and capacitor model as shown in Figure 1.It has multiple input grids and a floating boom utmost point, and wherein floating boom is formed by ground floor polysilicon, and multiple input control grid are formed by second layer polysilicon.Between input and floating boom, realize coupling by electric capacity.V in figure _frepresent the voltage on floating boom, V ₀for underlayer voltage, V ₁, V ₂..., V _nfor applied signal voltage.C ₀be the coupling capacitance between floating boom and substrate, it is mainly by gate oxide capacitor C _oxform C ₁, C ₂..., C _nfor the coupling capacitance between each input grid and floating boom.

In figure, D and S represent respectively drain electrode and source electrode.Net charge Q on floating boom _fprovided by following formula:

$Q_F=\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i(V_F-V_i)=V_F\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i-\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i{V}_i;---\left(1\right)$

For n raceway groove floating-gate MOS tube, substrate ground connection, therefore V ₀=0.Suppose that the initial charge on floating boom is zero, according to law of conservation of charge, can be obtained fom the above equation:

$V_F=\underset{i=1}{\overset{n}{\mathrm{\Σ}}}{w}_i{V}_i;---\left(2\right)$

$w_i=\frac{C_i}{C_0+\underset{j=1}{\overset{n}{\mathrm{\Σ}}}{C}_j};---\left(3\right)$

If V _tfor the threshold voltage of the pipe seen into by floating boom end, work as V _f>V _tshi Guanzi conducting.Can be found out by formula (2) and (3), input floating-gate MOS tube more and can, to the weighted sum of each grid input signal, go to control " opening " and " pass " of metal-oxide-semiconductor by the summed result calculating.The weighted sum computing of noticing all input signals that it carries out on floating boom utilizes capacitance coupling effect to carry out with voltage mode, and this has shown that it has the low-power consumption characteristic more outstanding than current-mode summation technology.If with V ₁as input, other inputs, as control end, have:

$V_1>\frac{\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i}{C_1}{V}_T-\frac{C_2}{C_1}{V}_2-...-\frac{C_n}{C_1}{V}_n;---\left(4\right)$

Like this, by V ₁the threshold voltage V of the pipe that end is seen into ^* _t1can be expressed as:

${V^{*}}_{t1}=\frac{\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i}{C_1}{V}_T-\frac{C_2}{C_1}{V}_2-...-\frac{C_n}{C_1}{V}_n;---\left(5\right)$

Above formula shows, without adjusting V _t, as long as by changing the proportionate relationship between coupling capacitance or changing control end voltage V _ijust can change floating-gate MOS tube with respect to input signal V ₁threshold voltage, thereby control conducting and the cut-off of metal-oxide-semiconductor.For p raceway groove floating-gate MOS tube, the common connection circuit maximum voltage sources of substrate is (as V _dD), therefore V in formula (1) ₀=V _dD, corresponding correction need be done in formula (2)-(5).

Below in conjunction with drawings and Examples, the specific embodiment of the present invention is described in further detail, it is more obvious that object of the present invention and effect will become.Following examples are used for illustrating the present invention, but are not used for limiting the scope of the invention.

The structure of a kind of difference type list edge D flip-flop circuit based on neuron mos pipe of the present invention as shown in Figure 2,

Comprise: the master flip-flop of differential configuration and the slave flipflop of differential configuration.

Described master flip-flop forms by forming two PMOS pipe m3 of differential configuration and m4, two three input N-shaped floating-gate MOS tube m1 and m2; Described slave flipflop forms by forming two PMOS pipe m7 of differential configuration and m8, two three input N-shaped floating-gate MOS tube m5 and m6, two inverter INV1 and INV2.

Described PMOS pipe m3, m4, m7, m8 source class meet operating voltage VDD, the source class ground connection of described three input N-shaped floating-gate MOS tube m1, m2, m5, m6.

In described master flip-flop, form two PMOS pipe m3 of differential configuration and the drain electrode of m4 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m1 and m2 respectively, and the output of generation master flip-flop

and x; In described slave flipflop, form two PMOS pipe m7 of differential configuration and the drain electrode of m8 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m5 and m6 respectively, and by two inverter INV1 and INV2 be connected to output Q with

The input of the three input floating-gate MOS tube m1 that adopt in the design (V1=D,

v3=GND) weight is identical, i.e. C1=C2=C3=C; The input of the three input floating-gate MOS tube m2 that adopt in the design

v3=GND) weight is identical, i.e. C1=C2=C3=C; The weight of the input (V1=x, V2=clk, V3=S) of the three input floating-gate MOS tube m5 that adopt in the design is: i.e. C1=C2=C, C3=2C; The input of the three input floating-gate MOS tube m6 that adopt in the design

v2=clk, V3=R) weight be: i.e. C1=C2=C, C3=2C.

According to formula (4):

For m1, only need

$\frac{V1*C1+V2*C2+V3*C3}{C1+C2+C3}\≥V_T=\frac{V_{\mathrm{DD}}}{2},$ M1 conducting,

? $\frac{V1+V2}{3}\≥V_T=\frac{V_{\mathrm{DD}}}{2};---\left(6\right)$

For m2, only need

$\frac{V1*C1+V2*C2+V3*C3}{C1+C2+C3}\≥V_T=\frac{V_{\mathrm{DD}}}{2},$ M2 conducting,

? $\frac{V1+V2}{3}\≥V_T=\frac{V_{\mathrm{DD}}}{2};---\left(7\right)$

For m5, only need

$\frac{V1*C1+V2*C2+V3*C3}{C1+C2+C3}\≥V_T=\frac{V_{\mathrm{DD}}}{2},$ M5 conducting,

? $\frac{V1+V2+2V3}{4}\≥V_T=\frac{V_{\mathrm{DD}}}{2};---\left(8\right)$

For m6, only need

$\frac{V1*C1+V2*C2+V3*C3}{C1+C2+C3}\≥V_T=\frac{V_{\mathrm{DD}}}{2},$ M6 conducting,

? $\frac{V1+V2+2V3}{4}\≥V_T=\frac{V_{\mathrm{DD}}}{2}.---\left(9\right)$

In the time of S=1 and R=0, formula (8) meets, m5 conducting, and output Q is 1; By the feedback of difference pipe m8,

be 0, realize asynchronous set function.

In the time of S=0 and R=1, formula (9) meets, m6 conducting, output

be 1; By the feedback of difference pipe m7, Q is 0, realizes asynchronous resetting function.

In the time of S=0 and R=0, described flip-flop operation state is as follows:

In the time of clk low level, according to formula (6) and (7), the V2=1 in m1 and m2, described master flip-flop receives input signal, in the time that input D is high level, m1 conducting and m2 cut-off, master flip-flop output x and

be respectively 1 and 0; Work as input

during for high level, m2 conducting and m1 cut-off, master flip-flop output x and

be respectively 0 and 1; Now according to formula (8) and (9), m5 and m6 cut-off, slave flipflop cuts out, output Q and

remain unchanged; In the time of clk rising edge, according to formula (6) and (7), the V2=0 in m1 and m2, master flip-flop cuts out, slave flipflop open, the output x of master flip-flop and

determine output Q and

in the time that x is high level, m5 conducting and m6 cut-off, output Q and

be 1 and 0; In the time that x is low level, m6 conducting and m5 cut-off, output Q and

be 0 and 1.

Represent arbitrary value with φ.According to the course of work above, the operating state that can sum up described a kind of difference type list edge D flip-flop circuit based on neuron mos pipe is as shown in the table:

Claims (1)

1. the difference type list edge D flip-flop based on neuron mos pipe, is characterized in that: comprise the master flip-flop of differential configuration and the slave flipflop of differential configuration;

Described master flip-flop is managed m3 and m4 by two PMOS that form differential configuration, inputs N-shaped floating-gate MOS tube m1 and m2 formation for two three; Described slave flipflop forms by forming two PMOS pipe m7 of differential configuration and m8, two three input N-shaped floating-gate MOS tube m5 and m6, two inverter INV1 and INV2;

Described PMOS pipe m3, m4, m7 and m8 source class meet operating voltage VDD, the source class ground connection of described three input N-shaped floating-gate MOS tube m1, m2, m5 and m6;

In described master flip-flop, form two PMOS pipe m3 of differential configuration and the drain electrode of m4 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m1 and m2 respectively, and the output of generation master flip-flop

and x; In described slave flipflop, form two PMOS pipe m7 of differential configuration and the drain electrode of m8 is connected with the drain electrodes of two three input N-shaped floating-gate MOS tube m5 and m6 respectively, and by two inverter INV1 and INV2 be connected to output Q with

In the time of clk low level, described master flip-flop receives input signal, determine master flip-flop output x and

now described slave flipflop cuts out, the output Q of slave flipflop and

remain unchanged; In the time of clk rising edge, master flip-flop cuts out, slave flipflop open, determine master flip-flop output x and

determine the output of slave flipflop, the output Q of whole trigger and s and R realize respectively asynchronous set and the asynchronous resetting function of trigger simultaneously.

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