CN102638248B - Voltage type four-value Schmidt trigger circuit based on neuron MOS (Metal Oxide Semiconductor) tube - Google Patents

Abstract

The invention discloses a voltage type four-value Schmidt trigger circuit based on a neuron MOS (Metal Oxide Semiconductor) tube. The voltage type four-value Schmidt trigger circuit comprises a threshold-0.5 reversed phase operation and threshold-0.5 operation circuit part 11 with return difference characteristic, a threshold-1.5 reversed phase operation and threshold-1.5 operation circuit part 12 with return difference characteristic, a threshold-2.5 reversed phase operation and threshold-2.5 operation circuit part 13 with return difference characteristic, and a four-value signal transmission control circuit part 14. The voltage type four-value Schmidt trigger circuit is completely based on a standard double-layer polycrystalline silicon CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process, and three return difference voltage values in the four-value Schmidt trigger circuit can be adjusted by changing a capacitance coupling coefficient. A complementary neuron MOS tube scheme with an independent floating boom structure is adopted, so that the circuit has the characteristics of low power consumption and high noise margin. Moreover, threshold operation of a neuron MOS tube design and a reverse phase circuit thereof are adopted, so that threshold values are easy to control, thus the four-value Schmidt trigger circuit has a simple structure.

Description

A kind of voltage-type four value Schmitt trigger circuits based on neuron mos pipe

Technical field

The present invention relates to a kind of Schmitt trigger circuit, relate in particular to a kind of voltage-type four value Schmitt trigger circuits based on neuron mos pipe.

Background technology

Schmidt trigger can effectively suppress to be superimposed upon the interference on signal, and erasure signal trembles and is used widely, and it is, in analog-and digital-system, signal is carried out to Shape correction, improves a kind of common circuit that ON/OFF is controlled.Two key characters of Schmidt circuit are: can effectively receive the input signal of slow variation and be changed into fast-changing output signal; Direct current transmission characteristic for forward and negative sense input signal has different detection thresholds, and both differences are referred to as return difference.In MULTI-VALUED LOGIC CIRCUIT, many-valued Schmidt circuit also should have its corresponding status of using.Circuit is by relatively the making of input signal and threshold value to the detection of signal value, and detection threshold occupy between adjacent two kinds of signal values.Therefore, for detecting a m value logical signal, its value is 0,1 ..., m-1, needs to arrange 0.5,1.5 in circuit ..., m-1.5, altogether m-1 detection threshold.In the design of many-valued Schmidt circuit, need this m-1 the detection threshold to control to realize the return difference characteristic of corresponding threshold value, therefore the design of many-valued Schmidt circuit is more complex than binarization circuit.

At present, the many-valued Schmidt circuit based on CMOS technological design mainly contains dividing of current mode and voltage-type.Many-valued current-mode CMOS Schmidt circuit is because existing DC channel conventionally need to consume larger power consumption, though many-valued voltage-type cmos schmitt circuit has the feature of low-power consumption, but many-valued voltage-type cmos circuit has the metal-oxide-semiconductor of a plurality of threshold values for realizing, need to increase extra ion injecting process or need adopt enhancement mode and two kinds of metal-oxide-semiconductors of depletion type simultaneously, this has increased process complexity, and practicality is placed restrictions on.Due to the interface of the easy realization of four-valued logic with two-valued function circuit, therefore the design of four value cmos schmitt circuit is just seemed to particularly meaningful.

Summary of the invention

The object of the invention is to propose a kind of voltage-type four value Schmitt trigger circuits based on neuron mos pipe, they can also carry out adjusting return difference voltage by changing input end capacitor coupling coefficient except having low-power consumption and feature simple in structure.

Design of the present invention is to achieve these goals.The invention provides a kind of voltage-type four value Schmitt trigger circuits based on neuron mos pipe, comprise threshold 0.5 circuit, threshold 1.5 circuit, threshold 2.5 circuit and four value signal transmission control circuits; Described threshold 0.5 circuit is connected with respectively power supply V _dD, power supply V ₂and input signal end V _in; Described threshold 1.5 circuit are connected with respectively power supply V _dD, power supply V ₂, power supply V ₁and input signal end V _in; Described threshold 2.5 circuit are connected with respectively power supply V _dD, power supply V ₁and input signal end V _in; Described four value signal transmission control circuits are connected with respectively power supply V _dD, power supply V ₁, power supply V ₂and output signal end V _out; Described threshold 0.5 circuit, threshold 1.5 circuit and threshold 2.5 circuit are connected with four value signal transmission control circuits respectively;

Described threshold 0.5 circuit comprises the anti-phase computing circuit of threshold 0.5 and threshold 0.5 computing circuit with return difference characteristic; The anti-phase computing circuit of described threshold 0.5 and threshold 0.5 computing circuit are made up of threshold 0.5 phase inverter, two-value CMOS phase inverter I and the feedback circuit of complementary type; Described complementary type threshold 0.5 phase inverter comprises neuron pMOS pipe m _P1With neuron nMOS pipe m _N1; Described two-value CMOS phase inverter I comprises pMOS pipe m _P2With nMOS pipe m _N2; Described neuron pMOS pipe m _P1Source electrode meet power supply V _DD, neuron pMOS manages m _P1Drain electrode meet described neuron nMOS pipe m _N1Drain electrode, neuron pMOS manages m _P1Have three grid inputs, the coupling capacitance between these three input grids and floating boom is respectively electric capacity C _P1, electric capacity C _P2With electric capacity C _P3; Described neuron nMOS pipe m _N1Source ground, neuron nMOS manages m _N1Have three grid inputs, the coupling capacitance between these three input grids and floating boom is respectively electric capacity C _N1, electric capacity C _N2With electric capacity C _N3; PMOS pipe m in described two-value CMOS phase inverter I _P2Source electrode meet power supply V _DD, pMOS manages m _P2Drain electrode meet in two-value CMOS phase inverter I nMOS pipe m _N2Drain electrode, nMOS manages m _N2Source ground;PMOS pipe m in described two-value CMOS phase inverter I _P2Grid and nMOS pipe m _N2Grid join as the input of two-value CMOS phase inverter I; Input and the described neuron pMOS pipe m of described two-value CMOS phase inverter I _P1Drain electrode and described neuron nMOS pipe m _N1Drain electrode be connected; Described neuron nMOS pipe m _N1A grid input and described neuron pMOS pipe m _P1A grid input and input signal end V _InJoin; Described neuron pMOS pipe m _P1Another grid input and power supply V _DDBe connected, neuron pMOS manages m _P1One of residue input grid and described two-value CMOS phase inverter I in pMOS manage m _P2Drain electrode and nMOS pipe m _N2The drain electrode formation positive-feedback circuit that joins; Described neuron nMOS pipe m _N1Another grid input termination power V ₂, neuron nMOS manages m _N1One of residue input grid and described two-value CMOS phase inverter I in pMOS manage m _P2Drain electrode and nMOS pipe m _N2The drain electrode formation positive-feedback circuit that joins; Described threshold 1.5 circuit comprises the anti-phase computing circuit of threshold 1.5 and threshold 1.5 computing circuit with return difference characteristic; The anti-phase computing circuit of described threshold 1.5 and threshold 1.5 computing circuit are made up of threshold 1.5 phase inverter, two-value CMOS phase inverter II and the feedback circuit of complementary type; Described complementary type threshold 1.5 phase inverter comprises neuron pMOS pipe m _P3With neuron nMOS pipe m _N3; Described two-value CMOS phase inverter II comprises pMOS pipe m _P4With nMOS pipe m _N4; Described neuron pMOS pipe m _P3Source electrode meet power supply V _DD, neuron pMOS manages m _P3Drain electrode meet neuron nMOS pipe m _N3Drain electrode, neuron pMOS manages m _P3Have three grid inputs, the coupling capacitance between these three input grids and floating boom is respectively electric capacity C _P4, electric capacity C _P5With electric capacity C _P6; Described neuron nMOS pipe m _N3Source ground, neuron nMOS manages m _N3Have three grid inputs, the coupling capacitance between these three input grids and floating boom is respectively electric capacity C _N4, electric capacity C _N5With electric capacity C _N6; PMOS pipe m in described two-value CMOS phase inverter II _P4Source electrode meet power supply V _DD, pMOS manages m _P4Drain electrode meet in two-value CMOS phase inverter II nMOS pipe m _N4Drain electrode, nMOS manages m _N4Source ground; PMOS pipe m in described two-value CMOS phase inverter II _P4Grid and nMOS pipe m _N4Grid join as the input of two-value CMOS phase inverter II; Input and the described neuron pMOS pipe m of described two-value CMOS phase inverter II _P3Drain electrode and described neuron nMOS pipe m _N3Drain electrode be connected; Described neuron nMOS pipe m _N3A grid input and described neuron pMOS pipe m _P3A grid input and input signal end V _InJoin; Described neuron pMOS pipe m _P3Another grid input termination power V ₂, neuron pMOS manages m _P3One of residue input grid and described two-value CMOS phase inverter II in pMOS manage m _P4Drain electrode and nMOS pipe m _N4The drain electrode formation positive-feedback circuit that joins; Described neuron nMOS pipe m _N3Another grid input termination power V ₁, neuron nMOS manages m _N3One of residue input grid and described two-value CMOS phase inverter II in pMOS manage m _P4Drain electrode and nMOS pipe m _N4The drain electrode formation positive-feedback circuit that joins; Described threshold 2.5 circuit comprises the anti-phase computing circuit of threshold 2.5 and threshold 2.5 computing circuit with return difference characteristic; The anti-phase computing circuit of described threshold 2.5 and threshold 2.5 computing circuit are made up of threshold 2.5 phase inverter, two-value CMOS phase inverter III and the feedback circuit of complementary type; Described threshold 2.5 phase inverter comprises neuron pMOS pipe m _P5With neuron nMOS pipe m _N5; Described two-value CMOS phase inverter III comprises pMOS pipe m _P6With nMOS pipe m _N6; Described neuron pMOS pipe m _P5Source electrode meet power supply V _DD, neuron pMOS manages m _P5Drain electrode meet described neuron nMOS pipe m _N5Drain electrode, neuron pMOS manages m _P5There are three grid inputs,Coupling capacitance between these three input grids and floating boom is respectively electric capacity C _P7, electric capacity C _P8With electric capacity C _P9; Described neuron nMOS pipe m _N5Source ground, neuron nMOS manages m _N5Have three grid inputs, the coupling capacitance between these three input grids and floating boom is respectively electric capacity C _N7, electric capacity C _N8With electric capacity C _N9; PMOS pipe m in described two-value CMOS phase inverter III _P6Source electrode meet power supply V _DD, pMOS manages m _P6Drain electrode meet in two-value CMOS phase inverter III nMOS pipe m _N6Drain electrode, nMOS manages m _N6Source ground; PMOS pipe m in described two-value CMOS phase inverter III _P6Grid and nMOS pipe m _N6Grid join as the input of two-value CMOS phase inverter III; Input and the described neuron pMOS pipe m of described two-value CMOS phase inverter III _P5Drain electrode and described neuron nMOS pipe m _N5Drain electrode be connected; Described neuron nMOS pipe m _N5A grid input and described neuron pMOS pipe m _P5A grid input and input signal end V _InJoin, described neuron pMOS pipe m _P5Another grid input termination power V ₁, neuron pMOS manages m _P5One of residue input grid and described two-value CMOS phase inverter III in pMOS manage m _P6Drain electrode and nMOS pipe m _N6The drain electrode formation positive-feedback circuit that joins; Described neuron nMOS pipe m _N5Another grid input end grounding, neuron nMOS manages m _N5One of residue input grid and described two-value CMOS phase inverter III in pMOS manage m _P6Drain electrode and nMOS pipe m _N6The drain electrode formation positive-feedback circuit that joins; Described four value signal transmission control circuits are managed m by pMOS _P7, pMOS manages m _P8, pMOS manages m _P9With nMOS pipe m _N7, nMOS manages m _N8, nMOS manages m _N9Composition; Described pMOS pipe m _P7Source electrode meet power supply V _DD, pMOS manages m _P7Drain electrode meet described nMOS pipe m _N7Drain electrode, pMOS manages m _P7Grid be connected in described threshold 0.5 circuit pMOS pipe m in two-value two-value CMOS phase inverter I _P2With nMOS pipe m _N2Drain electrode; Described nMOS pipe m _N7Source ground, nMOS manages m _N7Grid be connected in described threshold 2.5 circuit pMOS pipe m in two-value CMOS phase inverter III _P6With nMOS pipe m _N6Drain electrode; Described pMOS pipe m _P8Drain electrode and described pMOS pipe m _P9Source electrode be serially connected with power supply V ₂With output signal end V _outBetween, pMOS manages m _P8Grid be connected in described threshold 0.5 circuit neuron pMOS pipe m _P1With neuron nMOS pipe m _N1Drain electrode; Described nMOS pipe m _N8Source electrode and nMOS pipe m _N9Drain electrode be serially connected with output signal end V _outWith power supply V ₁Between; Described nMOS pipe m _N9Grid be connected in described threshold 2.5 circuit neuron pMOS pipe m _P5With neuron nMOS pipe m _N5Drain electrode; Described pMOS pipe m _P9Grid and described nMOS pipe m _N8Grid be connected to pMOS pipe m in two-value CMOS phase inverter II in described threshold 1.5 circuit _P4With nMOS pipe m _N4Drain electrode.

Compare with existing design, the beneficial effect that the present invention has is: for input, the threshold voltage of neuron MOS devices or circuit can be subject to the control of external control gate signal, and this has overcome traditional electrical die mould MULTI-VALUED LOGIC CIRCUIT has a plurality of threshold voltages metal-oxide-semiconductor for realizing effectively needs extra ion injecting process or need adopt enhancement mode and two kinds of metal-oxide-semiconductors of depletion type increase the defects such as process complexity simultaneously.The threshold value that circuit has utilized neuron mos pipe to have is easy to control this natural quality, without increasing special circuit, only need just can realize easily the Regenerative feedback in Schmidt circuit by increase respectively by a grid input in p-type and N-shaped floating-gate MOS tube, this makes designed circuit have very simple structure.Employing has the complementary floating-gate MOS tube scheme of independent floating gate structure, has guaranteed that circuit has the feature of low-power consumption and strong noise tolerance limit.And, can adjust easily hysteresis voltage by changing capacitive coupling coefficient.By increasing the fan-in of floating-gate MOS tube, can access easily external control signal, thereby change high and low two threshold voltages in Schmidt circuit.Therefore the maximum feature that the present invention has is adjust hysteresis voltage conveniently and can directly control threshold voltage by external control signal.The complete measured double level polysilicon CMOS technique of the present invention, except keeping the feature of voltage-type circuit low-power consumption, new design has that circuit structure is simple, hysteresis voltage regulates easily, and threshold voltage is controlled to the features such as convenient and flexible.

Accompanying drawing explanation

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in further detail.

Fig. 1 is the voltage-type four value Schmitt trigger circuits based on neuron mos pipe;

Fig. 2 is N-shaped neuron mos pipe and the symbol of p-type neuron mos pipe and their capacitor model related in Fig. 1;

Fig. 3 is the voltage-transfer characteristic curve { C of four value Schmitt trigger circuits shown in Fig. 1 _{n (p) i}: C _{n (p) (i+1)}: C _{n (p) (i+2)}=15:15:1, i ∈ (Isosorbide-5-Nitrae, 7) };

Fig. 4 is the voltage-transfer characteristic curve { C of four value Schmitt trigger circuits shown in Fig. 1 _{n (p) i}: C _{n (p) (i+1)}: C _{n (p) (i+2)}=6:6:1, i ∈ (Isosorbide-5-Nitrae, 7) }.

Embodiment

Embodiment 1, Fig. 1 have provided a kind of voltage-type four value Schmitt trigger circuits based on neuron mos pipe, comprise threshold 0.5 circuit 11, threshold 1.5 circuit 12, threshold 2.5 circuit 13 and four value signal transmission control circuits 14; Threshold 0.5 circuit 11 is connected with respectively power supply V _dD, power supply V ₂and input signal end V _in; Threshold 1.5 circuit 12 are connected with respectively power supply V _dD, power supply V ₂, power supply V ₁and input signal end V _in; Threshold 2.5 circuit 13 are connected with respectively power supply V _dD, power supply V ₁and input signal end V _in; Four value signal transmission control circuits 14 are connected with respectively power supply V _dD, power supply V ₁, power supply V ₂and output signal end V _out; Threshold 0.5 circuit 11, threshold 1.5 circuit 12 and threshold 2.5 circuit 13 are connected with four value signal transmission control circuits 14 respectively.Concrete connected mode is as follows:

Threshold 0.5 circuit 11 comprises the anti-phase computing circuit of threshold 0.5 and threshold 0.5 computing circuit with return difference characteristic; The anti-phase computing circuit of threshold 0.5 and threshold 0.5 computing circuit consist of threshold 0.5 inverter, two-value CMOS inverter I and the feedback circuit of complementary type; Complementary type threshold 0.5 inverter comprises neuron pMOS pipe m _p1with neuron nMOS pipe m _n1; Two-value CMOS inverter I comprises pMOS pipe m _p2with nMOS pipe m _n2.

Neuron pMOS manages m _p1source electrode meet power supply V _dD, neuron pMOS manages m _p1drain electrode meet neuron nMOS pipe m _n1drain electrode, neuron pMOS manages m _p1have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _p1, capacitor C _p2and capacitor C _p3; Neuron nMOS manages m _n1source ground, neuron nMOS manages m _n1have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _n1, capacitor C _n2and capacitor C _n3; PMOS pipe m in two-value CMOS inverter I _p2source electrode meet power supply V _dD, pMOS manages m _p2drain electrode meet in two-value CMOS inverter I nMOS pipe m _n2drain electrode, nMOS manages m _n2source ground; PMOS pipe m in two-value CMOS inverter I _p2grid and nMOS pipe m _n2grid join as the input of two-value CMOS inverter I; The input of two-value CMOS inverter I and neuron pMOS pipe m _p1drain electrode and neuron nMOS pipe m _n1drain electrode be connected; Neuron nMOS manages m _n1grid input and neuron pMOS pipe m _p1grid input and input signal end V _injoin; Neuron pMOS manages m _p1another grid input and power supply V _dDbe connected, neuron pMOS manages m _p1one of residue input grid and two-value CMOS inverter I in pMOS manage m _p2drain electrode and nMOS pipe m _n2the drain electrode formation regenerative circuit that joins; Neuron nMOS manages m _n1another grid input termination power V ₂, neuron nMOS manages m _n1one of residue input grid and two-value CMOS inverter I in pMOS manage m _p2drain electrode and nMOS pipe m _n2the drain electrode formation regenerative circuit that joins.

Threshold 1.5 circuit 12 comprise the anti-phase computing circuit of threshold 1.5 and threshold 1.5 computing circuits with return difference characteristic; The anti-phase computing circuit of threshold 1.5 and threshold 1.5 computing circuits are comprised of threshold 1.5 inverters, two-value CMOS inverter II and the feedback circuit of complementary type; Complementary type threshold 1.5 inverters comprise neuron pMOS pipe m _p3with neuron nMOS pipe m _n3; Two-value CMOS inverter II comprises pMOS pipe m _p4with nMOS pipe m _n4.

Neuron pMOS manages m _p3source electrode meet power supply V _dD, neuron pMOS manages m _p3drain electrode meet neuron nMOS pipe m _n3drain electrode, neuron pMOS manages m _p3have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _p4, capacitor C _p5and capacitor C _p6; Neuron nMOS manages m _n3source ground, neuron nMOS manages m _n3have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _n4, capacitor C _n5and capacitor C _n6; PMOS pipe m in two-value CMOS inverter II _p4source electrode meet power supply V _dD, pMOS manages m _p4drain electrode meet in two-value CMOS inverter II nMOS pipe m _n4drain electrode, nMOS manages m _n4source ground; PMOS pipe m in two-value CMOS inverter II _p4grid and nMOS pipe m _n4grid join as the input of two-value CMOS inverter II; The input of two-value CMOS inverter II and neuron pMOS pipe m _p3drain electrode and neuron nMOS pipe m _n3drain electrode be connected; Neuron nMOS manages m _n3grid input and neuron pMOS pipe m _p3grid input and input signal end V _injoin; Neuron pMOS manages m _p3another grid input termination power V ₂, neuron pMOS manages m _p3one of residue input grid and two-value CMOS inverter II in pMOS manage m _p4drain electrode and nMOS pipe m _n4the drain electrode formation regenerative circuit that joins; Neuron nMOS manages m _n3another grid input termination power V ₁, neuron nMOS manages m _n3one of residue input grid and two-value CMOS inverter II in pMOS manage m _p4drain electrode and nMOS pipe m _n4the drain electrode formation regenerative circuit that joins.

Threshold 2.5 circuit 13 comprise the anti-phase computing circuit of threshold 2.5 and threshold 2.5 computing circuits with return difference characteristic; The anti-phase computing circuit of threshold 2.5 and threshold 2.5 computing circuits are comprised of threshold 2.5 inverters, two-value CMOS inverter III and the feedback circuit of complementary type; Threshold 2.5 inverters comprise neuron pMOS pipe m _p5with neuron nMOS pipe m _n5; Two-value CMOS inverter III comprises pMOS pipe m _p6with nMOS pipe m _n6.

Neuron pMOS manages m _p5source electrode meet power supply V _dD, neuron pMOS manages m _p5drain electrode meet neuron nMOS pipe m _n5drain electrode, neuron pMOS manages m _p5have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _p7, capacitor C _p8and capacitor C _p9; Neuron nMOS manages m _n5source ground, neuron nMOS manages m _n5have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _n7, capacitor C _n8and capacitor C _n9; PMOS pipe m in two-value CMOS inverter III _p6source electrode meet power supply V _dD, pMOS manages m _p6drain electrode meet in two-value CMOS inverter III nMOS pipe m _n6drain electrode, nMOS manages m _n6source ground; PMOS pipe m in two-value CMOS inverter III _p6grid and nMOS pipe m _n6grid join as the input of two-value CMOS inverter III; The input of two-value CMOS inverter III and neuron pMOS pipe m _p5drain electrode and neuron nMOS pipe m _n5drain electrode be connected; Neuron nMOS manages m _n5grid input and neuron pMOS pipe m _p5grid input and input signal end V _injoin, neuron pMOS manages m _p5another grid input termination power V ₁, neuron pMOS manages m _p5one of residue input grid and two-value CMOS inverter III in pMOS manage m _p6drain electrode and nMOS pipe m _n6the drain electrode formation regenerative circuit that joins; Neuron nMOS manages m _n5another grid input end grounding, neuron nMOS manages m _n5one of residue input grid and two-value CMOS inverter III in pMOS manage m _p6drain electrode and nMOS pipe m _n6the drain electrode formation regenerative circuit that joins.

Four value signal transmission control circuits (14) are by pMOS pipe m _p7, pMOS manages m _p8, pMOS manages m _p9with nMOS pipe m _n7, nMOS manages m _n8, nMOS manages m _n9form; PMOS manages m _p7source electrode meet power supply V _dD, pMOS manages m _p7drain electrode meet nMOS pipe m _n7drain electrode, pMOS manages m _p7grid be connected in threshold 0.5 circuit 11 pMOS pipe m in two-value CMOS inverter I _p2with nMOS pipe m _n2drain electrode; NMOS manages m _n7source ground, nMOS manages m _n7grid be connected in threshold 2.5 circuit 13 pMOS pipe m in two-value CMOS inverter III _p6with nMOS pipe m _n6drain electrode; PMOS manages m _p8drain electrode and pMOS pipe m _p9source electrode be serially connected with power supply V ₂with output signal end V _outbetween, pMOS manages m _p8grid be connected in threshold 0.5 circuit 11 neuron pMOS pipe m _p1with neuron nMOS pipe m _n1drain electrode; NMOS manages m _n8source electrode and nMOS pipe m _n9drain electrode be serially connected with output signal end V _outwith power supply V ₁between; NMOS manages m _n9grid be connected in threshold 2.5 circuit 13 neuron pMOS pipe m _p5with neuron nMOS pipe m _n5drain electrode; PMOS manages m _p9grid and nMOS pipe m _n8grid be connected to pMOS pipe m in two-value CMOS inverter II in threshold 1.5 circuit 12 _p4with nMOS pipe m _n4drain electrode.

In the above four value signal transmission control circuit part 14, pMOS manages m _p7be used for transmitting power supply V _dDvoltage V _dD, pMOS manages m _p8with pMOS pipe m _p9be used for transmitting power supply V ₂voltage V ₂, nMOS manages m _n8with nMOS pipe m _n9be used for transmitting power supply V ₁voltage V ₁, nMOS manages m _n7be used for transmitting ground voltage 0.0, V ₁, V ₂and V _dDcorrespond respectively to quaternary logic signal (0,1,2,3).

Neuron mos pipe is a kind of new device with features such as high functionality, low-power consumption and threshold value control are flexible proposing in recent years, and people have carried out further investigation in a plurality of fields such as simulation, numeral and neural nets to its application.The double level polysilicon CMOS technique of the processing technology of this device and standard is completely compatible, and the symbol of N-shaped neuron mos pipe and p-type neuron mos pipe and their capacitor model are as shown in Figure 2.It has a plurality of input grids and a floating boom utmost point, and wherein floating boom is formed by ground floor polysilicon, and a plurality of input control grid are formed by second layer polysilicon.Between input and floating boom, by electric capacity, realize coupling.V in figure _frepresent the voltage on floating boom, V ₀for underlayer voltage, V ₁, V ₂..., V _nfor applied signal voltage.C ₀be the coupling capacitance between floating boom and substrate, it is mainly by gate oxide capacitor C _oxform C ₁, C ₂..., C _nfor the coupling capacitance between each input grid and floating boom.In figure, D and S represent respectively drain electrode and source electrode.

Net charge Q on floating boom _fby following formula, provided:

$Q_F=\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i(V_F-V_i)=V_F\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i-\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i{V}_i;---\left(1\right)$

For n raceway groove floating-gate MOS tube, substrate ground connection, so V ₀=0.Suppose that the initial charge on floating boom is zero, according to law of conservation of charge, can be obtained fom the above equation:

$V_F=\underset{i=1}{\overset{n}{\mathrm{\Σ}}}{w}_i{V}_i;---\left(2\right)$

$w_i=\frac{C_i}{C_0+\underset{j=1}{\overset{n}{\mathrm{\Σ}}}{C}_j}.---\left(3\right)$

W in formula _ifor input V _ielectric capacity weights.If V _tfor the threshold voltage of the pipe seen into by floating boom end, work as V _f>V _tshi Guanzi conducting.By formula (2) and (3), can be found out, neuron mos pipe can, to each grid input signal weighted sum, go to control " opening " and " pass " of metal-oxide-semiconductor by the summed result calculating.The weighted sum computing of noticing all input signals that it carries out on floating boom utilizes capacitance coupling effect to carry out with voltage mode, and this has shown that it has the low-power consumption characteristic more outstanding than current-mode summation technology.If with V ₁as input, other inputs, as control end, have:

$V_1>\frac{\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i}{C_1}{V}_T-\frac{C_2}{C_1}{V}_2-...-\frac{C_n}{C_1}{V}_n;---\left(4\right)$

Like this, by V ₁the threshold voltage V of the pipe that end is seen into ^* _t1can be expressed as:

${V^{*}}_{t1}=\frac{\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{C}_i}{C_1}{V}_T-\frac{C_2}{C_1}{V}_2-...-\frac{C_n}{C_1}{V}_n.---\left(5\right)$

Above formula shows, without adjusting V _t, as long as by changing the proportionate relationship between coupling capacitance or changing control end voltage V _ijust can change floating-gate MOS tube with respect to input signal V ₁threshold voltage, thereby control conducting and the cut-off of metal-oxide-semiconductor.This characteristic has overcome traditional electrical die mould MULTI-VALUED LOGIC CIRCUIT has a plurality of threshold voltages metal-oxide-semiconductor for realizing effectively to be needed extra ion injecting process or need adopt enhancement mode and two kinds of metal-oxide-semiconductors of depletion type increase the defects such as process complexity and design cost simultaneously.For p raceway groove floating-gate MOS tube, the maximum voltage sources in the common connection circuit of substrate is (as V _dD), so V in formula (1) ₀=V _dD, corresponding correction need be done in formula (2)-(5).

The present invention has utilized the threshold value of neuron mos pipe to be easy to control this natural quality just, has proposed a kind of new voltage-type four value Schmidt circuit designs.Without increasing special circuit, only need just can realize easily the Regenerative feedback in Schmidt circuit by increase respectively by a grid input in p-type and N-shaped floating-gate MOS tube, this makes designed circuit have very simple structure.Employing has the complementary floating-gate MOS tube scheme of independent floating gate structure, has guaranteed that circuit has the feature of low-power consumption and strong noise tolerance limit.And, can adjust easily hysteresis voltage by changing capacitive coupling coefficient.By increasing the fan-in of floating-gate MOS tube, can access easily external control signal, thereby change the threshold voltage in Schmidt circuit.The complete measured double level polysilicon CMOS technique of the present invention, except keeping the feature of voltage-type circuit low-power consumption, new design has that circuit structure is simple, hysteresis voltage regulates easily, and threshold voltage is controlled to the features such as convenient and flexible.Below in conjunction with drawings and Examples, the present invention is further described, and it is more obvious that object of the present invention and effect will become.

In the circuit shown in Fig. 1, the threshold voltage with threshold 0.5 circuit 11, threshold 1.5 circuit 12 and threshold 2.5 circuit 13 (being the anti-phase computing circuit of threshold 0.5 and threshold 0.5 computing circuit, the anti-phase computing circuit of threshold 1.5 and threshold 1.5 computing circuits and the anti-phase computing circuit of threshold 2.5 and threshold 2.5 computing circuits) of return difference characteristic is provided by following formula:

$V_{\mathrm{TH}}=\frac{V_{\mathrm{DD}}+{V^{*}}_{\mathrm{tp}}+{V^{*}}_{\mathrm{tn}}\sqrt{{K^{*}}_R}}{1+\sqrt{{K^{*}}_R}};---\left(6\right)$

Wherein, k _nand K _p(N-shaped floating-gate MOS tube is neuron nMOS pipe m to be respectively N-shaped and p-type floating-gate MOS tube _n1, neuron nMOS manages m _n3with neuron nMOS pipe m _n5; P-type floating-gate MOS tube is neuron pMOS pipe m _p1, neuron pMOS manages m _p3with neuron pMOS pipe m _p5) gain factor, w _{n (p) i}electric capacity weights for N-shaped or p-type floating-gate MOS tube input, are provided by formula (3).V ^* _tnand V ^* _tpbe respectively relative input end signal V _inn-shaped and the equivalent threshold voltage of p-type floating-gate MOS tube.Get K ^* _r=1, formula (6) can be reduced to:

$V_{\mathrm{TH}}=\frac{V_{\mathrm{DD}}+{V^{*}}_{\mathrm{tp}}+{V^{*}}_{\mathrm{tn}}}{2}.---\left(7\right)$

For the anti-phase computing circuit of threshold 0.5 shown in Fig. 1 and threshold 0.5 computing circuit, V while supposing to start _in=0 (V _inbe the input signal of input signal end), N-shaped floating-gate MOS tube m so _n1(be neuron nMOS pipe m _n1) cut-off, p-type floating-gate MOS tube m _p1(be neuron pMOS pipe m _p1) conducting, output v _0.5=0, wherein and V _0.5be respectively the output voltage of the anti-phase computing circuit of threshold 0.5 and threshold 0.5 computing circuit.Along with input signal end signal V _inrising, m _n1(be neuron nMOS pipe m _n1) conducting gradually, m _p1(be neuron pMOS pipe m _p1) cut-off gradually, finally cause output that state turnover occurs.By formula (7), can be tried to achieve when input signal rises, threshold voltage during circuit generation state turnover is:

$V_{\mathrm{TH}(0.5+)}=\frac{1}{2}[V_{\mathrm{DD}}+\frac{1}{w_{n1}}{V}_{\mathrm{tn}}-\frac{w_{n2}}{w_{n1}}{V}_2+\frac{1}{w_{p1}}{V}_{\mathrm{tp}}+\frac{1-w_{p1}}{w_{p1}}{V}_{\mathrm{DD}}-\frac{w_{p2}}{w_{p1}}{V}_{\mathrm{DD}}];---\left(8\right)$

Wherein, V _tnand V _tp(N-shaped floating-gate MOS tube is neuron nMOS pipe m to be respectively N-shaped and p-type floating-gate MOS tube _n1, neuron nMOS manages m _n3with neuron nMOS pipe m _n5; P-type floating-gate MOS tube is neuron pMOS pipe m _p1, neuron pMOS manages m _p3with neuron pMOS pipe m _p5) threshold voltage, w _{n (p) i}electric capacity weights for N-shaped or p-type floating-gate MOS tube input, are provided by formula (3).V _{tH (0.5+)}be in four value Schmidt circuits the high threshold voltage for threshold 0.5.Once by neuron pMOS pipe m _p1with neuron nMOS pipe m _n1the output switching activity of complementary type threshold 0.5 inverter circuit forming is low level, will make by m _p2and m _n2the output of the two-value CMOS inverter circuit forming becomes high level.This high level output signal feedback of two-value CMOS inverter is to the grid input of front stage circuits, and further the nMOS of accelerans unit manages m again _n1conducting and neuron pMOS pipe m _p1cut-off, thus Regenerative feedback set up, and the result of this positive feedback becomes rapidly the output voltage of threshold 0.5 anti-phase computing circuit the output voltage of threshold 0.5 computing circuit becomes rapidly V _0.5=V _dD.As input signal end signal V _inwhile being declined by high level, will there is contrary state-transition in circuit.In like manner can try to achieve input signal end signal V _inin decline process, threshold voltage when upset occurs circuit is:

$V_{\mathrm{TH}(0.5-)}=\frac{1}{2}[V_{\mathrm{DD}}+\frac{1}{w_{n1}}{V}_{\mathrm{tn}}-\frac{w_{n2}}{w_{n1}}{V}_2-\frac{w_{n3}}{w_{n1}}{V}_{\mathrm{DD}}+\frac{1}{w_{p1}}{V}_{\mathrm{tp}}+\frac{{1-w}_{p1}}{w_{p1}}{V}_{\mathrm{DD}}-\frac{w_{p2}}{w_{p1}}{V}_{\mathrm{DD}}-\frac{w_{p3}}{w_{p1}}{V}_{\mathrm{DD}}].---\left(9\right)$

V _{tH (0.5-)}be in four value Schmidt circuits the low threshold voltage with respect to threshold 0.5.Get w _p1=w _n1, w _p2=w _n2, w _p3=w _n3, by formula (8) and (9), can try to achieve hysteresis voltage and be

In like manner, for threshold 1.5 circuit 12 shown in Fig. 1, in input signal rising and decline process, the threshold voltage during conversion of circuit generation state is respectively:

$V_{\mathrm{TH}(1.5+)}=\frac{1}{2}[V_{\mathrm{DD}}+\frac{1}{w_{n4}}{V}_{\mathrm{tn}}-\frac{w_{n5}}{w_{n4}}{V}_1+\frac{1}{w_{p4}}{V}_{\mathrm{tp}}+\frac{1-w_{p4}}{w_{p4}}{V}_{\mathrm{DD}}-\frac{w_{p5}}{w_{p4}}{V}_2];---\left(10\right)$

$V_{\mathrm{TH}(1.5-)}=\frac{1}{2}[V_{\mathrm{DD}}+\frac{1}{w_{n4}}{V}_{\mathrm{tn}}-\frac{w_{n5}}{w_{n4}}{V}_1-\frac{w_{n6}}{w_{n4}}{V}_{\mathrm{DD}}+\frac{1}{w_{p4}}{V}_{\mathrm{tp}}+\frac{{1-w}_{p4}}{w_{p4}}{V}_{\mathrm{DD}}-\frac{w_{p5}}{w_{p4}}{V}_2-\frac{w_{p6}}{w_{p4}}{V}_{\mathrm{DD}}].---\left(11\right)$

V wherein _{tH (1.5+)}be in four value Schmidt circuits for the high threshold voltage of threshold 1.5, V _{tH (1.5-)}be in four value Schmidt circuits the low threshold voltage with respect to threshold 1.5.For threshold 2.5 circuit 13 shown in Fig. 1, in input signal rising and decline process, the threshold voltage during conversion of circuit generation state is respectively:

$V_{\mathrm{TH}(2.5+)}=\frac{1}{2}[V_{\mathrm{DD}}+\frac{1}{w_{n7}}{V}_{\mathrm{tn}}-\frac{1}{w_{p7}}{V}_{\mathrm{tp}}+\frac{1-w_{p7}}{w_{p7}}{V}_{\mathrm{DD}}-\frac{w_{p8}}{w_{p7}}{V}_1];---\left(12\right)$

$V_{\mathrm{TH}(2.5-)}=\frac{1}{2}[V_{\mathrm{DD}}+\frac{1}{w_{n7}}{V}_{\mathrm{tn}}-\frac{w_{n9}}{w_{n7}}{V}_{\mathrm{DD}}+\frac{1}{w_{p7}}{V}_{\mathrm{tp}}+\frac{1-w_{p7}}{w_{p7}}{V}_{\mathrm{DD}}-\frac{w_{p8}}{w_{p7}}{V}_1-\frac{w_{p9}}{w_{p7}}{V}_{\mathrm{DD}}].---\left(13\right)$

V wherein _{tH (2.5+)}be in four value Schmidt circuits for the high threshold voltage of threshold 2.5, V _{tH (2.5-)}be in four value Schmidt circuits the low threshold voltage with respect to threshold 2.5.Above-mentioned formula (8)-(13) show, by changing the proportionate relationship between coupling capacitance or changing three hysteresis voltages that control end voltage just can change this four values Schmidt circuit.Adopt TSMC0.35 μ m double level polysilicon CMOS technological parameter, and power taking source V _dDvoltage V _dD=3.3V, C _{n (p) i}: C _{n (p) (i+1)}: C _{n (p) (i+2)}=15:15:1, i ∈ (Isosorbide-5-Nitrae, 7), Fig. 3 has provided the voltage-transfer characteristic curve obtaining through HSPICE simulation.The hysteresis voltage value that simulation obtains and the error between theoretical value are less than 5%.If get C _{n (p) i}: C _{n (p) (i+1)}: C _{n (p) (i+2})=6:6:1, i ∈ (Isosorbide-5-Nitrae, 7), adopts same process parameter, and the voltage-transfer characteristic curve obtaining through HSPICE simulation is as shown in Figure 4.Analog result shows, by changing the coupling capacitance proportionality coefficient of grid input, can adjust easily the hysteresis voltage of Schmidt trigger.

The invention discloses a kind of voltage-type four value Schmitt trigger circuits based on neuron mos pipe, it (is neuron nMOS pipe m that circuit only needs 63 input neuron mos pipes _n1, neuron nMOS manages m _n3, neuron nMOS manages m _n5, neuron pMOS manages m _p1, neuron pMOS manages m _p3, neuron pMOS manages m _p5) and 12 metal-oxide-semiconductors (be nMOS pipe m _n2, nMOS manages m _n4, nMOS manages m _n6, nMOS manages m _n7, nMOS manages m _n8, nMOS manages m _n9, pMOS manages m _p2, pMOS manages m _p4, pMOS manages m _p6, pMOS manages m _p7, pMOS manages m _p8, pMOS manages m _p9).Therefore, circuit structure is very simple.Different from the complicated technology that needs to adopt multistage ion implantation technique to realize a plurality of threshold voltages in the many-valued Schmidt circuit design of voltage-type in the past, the new complete measured double level polysilicon CMOS technique of design, and three hysteresis voltage values in four value Schmitt trigger circuits can recently be adjusted by changing capacitive coupling coefficient.Employing has the complementary neuron mos pipe scheme of independent floating gate structure, has guaranteed that circuit has the feature of low-power consumption and strong noise tolerance limit.

Finally, it is also to be noted that, what more than enumerate is only a specific embodiment of the present invention.Obviously, the invention is not restricted to above embodiment, can also have many distortion.All distortion that those of ordinary skill in the art can directly derive or associate from content disclosed by the invention, all should think protection scope of the present invention.

Claims (1)

1. the voltage-type four based on neuron mos pipe is worth Schmitt trigger circuits; It is characterized in that: the described voltage-type four value Schmitt trigger circuits based on neuron mos pipe comprise threshold 0.5 circuit (11), threshold 1.5 circuit (12), threshold 2.5 circuit (13) and four value signal transmission control circuits (14);

Described threshold 0.5 circuit (11) is connected with respectively power supply V _dD, power supply V ₂and input signal end V _in;

Described threshold 1.5 circuit (12) are connected with respectively power supply V _dD, power supply V ₂, power supply V ₁and input signal end V _in;

Described threshold 2.5 circuit (13) are connected with respectively power supply V _dD, power supply V ₁and input signal end V _in;

Described four value signal transmission control circuits (14) are connected with respectively power supply V _dD, power supply V ₁, power supply V ₂and output signal end V _out;

Described threshold 0.5 circuit (11), threshold 1.5 circuit (12) and threshold 2.5 circuit (13) are connected with four value signal transmission control circuits (14) respectively;

Described threshold 0.5 circuit (11) comprises the anti-phase computing circuit of threshold 0.5 and threshold 0.5 computing circuit with return difference characteristic;

The anti-phase computing circuit of described threshold 0.5 and threshold 0.5 computing circuit consist of threshold 0.5 inverter, two-value CMOS inverter I and the feedback circuit of complementary type; Described complementary type threshold 0.5 inverter comprises neuron pMOS pipe m _p1with neuron nMOS pipe m _n1; Described two-value CMOS inverter I comprises pMOS pipe m _p2with nMOS pipe m _n2;

Described neuron pMOS pipe m _p1source electrode meet power supply V _dD, neuron pMOS manages m _p1drain electrode meet described neuron nMOS pipe m _n1drain electrode, neuron pMOS manages m _p1have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _p1, capacitor C _p2and capacitor C _p3; Described neuron nMOS pipe m _n1source ground, neuron nMOS manages m _n1have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _n1, capacitor C _n2and capacitor C _n3; PMOS pipe m in described two-value CMOS inverter I _p2source electrode meet power supply V _dD, pMOS manages m _p2drain electrode meet in two-value CMOS inverter I nMOS pipe m _n2drain electrode, nMOS manages m _n2source ground; PMOS pipe m in described two-value CMOS inverter I _p2grid and nMOS pipe m _n2grid join as the input of two-value CMOS inverter I; The input of described two-value CMOS inverter I and described neuron pMOS pipe m _p1drain electrode and described neuron nMOS pipe m _n1drain electrode be connected; Described neuron nMOS pipe m _n1a grid input and described neuron pMOS pipe m _p1grid input and input signal end V _injoin; Described neuron pMOS pipe m _p1another grid input and power supply V _dDbe connected, neuron pMOS manages m _p1one of residue input grid and described two-value CMOS inverter I in pMOS manage m _p2drain electrode and nMOS pipe m _n2the drain electrode formation regenerative circuit that joins; Described neuron nMOS pipe m _n1another grid input termination power V ₂, neuron nMOS manages m _n1one of residue input grid and described two-value CMOS inverter I in pMOS manage m _p2drain electrode and nMOS pipe m _n2the drain electrode formation regenerative circuit that joins;

Described threshold 1.5 circuit (12) comprise the anti-phase computing circuit of threshold 1.5 and threshold 1.5 computing circuits with return difference characteristic; The anti-phase computing circuit of described threshold 1.5 and threshold 1.5 computing circuits are comprised of threshold 1.5 inverters, two-value CMOS inverter II and the feedback circuit of complementary type; Described complementary type threshold 1.5 inverters comprise neuron pMOS pipe m _p3with neuron nMOS pipe m _n3; Described two-value CMOS inverter II comprises pMOS pipe m _p4with nMOS pipe m _n4;

Described neuron pMOS pipe m _p3source electrode meet power supply V _dD, neuron pMOS manages m _p3drain electrode meet neuron nMOS pipe m _n3drain electrode, neuron pMOS manages m _p3have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _p4, capacitor C _p5and capacitor C _p6; Described neuron nMOS pipe m _n3source ground, neuron nMOS manages m _n3have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _n4, capacitor C _n5and capacitor C _n6; PMOS pipe m in described two-value CMOS inverter II _p4source electrode meet power supply V _dD, pMOS manages m _p4drain electrode meet in two-value CMOS inverter II nMOS pipe m _n4drain electrode, nMOS manages m _n4source ground; PMOS pipe m in described two-value CMOS inverter II _p4grid and nMOS pipe m _n4grid join as the input of two-value CMOS inverter II; The input of described two-value CMOS inverter II and described neuron pMOS pipe m _p3drain electrode and described neuron nMOS pipe m _n3drain electrode be connected; Described neuron nMOS pipe m _n3a grid input and described neuron pMOS pipe m _p3grid input and input signal end V _injoin; Described neuron pMOS pipe m _p3another grid input termination power V ₂, neuron pMOS manages m _p3one of residue input grid and described two-value CMOS inverter II in pMOS manage m _p4drain electrode and nMOS pipe m _n4the drain electrode formation regenerative circuit that joins; Described neuron nMOS pipe m _n3another grid input termination power V ₁, neuron nMOS manages m _n3one of residue input grid and described two-value CMOS inverter II in pMOS manage m _p4drain electrode and nMOS pipe m _n4the drain electrode formation regenerative circuit that joins;

Described threshold 2.5 circuit (13) comprise the anti-phase computing circuit of threshold 2.5 and threshold 2.5 computing circuits with return difference characteristic; The anti-phase computing circuit of described threshold 2.5 and threshold 2.5 computing circuits are comprised of threshold 2.5 inverters, two-value CMOS inverter III and the feedback circuit of complementary type; Described threshold 2.5 inverters comprise neuron pMOS pipe m _p5with neuron nMOS pipe m _n5; Described two-value CMOS inverter III comprises pMOS pipe m _p6with nMOS pipe m _n6;

Described neuron pMOS pipe m _p5source electrode meet power supply V _dD, neuron pMOS manages m _p5drain electrode meet described neuron nMOS pipe m _n5drain electrode, neuron pMOS manages m _p5have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _p7, capacitor C _p8and capacitor C _p9; Described neuron nMOS pipe m _n5source ground, neuron nMOS manages m _n5have three grid inputs, these three coupling capacitances of inputting between grid and floating boom are respectively capacitor C _n7, capacitor C _n8and capacitor C _n9; PMOS pipe m in described two-value CMOS inverter III _p6source electrode meet power supply V _dD, pMOS manages m _p6drain electrode meet in two-value CMOS inverter III nMOS pipe m _n6drain electrode, nMOS manages m _n6source ground; PMOS pipe m in described two-value CMOS inverter III _p6grid and nMOS pipe m _n6grid join as the input of two-value CMOS inverter III; The input of described two-value CMOS inverter III and described neuron pMOS pipe m _p5drain electrode and described neuron nMOS pipe m _n5drain electrode be connected; Described neuron nMOS pipe m _n5a grid input and described neuron pMOS pipe m _p5grid input and input signal end V _injoin, described neuron pMOS pipe m _p5another grid input termination power V ₁, neuron pMOS manages m _p5one of residue input grid and described two-value CMOS inverter III in pMOS manage m _p6drain electrode and nMOS pipe m _n6the drain electrode formation regenerative circuit that joins; Described neuron nMOS pipe m _n5another grid input end grounding, neuron nMOS manages m _n5one of residue input grid and described two-value CMOS inverter III in pMOS manage m _p6drain electrode and nMOS pipe m _n6the drain electrode formation regenerative circuit that joins;

Described four value signal transmission control circuits (14) are by pMOS pipe m _p7, pMOS manages m _p8, pMOS manages m _p9with nMOS pipe m _n7, nMOS manages m _n8, nMOS manages m _n9form;

Described pMOS pipe m _p7source electrode meet power supply V _dD, pMOS manages m _p7drain electrode meet described nMOS pipe m _n7drain electrode, pMOS manages m _p7grid be connected in described threshold 0.5 circuit (11) pMOS pipe m in two-value CMOS inverter I _p2with nMOS pipe m _n2drain electrode; Described nMOS pipe m _n7source ground, nMOS manages m _n7grid be connected in described threshold 2.5 circuit (13) pMOS pipe m in two-value CMOS inverter III _p6with nMOS pipe m _n6drain electrode; Described pMOS pipe m _p8drain electrode and described pMOS pipe m _p9source electrode be serially connected with power supply V ₂with output signal end V _outbetween, pMOS manages m _p8grid be connected to neuron pMOS pipe m in described threshold 0.5 circuit (11) _p1with neuron nMOS pipe m _n1drain electrode; Described nMOS pipe m _n8source electrode and nMOS pipe m _n9drain electrode be serially connected with output signal end V _outwith power supply V ₁between; Described nMOS pipe m _n9grid be connected to neuron pMOS pipe m in described threshold 2.5 circuit (13) _p5with neuron nMOS pipe m _n5drain electrode; Described pMOS pipe m _p9grid and described nMOS pipe m _n8grid be connected to pMOS pipe m in two-value CMOS inverter II in described threshold 1.5 circuit (12) _p4with nMOS pipe m _n4drain electrode.