CN110429922A - Trigger - Google Patents
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- Publication number
- CN110429922A CN110429922A CN201910644322.2A CN201910644322A CN110429922A CN 110429922 A CN110429922 A CN 110429922A CN 201910644322 A CN201910644322 A CN 201910644322A CN 110429922 A CN110429922 A CN 110429922A
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- Prior art keywords
- tube
- nmos tube
- pmos tube
- conode
- trigger
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
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- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The present invention relates to triggers, it is related to semiconductor integrated circuit design, by designing the trigger including 4 PMOS tube and 4 NMOS tubes, the quantity of metal-oxide-semiconductor needed for can reduce trigger, reduce the chip area of trigger, and the voltage range of the input signal D of trigger can be between Vt to VDD, wherein Vt is the threshold voltage of the grid of the metal-oxide-semiconductor of trigger, requirement of the current integrated circuit to trigger performance can be better met, and the application range of trigger can be increased.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit more particularly to a kind of triggers.
Background technique
With the rapid development of integrated circuit technique, collect increasing on a large scale on one single chip, therefore it is required that device is got over
Next smaller to integrate more devices, the requirement to device performance is also higher and higher.Sequential logic structure is integrated circuit system
Essential a part, performance also directly affect system performance in system.Wherein trigger is commonly used in sequential logic structure
A kind of component, performance influences the performance of whole system very big.D type flip flop (DFF) as in standard block can not or
Scarce sequential logic structure is widely applied in various designs, also higher to the performance requirement of d type flip flop.
Referring to Fig. 1, Fig. 1 is the schematic diagram of the d type flip flop in the prior art with set function, as shown in Figure 1, including
First phase inverter inv1, the second phase inverter inv2, third phase inverter inv3, the 4th phase inverter inv4 using tri-state gate, use
5th phase inverter inv5 of tri-state gate, the first transmission gate being made of PMOS tube P01 and NMOS tube N01, by PMOS tube P02 and
The second transmission gate, the first NAND gate NAND1 and the second NAND gate NAND2 composition of NMOS tube N02 composition.Wherein, the first reverse phase
Device inv1, the second phase inverter inv2, third phase inverter inv3, using the 4th phase inverter inv4 of tri-state gate, using tri-state gate
5th phase inverter inv5, the first NAND gate NAND1 and the second NAND gate NAND2 are all made of metal-oxide-semiconductor realization, wherein general first is anti-
Phase device inv1, the second phase inverter inv2, third phase inverter inv3 need two metal-oxide-semiconductors to realize, using the 4th reverse phase of tri-state gate
Device inv4 and need four metal-oxide-semiconductors to realize using the 5th phase inverter inv5 of tri-state gate, the first NAND gate NAND1 and second with it is non-
Door NAND2 needs four metal-oxide-semiconductors to realize.Therefore, metal-oxide-semiconductor needed for the existing d type flip flop with set function as shown in Figure 1
Quantity is more, and chip area is big；And it can only operate in an electrical voltage point, namely without level conversion function.For these reasons
Existing d type flip flop is unable to satisfy current integrated circuit to the performance requirement of d type flip flop.
Summary of the invention
The purpose of the present invention is to provide a kind of triggers, to reduce the chip area of trigger, and can increase trigger
Application range.
Trigger provided by the invention, comprising: the source electrode of PMOS tube p1, PMOS tube p1 connect supply voltage VDD, PMOS tube
The grid of p1 receives clock signal CK；The drain electrode of the drain electrode connection PMOS tube p1 of NMOS tube n1, NMOS tube n1, form conode X,
The source electrode of NMOS tube n1 is grounded, and the grid of NMOS tube n1 receives the input signal D of trigger；PMOS tube p2, the source of PMOS tube p2
Pole connects supply voltage VDD, and the grid of PMOS tube p2 receives clock signal CK；The drain electrode of NMOS tube n2, NMOS tube n2 connect
The drain electrode of PMOS tube p2 forms conode Y, the source electrode ground connection of NMOS tube n2, the leakage of the grid connection NMOS tube n1 of NMOS tube n2
The conode X of the drain electrode of pole and PMOS tube p1 receives the voltage signal of conode X；The source electrode of PMOS tube p3, PMOS tube p3 connect
The conode Y of the drain electrode of the drain electrode and PMOS tube p2 of the grid connection NMOS tube n2 of supply voltage VDD, PMOS tube p3, receives altogether
The voltage signal of node Y；The drain electrode of the drain electrode connection PMOS tube p3 of NMOS tube n3, NMOS tube n3, form conode QB, NMOS tube
The source electrode of n3 is grounded, and the grid of NMOS tube n3 receives clock signal CK；The source electrode of PMOS tube p4, PMOS tube p4 connect supply voltage
The conode QB of the drain electrode of the drain electrode and PMOS tube p3 of the grid connection NMOS tube n3 of VDD, PMOS tube p4, receives conode QB's
Voltage signal；And the drain electrode of the drain electrode connection PMOS tube p4 of NMOS tube n4, NMOS tube n4, conode Q is formed, and defeated in Q point
The source electrode of the output signal Q of trigger out, NMOS tube n4 are grounded, the drain electrode of the grid connection NMOS tube n3 of NMOS tube n4 and PMOS
The conode QB of the drain electrode of pipe p3 receives the voltage signal of conode QB.
Further, at the t1 moment, the input signal D of trigger is high level, and clock signal CK is jumped from low level
For high level, D is high level, and NMOS tube n1 conducting, then the voltage signal at conode X is low level, then NMOS tube n2 is not led
Logical, because the eve clock signal CK at the t1 moment is low level, then PMOS tube p2 is connected, and the voltage signal at conode Y is
High level, then PMOS tube p3 is not turned on, and CK is high level from low level jump at this time, and NMOS tube n3 is connected, then at conode QB
Voltage signal be low level, low level conode QB place voltage signal through PMOS tube p4 and NMOS tube n4 composition reverse phase
It is high level that device, which obtains the output signal Q at conode Q,.
Further, at the t2 moment, the input signal D of trigger is low level, and clock signal CK is jumped from low level
For high level, D is low level, and NMOS tube n1 is not turned on, because the eve clock signal CK at the t2 moment is low level, then PMOS
Pipe p1 conducting, then the voltage signal at conode X is high level, then NMOS tube n2 is connected, then the voltage signal at conode Y is
Low level, then PMOS tube p3 is connected, then the voltage signal at conode QB is high level, the voltage at the conode QB of high level
It is low level that the phase inverter that signal is formed through PMOS tube p4 and NMOS tube n4, which obtains the output signal Q at conode Q,.
Further, the trigger is integrated in semi-conductive substrate.
Further, the trigger application CMOS technology is integrated in semi-conductive substrate,.
Further, the trigger only has 4 PMOS tube and 4 NMOS tubes.
Further, PMOS tube p1, PMOS tube p2, PMOS tube p3, PMOS tube p4, NMOS tube n1, NMOS tube n2, NMOS
Pipe n3 and NMOS tube n4 is high-voltage MOS pipe.
Further, the voltage of the high-voltage MOS pipe is 1.5V between 5V.
Further, the 1.5V has the deviation within 5%.
Further, the 5V has the deviation within 5%.
Further, the current capacity of NMOS tube n1, PMOS tube p2 and PMOS tube p3 compared with PMOS tube p1, NMOS tube n2 and
The current capacity of NMOS tube n3 is strong.
Further, the chip area of NMOS tube n1, PMOS tube p2 and PMOS tube p3 compared with PMOS tube p1, NMOS tube n2 and
The chip area of NMOS tube n3 is big.
Further, the voltage range of the input signal D of trigger is between Vt to VDD, and wherein Vt is in trigger
Metal-oxide-semiconductor threshold voltage of the grid.
Trigger provided by the invention can reduce by designing the trigger including 4 PMOS tube and 4 NMOS tubes
The quantity of metal-oxide-semiconductor needed for trigger reduces the chip area of trigger, and the voltage range of the input signal D of trigger can
With between Vt to VDD, wherein Vt is the threshold voltage of the grid of the metal-oxide-semiconductor of trigger, current integrated circuit can be better met
Requirement to trigger performance, and the application range of trigger can be increased.
Detailed description of the invention
Fig. 1 is the schematic diagram of the d type flip flop in the prior art with set function.
Fig. 2 is the schematic diagram of the trigger of one embodiment of the invention.
Fig. 3 is the working waveform figure of trigger shown in Fig. 2.
Fig. 4 is the working waveform figure of trigger shown in Fig. 2.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff's all other embodiment obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In an embodiment of the present invention, a kind of trigger is provided, which carries level conversion function, therefore voltage work
It is big to make range, and metal-oxide-semiconductor quantity used is few, chip area is small.Specifically, referring to Fig. 2, Fig. 2 is one embodiment of the invention
The schematic diagram of trigger.As shown in Fig. 2, trigger includes: PMOS tube p1, the source electrode of PMOS tube p1 connects supply voltage VDD,
The grid of PMOS tube p1 receives clock signal CK；The drain electrode of the drain electrode connection PMOS tube p1 of NMOS tube n1, NMOS tube n1, form altogether
Nodes X, the source electrode ground connection of NMOS tube n1, the grid of NMOS tube n1 receive the input signal D of trigger；PMOS tube p2, PMOS tube
The source electrode of p2 connects supply voltage VDD, and the grid of PMOS tube p2 receives clock signal CK；NMOS tube n2, the drain electrode of NMOS tube n2
The drain electrode of PMOS tube p2 is connected, conode Y, the source electrode ground connection of NMOS tube n2 are formed, the grid of NMOS tube n2 connects NMOS tube n1
Drain electrode and PMOS tube p1 drain electrode conode X, receive conode X voltage signal；PMOS tube p3, the source electrode of PMOS tube p3
Supply voltage VDD is connected, the conode Y of the drain electrode of the drain electrode and PMOS tube p2 of the grid connection NMOS tube n2 of PMOS tube p3 connects
Receive the voltage signal of conode Y；The drain electrode of the drain electrode connection PMOS tube p3 of NMOS tube n3, NMOS tube n3, form conode QB,
The source electrode of NMOS tube n3 is grounded, and the grid of NMOS tube n3 receives clock signal CK；The source electrode of PMOS tube p4, PMOS tube p4 connect electricity
The conode QB of the drain electrode of the drain electrode and PMOS tube p3 of the grid connection NMOS tube n3 of source voltage VDD, PMOS tube p4, receives section altogether
The voltage signal of point QB；The drain electrode of the drain electrode connection PMOS tube p4 of NMOS tube n4, NMOS tube n4, form conode Q, and in Q point
The source electrode of the output signal Q of output trigger, NMOS tube n4 is grounded, the drain electrode of the grid connection NMOS tube n3 of NMOS tube n4 with
The conode QB of the drain electrode of PMOS tube p3 receives the voltage signal of conode QB.
As shown in Fig. 2, trigger of the invention includes 4 PMOS tube and 4 NMOS tubes, relative to shown in FIG. 1 existing
The trigger of technology, metal-oxide-semiconductor quantity used in trigger provided by the invention are few very much.In an embodiment of the present invention, the touching
Hair device is integrated in semi-conductive substrate.More specifically, the trigger application CMOS technology is integrated in semi-conductive substrate,
Therefore the chip area of trigger of the invention is small.Further, in an embodiment of the present invention, trigger only has 4
PMOS tube and 4 NMOS tubes.
In an embodiment of the present invention, PMOS tube p1, PMOS tube p2, PMOS tube p3, PMOS tube p4, NMOS tube n1, NMOS
Pipe n2, NMOS tube n3 and NMOS tube n4 are high-voltage MOS pipe.More specifically, in an embodiment of the present invention, the electricity of high-voltage MOS pipe
Pressure is 1.5V between 5V.Specifically, above-mentioned 1.5V and 5V can have certain deviation, it is in an embodiment of the present invention, above-mentioned inclined
Difference is within 20%；Preferably, above-mentioned deviation is within 10%；More preferably, above-mentioned deviation is within 5%.
Referring to Fig. 3, Fig. 3 is the working waveform figure of trigger shown in Fig. 2.And incorporated by reference to Fig. 2, to explain shown in Fig. 2
Trigger working principle.As shown in figure 3, at the t1 moment, the input signal D of trigger is high level, clock signal CK from
Low level jump is high level, and D is high level, and NMOS tube n1 conducting, then the voltage signal at conode X is low level, then
NMOS tube n2 is not turned on, and because the eve clock signal CK at the t1 moment is low level, then PMOS tube p2 is connected, at conode Y
Voltage signal be high level, then PMOS tube p3 is not turned on, at this time CK from low level jump be high level, NMOS tube n3 conducting,
Then the voltage signal at conode QB is low level, and the voltage signal at low level conode QB is through PMOS tube p4 and NMOS tube
It is high level that the phase inverter of n4 composition, which obtains the output signal Q at conode Q, so realizes the function of d type flip flop.
Referring to Fig. 4, Fig. 4 is the working waveform figure of trigger shown in Fig. 2.And incorporated by reference to Fig. 2, to explain shown in Fig. 2
Trigger working principle.As shown in figure 4, at the t2 moment, the input signal D of trigger is low level, clock signal CK from
Low level jump is high level, and D is low level, and NMOS tube n1 is not turned on, because the eve clock signal CK at the t2 moment is low
Level, then PMOS tube p1 is connected, then the voltage signal at conode X is high level, then NMOS tube n2 is connected, then at conode Y
Voltage signal be low level, then PMOS tube p3 be connected, then voltage signal conode QB at be high level, the total section of high level
It is low that the phase inverter that voltage signal at point QB is formed through PMOS tube p4 and NMOS tube n4, which obtains the output signal Q at conode Q,
Level so realizes the function of d type flip flop.
In order to realize the function of d type flip flop, it need to prevent PMOS tube p1 and NMOS tube n1 from simultaneously turning on, PMOS tube p2 and NMOS
Pipe n2 is simultaneously turned on and PMOS tube p3 and NMOS tube n3 is simultaneously turned on, in an embodiment of the present invention, NMOS tube n1, PMOS tube
The current capacity of p2 and PMOS tube p3 are strong compared with the current capacity of PMOS tube p1, NMOS tube n2 and NMOS tube n3.Specifically, integrated
On circuit layout, the chip area of NMOS tube n1, PMOS tube p2 and PMOS tube p3 are compared with PMOS tube p1, NMOS tube n2 and NMOS tube n3
Chip area it is big.
According to fig. 2, Fig. 3 and Fig. 4 it is found that the voltage range of the input signal D of trigger provided by the invention in Vt to VDD
Between, wherein Vt is that the threshold voltage of the grid of the metal-oxide-semiconductor in trigger namely trigger provided by the invention carry level conversion
Function can preferably meet requirement of the current integrated circuit to trigger performance, and can increase the application range of trigger.
In conclusion the trigger by design including 4 PMOS tube and 4 NMOS tubes, can reduce needed for trigger
Metal-oxide-semiconductor quantity, reduce the chip area of trigger, and the voltage range of the input signal D of trigger can be from Vt to VDD
Between, wherein Vt is the threshold voltage of the grid of the metal-oxide-semiconductor of trigger, can better meet current integrated circuit to trigger performance
Requirement, and the application range of trigger can be increased.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (13)
1. a kind of trigger characterized by comprising
The source electrode of PMOS tube p1, PMOS tube p1 connect supply voltage VDD, and the grid of PMOS tube p1 receives clock signal CK；
The drain electrode of the drain electrode connection PMOS tube p1 of NMOS tube n1, NMOS tube n1, form conode X, and the source electrode of NMOS tube n1 is grounded,
The grid of NMOS tube n1 receives the input signal D of trigger；
The source electrode of PMOS tube p2, PMOS tube p2 connect supply voltage VDD, and the grid of PMOS tube p2 receives clock signal CK；
The drain electrode of the drain electrode connection PMOS tube p2 of NMOS tube n2, NMOS tube n2, form conode Y, and the source electrode of NMOS tube n2 is grounded,
The conode X of the drain electrode of the drain electrode and PMOS tube p1 of the grid connection NMOS tube n1 of NMOS tube n2, receives the voltage letter of conode X
Number；
The source electrode of PMOS tube p3, PMOS tube p3 connects supply voltage VDD, the drain electrode of the grid connection NMOS tube n2 of PMOS tube p3 with
The conode Y of the drain electrode of PMOS tube p2 receives the voltage signal of conode Y；
The drain electrode of the drain electrode connection PMOS tube p3 of NMOS tube n3, NMOS tube n3, form conode QB, the source electrode of NMOS tube n3 connects
The grid on ground, NMOS tube n3 receives clock signal CK；
The source electrode of PMOS tube p4, PMOS tube p4 connects supply voltage VDD, the drain electrode of the grid connection NMOS tube n3 of PMOS tube p4 with
The conode QB of the drain electrode of PMOS tube p3 receives the voltage signal of conode QB；And
The drain electrode of the drain electrode connection PMOS tube p4 of NMOS tube n4, NMOS tube n4, form conode Q, and in Q point output trigger
The source electrode of output signal Q, NMOS tube n4 are grounded, the drain electrode of the grid connection NMOS tube n3 of NMOS tube n4 and the drain electrode of PMOS tube p3
Conode QB, receive conode QB voltage signal.
2. trigger according to claim 1, which is characterized in that at the t1 moment, the input signal D of trigger is high electricity
Flat, clock signal CK is high level from low level jump, and D is high level, and NMOS tube n1 conducting, then the voltage at conode X is believed
Number be low level, then NMOS tube n2 is not turned on, because the eve clock signal CK at the t1 moment be low level, then PMOS tube p2 is led
Logical, the voltage signal at conode Y is high level, then PMOS tube p3 is not turned on, and it is high level that CK is jumped from low level at this time,
NMOS tube n3 conducting, then the voltage signal at conode QB is low level, the voltage signal warp at low level conode QB
It is high level that the phase inverter of PMOS tube p4 and NMOS tube n4 composition, which obtains the output signal Q at conode Q,.
3. trigger according to claim 1, which is characterized in that at the t2 moment, the input signal D of trigger is low electricity
Flat, clock signal CK is high level from low level jump, and D is low level, and NMOS tube n1 is not turned on, because of the eve at the t2 moment
Clock signal CK is low level, then PMOS tube p1 is connected, then the voltage signal at conode X is high level, then NMOS tube n2 is led
Logical, then the voltage signal at conode Y is low level, then PMOS tube p3 is connected, then the voltage signal at conode QB is high electricity
Flat, the phase inverter that the voltage signal at the conode QB of high level is formed through PMOS tube p4 and NMOS tube n4 obtains at conode Q
Output signal Q be low level.
4. trigger according to claim 1, which is characterized in that the trigger is integrated in semi-conductive substrate.
5. trigger according to claim 4, which is characterized in that the trigger application CMOS technology is integrated in half and leads
In body substrate,.
6. trigger according to claim 1, which is characterized in that the trigger only has 4 PMOS tube and 4 NMOS
Pipe.
7. trigger according to claim 1, which is characterized in that PMOS tube p1, PMOS tube p2, PMOS tube p3, PMOS tube
P4, NMOS tube n1, NMOS tube n2, NMOS tube n3 and NMOS tube n4 are high-voltage MOS pipe.
8. trigger according to claim 7, which is characterized in that the voltage of the high-voltage MOS pipe is 1.5V between 5V.
9. trigger according to claim 8, which is characterized in that the 1.5V has the deviation within 5%.
10. trigger according to claim 8, which is characterized in that the 5V has the deviation within 5%.
11. trigger according to claim 1, which is characterized in that the electric current of NMOS tube n1, PMOS tube p2 and PMOS tube p3
Ability is strong compared with the current capacity of PMOS tube p1, NMOS tube n2 and NMOS tube n3.
12. according to claim 1 or 11 described in any item triggers, which is characterized in that NMOS tube n1, PMOS tube p2 and PMOS
The chip area of pipe p3 is big compared with the chip area of PMOS tube p1, NMOS tube n2 and NMOS tube n3.
13. trigger according to claim 1, which is characterized in that the voltage range of the input signal D of trigger is arrived in Vt
Between VDD, wherein Vt is the threshold voltage of the grid of the metal-oxide-semiconductor in trigger.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910644322.2A CN110429922B (en) | 2019-07-17 | 2019-07-17 | Trigger device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910644322.2A CN110429922B (en) | 2019-07-17 | 2019-07-17 | Trigger device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110429922A true CN110429922A (en) | 2019-11-08 |
| CN110429922B CN110429922B (en) | 2023-07-04 |
Family
ID=68409788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910644322.2A Active CN110429922B (en) | 2019-07-17 | 2019-07-17 | Trigger device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110429922B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070070426A (en) * | 2005-12-29 | 2007-07-04 | 매그나칩 반도체 유한회사 | D flip flop |
| CN102497201A (en) * | 2011-12-21 | 2012-06-13 | 东南大学 | True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption |
| CN105162438A (en) * | 2015-09-28 | 2015-12-16 | 东南大学 | TSPC (True Single Phase Clock) type data flip-flop (DFF) capable of reducing glitch |
| CN107528568A (en) * | 2017-08-28 | 2017-12-29 | 天津大学 | The TSPC triggers of backfeed loop are kept with data |
-
2019
- 2019-07-17 CN CN201910644322.2A patent/CN110429922B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070070426A (en) * | 2005-12-29 | 2007-07-04 | 매그나칩 반도체 유한회사 | D flip flop |
| CN102497201A (en) * | 2011-12-21 | 2012-06-13 | 东南大学 | True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption |
| CN105162438A (en) * | 2015-09-28 | 2015-12-16 | 东南大学 | TSPC (True Single Phase Clock) type data flip-flop (DFF) capable of reducing glitch |
| CN107528568A (en) * | 2017-08-28 | 2017-12-29 | 天津大学 | The TSPC triggers of backfeed loop are kept with data |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110429922B (en) | 2023-07-04 |
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