CN101488737A - Digital programmable time delay apparatus based on dynamic current mirror - Google Patents

Abstract

The invention relates to a digital programmable time delay device belonging to the technical field of digital time delay circuits on the basis of a dynamic current mirror. The invention is characterized in that the digital programmable time delay device is formed by the sequential and serial connection of a digital control circuit and a time delay circuit, wherein, the time delay circuit adopts the dynamic current mirror to respectively control and output gate voltages of two MOS tubes of an inverter, thereby the power consumption can be reduced while the monotonicity of a transfer function is kept.

Description

Digital programmable time delay apparatus based on dynamic current mirror

Technical field

" based on the digital programmable time delay apparatus (DPDE) of dynamic current mirror " direct applied technical field is the low-power consumption VLSI (very large scale integrated circuit) designs.The circuit that proposes is that a class goes for DCO, DLL, ADPLL, the important module of microprocessor and internal memory.

Background technology

Communication in the past few years is a field that country relatively payes attention to always.This is because Modern Communication System has application more and more widely in society and natural environment.Because the widespread demand of communication system, especially emphasis is applied to military affairs, national security, and fields such as medical treatment and environment perception, reducing cost becomes the major issue that people are concerned about.Along with the voltage of the continuous development digital circuit of CMOS technology, also along with constantly reducing, speed has also risen for cost and power consumption.

General communication system the inside all needs to control inner module with clock generation circuit.Generally need use voltage controlled oscillator (VCO), delay phase-locked loop (DLL) or microprocessor in this clock generating module.Time delay unit is the pith of these modules.Since the benefit that digital CMOS brought, that is, low-power consumption, low cost and high-speed is just wished and can be realized the circuit that these were realized with analogy method in the past with digital CMOS.So LL changes into digital dll analog D, the VCO of simulation is changed into digital controlled oscillator (DCO).If realize this middle circuit, just need numerically controlled time delay unit.In order to reach the requirement of low-power consumption, suitable time delay unit should be low-power consumption, and is dull and low complex degree.CS I (current starved inverter) that delay cell of numerically controlled reality based on current mirror.(document sees reference ").This is because the delay of CSI DPDE is dullness and foreseeable.

Traditional C I DPDE changes delay by building and the resistance of controlling input inverter the inside NMOS.But the benefit of this method be low in energy consumption it weak point is also arranged.When digital controlled signal changes is to guarantee the monotonicity that postpones.(document M.Ma ymandi-Nejad and M.Sachdev sees reference, " A digitally programmable delay element; Designand analysis " IEEE Trans.On Very Large Scale Integration (VLSI) Systems, Vol.11, No.5, Oct.2003). in order to overcome the above problems, can adopt CS I DPDE based on current mirror.This DPDE is the change that changes discharging current acquisition delay by the electric current of Control current mirror.Her benefit is monotonicity and provides a control signal and just can estimate obtainable delay.Postpone in other words be can with record.Representative work comprises, (a kind of CSI DPDE. based on current mirror that Mohammad Maymandi-Nejadand Manoj Sachdev proposes sees reference document M.Maymandi-Nejad andM.Sachdev, " A digitally programmable delay element; Design and analysis " IEEE Trans.On VeryLarge Scale Integration (VLSI) Systems, Vol.11, No.5, Oct.2003) though. what MohammadMaymandi-Nejad proposed can obtain monotonicity, but have a very big shortcoming: static state and dynamic power consumption that it consumes are too big, do not do DP method D and compare with the traditional CSI DPDE of E.

Summary of the invention

The objective of the invention is on the basis of existing CSI DPDE circuit based on current mirror, to make certain improvements, propose a kind of CSI DPDE structure based on dynamic current mirror.

The invention is characterized in: it contains:

Digital programmable time delay apparatus based on dynamic current mirror is characterized in that; Form by digital control circuit and time delay circuit, wherein:

Digital control circuit, contain four PMOS pipes: the 5th PMOS manages (MP6), and the 6th PMOS manages (MP1),

The 7th PMOS manages (MP2), and the 8th PMOS manages (MP3), wherein: described four PMOS pipes (MP0), (MP1), (MP2) distinguish supplied with digital signal b successively with four grids (MP3) ₀, b ₁, b ₂, and b ₃, four source electrodes meet high level V jointly _DD, and drain electrode is interconnected each other:

Time delay circuit, contain: a PMOS manages (M2), the 2nd PMOS manages (M7), the 3rd PMOS pipe (M4) and the 4th a PMOS pipe (Mcs) of introducing the Control current mirror, also contain NMOS pipe (M1), the 2nd NMOS manages (M5), the 3rd NMOS manages (M6), be used for the 4th NMOS pipe (Mn1) and the 5th NMOS pipe (Mn2) that the control time postpones, and the 6th NMOS pipe (M3), wherein: the source electrode interconnection of described the 8th PMOS pipe (MP3) and the 4th PMOS pipe (Mcs), it is interconnected to drain, the grid of speed the one NMOS pipe (M1), the grid of the 2nd NMOS pipe (M5), the grid of the one PMOS pipe (M2), the grid of the 2nd PMOS pipe (M7), and meet input signal Din after the gate interconnect of the 3rd NMOS pipe (M6), the source electrode of the one NMOS pipe (M1), the source electrode of the 2nd NMOS pipe (M5), the source electrode of the 3rd NMOS pipe (M6), and the source electrode of the 6th NMOS pipe (M3), the source electrode of the 3rd NMOS pipe (M6), and the source electrode of the 6th NMOS pipe (M3) ground connection all, the drain electrode of the one NMOS pipe (M1) links to each other with the source electrode that the 4th NMOS manages (Mn1), the drain electrode of the 2nd NMOS pipe (M5) links to each other with the source electrode that the 5th NMOS manages (Mn2), the drain electrode of the 4th NMOS pipe (Mn1), the drain electrode of the one PMOS pipe (M2), the source electrode of the grid of the 3rd PMOS pipe (M4) and the 2nd PMOS pipe (M7) links to each other, the drain electrode of the 2nd PMOS pipe (M7), the drain electrode of the 3rd NMOS pipe (M6) links to each other with the grid that the 6th NMOS manages (M3), the grid of the 4th NMOS pipe (Mn1), the grid and the drain electrode of the 5th NMOS pipe (Mn2), and the drain electrode interconnection of the 4th PMOS pipe (Mcs), the drain electrode of the 6th NMOS pipe (M3), the output Dout that forms described time delay circuit after the gate interconnect of the drain electrode of the 3rd PMOS pipe (M4) and the 4th PMOS pipe (Mcs), PMOS pipe (M2) the source electrode of source electrode and the 3rd PMOS pipe (M4) meets high level V after interconnecting _DD.

T time of delay of described digital programmable time delay apparatus based on dynamic current mirror _dDetermine by following formula:

t _d＝C _g.V _TP/I

V wherein _TPBe the threshold voltage of the grid of the 3rd PMOS pipe (M4), I is for flowing through the leakage current of the 5th NMOS pipe (Mn2), C _gIt is the gate capacitance of the 3rd PMOS pipe (M4).

The invention has the beneficial effects as follows: compare with traditional current mirror CSI DPDE structure, the present invention propose based on dynamic current mirror CSI DPDE, under similar test condition part, can save energy up to 90%; Its worker of while postpones predictability and has improved, and the circuit engineering that is proposed is suitable as the important module of low-power consumption DCO circuit very much

Description of drawings

Fig. 1. digital control time delay unit block diagram.B wherein ₀～b ₃Be digital control input code, Din is the signal that will postpone, and Dout is output.

The CS I DPDE that Fig. 2 .Mohammad Maymandi-Nejad is proposed.Din, Dout, and b ₀～b ₃Meaning and Fig. 1 similar.

Fig. 3. circuit structure diagram of the present invention.Din, Dout, and b ₀～b ₃Meaning and Fig. 1 similar.

Fig. 4. output inverter PMOS and NMOS delete voltage.

Fig. 5. DPDE of the present invention is to the voltage output of difference control input code.

Fig. 6. the present invention postpones the variation with the control input.

Fig. 7. an application of the present invention

Embodiment

The technical scheme that the present invention solves its technical problem is: the present invention propose based on the dynamic current mirror time delay unit, as shown in Figure 3.DPDE of the present invention has the switching current of employing mirror quiescent current is turned off, and has separated the control voltage of two efferent ducts, with the short circuit current power consumption that is consumed under the situation of avoiding delay cell output PMOS and NMOS to open simultaneously.

The operation principle of DPDE is simple.When Din was low level, the unit was in reset mode, and it is 0 level that M2, M3 open Dout.When Din became high level, M1 opened M3, and the grid capacitance of M4 begins discharge.The speed of discharge is by the electric current I control of Mn1 (Mn2).This electric current for the Control current by Msc and.Control current is provided by Mp0～Mp3.

The present invention is by control section, and dynamic current mirror (also can call off and close current mirror) and an output inverter are formed.Separately to control be two cores of the present invention to the grid of NMOS (M3) and PMOS (M4) in dynamic current mirror and the output inverter.

Traditional DPDE of operation principle of the present invention and traditional Fig. 2 is similar, also comprises two patterns: when reset mode, Din is that low spot is flat, M1, and M5 and M6 turn-off.This moment M2 the grid voltage of M4 is moved to high level is that it turn-offs then M7 and opens and the grid of M3 is moved to high level M3 is opened.Because M4 has turned off, do not have straight-through electric current and pass through.So at this moment export Dout is that low level Msc also can open.Because M1 and M5 be turn-off do not have a quiescent current.When postponing than pattern, Din becomes high level, and M2 and M6 are turned off and M1, and M5 and M6 open opening of .M6 and can move the grid voltage of M3 to low level and allow him turn-off.At this moment operation principle is similar with Fig. 2.When M4 opens, output is moved to high level.At this moment the Msc that opened originally just has been switched off because carryover effects has obtained, and so just reaches the effect that reduces dynamic current.

In order to verify performance of the present invention and the improved effect of being brought, we have used spectre ^TMEmulation tool carries out emulation to circuit.Simulation result is relatively referring to table 1.

Table 1: the comparator performance

	Mohammad Maymandi-Nejad	The present invention
			Technology (um)	0.18	0.18
Supply voltage (V)	1.8	1V
			High operation speed (MHz)	400	450
Power consumption (uW)	211	20

Fig. 4 the present invention exports the grid-control voltage of M3 and M4 in the inverter.Be different from traditional C I DPDE, the control voltage of M4 always lags behind the grid voltage of M3.So any moment has only a MOS to open, make the through current that originally when Din changes, is produced be cancelled.Fig. 5 is the output voltage with the input control code of the present invention.Fig. 6 represents the delay of the present invention in different input control codes.Completely monotone changes when postponing as can be seen.

Sum up:

This delay unit circuit comprises: control section can provide different electric currents.Dynamic current mirror is opened in the needs electric current, turn-offs in the time of unwanted and almost is automatic.An input inverter and an output inverter.

Low-power consumption characteristic of the present invention makes it be suitable as very much the important module of DCO circuit, as shown in Figure 7.TDCO is the DCO output signal, and Enable is that enable signal is used for starting DCO.

$\mathrm{TDCO}=f\left(\underset{k=0}{\overset{N-1}{\mathrm{\Σ}}}{b}_k{2}^k\right)---\left(2\right)$

N is the bit number of control input in the examination (2).N is divided into 4 bits " coarse code " (thick sign indicating number) and 4 bits among Fig. 7 " fine code " (microcode), i.e. N=8.

Claims (1)

1. based on the digital programmable time delay apparatus of dynamic current mirror, it is characterized in that: form by digital control circuit and time delay circuit, wherein:

Digital control circuit, contain four PMOS pipes: the 5th PMOS manages (MP6), and the 6th PMOS manages (MP1),

The 7th PMOS manages (MP2), and the 8th PMOS manages (MP3), wherein: described four PMOS pipes (MP0), (MP1), (MP2) distinguish supplied with digital signal b successively with four grids (MP3) ₀, b ₁, b ₂, and b ₃, four source electrodes meet high level V jointly _DD, and drain electrode is interconnected each other:

Time delay circuit, contain: a PMOS manages (M2), the 2nd PMOS manages (M7), the 3rd PMOS pipe (M4) and the 4th a PMOS pipe (Mcs) of introducing the Control current mirror, also contain NMOS pipe (M1), the 2nd NMOS manages (M5), the 3rd NMOS manages (M6), be used for the 4th NMOS pipe (Mn1) and the 5th NMOS pipe (Mn2) that the control time postpones, and the 6th NMOS pipe (M3), wherein: the source electrode interconnection of described the 8th PMOS pipe (MP3) and the 4th PMOS pipe (Mcs), it is interconnected to drain, the grid of speed the one NMOS pipe (M1), the grid of the 2nd NMOS pipe (M5), the grid of the one PMOS pipe (M2), the grid of the 2nd PMOS pipe (M7), and meet input signal Din after the gate interconnect of the 3rd NMOS pipe (M6), the source electrode of the one NMOS pipe (M1), the source electrode of the 2nd NMOS pipe (M5), the source electrode of the 3rd NMOS pipe (M6), and the source electrode of the 6th NMOS pipe (M3), the source electrode of the 3rd NMOS pipe (M6), and the source electrode of the 6th NMOS pipe (M3) ground connection all, the drain electrode of the one NMOS pipe (M1) links to each other with the source electrode that the 4th NMOS manages (Mn1), the drain electrode of the 2nd NMOS pipe (M5) links to each other with the source electrode that the 5th NMOS manages (Mn2), the drain electrode of the 4th NMOS pipe (Mn1), the drain electrode of the one PMOS pipe (M2), the source electrode of the grid of the 3rd PMOS pipe (M4) and the 2nd PMOS pipe (M7) links to each other, the drain electrode of the 2nd PMOS pipe (M7), the drain electrode of the 3rd NMOS pipe (M6) links to each other with the grid that the 6th NMOS manages (M3), the grid of the 4th NMOS pipe (Mn1), the grid and the drain electrode of the 5th NMOS pipe (Mn2), and the drain electrode interconnection of the 4th PMOS pipe (Mcs), the drain electrode of the 6th NMOS pipe (M3), the output Dout that forms described time delay circuit after the gate interconnect of the drain electrode of the 3rd PMOS pipe (M4) and the 4th PMOS pipe (Mcs), PMOS pipe (M2) the source electrode of source electrode and the 3rd PMOS pipe (M4) meets high level V after interconnecting _DD

T time of delay of described digital programmable time delay apparatus based on dynamic current mirror _dDetermine by following formula:

t _d＝C _g·V _TP/I

V wherein _TPBe the threshold voltage of the grid of the 3rd PMOS pipe (M4), I is for flowing through the leakage current of the 5th NMOS pipe (Mn2), C _gIt is the gate capacitance of the 3rd PMOS pipe (M4).

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