CN101488737B - Digital programmable time delay apparatus based on dynamic current mirror - Google Patents

Abstract

A digital programmable time delay device based on a dynamic current mirror belongs to the technical field of digital time delay circuits, and is characterized in that it is composed of a digital control circuit and a time delay circuit in series, wherein the time delay circuit adopts a dynamic current mirror to control the output feedback respectively. The gate voltage of the two MOS tubes of the phase device reduces power consumption while maintaining the monotonicity of the transfer function.

Description

Digital Programmable Time Delay Device Based on Dynamic Current Mirror

technical field

The technical field of direct application of "Digital Programmable Time Delay Device (DPDE) based on dynamic current mirror" is the design of low-power VLSI. The proposed circuit is a class of important modules that can be applied to DCO, DLL, ADPLL, microprocessor and memory.

Background technique

Communication has always been an area that a country attaches great importance to for several years. This is because modern communication systems have more and more applications in social and natural environments. Due to the wide demand of communication systems, especially in the fields of military, national security, medical treatment and environmental observation, cost reduction has become an important issue that people are concerned about. With the continuous development of CMOS technology, the voltage, cost and power consumption of digital circuits are also continuously reduced, and the speed is also increased.

In general communication systems, clock generation circuits are required to control internal modules. A voltage-controlled oscillator (VCO), a delay-locked loop (DLL) or a microprocessor is generally required in this clock generation module. The time delay unit is an important part of these blocks. Because of the benefits brought by digital CMOS, ie, low power consumption, low cost, and high speed, it is desirable to implement these circuits previously implemented by analog methods in digital CMOS. So, change the analog DLL to a digital DLL, and change the analog VCO to a digitally controlled oscillator (DCO). If such a middle circuit is to be implemented, a digitally controlled time delay unit is required. In order to meet the requirement of low power consumption, the applicable time delay unit should be low power consumption, monotonic and low complexity. The actual delay unit based on the CSI (current starved inverter) digital control of the current mirror. (See "References"). This is because the latency of CSIDPDE is monotonic and predictable.

The traditional CSI DPDE changes the delay by controlling the building and resistance of the NMOS in the input inverter. The advantage of this method is low power consumption but it also has disadvantages. Monotonicity of the delay cannot be guaranteed when the digital control signal changes. (See references M.Maymandi-Nejad and M.Sachdev, "A digitally programmable delay element, Design and analysis" IEEE Trans. On Very Large Scale Integration (VLSI) Systems, Vol.11, No.5, Oct.2003). In order to solve the above problems, CSI DPDE based on current mirror can be adopted. This DPDE changes the discharge current by controlling the current of the current mirror to obtain the delay change. Her advantage is monotonicity and the delay that can be obtained can be estimated by giving a control signal. That is to say, the delay is measurable and measurable. Representative works include a current mirror-based CSI DPDE proposed by Mohammad Maymandi-Nejad and Manoj Sachdev. (See references M.Maymandi-Nejad and M.Sachdev, "A digitally programmable delay element, Design and analysis" IEEE Trans.On VeryLarge Scale Integration (VLSI) Systems, Vol.11, No.5, Oct.2003). Although the DPDE proposed by MohammadMaymandi-Nejad can obtain monotonicity, it has a big disadvantage: the static and dynamic power consumption it consumes Too big, there is no way to compare with traditional CSI DPDE.

Contents of the invention

The purpose of the present invention is to make certain improvements on the basis of the existing CSI DPDE circuit based on the current mirror, and propose a CSI DPDE structure based on the dynamic current mirror.

The present invention is characterized in that: it contains:

The digital programmable time delay device based on the dynamic current mirror is characterized in that; it is composed of a digital control circuit and a time delay circuit, wherein:

Digital control circuit, including four PMOS transistors: the fifth PMOS transistor (MP6), the sixth PMOS transistor (MP1),

The seventh PMOS transistor (MP2), the eighth PMOS transistor (MP3), wherein: the four gates of the four PMOS transistors (MP0), (MP1), (MP2) and (MP3) respectively input digital signals b in sequence ₀ , b ₁ , b ₂ , and b ₃ , the four sources are connected to high level V _DD , and the drains are connected to each other:

The time delay circuit includes: a first PMOS transistor (M2), a second PMOS transistor (M7), a third PMOS transistor (M4) and a fourth PMOS transistor (Mcs) introduced into a control current mirror, and also includes a first NMOS transistor (M1), the second NMOS transistor (M5), the third NMOS transistor (M6), the fourth NMOS transistor (Mn1) and the fifth NMOS transistor (Mn2) for controlling the time delay, and the sixth NMOS transistor (M3) , wherein: the source interconnection of the eighth PMOS transistor (MP3) and the fourth PMOS transistor (Mcs), the drain interconnection, the gate of the first NMOS transistor (M1), the second NMOS transistor (M5) The gate of the first PMOS transistor (M2), the gate of the second PMOS transistor (M7), and the gate of the third NMOS transistor (M6) are interconnected and then connected to the input signal Din, and the first NMOS transistor (M1 ), the source of the second NMOS transistor (M5), the source of the third NMOS transistor (M6), and the source of the sixth NMOS transistor (M3), the source of the third NMOS transistor (M6), And the source of the sixth NMOS transistor (M3) is grounded, the drain of the first NMOS transistor (M1) is connected to the source of the fourth NMOS transistor (Mn1), and the drain of the second NMOS transistor (M5) is connected to the fifth NMOS transistor (M5). The source of the NMOS transistor (Mn2) is connected, the drain of the fourth NMOS transistor (Mn1), the drain of the first PMOS transistor (M2), the gate of the third PMOS transistor (M4) and the second PMOS transistor (M7) The source of the second PMOS transistor (M7) is connected, the drain of the third NMOS transistor (M6) is connected to the gate of the sixth NMOS transistor (M3), the gate of the fourth NMOS transistor (Mn1), The gate and drain of the fifth NMOS transistor (Mn2), and the drain interconnection of the fourth PMOS transistor (Mcs), the drain of the sixth NMOS transistor (M3), the drain of the third PMOS transistor (M4) and The gate of the fourth PMOS transistor (Mcs) is interconnected to form the output end Dour of the time delay circuit, and the source of the first PMOS transistor (M2) and the source of the third PMOS transistor (M4) are interconnected and then connected to a high voltage. flat V _DD .

The delay time _t of the digital programmable time delay device based on the dynamic current mirror is determined by the following formula:

t _d =C _g .V _TP /I

Wherein V _TP is the gate threshold voltage of the third PMOS transistor (M4), I is the leakage current flowing through the fifth NMOS transistor (Mn2), and C _g is the gate capacitance of the third PMOS transistor (M4).

The beneficial effects of the present invention are: compared with the traditional current mirror CSI DPDE structure, the dynamic current mirror CSI DPDE proposed by the present invention can save up to 90% of energy under similar test conditions; The predictability is improved, and the proposed circuit technique is well suited as an important building block for low-power DCO circuits

Description of drawings

Figure 1. Block diagram of a digitally controlled time delay unit. Among them, b ₀ ~ b ₃ are digital control input codes, Din is the signal to be delayed, and Dout is the output.

Figure 2. CSI DPDE proposed by Mohammad Maymandi-Nejad. The meanings of Din, Dout, and b ₀ to b ₃ are similar to those in Figure 1.

Fig. 3. Circuit structure diagram of the present invention. The meanings of Din, Dout, and b ₀ to b ₃ are similar to those in Figure 1.

Figure 4. Output inverter PMOS and NMOS voltages.

Fig. 5. The voltage output of the DPDE of the present invention to different control input codes.

Figure 6. Inventive delay variation with control input.

Figure 7. An application of the present invention

Detailed ways

The technical solution of the present invention to solve the technical problem is: the time delay unit based on the dynamic current mirror proposed by the present invention, as shown in FIG. 3 . The DPDE of the present invention uses a switching current mirror to turn off the quiescent current, and separates the control voltages of the two output transistors, so as to avoid short-circuit current consumption when the output terminals PMOS and NMOS of the delay unit are turned on at the same time.

The working principle of DPDE is simple. When Din is low level, the unit is in the reset state, M2, M3 open Dout is 0 level. When Din goes high, M1 turns on M3, and the gate capacitance of M4 starts to discharge. The speed of discharge is controlled by the current I of Mn1 (Mn2). This current is the sum of the control currents through Msc. The control current is provided by Mp0 ~ Mp3.

The invention consists of a control part, a dynamic current mirror (also called a switch current mirror) and an output inverter. The separate gate control of NMOS (M3) and PMOS (M4) in the dynamic current mirror and output inverter are the two cores of the present invention.

The working principle of the present invention is similar to the conventional DPDE in FIG. 2 , and also includes two modes: in the reset mode, Din is at low level, and M1, M5 and M6 are turned off. At this time, M2 pulls the gate voltage of M4 to a high level, it is turned off, and then M7 is turned on, and the gate of M3 is pulled to a high level to turn on M3. Because M4 has been turned off, there will be no through current. At this time, the output Dout is low level so Msc will also be turned on. Because M1 and M5 are turned off, there will be no quiescent current. In the delay comparison mode, Din becomes high level, M2 and M7 are turned off and M1, M5, and M6 are turned on. The opening of M6 will pull the gate voltage of M3 to low level to turn him off. At this time, the working principle is similar to that in Figure 2. Pull the output high when M4 is on. At this time, the originally opened Msc is turned off because the delay effect has been obtained, so as to achieve the effect of reducing the dynamic current.

In order to verify the performance of the present invention and the improved effect brought by it, we used the spectre ^TM simulation tool to simulate the circuit. The simulation results are compared in Table 1.

Table 1: Comparator Performance

Mohammad Maymandi-Nejad this invention Process (um) 0.18 0.18 Power supply voltage (V) 1.8 1V Maximum working speed (MHz) 400 450 Power consumption (uW) 211 20

Fig. 4 The gate control voltages of M3 and M4 in the output inverter of the present invention. Unlike traditional CSI DPDE, the control voltage of M4 always lags behind the gate voltage of M3. Therefore, only one MOS is turned on at any time, so that the direct current generated during Din conversion is canceled. Fig. 5 is the output voltage with the input control code of the present invention. Fig. 6 shows the delay of the present invention at different input control codes. It can be seen that the delay varies completely monotonically.

Summarize:

This delay cell circuit includes: the control part can provide different currents. Dynamic current mirrors turn on when current is needed and turn off when not needed almost automatically. One input inverter and one output inverter.

The low power consumption characteristic of the present invention makes it very suitable as an important module of the DCO circuit, as shown in FIG. 7 . TDCO is the DCO output signal, and Enable is the enable signal used to start the DCO.

$\mathrm{<span\; class="notranslate">\; TDCO</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\underset{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{\overset{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}}{\mathrm{<span\; class="notranslate">\; b</span>}}_{\mathrm{<span\; class="notranslate">\; k</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}^{\mathrm{<span\; class="notranslate">\; k</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

In test (2), N is the number of bits that control the input. In Fig. 7, N is divided into "coarse code" (coarse code) of 4 bits and " fine code " (microcode) of 4 bits, namely N=8.

Claims (1)

1. The digital programmable time delay device based on dynamic current mirror is characterized in that; it is made up of digital control circuit and time delay circuit, wherein: Digital control circuit, including four PMOS transistors: the fifth PMOS transistor (MP6), the sixth PMOS transistor (MP1), The seventh PMOS transistor (MP2), the eighth PMOS transistor (MP3), wherein: the four gates of the four PMOS transistors (MP0), (MP1), (MP2) and (MP3) respectively input digital signals b in sequence ₀ , b ₁ , b ₂ , and b ₃ , the four sources are connected to high level V _DD , and the drains are connected to each other: The time delay circuit includes: a first PMOS transistor (M2), a second PMOS transistor (M7), a third PMOS transistor (M4) and a fourth PMOS transistor (Mcs) introduced into a control current mirror, and also includes a first NMOS transistor (M1), the second NMOS transistor (M5), the third NMOS transistor (M6), the fourth NMOS transistor (Mn1) and the fifth NMOS transistor (Mn2) for controlling the time delay, and the sixth NMOS transistor (M3) , wherein: the source interconnection of the eighth PMOS transistor (MP3) and the fourth PMOS transistor (Mcs), the drain interconnection, the gate of the first NMOS transistor (M1), the second NMOS transistor (M5) The gate of the first PMOS transistor (M2), the gate of the second PMOS transistor (M7), and the gate of the third NMOS transistor (M6) are interconnected and then connected to the input signal Din, and the first NMOS transistor (M1 ), the source of the second NMOS transistor (M5), the source of the third NMOS transistor (M6), and the source of the sixth NMOS transistor (M3) are all grounded, and the drain of the first NMOS transistor (M1) pole is connected to the source of the fourth NMOS transistor (Mn1), the drain of the second NMOS transistor (M5) is connected to the source of the fifth NMOS transistor (Mn2), the drain of the fourth NMOS transistor (Mn1), the first The drain of the PMOS transistor (M2), the gate of the third PMOS transistor (M4) and the source of the second PMOS transistor (M7) are connected, the drain of the second PMOS transistor (M7), and the third NMOS transistor (M6) The drain of the drain is connected to the gate of the sixth NMOS transistor (M3), the gate of the fourth NMOS transistor (Mn1), the gate and drain of the fifth NMOS transistor (Mn2), and the gate of the fourth PMOS transistor (Mcs) Drain interconnection, the drain of the sixth NMOS transistor (M3), the drain of the third PMOS transistor (M4) and the gate of the fourth PMOS transistor (Mcs) are interconnected to form the output terminal Dout of the time delay circuit, The source of the first PMOS transistor (M2) and the source of the third PMOS transistor (M4) are interconnected and then connected to a high level V _DD ; The delay time _t of the digital programmable time delay device based on the dynamic current mirror is determined by the following formula: t _d =C _g .V _TP /I Wherein V _TP is the gate threshold voltage of the third PMOS transistor (M4), I is the leakage current flowing through the fifth NMOS transistor (Mn2), and C _g is the gate capacitance of the third PMOS transistor (M4).

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