CN203492002U - Low-power-consumption automatic power-off circuit and level switching circuit thereof - Google Patents
Low-power-consumption automatic power-off circuit and level switching circuit thereof Download PDFInfo
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- CN203492002U CN203492002U CN201320531888.2U CN201320531888U CN203492002U CN 203492002 U CN203492002 U CN 203492002U CN 201320531888 U CN201320531888 U CN 201320531888U CN 203492002 U CN203492002 U CN 203492002U
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Abstract
The utility model provides a low-power-consumption automatic power-off circuit and a level switching circuit thereof. When a voltage shut-off signal generated by a working circuit hops from a low level to a high level, the signal is subjected to voltage domain switching by the level switching circuit and sent to a clock terminal of a trigger, and the output terminal of the trigger outputs a high voltage to a power circuit to cut off the voltage provided by the power circuit for the working circuit. After the voltage supply is cut off, the level of the voltage shut-off signal of the working circuit returns to zero slowly, and the level of the output signal of the level switching circuit is kept being clamped at a low level. Active-low signals of a wakeup signal and a power-on reset signal are connected to the trigger through an AND gate to clear the trigger, so that the power circuit is controlled to provide voltage for the working circuit normally. According to the utility model, when the self power supply is shut down, the low-power-consumption automatic power-off circuit is capable of keeping the level of a power cut-off signal constant to maintain the power-off state and reduce the power consumption; besides, the circuit has no static power consumption in normal operation.
Description
Technical field
The utility model belongs to power supply control field, is specifically related to a kind of power supply output power-down circuit and level shifting circuit wherein of low-power consumption.
Background technology
Along with the requirement of people to mobile electronic device demand and stand-by time, when the dynamic power consumption by control chip and standby leakage power consumption are promoted to chip performance, prolongs standby time has been proposed to challenge.For this reason, present SoC chip design has adopted multinomial power consumption control technology, comprise chip be divided into a plurality of voltage domains, a certain functional module of chip without when work by its dump to save power consumption.
Meanwhile, SoC chip comprises digital circuit and a plurality of analog module conventionally.Digital circuit blocks is usually operated at lower voltage to save power consumption.The voltage of digital circuit conventionally by power circuit as LDO(low pressure difference linear voltage regulator) circuit, DC/DC circuit etc. provides.In order to save power consumption, when not needing digital circuit work, the voltage of supplying with digital circuit need to be cut off.Yet this voltage shutoff signal is also produced by digital circuit itself.Therefore, when being cut off, voltage how to guarantee that the normal work of this control signal is a difficult problem.
In order to guarantee the normal work of this voltage cutting-off controlling signal, a kind of current method is that digital circuit is divided into two voltage domains, that is, the normal open domain of the voltage of a direct power supply, another can cut off the voltage domain that voltage is supplied with.Most of circuit working is at the voltage domain that can cut off voltage supply, and voltage shutoff signal produces in the normal open domain of voltage of a direct power supply.Yet, by digital circuit Further Division, be that two voltage domains have increased design difficulty and chip design area.Meanwhile, the normal open domain of the voltage of a direct power supply, the power consumption that has increased chip is stand-by power consumption especially.
Another kind method is that voltage shutoff signal is produced by digital circuit, and wake-up signal is produced by external signal or other modules, the normal work of digital circuit while simultaneously guaranteeing initially to power on by the function that power-on reset signal produces and wake-up signal is same.Yet because the level of digital circuit work is different with the level of power circuit work, it is inevitable through level shifting circuit before that voltage shutoff signal is sent to power circuit.Simultaneously, because the voltage of digital circuit is completely severed after power-off, employing Latch(latch) level shifting circuit of structure, for example, be the similar circuit shown in Fig. 1 or Fig. 2, and after the complete power-off of the power vd D2 of digital circuit, its output cannot be expected and throw into question.Therefore, how to guarantee that the normal work of this voltage shutoff signal is a difficult problem.
Utility model content
In order to overcome an above-mentioned difficult problem, guarantee that the normal work of power cutting circuit also reduces the power consumption of power cutting circuit the largelyst, the utility model proposes a kind of low-power consumption Self-disconnecting circuit of novelty and level shifting circuit wherein.
In order to achieve the above object, first technical scheme of the present utility model is to provide a kind of level shifting circuit;
The input signal of described level shifting circuit is the signal PD in second voltage territory, by the output signal obtaining after this signal conversion, be the signal PD_OUT of the first voltage domain, wherein, the first voltage VDD1 of described the first voltage domain is greater than the second voltage VDD2 in second voltage territory;
Described level shifting circuit, two nmos pass transistors that comprise pipe MN1 and pipe MN2, two PMOS transistors of pipe MP1 and pipe MP2, and diode string; Described diode string is connected to form by the PMOS transistor of a plurality of diode connections, and described in each, the transistorized grid of the PMOS of diode connection is connected with drain electrode; In described diode string, the transistorized source electrode of PMOS of first diode connection meets the first voltage VDD1;
Manage MN1 and manage MP1 and form an inverter: make the grid of managing MN1 and managing MP1 be connected to the signal PD that reception second voltage territory is brought in input, the drain electrode of pipe MN1 and pipe MP1 is connected in signal end PD_, the source ground of pipe MN1, the source electrode of pipe MP1 connects in described diode string the transistorized drain electrode of PMOS of diode connection described in last;
Pipe MN2 and pipe MP2 form another inverter: the grid of pipe MN2 and pipe MP2 is connected in signal end PD_, the drain electrode of pipe MN2 and pipe MP2 is connected to output and brings in the signal PD_OUT that sends the first voltage domain, the source ground of pipe MN2, the source electrode of pipe MP2 meets the first voltage VDD1;
When the signal PD in second voltage territory is the second voltage VDD2 of high level, due to the effect of described diode string, pipe MN1 conducting and manage MP1 and turn-off; When the signal PD in described second voltage territory is low level, pipe MN1 turn-offs and pipe MP1 conducting, thereby there is no quiescent current on this level shifting circuit.
The transistorized quantity of PMOS of diode connection in described diode string, by the voltage difference of described the first voltage VDD1 and second voltage VDD2 and described in any one the transistorized forward conduction threshold voltage of the PMOS of diode connection determine, this quantity integer value that to be described voltage difference obtain divided by the value round off of described forward conduction threshold voltage.
Another technical scheme of the present utility model is to provide a kind of low-power consumption Self-disconnecting circuit;
Described low-power consumption Self-disconnecting circuit comprises: be operated in the operating circuit under the second voltage VDD2 in second voltage territory, and be operated in level shifting circuit under the first voltage VDD1 of the first voltage domain, trigger, power circuit, with door, connect high circuit;
The voltage cut-off signals PD that described operating circuit produces, after described level shifting circuit conversion, is sent to the clock end CK of described trigger; The output Q of described trigger is connected to described power circuit, so that control this power circuit, whether to operating circuit, provides second voltage VDD2; The input D of described trigger is connected to the first voltage VDD1 of high level by connecing high circuit;
Only, when the saltus step from low level to high level appears in described voltage cut-off signals PD, the output Q of described trigger output high level, its second voltage VDD2 providing to described operating circuit of described power-circuit breaking is provided and supplies with; After voltage supply is cut off, the second voltage VDD2 level of described operating circuit slowly makes zero, and the level of described voltage cut-off signals PD is slowly made zero, and then the signal level after changing by level shifting circuit is continued to clamper in low level;
Wake-up signal WAKEUP and power-on reset signal POR are connected to respectively input described and door, and output described and door is connected to the clear terminal RN of trigger; By the Low level effective signal of described wake-up signal WAKEUP and power-on reset signal POR, by described trigger zero clearing, control described power circuit and normally to operating circuit, provide second voltage VDD2.
When described the first voltage VDD1 is greater than second voltage VDD2, with the level shifting circuit described in first technical scheme, carry out the conversion in signal voltage territory.And when described the first voltage VDD1 is less than second voltage VDD2, with in described level shifting circuit the part except diode string carry out the conversion in signal voltage territory:, wherein, the source electrode of pipe MP1 directly connects described the first voltage VDD1, and the device syndeton of other parts is constant.
Preferably, described power circuit is to produce by inputting the first voltage VDD1 LDO circuit or the DC/DC circuit of second voltage VDD2 output.
Preferably, in the circuit between described level shifting circuit and trigger, and described wake-up signal WAKEUP and power-on reset signal POR input to door before circuit in, be also respectively arranged with Dolby circuit.When input signal is Low level effective signal, Smith's circuits for triggering that described Dolby circuit comprises filtering voltage domain noise, and the delay circuit of filtering time domain noise and or door.When input signal is high level useful signal, Smith's circuits for triggering that described Dolby circuit comprises filtering voltage domain noise, and the delay circuit of filtering time domain noise and with door.
Compared with prior art, low-power consumption Self-disconnecting circuit described in the utility model and wherein level shifting circuit, its beneficial effect is: the utility model can guarantee that the voltage shutoff signal of its output in the situation that operating circuit is de-energized still can normally work, this Self-disconnecting circuit, without quiescent dissipation, has farthest reduced the power consumption of circuit simultaneously.In addition, adopt Dolby circuit to come filtering noise to guarantee the reliability of circuit working.
Accompanying drawing explanation
Fig. 1 is a kind of level shifting circuit of the Latch of employing structure;
Fig. 2 is the level shifting circuit of the another kind of Latch of employing structure;
Fig. 3 is the level shifting circuit that adopts inverter structure;
Fig. 4 is the level shifting circuit that uses resistance;
Fig. 5 is level shifting circuit of the present utility model;
Fig. 6 is Dolby circuit of the present utility model (input signal is Low level effective);
Fig. 7 is Dolby circuit of the present utility model (input signal is that high level is effective);
Fig. 8 is low-power consumption Self-disconnecting circuit of the present utility model.
Embodiment
The utility model provides the circuit of low-power consumption Self-disconnecting as shown in Figure 8, wherein comprise operating circuit 401, level shifting circuit 402, Dolby circuit 403,406,407, trigger 404, power circuit 405, with door 408, connect height (Tie-high) circuit 409.
Described operating circuit 401 is operated in VDD2 voltage domain, and other circuit workings are at VDD1 voltage domain.The control circuit of operating circuit 401 produces voltage cut-off signals PD, and this signal PD is converted to the signal of VDD1 voltage domain through level shifting circuit 402, then after the processing of Dolby circuit 403, is connected to the clock CK end of trigger 404.Under the output Q of trigger 404 end is controlled, power circuit 405 determines whether to provide voltage to VDD2.Power circuit 405 can be LDO circuit, and DC/DC circuit etc. can produce from a service voltage VDD1 circuit of another Voltage-output VDD2.Wake-up signal WAKEUP and power-on reset signal POR are connected to the input with door 408 after all processing by corresponding Dolby circuit 406,407, be connected to the clear terminal RN of trigger 404 with the output of door 408.The input D of trigger 404 is connected to high level VDD1 by connecing high circuit 409.
The utility model is by adopting specific level shifting circuit 402, guarantees that in the cut situation of operating circuit 401 voltage shutoff signal this circuit simultaneously of still normally working does not bring quiescent dissipation.
Specifically, when VDD1<VDD2, the inverter structure that described level shifting circuit 402 is used as shown in Figure 3, comprises nmos pass transistor MN1 and MN2, PMOS transistor MP1 and MP2.MN1 and MP1 form inverter; The grid of MN1 and MP1 is connected to input signal PD, and the drain electrode of MN1 and MP1 is connected in PD_, the source ground of MN1, and the source electrode of MP1 meets power vd D1.MN2 and MP2 form inverter simultaneously; The grid of MN2 and MP2 is connected in signal PD_, and the drain electrode of MN2 and MP2 is connected to output PD_OUT, the source ground of MN2, and the source electrode of MP2 meets power vd D1.When voltage shutoff signal PD is low level, MP1 conducting and MN1 turn-off, and when PD is high level VDD2, MP1 turn-offs and MN1 conducting.Yet when VDD1>VDD2, can not adopt this circuit to realize level conversion.Because when PD is high level VDD2, due to VDD1>VDD2, when MN1 conducting MP1 also conducting have quiescent current, when serious, because transistor size is improper, add process deviation by cisco unity malfunction.
When VDD1>VDD2, employing circuit as shown in Figure 4 also can guarantee the normal work of level shifting circuit, yet this circuit has quiescent dissipation when PD signal is high level.
Therefore,, when VDD1>VDD2, the circuit structure that the level shifting circuit 402 described in preferred embodiment of the present utility model is used as shown in Figure 5, wherein comprises nmos pass transistor MN1 and MN2, PMOS transistor MP1, MP2, MP3 and MP4.MN1 and MP1 form inverter; The grid of MN1 and MP1 is connected to input signal PD, and the drain electrode of MN1 and MP1 is connected in PD_, the source ground of MN1, and the source electrode of MP1 connects the drain electrode of MP3.Meanwhile, MN2 and MP2 form inverter; The grid of MN2 and MP2 is connected in PD_, and the drain electrode of MN2 and MP2 is connected to output PD_OUT, the source ground of MN2, and the source electrode of MP2 meets VDD1.MP3 and MP4 all adopt diode connection, that is, its grid is separately connected with drain electrode.The drain electrode of MP3 is connected with the source electrode of MP1, and the source electrode of MP3 is connected with the drain electrode of MP4, and the source electrode of MP4 meets power vd D1.MP3 and MP4 have formed diode string.
In side circuit, the number of diode string is determined by the voltage difference of VDD1 and VDD2 and the transistorized forward conduction threshold voltage of the PMOS of diode connection, for [VDD1-VDD2/ diode forward conduction threshold voltage+0.5], that is the integer value, obtaining divided by the value round off of diode forward conduction threshold voltage for the voltage difference of VDD1 and VDD2.Like this when PD is high level VDD2, due to the effect of diode string, MN1 conducting and MP1 turn-offs, has guaranteed the normal work of circuit.When PD is low level, MN1 turn-offs and MP1 conducting.Like this, circuit does not have quiescent current completely.
Meanwhile, the voltage shutoff signal after level shifting circuit 402 and Dolby circuit 403 processing is sent to the clock end CK of trigger 404.And the D termination high level of trigger 404.Like this, only when the saltus step from low level to high level appears in PD signal, the output of trigger 404 is just exported high level, and and then makes power circuit 405 cut off the voltage supply of VDD2.After the voltage of VDD2 is supplied with and is cut off, due to electric leakage, the level on VDD2 can slowly make zero, and level on PD also can slowly make zero due to electric leakage, and the level after level shifting circuit 402 will continue to be clamped at the normal work that low level guarantees circuit.When electrification reset or operating circuit 401 need to wake up, the Low level effective signal on POR and WAKEUP signal trigger 404 zero clearings can be made power circuit 405 normal supply voltages to VDD2 to guarantee the normal work of operating circuit 401.
In order to prevent PD, WAKEUP, and the noise on por signal makes trigger 404 produce misoperations, adopts circuit structure as shown in Figure 6 and Figure 7 to use as described Dolby circuit 403,406,407 in the utility model.When input signal is Low level effective signal, comprise Smith's circuits for triggering 501 as shown in Figure 6, delay circuit 502 and or door 503 circuit; When input signal is high level useful signal, comprise Smith's circuits for triggering 601 as shown in Figure 7, delay circuit 602 and with door 603 circuit.Smith's circuits for triggering 501,601 are used for the noise of filtering voltage domain, and delay circuit 502,602 with or the combination of door 503/ and door 603 be used for the noise of filtering time domain.Like this, low-voltage noise and burst pulse noise have all been guaranteed the reliability of circuit working by effective filtering.
In sum, low-power consumption Self-disconnecting circuit described in the utility model, for the power supply that cuts off circuit itself to save power consumption.By using level shifting circuit and the register of ad hoc structure, this circuit can keep the constant off-position that keeps of dump signal level to reduce power consumption in the cut situation of self power supply.Meanwhile, when circuit is normally worked, this circuit does not have quiescent dissipation yet.Like this, this circuit has reached and has farthest reduced power consumption to save the object of power consumption.
Although content of the present utility model has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to restriction of the present utility model.Those skilled in the art, read after foregoing, for multiple modification of the present utility model with to substitute will be all apparent.Therefore, protection range of the present utility model should be limited to the appended claims.
Claims (10)
1. a level shifting circuit, is characterized in that,
The input signal of described level shifting circuit is the signal PD in second voltage territory, by the output signal obtaining after this signal conversion, be the signal PD_OUT of the first voltage domain, wherein, the first voltage VDD1 of described the first voltage domain is greater than the second voltage VDD2 in second voltage territory;
Described level shifting circuit, two nmos pass transistors that comprise pipe MN1 and pipe MN2, two PMOS transistors of pipe MP1 and pipe MP2, and diode string; Described diode string is connected to form by the PMOS transistor of a plurality of diode connections, and described in each, the transistorized grid of the PMOS of diode connection is connected with drain electrode; In described diode string, the transistorized source electrode of PMOS of first diode connection meets the first voltage VDD1;
Manage MN1 and manage MP1 and form an inverter: make the grid of managing MN1 and managing MP1 be connected to the signal PD that reception second voltage territory is brought in input, the drain electrode of pipe MN1 and pipe MP1 is connected in signal end PD_, the source ground of pipe MN1, the source electrode of pipe MP1 connects in described diode string the transistorized drain electrode of PMOS of diode connection described in last;
Pipe MN2 and pipe MP2 form another inverter: the grid of pipe MN2 and pipe MP2 is connected in signal end PD_, the drain electrode of pipe MN2 and pipe MP2 is connected to output and brings in the signal PD_OUT that sends the first voltage domain, the source ground of pipe MN2, the source electrode of pipe MP2 meets the first voltage VDD1.
2. level shifting circuit as claimed in claim 1, is characterized in that,
The transistorized quantity of PMOS of diode connection in described diode string, by the voltage difference of described the first voltage VDD1 and second voltage VDD2 and described in any one the transistorized forward conduction threshold voltage of the PMOS of diode connection determine, this quantity integer value that to be described voltage difference obtain divided by the value round off of described forward conduction threshold voltage.
3. a low-power consumption Self-disconnecting circuit, is characterized in that, described low-power consumption Self-disconnecting circuit comprises:
Be operated in the operating circuit (401) under the second voltage VDD2 in second voltage territory, and be operated in level shifting circuit (402) under the first voltage VDD1 of the first voltage domain, trigger (404), power circuit (405), with door (408), connect high circuit (409);
The voltage cut-off signals PD that described operating circuit (401) produces, after described level shifting circuit (402) conversion, is sent to the clock end CK of described trigger (404); The output Q of described trigger (404) is connected to described power circuit (405), so that control this power circuit (405), whether to operating circuit (401), provides second voltage VDD2; The input D of described trigger (404) is connected to the first voltage VDD1 of high level by connecing high circuit (409); Wake-up signal WAKEUP and power-on reset signal POR are connected to respectively input described and door (408), and output described and door (408) is connected to the clear terminal RN of trigger (404).
4. low-power consumption Self-disconnecting circuit as claimed in claim 3, is characterized in that,
When described the first voltage VDD1 is greater than second voltage VDD2, two nmos pass transistors that described level shifting circuit (402) comprises pipe MN1 and pipe MN2, two PMOS transistors of pipe MP1 and pipe MP2, and diode string;
Described diode string is connected to form by the PMOS transistor of a plurality of diode connections, and described in each, the transistorized grid of the PMOS of diode connection is connected with drain electrode; In described diode string, the transistorized source electrode of PMOS of first diode connection meets the first voltage VDD1;
Manage MN1 and manage MP1 and form an inverter: make the grid of managing MN1 and managing MP1 be connected to the signal PD that reception second voltage territory is brought in input, the drain electrode of pipe MN1 and pipe MP1 is connected in signal end PD_, the source ground of pipe MN1, the source electrode of pipe MP1 connects in described diode string the transistorized drain electrode of PMOS of diode connection described in last;
Pipe MN2 and pipe MP2 form another inverter: the grid of pipe MN2 and pipe MP2 is connected in signal end PD_, the drain electrode of pipe MN2 and pipe MP2 is connected to output and brings in the signal PD_OUT that sends the first voltage domain, the source ground of pipe MN2, the source electrode of pipe MP2 meets the first voltage VDD1.
5. low-power consumption Self-disconnecting circuit as claimed in claim 4, is characterized in that,
The transistorized quantity of PMOS of diode connection described in described diode string, by the voltage difference of described the first voltage VDD1 and second voltage VDD2 and described in any one the transistorized forward conduction threshold voltage of the PMOS of diode connection determine, this quantity integer value that to be described voltage difference obtain divided by the value round off of described forward conduction threshold voltage.
6. low-power consumption Self-disconnecting circuit as claimed in claim 3, is characterized in that,
When described the first voltage VDD1 is less than second voltage VDD2, two nmos pass transistors that described level shifting circuit (402) comprises pipe MN1 and pipe MN2, and two PMOS transistors of pipe MP1 and pipe MP2;
Manage MN1 and manage MP1 and form an inverter: make the grid of managing MN1 and managing MP1 be connected to the signal PD that reception second voltage territory is brought in input, the drain electrode of pipe MN1 and pipe MP1 is connected in signal end PD_, the source ground of pipe MN1, the source electrode of pipe MP1 meets described the first voltage VDD1;
Pipe MN2 and pipe MP2 form another inverter: the grid of pipe MN2 and pipe MP2 is connected in signal end PD_, the drain electrode of pipe MN2 and pipe MP2 is connected to output and brings in the signal PD_OUT that sends the first voltage domain, the source ground of pipe MN2, the source electrode of pipe MP2 meets the first voltage VDD1.
7. low-power consumption Self-disconnecting circuit as claimed in claim 3, is characterized in that,
Described power circuit (405) is to produce by inputting the first voltage VDD1 LDO circuit or the DC/DC circuit of second voltage VDD2 output.
8. low-power consumption Self-disconnecting circuit as claimed in claim 3, is characterized in that,
In circuit between described level shifting circuit (402) and trigger (404), and described wake-up signal WAKEUP and power-on reset signal POR input to door (408) circuit before in, be also respectively arranged with Dolby circuit (403,406,407).
9. low-power consumption Self-disconnecting circuit as claimed in claim 8, is characterized in that,
When input signal is Low level effective signal, Smith's circuits for triggering (501) that described Dolby circuit (403,406,407) comprises filtering voltage domain noise, and the delay circuit of filtering time domain noise (502) and or door (503).
10. low-power consumption Self-disconnecting circuit as claimed in claim 8, is characterized in that,
When input signal is high level useful signal, Smith's circuits for triggering (601) that described Dolby circuit (403,406,407) comprises filtering voltage domain noise, and the delay circuit of filtering time domain noise (602) and with door (603).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320531888.2U CN203492002U (en) | 2013-08-29 | 2013-08-29 | Low-power-consumption automatic power-off circuit and level switching circuit thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320531888.2U CN203492002U (en) | 2013-08-29 | 2013-08-29 | Low-power-consumption automatic power-off circuit and level switching circuit thereof |
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| CN203492002U true CN203492002U (en) | 2014-03-19 |
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| CN201320531888.2U Withdrawn - After Issue CN203492002U (en) | 2013-08-29 | 2013-08-29 | Low-power-consumption automatic power-off circuit and level switching circuit thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103412509A (en) * | 2013-08-29 | 2013-11-27 | 灿芯半导体(上海)有限公司 | Low-power-consumption self-cutting-off circuit and level switching circuit thereof |
| CN111427441A (en) * | 2020-04-02 | 2020-07-17 | 大唐微电子技术有限公司 | Power supply awakening method and device |
-
2013
- 2013-08-29 CN CN201320531888.2U patent/CN203492002U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103412509A (en) * | 2013-08-29 | 2013-11-27 | 灿芯半导体(上海)有限公司 | Low-power-consumption self-cutting-off circuit and level switching circuit thereof |
| CN103412509B (en) * | 2013-08-29 | 2016-04-13 | 灿芯半导体(上海)有限公司 | Low-power consumption Self-disconnecting circuit and level shifting circuit thereof |
| CN111427441A (en) * | 2020-04-02 | 2020-07-17 | 大唐微电子技术有限公司 | Power supply awakening method and device |
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