CN103412509A - Low-power-consumption self-cutting-off circuit and level switching circuit thereof - Google Patents
Low-power-consumption self-cutting-off circuit and level switching circuit thereof Download PDFInfo
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Abstract
The invention provides a low-power-consumption self-cutting-off circuit and a level switching circuit of the low-power-consumption self-cutting-off circuit. When a voltage cutting-off signal generated by a working circuit hops from a low level to a high level, voltage domain switching of the signal is conducted through the level switching circuit, the signal is sent to the clock end of a trigger, and then the output end of the trigger outputs high voltage to a power circuit so that the voltage provided for the working circuit by the power circuit can be cut off. After the voltage supplying is cut off, the level of the voltage cutting-off signal of the working circuit slowly returns to zero, and the level of the signal output by the level switching circuit is kept being clamped at a low level. A low level efficient signal of a power-on reset signal is awakened to be connected to the trigger through an and gate and is reset so that the power circuit can be controlled to normally provide the voltage for the working circuit. Under the condition that a power supply is shut down, according to the low-power-consumption self-cutting-off circuit and the level switching circuit of the low-power-consumption self-cutting-off circuit, the level of a power cutting-off signal can be kept unchanged, therefore, the off-position is kept, and power consumption is reduced. Meanwhile, no static power consumption is produced by the circuits when the circuits work normally.
Description
Technical field
The invention belongs to the power supply control field, be specifically related to a kind of power supply output power-down circuit and level shifting circuit wherein of low-power consumption.
Background technology
Along with the requirement of people to mobile electronic device demand and stand-by time, when the dynamic power consumption by control chip and standby leakage power consumption are promoted to chip performance, prolongs standby time has been proposed to challenge.For this reason, multinomial power consumption control technology has been adopted in present SoC chip design, comprise chip be divided into to a plurality of voltage domains, a certain functional module of chip without when work by its dump to save power consumption.
Simultaneously, the SoC chip comprises digital circuit and a plurality of analog module usually.Digital circuit blocks is usually operated at lower voltage to save power consumption.The voltage of digital circuit is usually by power circuit such as LDO(low pressure difference linear voltage regulator) circuit, DC/DC circuit etc. provides.In order to save power consumption, the voltage of supplying with digital circuit need to be cut off when not needing digital circuit work.Yet this voltage shutoff signal is also produced by digital circuit itself.Therefore, when being cut off, voltage how to guarantee that this control signal normal operation is a difficult problem.
In order to guarantee the normal operation of this voltage cutting-off controlling signal, a kind of current method is that digital circuit is divided into to two voltage domains, that is, the normal open domain of the voltage of a direct power supply, another can cut off the voltage domain that voltage is supplied with.Most of circuit working is at the voltage domain that can cut off the voltage supply, and the voltage shutoff signal produces in the normal open domain of the voltage of a direct power supply.Yet, be that two voltage domains have increased design difficulty and chip design area by the digital circuit Further Division.Simultaneously, the normal open domain of the voltage of a direct power supply, the power consumption that has increased chip is stand-by power consumption especially.
Another kind method is that the voltage shutoff signal is produced by digital circuit, and wake-up signal is produced by external signal or other modules, the normal operation of digital circuit while guaranteeing initially to power on by the function that power-on reset signal produces and wake-up signal is same simultaneously.Yet because the level of digital circuit work is different with the level of power circuit work, it is inevitable through level shifting circuit before that the voltage shutoff signal is sent to power circuit.Simultaneously, because the voltage of digital circuit is completely severed after outage, employing Latch(latch) level shifting circuit of structure, be for example Fig. 1 or similar circuit shown in Figure 2, and its output can't be expected and throw into question after the power vd D2 of digital circuit cuts off the power supply fully.Therefore, how to guarantee that this voltage shutoff signal normal operation is a difficult problem.
Summary of the invention
In order to overcome an above-mentioned difficult problem, guarantee that the normal operation of power cutting circuit also reduces the power consumption of power cutting circuit the largelyst, the present invention proposes a kind of low-power consumption Self-disconnecting circuit of novelty and level shifting circuit wherein.
In order to achieve the above object, first technical scheme of the present invention is to provide a kind of level shifting circuit;
The input signal of described level shifting circuit is the signal PD in second voltage territory, by the output signal obtained after this signal conversion, be the signal PD_OUT of the first voltage domain, wherein, the first voltage VDD1 of described the first voltage domain is greater than the second voltage VDD2 in second voltage territory;
Described level shifting circuit, comprise nmos pass transistor MN1 and MN2, PMOS transistor MP1 and MP2, and diode string; Described diode string is connected to form by the PMOS transistor of a plurality of diode connections, and the transistorized grid of the PMOS of each described diode connection is connected with drain electrode; In described diode string, the transistorized source electrode of PMOS of first diode connection meets the first voltage VDD1;
Manage MN1 and phase inverter of pipe MP1 composition: make the grid of managing MN1 and managing MP1 be connected to input and bring in the signal PD that receives the second voltage territory, the drain electrode of pipe MN1 and pipe MP1 is connected in signal end PD_, the source ground of pipe MN1, the source electrode of pipe MP1 connects the transistorized drain electrode of PMOS of last described diode connection in described diode string;
Pipe MN2 and pipe MP2 form another phase inverter: the grid of pipe MN2 and pipe MP2 is connected in signal end PD_, the drain electrode of pipe MN2 and pipe MP2 is connected to output and brings in the signal PD_OUT that sends the first voltage domain, the source ground of pipe MN2, the source electrode of pipe MP2 meets the first voltage VDD1;
When the signal PD in second voltage territory is the second voltage VDD2 of high level, due to the effect of described diode string, pipe MN1 conducting and manage MP1 and turn-off; When the signal PD in described second voltage territory was low level, pipe MN1 turn-offed and pipe MP1 conducting, thereby there is no quiescent current on this level shifting circuit.
The transistorized quantity of PMOS of diode connection in described diode string, by the transistorized forward conduction threshold voltage of the PMOS of the voltage difference of described the first voltage VDD1 and second voltage VDD2 and any one described diode connection, determined this quantity round values that to be described voltage difference obtain divided by the value round off of described forward conduction threshold voltage.
Another technical scheme of the present invention is to provide a kind of low-power consumption Self-disconnecting circuit;
Described low-power consumption Self-disconnecting circuit comprises: be operated in the operating circuit under the second voltage VDD2 in second voltage territory, and be operated in level shifting circuit under the first voltage VDD1 of the first voltage domain, trigger, power circuit, with door, connect high circuit;
The voltage cut-off signals PD that described operating circuit produces, after described level shifting circuit conversion, be sent to the clock end CK of described trigger; The output terminal Q of described trigger is connected to described power circuit, whether to operating circuit, provides second voltage VDD2 so that control this power circuit; The input end D of described trigger is connected to the first voltage VDD1 of high level by connecing high circuit;
Only when the saltus step from the low level to the high level appearred in described voltage cut-off signals PD, the output terminal Q of described trigger output high level, its second voltage VDD2 supply provided to described operating circuit of described power-circuit breaking was provided; After the voltage supply was cut off, the second voltage VDD2 level of described operating circuit slowly made zero, and the level of described voltage cut-off signals PD is slowly made zero, and then the signal level after changing by level shifting circuit continues clamper in low level;
Wake-up signal WAKEUP and power-on reset signal POR are connected to respectively input end described and door, and described output terminal with door is connected to the clear terminal RN of trigger; By the Low level effective signal of described wake-up signal WAKEUP and power-on reset signal POR, by described trigger zero clearing, control described power circuit and normally to operating circuit, provide second voltage VDD2.
When described the first voltage VDD1 is greater than second voltage VDD2, carry out the conversion in signal voltage territory with the level shifting circuit described in first technical scheme.And when described the first voltage VDD1 is less than second voltage VDD2, with in described level shifting circuit the part except the diode string carry out the conversion in signal voltage territory: namely, wherein, the source electrode of MP1 directly connects described the first voltage VDD1, and the device syndeton of other parts is constant.
Preferably, described power circuit is to produce by inputting the first voltage VDD1 LDO circuit or the DC/DC circuit of second voltage VDD2 output.
Preferably, in the circuit between described level shifting circuit and trigger, and described wake-up signal WAKEUP and power-on reset signal POR input to door before circuit in, also be respectively arranged with Dolby circuit.When input signal was the Low level effective signal, described Dolby circuit comprised Smith's trigger circuit of filtering voltage domain noise, and the delay circuit of filtering time domain noise and or door.When input signal was the high level useful signal, described Dolby circuit comprised Smith's trigger circuit of filtering voltage domain noise, and the delay circuit of filtering time domain noise and with door.
Compared with prior art, low-power consumption Self-disconnecting circuit of the present invention reaches wherein level shifting circuit, its beneficial effect is: the present invention can guarantee in the situation that operating circuit is de-energized the voltage shutoff signal of its output still can work, this Self-disconnecting circuit, without quiescent dissipation, has farthest reduced the power consumption of circuit simultaneously.In addition, adopt Dolby circuit to come filtering noise to guarantee the reliability of circuit working.
The accompanying drawing explanation
Fig. 1 is a kind of level shifting circuit of the Latch of employing structure;
Fig. 2 is the level shifting circuit of the another kind of Latch of employing structure;
Fig. 3 is the level shifting circuit that adopts inverter structure;
Fig. 4 is the level shifting circuit that uses resistance;
Fig. 5 is level shifting circuit of the present invention;
Fig. 6 is Dolby circuit of the present invention (input signal is Low level effective);
Fig. 7 is Dolby circuit of the present invention (input signal is that high level is effective);
Fig. 8 is low-power consumption Self-disconnecting circuit of the present invention.
Embodiment
The invention provides low-power consumption Self-disconnecting circuit as shown in Figure 8, wherein comprise operating circuit 401, level shifting circuit 402, Dolby circuit 403,406,407, trigger 404, power circuit 405, with door 408, connect height (Tie-high) circuit 409.
Described operating circuit 401 is operated in the VDD2 voltage domain, and other circuit workings are at the VDD1 voltage domain.The control circuit of operating circuit 401 produces voltage cut-off signals PD, and this signal PD is converted to the signal of VDD1 voltage domain through level shifting circuit 402, then after the processing of Dolby circuit 403, is connected to the clock CK end of trigger 404.Under the output Q of trigger 404 end was controlled, power circuit 405 determined whether to provide voltage to VDD2.Power circuit 405 can be the LDO circuit, and DC/DC circuit etc. can produce from a service voltage VDD1 circuit of another Voltage-output VDD2.Wake-up signal WAKEUP and power-on reset signal POR are connected to the input end with door 408 after all by corresponding Dolby circuit 406,407, processing, be connected to the clear terminal RN of trigger 404 with the output terminal of door 408.The input end D of trigger 404 is connected to high level VDD1 by connecing high circuit 409.
The present invention is by adopting specific level shifting circuit 402, guarantees that in the cut situation of operating circuit 401 voltage shutoff signal this circuit simultaneously that still works does not bring quiescent dissipation.
Specifically, when VDD1<VDD2, the inverter structure that described level shifting circuit 402 is used as shown in Figure 3, comprise nmos pass transistor MN1 and MN2, PMOS transistor MP1 and MP2.MN1 and MP1 form phase inverter; The grid of MN1 and MP1 is connected to input signal PD, and the drain electrode of MN1 and MP1 is connected in PD_, the source ground of MN1, and the source electrode of MP1 meets power vd D1.MN2 and MP2 form phase inverter simultaneously; The grid of MN2 and MP2 is connected in signal PD_, and the drain electrode of MN2 and MP2 is connected to output PD_OUT, the source ground of MN2, and the source electrode of MP2 meets power vd D1.When voltage shutoff signal PD was low level, MP1 conducting and MN1 turn-offed, and when PD was high level VDD2, MP1 turn-offed and the MN1 conducting.Yet as VDD1 > can not adopt this circuit to realize level conversion during VDD2.Because when PD is high level VDD2, due to VDD1 > VDD2, when the MN1 conducting MP1 also conducting have quiescent current, when serious, add process deviation by cisco unity malfunction because transistor size is improper.
As VDD1 > adopt during VDD2 circuit as shown in Figure 4 also can guarantee the normal operation of level shifting circuit, however this circuit has quiescent dissipation when the PD signal is high level.
Therefore, at VDD1 > during VDD2, the circuit structure that the level shifting circuit 402 described in the preferred embodiments of the present invention is used as shown in Figure 5, wherein comprise nmos pass transistor MN1 and MN2, PMOS transistor MP1, MP2, MP3 and MP4.MN1 and MP1 form phase inverter; The grid of MN1 and MP1 is connected to input signal PD, and the drain electrode of MN1 and MP1 is connected in PD_, the source ground of MN1, and the source electrode of MP1 connects the drain electrode of MP3.Simultaneously, MN2 and MP2 form phase inverter; The grid of MN2 and MP2 is connected in PD_, and the drain electrode of MN2 and MP2 is connected to output PD_OUT, the source ground of MN2, and the source electrode of MP2 meets VDD1.MP3 and MP4 all adopt the diode connection, that is, its grid separately is connected with drain electrode.The drain electrode of MP3 is connected with the source electrode of MP1, and the source electrode of MP3 is connected with the drain electrode of MP4, and the source electrode of MP4 meets power vd D1.MP3 and MP4 have formed the diode string.
In side circuit, the number of diode string is determined by the voltage difference of VDD1 and VDD2 and the transistorized forward conduction threshold voltage of PMOS of diode connection, for [VDD1-VDD2/ diode forward conduction threshold voltage+0.5], that is the round values, obtained divided by the value round off of diode forward conduction threshold voltage for the voltage difference of VDD1 and VDD2.Like this when PD is high level VDD2, due to the effect of diode string, MN1 conducting and MP1 turn-offs, guaranteed the normal operation of circuit.When PD was low level, MN1 turn-offed and the MP1 conducting.Like this, circuit does not have quiescent current fully.
Simultaneously, the voltage shutoff signal after level shifting circuit 402 and Dolby circuit 403 processing is sent to the clock end CK of trigger 404.And the D termination high level of trigger 404.Like this, only the output terminal of trigger 404 is just exported high level when the saltus step from the low level to the high level appears in the PD signal, and and then makes power circuit 405 cut off the voltage supply of VDD2.After the voltage supply of VDD2 was cut off, due to electric leakage, the level on VDD2 can slowly make zero, and the level on PD also can slowly make zero due to electric leakage, and the level after level shifting circuit 402 will continue to be clamped at the normal operation that low level guarantees circuit.When electrification reset or operating circuit 401 need to wake up, the Low level effective signal on POR and WAKEUP signal trigger 404 zero clearings can be made power circuit 405 normal supply voltages to VDD2 to guarantee the normal operation of operating circuit 401.
In order to prevent PD, WAKEUP, and the noise on por signal makes trigger 404 produce misoperations, in the present invention, adopts circuit structure as shown in Figure 6 and Figure 7 to use as described Dolby circuit 403,406,407.When input signal is the Low level effective signal, comprise Smith's trigger circuit 501 as shown in Figure 6, delay circuit 502 and or door 503 circuit; When input signal is the high level useful signal, comprise Smith's trigger circuit 601 as shown in Figure 7, delay circuit 602 and with door 603 circuit.Smith's trigger circuit 501,601 are used for the noise of filtering voltage domain, and delay circuit 502,602 with or door 503/ and door 603 in conjunction with being used for the noise of filtering time domain.Like this, low-voltage noise and burst pulse noise have all been guaranteed the reliability of circuit working by effective filtering.
In sum, low-power consumption Self-disconnecting circuit of the present invention, be used to the power supply that cuts off circuit itself to save power consumption.By using level shifting circuit and the register of ad hoc structure, this circuit can keep the constant off-position that keeps of dump signal level to reduce power consumption in the cut situation of self power supply.Simultaneously, when circuit worked, this circuit did not have quiescent dissipation yet.Like this, this circuit has reached and has farthest reduced power consumption to save the purpose of power consumption.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (8)
1. a level shifting circuit, is characterized in that,
The input signal of described level shifting circuit is the signal PD in second voltage territory, by the output signal obtained after this signal conversion, be the signal PD_OUT of the first voltage domain, wherein, the first voltage VDD1 of described the first voltage domain is greater than the second voltage VDD2 in second voltage territory;
Described level shifting circuit, comprise nmos pass transistor MN1 and MN2, PMOS transistor MP1 and MP2, and diode string; Described diode string is connected to form by the PMOS transistor of a plurality of diode connections, and the transistorized grid of the PMOS of each described diode connection is connected with drain electrode; In described diode string, the transistorized source electrode of PMOS of first diode connection meets the first voltage VDD1;
Manage MN1 and phase inverter of pipe MP1 composition: make the grid of managing MN1 and managing MP1 be connected to input and bring in the signal PD that receives the second voltage territory, the drain electrode of pipe MN1 and pipe MP1 is connected in signal end PD_, the source ground of pipe MN1, the source electrode of pipe MP1 connects the transistorized drain electrode of PMOS of last described diode connection in described diode string;
Pipe MN2 and pipe MP2 form another phase inverter: the grid of pipe MN2 and pipe MP2 is connected in signal end PD_, the drain electrode of pipe MN2 and pipe MP2 is connected to output and brings in the signal PD_OUT that sends the first voltage domain, the source ground of pipe MN2, the source electrode of pipe MP2 meets the first voltage VDD1;
When the signal PD in second voltage territory is the second voltage VDD2 of high level, due to the effect of described diode string, pipe MN1 conducting and manage MP1 and turn-off; When the signal PD in described second voltage territory was low level, pipe MN1 turn-offed and pipe MP1 conducting, thereby there is no quiescent current on this level shifting circuit.
2. level shifting circuit as claimed in claim 1, is characterized in that,
The transistorized quantity of PMOS of diode connection in described diode string, by the transistorized forward conduction threshold voltage of the PMOS of the voltage difference of described the first voltage VDD1 and second voltage VDD2 and any one described diode connection, determined this quantity round values that to be described voltage difference obtain divided by the value round off of described forward conduction threshold voltage.
3. a low-power consumption Self-disconnecting circuit, is characterized in that, described low-power consumption Self-disconnecting circuit comprises:
Be operated in the operating circuit (401) under the second voltage VDD2 in second voltage territory, and be operated in level shifting circuit (402) under the first voltage VDD1 of the first voltage domain, trigger (404), power circuit (405), with door (408), connect high circuit (409);
When described the first voltage VDD1 is greater than second voltage VDD2, the voltage cut-off signals PD that described operating circuit (401) produces, after level shifting circuit as claimed in claim 1 (402) carries out the conversion in signal voltage territory, be sent to the clock end CK of described trigger (404); The output terminal Q of described trigger (404) is connected to described power circuit (405), whether to operating circuit (401), provides second voltage VDD2 so that control this power circuit (405); The input end D of described trigger (404) is connected to the first voltage VDD1 of high level by connecing high circuit (409);
Only when the saltus step from the low level to the high level appears in described voltage cut-off signals PD, the output terminal Q output high level of described trigger (404), control described power circuit (405) and cut off the second voltage VDD2 supply that it provides to described operating circuit (401); After the voltage supply is cut off, the second voltage VDD2 level of described operating circuit (401) slowly makes zero, the level of described voltage cut-off signals PD is slowly made zero, and then will by the signal level after level shifting circuit (402) conversion, continue clamper in low level;
Wake-up signal WAKEUP and power-on reset signal POR are connected to respectively input end described and door (408), and described output terminal with door (408) is connected to the clear terminal RN of trigger (404); By the Low level effective signal of described wake-up signal WAKEUP and power-on reset signal POR, by described trigger (404) zero clearing, control described power circuit (405) and normally to operating circuit (401), provide second voltage VDD2.
4. low-power consumption Self-disconnecting circuit as claimed in claim 3, is characterized in that,
When described the first voltage VDD1 is less than second voltage VDD2, in described level shifting circuit (402), use except the diode string respectively by pipe MN1 and pipe MP1, pipe MN2 carries out the conversion in signal voltage territory with two phase inverters that pipe MP2 forms, and the source electrode that makes wherein to manage MP1 changes described the first voltage VDD1 of connection into.
5. low-power consumption Self-disconnecting circuit as claimed in claim 3, is characterized in that,
Described power circuit (405) is to produce by inputting the first voltage VDD1 LDO circuit or the DC/DC circuit of second voltage VDD2 output.
6. low-power consumption Self-disconnecting circuit as claimed in claim 3, is characterized in that,
In circuit between described level shifting circuit (402) and trigger (404), and described wake-up signal WAKEUP and power-on reset signal POR input to door (408) circuit before in, also be respectively arranged with Dolby circuit (403,406,407).
7. low-power consumption Self-disconnecting circuit as claimed in claim 6, is characterized in that,
When input signal was the Low level effective signal, described Dolby circuit (403,406,407) comprised Smith's trigger circuit (501) of filtering voltage domain noise, and the delay circuit of filtering time domain noise (502) and or door (503).
8. low-power consumption Self-disconnecting circuit as claimed in claim 6, is characterized in that,
When input signal was the high level useful signal, described Dolby circuit (403,406,407) comprised Smith's trigger circuit (601) of filtering voltage domain noise, and the delay circuit of filtering time domain noise (602) and with door (603).
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| CN107231084A (en) * | 2016-04-29 | 2017-10-03 | 上海良信电器股份有限公司 | A kind of controllable power supply circuit of Width funtion input |
| CN108322210A (en) * | 2017-01-16 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of level shifting circuit |
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| CN110277128A (en) * | 2019-06-03 | 2019-09-24 | 上海华力集成电路制造有限公司 | Booster circuit applied to low pressure flash memories |
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