CN102468841A - Low-voltage level to high-voltage level circuit adopting diode framework - Google Patents
Low-voltage level to high-voltage level circuit adopting diode framework Download PDFInfo
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- CN102468841A CN102468841A CN2010105469262A CN201010546926A CN102468841A CN 102468841 A CN102468841 A CN 102468841A CN 2010105469262 A CN2010105469262 A CN 2010105469262A CN 201010546926 A CN201010546926 A CN 201010546926A CN 102468841 A CN102468841 A CN 102468841A
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Abstract
The invention discloses a low-voltage level to high-voltage level circuit adopting a diode framework, which comprises a diode, a high-voltage N-channel metal oxide semiconductor (NMOS) tube, a current mirror and a latch, wherein the diode comprises a first diode D1 and a second diode D2; the high-voltage NMOS tube comprises a first high-voltage NMOS tube N1 and a second high-voltage NMOS tube N2; the current mirror consists of a first P-channel metal oxide semiconductor (PMOS) tube P1 and a second PMOS tube P2; the latch consists of a first inverter I1 and a second inverter I2; power ends of the first inverter I1 and the second inverter I2 are connected with a first high-voltage potential HVDD, and ground ends of the first inverter I1 and the second inverter I2 are connected with a second high-voltage potential VSW; the output of the first inverter I1 is taken as the input of the second inverter I2, and the output of the second inverter I2 is taken as the input of the first inverter I1; the input of the first inverter I1 is simultaneously connected with a negative end of the second diode D2 and a drain terminal of the second PMOS tube P2; and an output end OUT of the latch (4) is an output end of the first inverter I1. Compared with the prior art, the low-voltage level to high-voltage level circuit has the advantages of being simple in circuit structure, stable and reliable in control and the like.
Description
Technical field
The invention belongs to the ic core chip technology, be specifically related to a kind of low tension that adopts diode framework high voltage level circuit of flatting turn.
Background technology
The integrated circuit of high voltage supply, its internal circuit can be divided into high-tension circuit module and low-voltage circuit module.The power supply of high-tension circuit module is directly provided by external power supply, and the power supply of low-voltage circuit module is provided by inner low-tension supply, and the processing of the control signal between high-pressure modular and the low-voltage module is the problem that each high voltage integrated circuit all must solve.The signal absolute voltage of high-pressure modular output is high, and generally can not directly use, otherwise also be so to low-voltage module,
Otherwise can damage internal components.
The existing method of problem that solves this respect generally is to make the input of device can accept high-voltage signal, and this method circuit is controlled fairly simple, can realize with common level shifting circuit.But this scheme is to be cost to increase the chip technology cost, in the integrated circuit production technology, needs a photoetching of extra increase, though therefore this scheme circuit has simply increased the cost of product.And along with the raising of supply voltage, the high voltage that input need tolerate is increasingly high, and technology difficulty is increasing.
Increasingly high in view of the consideration and the chip operating voltage of the cost of existing product, need a kind of new framework to solve the flat turn problem of high voltage level of low tension.
Summary of the invention:The technical problem that the present invention will solve provides a kind of reliable and stable low tension high voltage level change-over circuit of flatting turn; This circuit goes for the integrated circuit of any high voltage supply; Circuit is simple relatively, and working stability is reliable, and is not high to the requirement of withstand voltage of device.
Technical scheme of the present invention comprises diode, high pressure NMOS pipe, current mirror and latch.Diode comprises the first diode D1 and the second diode D2, they the positive termination second high-voltage VSW, negative terminal connects the input of high pressure NMOS pipe and the output of current mirror; The high pressure NMOS pipe comprises the first high pressure NMOS pipe N1 and the second high pressure NMOS pipe N2; The grid termination first control signal SET of the first high pressure NMOS pipe; The grid termination second control signal CLR of the second high pressure NMOS pipe; The source termination earth potential VGND of two high pressure NMOS pipes, the drain terminal of two high pressure NMOS pipes connects the negative terminal of the first diode D1 and the second diode D2 and the output of current mirror as input; Current mirror is made up of PMOS pipe P1 and the 2nd PMOS pipe P2; The source termination first high-voltage HVDD of the one PMOS pipe P1 and the 2nd PMOS pipe P2; Both grid link together and receive the drain terminal of PMOS pipe P1, and both drain terminals are as the output of current mirror; Latch is made up of the first inverter I1 and the second inverter I2; The power supply termination first high-voltage HVDD of these two inverters; The ground termination second high-voltage VSW; And the voltage of the first high-voltage HVDD is greater than the second high-voltage VSW, and the output of the first inverter I1 is as the input of the second inverter I2, and the output of the second inverter I2 is as the input of the first inverter I1 simultaneously; The negative terminal of the second diode D2 and the drain terminal of the 2nd PMOS pipe P2 are received in the input of the first inverter I1 simultaneously, and the output OUT of latch is the output of the first inverter I1.
As the improvement of such scheme, the said first diode D1 and the second diode D2 can be that forward conduction voltage is that general-purpose diode or forward conduction voltage about 0.7V is the Schottky diode about 0.3V.
The present invention adopts the low tension of the diode framework high voltage level circuit of flatting turn, and does not need special device, directly adopts in the high-pressure process device commonly used to realize that the low voltage level signal is converted into the purpose of high voltage level signal.Circuit structure is fairly simple, and control is got up reliable and stable.Particularly; The present invention has following technical advantage: circuit of the present invention converts the processing of high level signal into for low level signal; Do not need the input on the traditional structure to need high voltage bearing technology device; The most frequently used device is realized identical functions in the employing high-pressure process, therefore can reduce the technology manufacturing cost; Simultaneously, the present invention has adopted latch to latch the high voltage level signal that the low voltage level conversion is come.The low voltage level signal only needs the pulse signal of a very short time just can latch this low voltage level signal, can well control circuit power consumption thus well.
Description of drawings:
Combine accompanying drawing and embodiment that technical scheme of the present invention is done further explanation at present:
The low tension that Fig. 1 adopts the diode framework for the present invention the is a kind of high voltage level circuit of flatting turn.
Fig. 2 is the structural representation of diode of the present invention.
Fig. 3 is the structural representation of high pressure NMOS pipe of the present invention.
Fig. 4 is the structural representation of current mirror of the present invention.
Fig. 5 is the structural representation of latch of the present invention.
Fig. 6 is a circuit input and output waveform sketch map of the present invention.
Embodiment:
The present invention as shown in Figure 1 adopts the low tension of the diode framework high voltage level circuit of flatting turn, and this comprises diode (1), high pressure NMOS pipe (2), current mirror (3), latch (4).Annexation is: the positive termination second high-voltage VSW of the first diode D1 in the diode (1) and the second diode D2, the negative terminal of the first diode D1 connect the drain terminal of the first high pressure NMOS pipe N1 in the high pressure NMOS pipe (2) and drain terminal and the grid end of the pipe of the PMOS in the current mirror (3) P1; The negative terminal of the second diode D2 connects the drain terminal of the second high pressure NMOS pipe N2 in the high pressure NMOS pipe (2) and the drain terminal of the pipe of the 2nd PMOS in the current mirror (3) P2, receives the input of the first inverter I1 in the latch (4) simultaneously; The grid termination first control signal SET of the first high pressure NMOS pipe N1 in the high pressure NMOS pipe (2), source termination earth potential VGND; The grid termination second control signal CLR of the second high pressure NMOS pipe N2, source termination earth potential VGND; The source termination first high-voltage HVDD of PMOS pipe P1 in the current mirror (3), grid end and drain terminal connect together, receive the negative terminal of the first diode D1 and the drain terminal of the first high pressure NMOS pipe N1; The source termination first high-voltage HVDD of the 2nd PMOS pipe P2; Drain terminal connects the negative terminal of the second diode D2 and the drain terminal of the second high pressure NMOS pipe N2; Receive the input of the first inverter I1 in the latch (4) simultaneously, grid end and the drain terminal of its grid termination the one PMOS pipe P1; The input of latch (4) is the input of the first inverter I1 wherein.Output OUT is the output of the first inverter I1.
Like Fig. 2 is the structural representation of diode of the present invention (1); Be made up of the first diode D1 and the second diode D2, the first diode D1 and the second diode D2 can be that general-purpose diode or forward conduction voltage about 0.7V is that Schottky diode about 0.3V is formed by forward conduction voltage.The positive termination second high-voltage VSW of these two diodes, the circuit connecting of negative terminal is explained in the description of Fig. 1.
Like Fig. 3 is the structural representation of high pressure NMOS pipe of the present invention (2); Form by the first high pressure NMOS pipe N1 and the second high pressure NMOS pipe N2; The grid end of these two high pressure NMOS pipes meets the first control signal SET and the second control signal CLR respectively, and source end all earthing potential VGND. drain terminal institute connection circuit is described shown in description among Fig. 1.The drain terminal of the first high pressure NMOS pipe N1 and the second high pressure NMOS pipe N2 and the voltage difference VDS of source end can be high-voltages; So when the current potential of the second high-voltage VSW is High Pressure Difference with respect to earth potential VGND; Basic all pressure drops can be fallen on these two high pressure NMOS pipes and can not damaged device; Because the grid terminal potential and the source terminal potential voltage difference VGS of these two high pressure NMOS pipes can not bear high pressure, promptly common low voltage signal, in general the highest is about 5V.So the first control signal SET and the second control signal CLR generally are the low-voltage signals that is up to below the 5V, are high-tension high-voltage signal through becoming with respect to earth potential VGND after the circuit conversion of the present invention.
Fig. 4 is current mirror (3) circuit among the present invention; Form by PMOS pipe P1 and the 2nd PMOS pipe P2; The source of two PMOS pipes terminates to the first high tension voltage HVDD; Grid end and the drain terminal of the one PMOS pipe P1 are connected together, and the grid end of grid termination the one PMOS pipe P1 of the 2nd PMOS pipe P2 is according to PMOS pipe saturation region current formula I=K (VGS-VTH)
2If the gate pmos end is consistent with the voltage difference VGS of source end, the electric current that then flows through these two PMOS pipes is consistent, and this is the operation principle of this current mirror (4).The drain terminal circuit connecting of the one PMOS pipe P1 and the 2nd PMOS pipe P2 sees that Fig. 1 describes.
Fig. 5 is latch (4) circuit among the present invention; Latch (4) is made up of the first inverter I1 and the second inverter I2; The power supply of these two inverters is the first high tension voltage HVDD; Meet the second high tension voltage VSW, and the first high tension voltage HVDD is higher than the second high tension voltage VSW voltage, both voltage differences can guarantee that latch (4) circuit can operate as normal.The input of the output termination second inverter I2 of the first inverter I1, the input of the output termination first inverter I1 of the second inverter I2 constitutes latch (4) with this structure.
Fig. 6 is the input and output waveform sketch map of circuit of the present invention; This circuit control signal is the first control signal SET and the second control signal CLR; If high level pulse appears in the first control signal SET; Then latch (4) output OUT is a low level, and this low level is maintained low level always after the first control signal SET becomes low level, has only when high level pulse appears in the second control signal CLR; Latch (4) output OUR just becomes high level; And latch (4) output OUT keeps the output high level after the second control signal CLR becomes low level, has only when high level pulse appears in the first control signal SET, and latch (4) output OUT just becomes low level.So the output OUT of latch (4) is controlled by the first control signal SET and the second control signal CLR.
Claims (2)
1. a low tension that adopts diode framework high voltage level circuit of flatting turn comprises diode (1), high pressure NMOS pipe (2), current mirror (3) and latch (4), it is characterized in that:
Said diode (1) comprises the first diode D1 and the second diode D2, they the positive termination second high-voltage VSW, negative terminal connects the input of high pressure NMOS pipe (2) and the output of current mirror (3);
Said high pressure NMOS pipe (2) comprises the first high pressure NMOS pipe N1 and the second high pressure NMOS pipe N2; The grid termination first control signal SET of the first high pressure NMOS pipe; The grid termination second control signal CLR of the second high pressure NMOS pipe; The source termination earth potential VGND of two high pressure NMOS pipes, the drain terminal of two high pressure NMOS pipes connect the negative terminal of the first diode D1 and the second diode D2 and the output of current mirror (3) as input;
Said current mirror (3) is made up of PMOS pipe P1 and the 2nd PMOS pipe P2; The source termination first high-voltage HVDD of the one PMOS pipe P1 and the 2nd PMOS pipe P2; Both grid link together and receive the drain terminal of PMOS pipe P1, and both drain terminals are as the output of current mirror (3);
Said latch (4) is made up of the first inverter I1 and the second inverter I2; The power supply termination first high-voltage HVDD of these two inverters; The ground termination second high-voltage VSW; And the voltage of the first high-voltage HVDD is greater than the second high-voltage VSW, and the output of the first inverter I1 is as the input of the second inverter I2, and the output of the second inverter I2 is as the input of the first inverter I1 simultaneously; The negative terminal of the second diode D2 and the drain terminal of the 2nd PMOS pipe P2 are received in the input of the first inverter I1 simultaneously, and the output OUT of latch (4) is the output of the first inverter I1.
2. the low tension of the employing diode framework according to claim 1 high voltage level circuit of flatting turn is characterized in that the said first diode D1 and the second diode D2 can be that forward conduction voltage is that general-purpose diode or forward conduction voltage about 0.7V is the Schottky diode about 0.3V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010546926.2A CN102468841B (en) | 2010-11-17 | 2010-11-17 | Low-voltage level to high-voltage level circuit adopting diode framework |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010546926.2A CN102468841B (en) | 2010-11-17 | 2010-11-17 | Low-voltage level to high-voltage level circuit adopting diode framework |
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| CN102468841A true CN102468841A (en) | 2012-05-23 |
| CN102468841B CN102468841B (en) | 2014-01-29 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103412509A (en) * | 2013-08-29 | 2013-11-27 | 灿芯半导体(上海)有限公司 | Low-power-consumption self-cutting-off circuit and level switching circuit thereof |
| CN103856205A (en) * | 2012-12-05 | 2014-06-11 | 艾尔瓦特集成电路科技（天津）有限公司 | Level switching circuit, drive circuit for driving high voltage devices and corresponding method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5359553A (en) * | 1989-05-19 | 1994-10-25 | Mitsubishi Denki Kabushiki Kaisha | Low power ECL/MOS level converting circuit and memory device and method of converting a signal level |
| JP2005101965A (en) * | 2003-09-25 | 2005-04-14 | Ricoh Co Ltd | Level shift circuit and semiconductor integrated circuit having the same |
| CN201887743U (en) * | 2010-11-17 | 2011-06-29 | 无锡芯朋微电子有限公司 | Circuit used for converting low-voltage level into high-voltage level and adopting diode framework |
-
2010
- 2010-11-17 CN CN201010546926.2A patent/CN102468841B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5359553A (en) * | 1989-05-19 | 1994-10-25 | Mitsubishi Denki Kabushiki Kaisha | Low power ECL/MOS level converting circuit and memory device and method of converting a signal level |
| US20070229137A1 (en) * | 2003-09-23 | 2007-10-04 | Kazuya Nishimura | Level shift circuit capable of preventing occurrence of malfunction when low power supply fluctuates, and semiconductor integrated circuit including the circuit |
| JP2005101965A (en) * | 2003-09-25 | 2005-04-14 | Ricoh Co Ltd | Level shift circuit and semiconductor integrated circuit having the same |
| CN201887743U (en) * | 2010-11-17 | 2011-06-29 | 无锡芯朋微电子有限公司 | Circuit used for converting low-voltage level into high-voltage level and adopting diode framework |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103856205A (en) * | 2012-12-05 | 2014-06-11 | 艾尔瓦特集成电路科技（天津）有限公司 | Level switching circuit, drive circuit for driving high voltage devices and corresponding method |
| CN103856205B (en) * | 2012-12-05 | 2016-04-20 | 艾尔瓦特集成电路科技（天津）有限公司 | Level shifting circuit, for driving the drive circuit of high tension apparatus and corresponding method |
| CN103412509A (en) * | 2013-08-29 | 2013-11-27 | 灿芯半导体(上海)有限公司 | Low-power-consumption self-cutting-off circuit and level switching circuit thereof |
| CN103412509B (en) * | 2013-08-29 | 2016-04-13 | 灿芯半导体(上海)有限公司 | Low-power consumption Self-disconnecting circuit and level shifting circuit thereof |
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| CN102468841B (en) | 2014-01-29 |
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Address after: 8 building, building 21-1, genesis building, 214028 Changjiang Road, New District, Jiangsu, Wuxi Applicant after: Wuxi Chipown Microelectronics Co., Ltd. Address before: 8 building, building 21-1, genesis building, 214028 Changjiang Road, New District, Jiangsu, Wuxi Applicant before: Wuxi Xinpeng Micro-electronics Co., Ltd. |
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