CN103412509B - Low-power consumption Self-disconnecting circuit and level shifting circuit thereof - Google Patents
Low-power consumption Self-disconnecting circuit and level shifting circuit thereof Download PDFInfo
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Abstract
The invention provides a kind of low-power consumption Self-disconnecting circuit and level shifting circuit thereof, when the voltage cut-off signals that operating circuit produces is from low level to high level saltus step, the voltage domain carrying out signal through level shifting circuit by signal is changed and is sent to the clock end of trigger, make the output terminal of trigger to power circuit output HIGH voltage, the voltage provided to operating circuit with circuit of cutting off the electricity supply; After voltage supply is cut off, the voltage cut-off signals level of operating circuit slowly makes zero, and the level that level shifting circuit outputs signal is continued clamper in low level; Wake the Low level effective signal with power-on reset signal up, via being connected to trigger with door and being reset, control described power circuit and normally provide voltage to operating circuit.When own power source is cut-off, circuit of the present invention can keep the constant off-position that keeps of dump signal level to reduce power consumption.Meanwhile, when circuit normally works, this circuit does not have quiescent dissipation yet.
Description
Technical field
The invention belongs to Energy control field, the power supply being specifically related to a kind of low-power consumption exports power-down circuit and level shifting circuit wherein.
Background technology
Along with people are to the requirement of mobile electronic device demand and stand-by time, while promoting chip performance by the dynamic power consumption of control chip and standby leakage power consumption, challenge is proposed to prolongs standby time.For this reason, present SoC chip design have employed multinomial power consumption control techniques, comprises and chip is divided into multiple voltage domain, when a certain functional module of chip is without the need to working by its dump to save power consumption.
Meanwhile, SoC chip comprises digital circuit and multiple analog module usually.Digital circuit blocks is usually operated at lower voltage to save power consumption.The voltage of digital circuit usually by power circuit as LDO(low pressure difference linear voltage regulator) circuit, DC/DC circuit etc. provides.In order to save power consumption, when not needing digital circuit to work, the voltage of supply digital circuit cuts off by needs.But this voltage shutoff signal is also produced by digital circuit itself.Therefore, how ensureing when voltage is cut off that this control signal normally works is a difficult problem.
In order to ensure the normal work of this voltage cutting-off controlling signal, a kind of current method digital circuit is divided into two voltage domains, that is, the normal open domain of the voltage of a direct power supply, and another can cut off the voltage domain of voltage supply.Major part circuit working is at the voltage domain that can cut off voltage supply, and voltage shutoff signal produces in the normal open domain of the voltage of a direct power supply.But, be that two voltage domains add design difficulty and chip design area by digital circuit Further Division.Meanwhile, the normal open domain of voltage of a direct power supply, adds the power consumption especially stand-by power consumption of chip.
Another kind method is that voltage shutoff signal is produced by digital circuit, and wake-up signal is produced by external signal or other modules, uses power-on reset signal to produce the normal work of digital circuit when the function same with wake-up signal ensures initially to power on simultaneously.But because the level of digital circuit work is different with the level of power circuit work, voltage shutoff signal is inevitable through level shifting circuit before being sent to power circuit.Simultaneously, because the voltage of digital circuit is completely severed after a loss of power, adopt Latch(latch) level shifting circuit of structure, be such as the similar circuit shown in Fig. 1 or Fig. 2, after the complete power-off of power vd D2 of digital circuit, its output cannot be expected and throw into question.Therefore, how ensureing that this voltage shutoff signal normally works is a difficult problem.
Chinese patent literature CN101515755A is the immediate prior art of the present invention.
Summary of the invention
In order to overcome an above-mentioned difficult problem, ensureing the normal work of power cutting circuit and maximally reducing the power consumption of power cutting circuit, the present invention proposes a kind of low-power consumption Self-disconnecting circuit and level shifting circuit wherein of novelty.
In order to achieve the above object, first technical scheme of the present invention is to provide a kind of level shifting circuit;
The input signal of described level shifting circuit is the signal PD of the second voltage domain, the output signal obtained after being changed by this signal is the signal PD_OUT of the first voltage domain, wherein, the first voltage VDD1 of described first voltage domain is greater than the second voltage VDD2 of the second voltage domain;
Described level shifting circuit, comprises nmos pass transistor MN1 and MN2, PMOS transistor MP1 and MP2, and diode string; Described diode string is connected to form by the PMOS transistor of multiple diode connection, and the grid of the PMOS transistor of each described diode connection is connected with drain electrode; In described diode string, the source electrode of the PMOS transistor of first diode connection meets the first voltage VDD1;
Pipe MN1 and pipe MP1 forms a phase inverter: make the grid of pipe MN1 and pipe MP1 be connected to input end to receive the signal PD of the second voltage domain, the drain electrode of pipe MN1 and pipe MP1 is connected to signal end PD_, the source ground of pipe MN1, the source electrode of pipe MP1 connects the drain electrode of the PMOS transistor of diode connection described in last in described diode string;
Pipe MN2 and pipe MP2 forms another phase inverter: the grid of pipe MN2 and pipe MP2 is connected to signal end PD_, the drain electrode of pipe MN2 and pipe MP2 is connected to output terminal to send the signal PD_OUT of the first voltage domain, the source ground of pipe MN2, the source electrode of pipe MP2 meets the first voltage VDD1;
When the signal PD of the second voltage domain is the second voltage VDD2 of high level, due to the effect of described diode string, pipe MN1 conducting and pipe MP1 turns off; When the signal PD of described second voltage domain is low level, pipe MN1 turns off and pipe MP1 conducting, thus does not have quiescent current on this level shifting circuit.
The quantity of the PMOS transistor of diode connection in described diode string, determined by the forward conduction threshold voltage of the voltage difference of described first voltage VDD1 and the second voltage VDD2 and the PMOS transistor of diode connection described in any one, this quantity round values that to be described voltage difference obtain divided by the value round off of described forward conduction threshold voltage.
Another technical scheme of the present invention is to provide a kind of low-power consumption Self-disconnecting circuit;
Described low-power consumption Self-disconnecting circuit comprises: be operated in the operating circuit under the second voltage VDD2 of the second voltage domain, and level shifting circuit, trigger, power circuit under the first voltage VDD1 being operated in the first voltage domain, with door, connects high circuit;
The voltage cut-off signals PD that described operating circuit produces, after described level shifting circuit conversion, is sent to the clock end CK of described trigger; The output terminal Q of described trigger is connected to described power circuit, so that control this power circuit whether provide the second voltage VDD2 to operating circuit; The input end D of described trigger is connected to the first voltage VDD1 of high level by connecing high circuit;
Only when the saltus step from low level to high level appears in described voltage cut-off signals PD, the output terminal Q of described trigger exports high level, controls its second voltage VDD2 provided to described operating circuit of described power-circuit breaking and supplies; After voltage supply is cut-off, the second voltage VDD2 level of described operating circuit slowly makes zero, and the level of described voltage cut-off signals PD is slowly made zero, and then the signal level after being changed by level shifting circuit is continued clamper in low level;
Wake-up signal WAKEUP and power-on reset signal POR is connected to input end that is described and door respectively, the described clear terminal RN being connected to trigger with the output terminal of door; By the Low level effective signal of described wake-up signal WAKEUP and power-on reset signal POR, described trigger is reset, control described power circuit and normally provide the second voltage VDD2 to operating circuit.
When described first voltage VDD1 is greater than the second voltage VDD2, the level shifting circuit described in first technical scheme is used to carry out the conversion in signal voltage territory.And when described first voltage VDD1 is less than the second voltage VDD2, employ part in described level shifting circuit except diode string to carry out the conversion in signal voltage territory: namely, wherein, the source electrode of MP1 directly connects described first voltage VDD1, and the device syndeton of other parts is constant.
Preferably, described power circuit is LDO circuit or the DC/DC circuit that can produce the second voltage VDD2 output by inputting the first voltage VDD1.
Preferably, in the circuit between described level shifting circuit and trigger, and described wake-up signal WAKEUP and power-on reset signal POR input to door before circuit in, be also respectively arranged with Dolby circuit.When input signal is Low level effective signal, described Dolby circuit comprises Smith's trigger circuit of filtering voltage domain noise, and the delay circuit of filtering time domain noise and or door.When input signal is high level useful signal, described Dolby circuit comprises Smith's trigger circuit of filtering voltage domain noise, and the delay circuit of filtering time domain noise and with door.
Compared with prior art, low-power consumption Self-disconnecting circuit of the present invention and wherein level shifting circuit, its beneficial effect is: the present invention can ensure that the voltage shutoff signal that it exports when operating circuit is de-energized still can normally work, this Self-disconnecting circuit is without quiescent dissipation simultaneously, farthest reduces the power consumption of circuit.In addition, Dolby circuit is adopted to carry out the reliability that filtering noise ensure that circuit working.
Accompanying drawing explanation
Fig. 1 is a kind of level shifting circuit adopting Latch structure;
Fig. 2 is the another kind of level shifting circuit adopting Latch structure;
Fig. 3 is the level shifting circuit adopting inverter structure;
Fig. 4 is the level shifting circuit using resistance;
Fig. 5 is level shifting circuit of the present invention;
Fig. 6 is Dolby circuit of the present invention (input signal is Low level effective);
Fig. 7 is Dolby circuit of the present invention (input signal is that high level is effective);
Fig. 8 is low-power consumption Self-disconnecting circuit of the present invention.
Embodiment
The invention provides low-power consumption Self-disconnecting circuit as shown in Figure 8, wherein comprise operating circuit 401, level shifting circuit 402, Dolby circuit 403,406,407, trigger 404, power circuit 405, with door 408, connect height (Tie-high) circuit 409.
Described operating circuit 401 is operated in VDD2 voltage domain, and other circuit workings are at VDD1 voltage domain.The control circuit of operating circuit 401 produces voltage cut-off signals PD, and this signal PD is converted to the signal of VDD1 voltage domain through level shifting circuit 402, the clock CK being then connected to trigger 404 after the process of Dolby circuit 403 holds.Under the output Q of trigger 404 holds control, power circuit 405 determines whether to provide voltage to VDD2.Power circuit 405 can be LDO circuit, and DC/DC circuit etc. can produce from a service voltage VDD1 circuit that another voltage exports VDD2.Wake-up signal WAKEUP and power-on reset signal POR is connected to the input end with door 408 after all being processed by corresponding Dolby circuit 406,407, is connected to the clear terminal RN of trigger 404 with the output terminal of door 408.The input end D of trigger 404 is connected to high level VDD1 by connecing high circuit 409.
The present invention, by adopting specific level shifting circuit 402, to ensure that when operating circuit 401 is cut-off voltage shutoff signal this circuit simultaneously that still normally works does not bring quiescent dissipation.
Specifically, when VDD1<VDD2, described level shifting circuit 402 uses inverter structure as shown in Figure 3, comprises nmos pass transistor MN1 and MN2, PMOS transistor MP1 and MP2.MN1 and MP1 forms phase inverter; The grid of MN1 and MP1 is connected to input signal PD, and the drain electrode of MN1 and MP1 is connected to PD_, the source ground of MN1, and the source electrode of MP1 meets power vd D1.MN2 and MP2 forms phase inverter simultaneously; The grid of MN2 and MP2 is connected to signal PD_, and the drain electrode of MN2 and MP2 is connected to the source ground exporting PD_OUT, MN2, and the source electrode of MP2 meets power vd D1.When voltage shutoff signal PD is low level, MP1 conducting and MN1 turn off, and when PD is high level VDD2, MP1 turns off and MN1 conducting.But this circuit can not be adopted to realize level conversion as VDD1>VDD2.Because when PD is high level VDD2, due to VDD1>VDD2, when MN1 conducting MP1 also conducting have quiescent current, add process deviation by cisco unity malfunction because transistor size is improper time serious.
Adopt circuit as shown in Figure 4 also can ensure the normal work of level shifting circuit as VDD1>VDD2, but this circuit have quiescent dissipation when PD signal is high level.
Therefore, when VDD1>VDD2, the level shifting circuit 402 described in the preferred embodiments of the present invention uses circuit structure as shown in Figure 5, wherein comprises nmos pass transistor MN1 and MN2, PMOS transistor MP1, MP2, MP3 and MP4.MN1 and MP1 forms phase inverter; The grid of MN1 and MP1 is connected to input signal PD, and the drain electrode of MN1 and MP1 is connected to PD_, the source ground of MN1, and the source electrode of MP1 connects the drain electrode of MP3.Meanwhile, MN2 and MP2 forms phase inverter; The grid of MN2 and MP2 is connected to PD_, and the drain electrode of MN2 and MP2 is connected to the source ground exporting PD_OUT, MN2, and the source electrode of MP2 meets VDD1.MP3 and MP4 all adopts diode-connected, that is, its respective grid is connected with drain electrode.The drain electrode of MP3 is connected with the source electrode of MP1, and the source electrode of MP3 is connected with the drain electrode of MP4, and the source electrode of MP4 meets power vd D1.MP3 and MP4 constitutes diode string.
In side circuit, the number of diode string is determined by the forward conduction threshold voltage of the voltage difference of VDD1 and VDD2 and the PMOS transistor of diode connection, for [VDD1-VDD2/ diode forward conduction threshold voltage+0.5], that is, be round values that the voltage difference of VDD1 and VDD2 obtains divided by the value round off of diode forward conduction threshold voltage.Like this when PD is high level VDD2, due to the effect of diode string, MN1 conducting and MP1 turn off, and ensure that the normal work of circuit.When PD is low level, MN1 turns off and MP1 conducting.Like this, circuit does not have quiescent current completely.
Meanwhile, the voltage shutoff signal after level shifting circuit 402 and Dolby circuit 403 process is sent to the clock end CK of trigger 404.And the D termination high level of trigger 404.Like this, only when the saltus step from low level to high level appears in PD signal, the output terminal of trigger 404 just exports high level, and and then makes power circuit 405 cut off the voltage supply of VDD2.After the voltage supply of VDD2 is cut-off, due to electric leakage, the level meeting slowly zero on VDD2, and the level on PD also slowly can make zero due to electric leakage, the level after level shifting circuit 402 will continue to be clamped at the normal work that low level ensures circuit.When electrification reset or operating circuit 401 need to wake up, trigger 404 can reset and make power circuit 405 normal supply voltage to VDD2 to ensure the normal work of operating circuit 401 by the Low level effective signal on POR and WAKEUP signal.
In order to prevent PD, WAKEUP, and the noise on por signal makes trigger 404 produce misoperation, adopts circuit structure as shown in Figure 6 and Figure 7 to use as described Dolby circuit 403,406,407 in the present invention.When input signal is Low level effective signal, comprise Smith's trigger circuit 501 as shown in Figure 6, delay circuit 502 and or door 503 circuit; When input signal is high level useful signal, comprise Smith's trigger circuit 601 as shown in Figure 7, delay circuit 602 and with door 603 circuit.Smith's trigger circuit 501,601 are used for the noise of filtering voltage domain, and delay circuit 502,602 with or door 503/ and the combination of door 603 be then used for the noise of filtering time domain.Like this, low-voltage noise and burst pulse noise all be ensure that the reliability of circuit working by effective filtering.
In sum, low-power consumption Self-disconnecting circuit of the present invention, for cutting off the power supply of circuit itself to save power consumption.By using level shifting circuit and the register of ad hoc structure, this circuit can keep the constant off-position that keeps of dump signal level to reduce power consumption when own power source is cut-off.Meanwhile, when circuit normally works, this circuit does not have quiescent dissipation yet.Like this, this circuit reaches and farthest reduces power consumption to save the object of power consumption.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (8)
1. a level shifting circuit, is characterized in that,
The input signal of described level shifting circuit is the signal PD of the second voltage domain, the output signal obtained after being changed by this signal is the signal PD_OUT of the first voltage domain, wherein, the first voltage VDD1 of described first voltage domain is greater than the second voltage VDD2 of the second voltage domain;
Described level shifting circuit, comprises nmos pass transistor MN1 and MN2, PMOS transistor MP1 and MP2, and diode string; Described diode string is connected to form by the PMOS transistor of multiple diode connection, and the grid of the PMOS transistor of each described diode connection is connected with drain electrode; In described diode string, the source electrode of the PMOS transistor of first diode connection meets the first voltage VDD1;
Pipe MN1 and pipe MP1 forms a phase inverter: make the grid of pipe MN1 and pipe MP1 be connected to input end to receive the signal PD of the second voltage domain, the drain electrode of pipe MN1 and pipe MP1 is connected to signal end PD_, the source ground of pipe MN1, the source electrode of pipe MP1 connects the drain electrode of the PMOS transistor of diode connection described in last in described diode string;
Pipe MN2 and pipe MP2 forms another phase inverter: the grid of pipe MN2 and pipe MP2 is connected to signal end PD_, the drain electrode of pipe MN2 and pipe MP2 is connected to output terminal to send the signal PD_OUT of the first voltage domain, the source ground of pipe MN2, the source electrode of pipe MP2 meets the first voltage VDD1;
When the signal PD of the second voltage domain is the second voltage VDD2 of high level, due to the effect of described diode string, pipe MN1 conducting and pipe MP1 turns off; When the signal PD of described second voltage domain is low level, pipe MN1 turns off and pipe MP1 conducting, thus does not have quiescent current on this level shifting circuit.
2. level shifting circuit as claimed in claim 1, is characterized in that,
The quantity of the PMOS transistor of diode connection in described diode string, determined by the forward conduction threshold voltage of the voltage difference of described first voltage VDD1 and the second voltage VDD2 and the PMOS transistor of diode connection described in any one, this quantity round values that to be described voltage difference obtain divided by the value round off of described forward conduction threshold voltage.
3. a low-power consumption Self-disconnecting circuit, is characterized in that, described low-power consumption Self-disconnecting circuit comprises:
Be operated in the operating circuit (401) under the second voltage VDD2 of the second voltage domain, and level shifting circuit (402), trigger (404), power circuit (405) under the first voltage VDD1 being operated in the first voltage domain, with door (408), connect high circuit (409);
When described first voltage VDD1 is greater than the second voltage VDD2, the voltage cut-off signals PD that described operating circuit (401) produces, after level shifting circuit as claimed in claim 1 (402) carries out the conversion in signal voltage territory, be sent to the clock end CK of described trigger (404); The output terminal Q of described trigger (404) is connected to described power circuit (405), so that control this power circuit (405) whether provide the second voltage VDD2 to operating circuit (401); The input end D of described trigger (404) is connected to the first voltage VDD1 of high level by connecing high circuit (409);
Only when the saltus step from low level to high level appears in described voltage cut-off signals PD, the output terminal Q of described trigger (404) exports high level, controls the second voltage VDD2 that described power circuit (405) cuts off it and provide to described operating circuit (401) and supplies; After voltage supply is cut-off, second voltage VDD2 level of described operating circuit (401) slowly makes zero, the level of described voltage cut-off signals PD is slowly made zero, and then continues clamper in low level by by the signal level after level shifting circuit (402) conversion;
Wake-up signal WAKEUP and power-on reset signal POR is connected to input end that is described and door (408) respectively, the described clear terminal RN being connected to trigger (404) with the output terminal of door (408); By the Low level effective signal of described wake-up signal WAKEUP and power-on reset signal POR, described trigger (404) is reset, controls described power circuit (405) and normally provide the second voltage VDD2 to operating circuit (401).
4. low-power consumption Self-disconnecting circuit as claimed in claim 3, is characterized in that,
When described first voltage VDD1 is less than the second voltage VDD2, use except diode string respectively by pipe MN1 and pipe MP1 in described level shifting circuit (402), two phase inverters that pipe MN2 and pipe MP2 forms carry out the conversion in signal voltage territory, the source electrode of wherein pipe MP1 is changed into and connects described first voltage VDD1.
5. low-power consumption Self-disconnecting circuit as claimed in claim 3, is characterized in that,
Described power circuit (405) is LDO circuit or the DC/DC circuit that can produce the second voltage VDD2 output by inputting the first voltage VDD1.
6. low-power consumption Self-disconnecting circuit as claimed in claim 3, is characterized in that,
In circuit between described level shifting circuit (402) and trigger (404), and described wake-up signal WAKEUP and power-on reset signal POR input to door (408) before circuit in, be also respectively arranged with Dolby circuit (403,406,407).
7. low-power consumption Self-disconnecting circuit as claimed in claim 6, is characterized in that,
When input signal is Low level effective signal, described Dolby circuit (403,406,407) comprises Smith's trigger circuit (501) of filtering voltage domain noise, and the delay circuit of filtering time domain noise (502) and or door (503).
8. low-power consumption Self-disconnecting circuit as claimed in claim 6, is characterized in that,
When input signal is high level useful signal, described Dolby circuit (403,406,407) comprises Smith's trigger circuit (601) of filtering voltage domain noise, and the delay circuit of filtering time domain noise (602) and with door (603).
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| CN201310383652.3A CN103412509B (en) | 2013-08-29 | 2013-08-29 | Low-power consumption Self-disconnecting circuit and level shifting circuit thereof |
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| CN107231084B (en) * | 2016-04-29 | 2023-12-12 | 上海良信电器股份有限公司 | Controllable power supply circuit with wide voltage input |
| CN108322210A (en) * | 2017-01-16 | 2018-07-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of level shifting circuit |
| CN110277128B (en) * | 2019-06-03 | 2023-02-03 | 上海华力集成电路制造有限公司 | Boost circuit applied to low-voltage flash memory |
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| CN112272022B (en) * | 2020-09-30 | 2022-11-08 | 合肥寰芯微电子科技有限公司 | Low-power-consumption external interrupt wake-up circuit and control method thereof |
| CN113193750B (en) * | 2021-07-01 | 2021-09-17 | 成都市安比科技有限公司 | High-voltage-resistant LDO linear power supply realized by low-voltage MOSFET |
| CN114172507B (en) * | 2021-11-30 | 2023-03-17 | 合肥鲸鱼微电子有限公司 | Reset signal transmission circuit, chip and electronic equipment |
| CN114387932B (en) * | 2022-01-18 | 2022-12-16 | 北京奕斯伟计算技术股份有限公司 | Protection circuit and protection method, output unit, source driver and display device |
| CN115664408B (en) * | 2022-11-10 | 2023-11-21 | 江苏谷泰微电子有限公司 | Level shifter of unknown voltage domain |
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