CN102571005B - Rail-to-rail operational amplifier - Google Patents
Rail-to-rail operational amplifier Download PDFInfo
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- CN102571005B CN102571005B CN201010605359.3A CN201010605359A CN102571005B CN 102571005 B CN102571005 B CN 102571005B CN 201010605359 A CN201010605359 A CN 201010605359A CN 102571005 B CN102571005 B CN 102571005B
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- rail
- input stage
- pmos
- operational amplifier
- mirror image
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Abstract
A kind of rail-to-rail operational amplifier, comprising: operational amplification input stage, buck stages and output stage, described operational amplification input stage includes PMOS input stage and NMOS input stage；Described operational amplification input stage also includes mirror image input stage, described mirror image input stage and PMOS input stage, NMOS input stage three grades input in parallel.On the premise of not being significantly increased circuit complexity, under the conditions of enabling rail-to-rail operational amplifier to be applied to the even lower supply voltage of 1.8V, significantly reduce the power consumption of circuit, it is possible to meet the design requirement of low-voltage and low-power dissipation.
Description
[technical field]
The present invention relates to a kind of IC design, particularly relate to monolithic operational amplifier, arrive to obtain rail
The input capability of rail (rail to rail).
[background technology]
Industry trends with the electronic system of operational amplifier is just relatively low towards provided by battery supply
The direction of running voltage is developed.So, amplifier is in use, except requiring the regulation with traditional amplifier
Such as high input impedance, low input offset voltage, low noise, wide bandwidth, high speed with sufficiently export driving
Beyond ability, also require that low pressure single supply works.Although various types of input stages are all by single-power voltage source
Power supply, but the low-voltage of amplifier operation is but because of the type of input stage and the manufacturing process of integrated circuit
Different.
Rail-to-rail operational amplifier is that one can be at common-mode voltage range (the most rail-to-rail voltage model
Enclose) in the operational amplifier of normal work.Owing to supply voltage is rapid along with the reduction of technology feature size
Reducing, the input/output scope of the operational amplifier of traditional structure reduces the most immediately, thus the signal to noise ratio of signal
The most correspondingly diminish；In order to obtain enough signal to noise ratios, operational amplifier requires to process rail-to-rail defeated
Enter/output voltage range.
With reference to shown in Fig. 1, in order to enable traditional rail-to-rail operational amplifier to be applied to lower pressure, often
The solution of rule is the source electrode of PMOS input stage to be connected with substrate reduce the threshold value of PMOS input stage
Voltage Vth to Vth0, and then make supply voltage reduce, indirectly expand the common-mode input range of circuit.But
This structural circuit still cannot be applied to the design under the conditions of 1.8V supply voltage.As in figure 2 it is shown, work as power supply
Voltage from 3.3V be reduced to 1.8V the lowest time, the maximum ICMR of PMOS input stage will be less than NMOS
The minimum ICMR of input stage, produces the problem that input was lost efficacy near VDD/2, although PMOS input stage
Threshold voltage is reduced to Vth0 also cannot solve this problem.
In view of above drawback, but it is necessary that the rail-to-rail operational amplifier providing a kind of improvement is to solve above-mentioned lacking
Fall into.
[summary of the invention]
It is an object of the invention to provide a kind of rail that can work at low supply voltages and leakage current can be suppressed
To rail operational amplifier.
For solving the problems referred to above, the present invention provides a kind of rail-to-rail operational amplifier, comprising: amplifier input
Level, buck stages and output stage, described operational amplification input stage includes PMOS input stage and NMOS input
Level；It is characterized in that: described operational amplification input stage also includes mirror image input stage, described mirror image input stage and PMOS
The input in parallel of input stage, NMOS input stage three grades.
Alternatively, the circuit of described buck stages is the N-WELL for controlling PMOS input pipe underlayer voltage
Reduction voltage circuit.
Alternatively, described mirror image input stage is PMOS mirror image input stage, defeated for PMOS described in mirror image
Enter the electric current of level, and described electric current is introduced N-WELL reduction voltage circuit.
Alternatively, described output stage uses CASCODE output stage.
Alternatively, described PMOS input stage is made up of a pair PMOS M1, M2.
Alternatively, described NMOS input stage is made up of a pair NMOS tube M4, M5.
Alternatively, described mirror image PMOS input stage include by metal-oxide-semiconductor M20, metal-oxide-semiconductor M21 and
For the metal-oxide-semiconductor M22 by described current mirror to N-WELL reduction voltage circuit.
Alternatively, the N-WELL reduction voltage circuit of described rail-to-rail operational amplifier includes and mirror image PMOS
Metal-oxide-semiconductor M23 that the metal-oxide-semiconductor M22 of input stage connects and for suppressing the metal-oxide-semiconductor of leakage current
M25。
Alternatively, the circuit of described mirror image PMOS input stage reflects in PMOS input stage accurately
The duty of PMOS input pipe.
Compared with prior art, above-mentioned rail-to-rail operational amplifier has the advantage that and be not significantly increased
On the premise of circuit complexity, rail-to-rail operational amplifier is enable to be applied to the even lower power supply of 1.8V
Under voltage conditions, significantly reduce the power consumption of circuit, it is possible to meet the design requirement of low-voltage and low-power dissipation.
[accompanying drawing explanation]
Fig. 1 is the electrical block diagram of rail-to-rail operational amplifier in prior art；
Fig. 2 is the ICMR schematic diagram of rail-to-rail operational amplifier in prior art；
Fig. 3 is the electrical block diagram of the rail-to-rail operational amplifier of the present invention；
Fig. 4 is the principle explanatory diagram of buck stages in rail-to-rail operational amplifier shown in Fig. 3.
[detailed description of the invention]
Rail-to-rail operational amplifier is that one can be at common-mode voltage range (the most rail-to-rail voltage model
Enclose) in the operational amplifier of normal work.Owing to supply voltage is rapid along with the reduction of technology feature size
Reducing, the input/output scope of the operational amplifier of traditional structure reduces the most immediately, thus the signal to noise ratio of signal
The most correspondingly diminish；In order to obtain enough signal to noise ratios, operational amplifier requires to process rail-to-rail defeated
Enter/output voltage range.Generally, traditional rail-to-rail operational amplifier be substantially employing operational amplification input stage and
The multi-stage operational amplifier that CASCODE output stage is constituted.Operational amplification input stage and CASCODE output stage can
To process rail-to-rail voltage range, and CASCODE output stage have stronger load driving force and
Efficiency, the most this rail-to-rail operational amplifier can serve as the output buffer stage of analog circuit.
Operational amplification input stage is actually and uses NMOS input stage and the two grades of parallel connections of PMOS input stage simultaneously
The input structure realized.When supply voltage from 3.3V be reduced to 1.8V the lowest time, then operation amplifier
NMOS input stage and PMOS input stage in input stage are to end near VDD/2 at input voltage simultaneously,
Failure state occurs.
With reference to shown in Fig. 3, it is the embodiment of the rail-to-rail operational amplifier of the present invention, comprising: amplifier
Input stage, buck stages and CASCODE output stage.Described operational amplification input stage adds described in a mirror image
The mirror image PMOS input stage of PMOS input stage, it is achieved NMOS input stage, PMOS input stage and
Mirror image PMOS input stage three grades input in parallel.The circuit of described buck stages is for being used for controlling PMOS input
The N-WELL reduction voltage circuit of pipe underlayer voltage, described mirror image PMOS input stage is for PMOS described in mirror image
The electric current of input stage, and this electric current is introduced described N-WELL reduction voltage circuit.
The PMOS input pipe of metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 composition PMOS input stage.Metal-oxide-semiconductor
M4 and metal-oxide-semiconductor M5 is the NMOS input pipe of composition NMOS input stage.Metal-oxide-semiconductor M20 and
Metal-oxide-semiconductor M21 is the PMOS input pipe of composition mirror image PMOS input stage, and metal-oxide-semiconductor M22 is mirror image
Current mirror in PMOS input stage is in the N-WELL reduction voltage circuit of buck stages.Mirror image PMOS is defeated
The circuit design entering level can accurately reflect the duty of PMOS input pipe in PMOS input stage,
When in PMOS input stage, the grid common-mode voltage of PMOS input pipe raises, in PMOS input stage
PMOS input pipe electric current reduces and finally turns off, and the effect of mirror image PMOS input stage is that PMOS is defeated
The running status entering level reflects in buck stages.
With reference to shown in Fig. 4, it is buck stages principle explanatory diagram in the rail-to-rail operational amplifier of the present invention.
With reference to shown in Fig. 3, the circuit of the buck stages in the rail-to-rail operational amplifier of the present invention is N-WELL fall
Volt circuit, wherein metal-oxide-semiconductor M25 makees diode connection so that it is VSD is more than the electricity of PMOS input stage
The voltage VDST of road tail current M3.Thus ensure when the grid of PMOS input pipe in PMOS input stage
When pole common-mode voltage becomes big, enable source electrode and the underlayer voltage of the PMOS input pipe of PMOS input stage
Realize the design of Fig. 4.
By threshold voltage formula
Understand, when VSB is timing, PMOS
The absolute value of the threshold voltage vt h of input pipe will diminish, to increase the ICMR of PMOS input stage circuit
The upper limit, and guarantee to meet V under lower pressureDD-Vdsat_M3-|VTh, P| ＞ Vgs_M4+Vdsat_M6+VSS。
When in PMOS input stage circuit the grid common-mode voltage of PMOS input pipe more than PMOS input stage
During the upper limit of the ICMR of circuit, the electric current of PMOS input stage circuit is by reduction and ultimately results in PMOS
Input pipe turns off, and in PMOS input stage circuit, the source voltage of metal-oxide-semiconductor M1 and metal-oxide-semiconductor M2 will become
Very big, PN junction in PMOS input stage can positively biased, produce big substrate leakage current.In the case,
The circuit of mirror image PMOS input stage is identical with the input signal of the circuit of PMOS input stage, MOS
Pipe M22 is in the current mirror in mirror image PMOS input stage to N-WELL reduction voltage circuit.Now,
N-WELL reduction voltage circuit reflects the duty of PMOS input pipe in PMOS input stage accurately.
Because the electric current in PMOS input stage reduces and finally turns off, the electric current in metal-oxide-semiconductor M22 also synchronizes change
And it is mirrored to metal-oxide-semiconductor M23 according to a certain percentage, finally by the voltage at metal-oxide-semiconductor M25 source and drain two ends
Reduce and promote the voltage of PMOS input pipe substrate, make that PN junction is reverse-biased suppresses leakage current.Described mirror image
The circuit of PMOS input stage and N-WELL reduction voltage circuit synergy improve PMOS input pipe and turn off
After underlayer voltage, and then suppression substrate leakage current.
In sum, the rail-to-rail operational amplifier of the present invention on the premise of not being significantly increased circuit complexity,
Under the conditions of enabling rail-to-rail operational amplifier to be applied to the even lower supply voltage of 1.8V, significantly
Reduce the power consumption of circuit, it is possible to meet the design requirement of low-voltage and low-power dissipation；Simultaneously the most cleverly to PMOS
The substrate leakage current of input pipe is suppressed.
Although the present invention discloses as above with preferred embodiment, but the present invention is not limited to this.Any ability
Field technique personnel, without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore
Protection scope of the present invention should be as the criterion with claim limited range.
Claims (7)
1. a rail-to-rail operational amplifier, comprising: operational amplification input stage, buck stages and output stage, described
Operational amplification input stage includes PMOS input stage and NMOS input stage；It is characterized in that: described amplifier
Input stage also includes mirror image input stage, described mirror image input stage and PMOS input stage, NMOS input
Level three grades input in parallel, the circuit of described buck stages is for controlling PMOS input pipe underlayer voltage
N-WELL reduction voltage circuit, described mirror image input stage is PMOS mirror image input stage, for described in mirror image
The electric current of PMOS input stage, and described electric current is introduced N-WELL reduction voltage circuit.
2. the rail-to-rail operational amplifier as described in claim 1 any one, it is characterised in that described output
Level uses CASCODE output stage.
Rail-to-rail operational amplifier the most as claimed in claim 2, it is characterised in that described PMOS inputs
Level is made up of a pair PMOS M1, M2.
Rail-to-rail operational amplifier the most as claimed in claim 3, it is characterised in that described NMOS inputs
Level is made up of a pair NMOS tube M4, M5.
Rail-to-rail operational amplifier the most as claimed in claim 4, it is characterised in that described mirror image PMOS
Input stage include by metal-oxide-semiconductor M20, metal-oxide-semiconductor M21 and for by described current mirror to
The metal-oxide-semiconductor M22 of N-WELL reduction voltage circuit.
Rail-to-rail operational amplifier the most as claimed in claim 5, it is characterised in that described rail-to-rail computing is put
The N-WELL reduction voltage circuit of big device includes that the metal-oxide-semiconductor M22 with mirror image PMOS input stage is even
The metal-oxide-semiconductor M23 that connects and for suppressing the metal-oxide-semiconductor M25 of leakage current.
Rail-to-rail operational amplifier the most as claimed in claim 6, it is characterised in that described mirror image PMOS
The circuit of input stage reflects the duty of PMOS input pipe in PMOS input stage accurately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010605359.3A CN102571005B (en) | 2010-12-27 | 2010-12-27 | Rail-to-rail operational amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010605359.3A CN102571005B (en) | 2010-12-27 | 2010-12-27 | Rail-to-rail operational amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102571005A CN102571005A (en) | 2012-07-11 |
| CN102571005B true CN102571005B (en) | 2016-08-17 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010605359.3A Active CN102571005B (en) | 2010-12-27 | 2010-12-27 | Rail-to-rail operational amplifier |
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| CN (1) | CN102571005B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104656738B (en) * | 2014-12-23 | 2016-05-11 | 工业和信息化部电子第五研究所 | The rail-to-rail output-stage circuit of the permanent mutual conductance of infrared focus plane two-forty |
| CN104883146A (en) * | 2015-04-20 | 2015-09-02 | 成都岷创科技有限公司 | Rail-to-rail differential amplifier |
| CN110690865B (en) * | 2019-10-24 | 2020-11-13 | 杭州雄迈集成电路技术股份有限公司 | High transconductance low input capacitance rail-to-rail operational amplifier |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101860332A (en) * | 2009-04-07 | 2010-10-13 | 斯沃奇集团研究和开发有限公司 | Amplifier circuit with reduced phase noise |
| CN102158188A (en) * | 2011-03-15 | 2011-08-17 | 清华大学 | Low-power consumption bandwidth-multiplying operational amplifier realized by metal oxide semiconductor (MOS) devices |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7075370B2 (en) * | 2004-08-03 | 2006-07-11 | Intersil Americas Inc. | CMOS-configured transconductance amplifier circuit |
-
2010
- 2010-12-27 CN CN201010605359.3A patent/CN102571005B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101860332A (en) * | 2009-04-07 | 2010-10-13 | 斯沃奇集团研究和开发有限公司 | Amplifier circuit with reduced phase noise |
| CN102158188A (en) * | 2011-03-15 | 2011-08-17 | 清华大学 | Low-power consumption bandwidth-multiplying operational amplifier realized by metal oxide semiconductor (MOS) devices |
Non-Patent Citations (1)
| Title |
|---|
| 一种低压轨至轨输入输出稳定跨导运算放大器的设计;张扬;《中国优秀硕士论文全文数据库（信息科技辑）》;20081215(第12期);第3章第3.1-3.2节，附图3-1，3-4 * |
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| CN102571005A (en) | 2012-07-11 |
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Free format text: FORMER OWNER: WUXI HUARUN SHANGHUA TECHNOLOGY CO., LTD. Effective date: 20131216 |
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| TA01 | Transfer of patent application right |
Effective date of registration: 20131216 Address after: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Applicant after: Wuxi CSMC Semiconductor Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Applicant before: Wuxi CSMC Semiconductor Co., Ltd. Applicant before: Wuxi Huarun Shanghua Technology Co., Ltd. |
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Effective date of registration: 20171130 Address after: 214028 Xinzhou Road, Wuxi national hi tech Industrial Development Zone, Jiangsu, China, No. 8 Patentee after: Wuxi Huarun Shanghua Technology Co., Ltd. Address before: 214028 Wuxi provincial high tech Industrial Development Zone, Hanjiang Road, No. 5, Jiangsu, China Patentee before: Wuxi CSMC Semiconductor Co., Ltd. |
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