CN102522829B - Power supply management circuit - Google Patents
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- CN102522829B CN102522829B CN201110447635.2A CN201110447635A CN102522829B CN 102522829 B CN102522829 B CN 102522829B CN 201110447635 A CN201110447635 A CN 201110447635A CN 102522829 B CN102522829 B CN 102522829B
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Abstract
The invention discloses a power supply management circuit which is used to provide a predetermined voltage to a memory cell. The power supply management circuit comprises: a first transistor, a second transistor, a first input terminal, a second input terminal and an output terminal. A source electrode of the first transistor is connected with a power supply terminal VCC. A grid electrode of the first transistor is connected with a drain electrode of the second transistor and is connected with the first input terminal. The drain electrode of the first transistor is connected with the source electrode of the second transistor and is connected with the output terminal. The grid electrode of the second transistor is connected with the second input terminal. The first input terminal and the second input terminal provide a logic control signal. By using the power supply management circuit, storage circuit power consumption can be reduced and simultaneously a maintenance capability to data can be increased. And an area occupied by the power supply management circuit is small.
Description
Technical field
The present invention relates to a kind of electric power management circuit, be specifically related to a kind of electric power management circuit that is applied to memory cell.
Background technology
Along with improving constantly of CMOS technological level, and constantly the dwindling of minimum feature size, threshold voltage constantly reduces, and memory device presents two very important problems: leakage current constantly increase and stable state under the loss of data.If can not above problem be taken in, will certainly there is in some cases logic error, disabler.
The power consumption that at present memory produces is occupied important proportion in SOC (System-on-a-Chip) chip power-consumption, and along with the progress of technique, will account for larger ratio, so the problem of power consumption of memory has caused widely and payes attention to.In order to reduce power consumption of memory, its key is to reduce leakage current.Meanwhile, in order better to guarantee, the performance of memory also should improve the ability that data are kept.The technology of now this two large problems being taked is on memory circuitry, to connect an electric power management circuit (power gating).
Electric power management circuit in existing memory mainly contains header and two kinds of structures of footer, joins respectively shown in Fig. 1 and Fig. 2.Header and footer electric power management circuit are controlled by signal respectively and are drawn the conducting of PMOS pipe or pull-down NMOS pipe and close, thereby realize normal operation and the resting state of memory.Header and footer electric power management circuit are keeping, under the mode of operation or value preserving state of memory value, by power supply, providing voltage VDD, so under value preserving state, circuit produces larger power consumption.
In order to reduce the power consumption in circuit, take at value preserving state decline low supply voltage, and can guarantee that storing value do not lose simultaneously.Shown in ginseng Fig. 3, increased a PMOS pipe, and its grid has been connected with drain electrode, effect is equivalent to a diode, in the situation of normal operation, P1 conducting, power supply provides supply voltage for memory, when signal signal is high level, P1 closes, and by P2, is communicated with VDD and memory, and P2 produces a pressure drop, to memory, provide a relatively low voltage, make memory reduce power consumption under value preserving state.But owing to needing in this kind of circuit, the size tune by P1 and P2 is very large, could realize its function, applies in more cell array, occupies sizable area.
In view of this, be necessary to provide a kind of novel electric power management circuit.
Summary of the invention
For the deficiencies in the prior art, the technical problem that the present invention solves is to provide a kind of electric power management circuit, this electric power management circuit, when reducing memory circuit power consumption, can also improve the hold facility to data, and the shared area of this electric power management circuit is little simultaneously.
For solving the problems of the technologies described above, technical scheme of the present invention is achieved in that a kind of electric power management circuit, in order to predetermined voltage is offered to memory cell, especially, described electric power management circuit comprises the first transistor, transistor seconds, first input end, the second input and output, the source electrode of described the first transistor is connected with power end VCC, the grid of described the first transistor connects altogether with the drain electrode of transistor seconds and is connected with first input end, the drain electrode of described the first transistor connects altogether with the source electrode of transistor seconds and is connected with output, the grid of described transistor seconds is connected with the second input, described first input end and the second input provide logic control signal.
Preferably, in above-mentioned electric power management circuit, described electric power management circuit also comprises the 3rd transistor, and described the 3rd transistor is connected between first input end and the grid of the first transistor, and described the 3rd transistorized grid is connected in described the second input.
Preferably, in above-mentioned electric power management circuit, described electric power management circuit also comprises the 4th transistor, described the 4th transistorized drain electrode is connected with the grid of described the first transistor, described the 4th transistorized source electrode is connected with power end VCC, described the 4th transistor during not conducting, offers the voltage of power end VCC the grid of the first transistor at the first transistor and transistor seconds.
Preferably, in above-mentioned electric power management circuit, described electric power management circuit also comprises a not gate, and described not gate is connected between described first input end and the 4th transistorized grid.
Preferably, in above-mentioned electric power management circuit, described the first transistor and transistor seconds are PMOS pipe.
Compared with prior art, the invention has the advantages that:
(1) in the situation that of transistor seconds conducting, the grid of the first transistor is communicated with drain electrode, now the first transistor formation one has the diode of certain threshold voltage, hypotensive effect due to diode, current potential that output obtains is less than the current potential of power end VCC, thereby played the effect that reduces power consumption, the voltage that output obtains simultaneously can play again the data maintenance effect of memory cell.
(2) grid of the first transistor is connected with the 4th transistor, grid for the first transistor during the 4th transistor turns provides high voltage, make the first transistor all the time in cut-off state, thereby memory cell is stabilized in resting state, due to the raising of the first transistor grid voltage, can reduce leakage current unnecessary in circuit simultaneously.
(3) size due to transistor seconds, the 3rd transistor, the 4th transistor and not gate is all far smaller than the first transistor size, therefore the area that transistor seconds, the 3rd transistor, the 4th transistor and not gate take in circuit is very little.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Figure 1 shows that the schematic diagram of the header structure of electric power management circuit in prior art;
Figure 2 shows that the schematic diagram of the footer structure of electric power management circuit in prior art;
Figure 3 shows that the structural representation of another electric power management circuit in prior art;
Figure 4 shows that the structural representation of electric power management circuit in the specific embodiment of the invention.
Embodiment
The object of the invention is to provide a kind of electric power management circuit, and this electric power management circuit, when reducing memory circuit power consumption, can also improve the hold facility to data, and the shared area of this electric power management circuit is little simultaneously.
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is described in detail, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, the every other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work, belongs to the scope of protection of the invention.
Now join Fig. 4, the structure for memory cell electric power management circuit is described.Electric power management circuit comprises the first transistor 10, transistor seconds 20, the 3rd transistor 30, the 4th transistor 40, not gate 50, first input end CLP, the second input DCP and output VDDCI.Electric power management circuit memory cell during in different operating state (operating state, resting state, value preserving state) different control voltage is provided respectively.
The first transistor 10, transistor seconds 20 and the 4th transistor 40 are P type metal-oxide-semiconductor, and the 3rd transistor 30 is N-type metal-oxide-semiconductor, and first input end CLP and the second input DCP are used for providing logic control signal.The size of transistor seconds 20, the 3rd transistor 30, the 4th transistor 40 and not gate 50 is all far smaller than the first transistor 10 sizes, therefore the area that transistor seconds 20, the 3rd transistor 30, the 4th transistor 40 and not gate 50 take in circuit is very little.
The source electrode of the first transistor 10 is connected with power end VCC, the grid of the first transistor 10 connects altogether with the drain electrode of transistor seconds 20 and is connected with first input end CLP, and the drain electrode of the first transistor 10 connects altogether with the source electrode of transistor seconds 20 and is connected with output VDDCI; The grid of transistor seconds 20 is connected with the second input DCP; The 3rd transistor 30 is connected between first input end CLP and the grid of the first transistor 10, and the grid of the 3rd transistor 30 is connected in the second input DCP; Not gate 50 is connected between first input end CLP and the grid of the 4th transistor 40; The source electrode of the 4th transistor 40 is connected with power end VCC, and the drain electrode of the 4th transistor 40 is connected with the grid of the first transistor 10.
First input end CLP is by providing high level or low level to control cut-off or the conducting of the first transistor 10.
The second input DCP is by providing high level or low level to control cut-off or the conducting of transistor seconds 20.
The first transistor 10 is realized the effect of a diode under value preserving state, and keeping voltage for output VDDCI provides the data that are less than power end VCC voltage, data keep voltage to equal the voltage of power end VCC and the first transistor 10 as the difference between the threshold voltage of diode.
Transistor seconds 20 conducting under value preserving state, with being communicated with between the grid of realizing the first transistor 10 and drain electrode, thereby makes P1 form a diode.
The 3rd transistor 30, can be according to the logic signal value of first input end CLP, for the first transistor 10 provides gate voltage in the situation that of conducting.Simultaneously it can also realization condition: only, the in the situation that of transistor seconds 20 cut-off, first input end CLP just can provide gate voltage for the first transistor 10.
The 4th transistor 40 is in conducting situation, the 4th transistor 40 and not gate 50, the 3rd transistor 30 form a positive feedback, can provide high voltage for the grid of the first transistor 10, when resting state, can be so that the first transistor 10 cut-offs, so that memory cell is stabilized in resting state, simultaneously owing to having improved the grid voltage of the first transistor 10, can also reduce the leakage current in circuit.
Not gate 50 is connected between the 4th transistor 40 and first input end CLP, can will after the logical signal negate of first input end CLP, control cut-off or the conducting of the 4th transistor 40.
Now join Fig. 4, the work for memory cell electric power management circuit is described.When the second input DCP is high level, the 3rd transistor 30 conductings, transistor seconds 20 cut-offs, the grid of the first transistor 10 and drain electrode are not communicated with.If first input end CLP is low level, the first transistor 10 conductings, the 4th transistor 40 cut-offs, output VDDCI is output as the voltage of power end VCC, and now circuit is in running order.If first input end CLP is high level, the first transistor 10 cut-offs, the 4th transistor 40 conductings, not gate 50, the 3rd transistor 30 and the 4th transistor 40 form the grid that a positive feedback is the first transistor 10 provides high level, it is not worked, and now circuit is in resting state.
When the second input DCP is low level, the 3rd transistor 30 cut-offs, transistor seconds 20 conductings, the grid of the first transistor 10 and drain electrode are communicated with, and the first transistor 10 plays diode action, because diode has threshold voltage, the voltage that makes output VDDCI decreases with respect to the voltage of power end VCC, when reducing power consumption, also, for memory cell provides one to keep voltage, now circuit is in value preserving state.
In sum, the invention has the advantages that:
(1) in the situation that of transistor seconds conducting, the grid of the first transistor is communicated with drain electrode, now the first transistor formation one has the diode of certain threshold voltage, hypotensive effect due to diode, current potential that output obtains is less than the current potential of power end VCC, thereby played the effect that reduces power consumption, the voltage that output obtains simultaneously can play again the data maintenance effect of memory cell.
(2) grid of the first transistor is connected with the 4th transistor, grid for the first transistor during the 4th transistor turns provides high voltage, make the first transistor all the time in cut-off state, thereby memory cell is stabilized in resting state, due to the raising of the first transistor grid voltage, can reduce leakage current unnecessary in circuit simultaneously.
(3) size due to transistor seconds, the 3rd transistor, the 4th transistor and not gate is all far smaller than the first transistor size, therefore the area that transistor seconds, the 3rd transistor, the 4th transistor and not gate take in circuit is very little.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned one exemplary embodiment, and in the situation that not deviating from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore, no matter from which point, all should regard embodiment as exemplary, and be nonrestrictive, scope of the present invention is limited by claims rather than above-mentioned explanation, is therefore intended to include in the present invention dropping on the implication that is equal to important document of claim and all changes in scope.Any Reference numeral in claim should be considered as limiting related claim.
In addition, be to be understood that, although this specification is described according to execution mode, but not each execution mode only comprises an independently technical scheme, this narrating mode of specification is only for clarity sake, those skilled in the art should make specification as a whole, and the technical scheme in each embodiment also can, through appropriately combined, form other execution modes that it will be appreciated by those skilled in the art that.
Claims (4)
1. an electric power management circuit, in order to predetermined voltage is offered to memory cell, it is characterized in that: described electric power management circuit comprises the first transistor, transistor seconds, first input end, the second input and output, the source electrode of described the first transistor is connected with power end VCC, the grid of described the first transistor connects altogether with the drain electrode of transistor seconds and is connected with first input end, the drain electrode of described the first transistor connects altogether with the source electrode of transistor seconds and is connected with output, the grid of described transistor seconds is connected with the second input, described first input end and the second input provide logic control signal, described electric power management circuit also comprises the 4th transistor, described the 4th transistorized drain electrode is connected with the grid of described the first transistor, described the 4th transistorized source electrode is connected with power end VCC, described the 4th transistor is at the first transistor and transistor seconds during not conducting, the voltage of power end VCC is offered to the grid of the first transistor.
2. electric power management circuit according to claim 1, it is characterized in that: described electric power management circuit also comprises the 3rd transistor, described the 3rd transistor is connected between first input end and the grid of the first transistor, and described the 3rd transistorized grid is connected in described the second input.
3. electric power management circuit according to claim 1, is characterized in that: described electric power management circuit also comprises a not gate, and described not gate is connected between described first input end and the 4th transistorized grid.
4. according to the electric power management circuit described in claims 1 to 3 any one, it is characterized in that: described the first transistor and transistor seconds are PMOS pipe.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110447635.2A CN102522829B (en) | 2011-12-28 | 2011-12-28 | Power supply management circuit |
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| CN201110447635.2A CN102522829B (en) | 2011-12-28 | 2011-12-28 | Power supply management circuit |
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| CN102522829A CN102522829A (en) | 2012-06-27 |
| CN102522829B true CN102522829B (en) | 2014-02-26 |
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| CN105979178A (en) * | 2016-06-28 | 2016-09-28 | 严媚 | Self-powered image sensor for environment monitoring |
| CN108735258B (en) * | 2017-04-24 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Address decoder circuit |
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| CN100541577C (en) * | 2005-09-20 | 2009-09-16 | 三星移动显示器株式会社 | The organic light emitting display of scan drive circuit and this scan drive circuit of use |
| CN101540599A (en) * | 2008-03-21 | 2009-09-23 | 广芯电子技术(上海)有限公司 | Analog switch control circuit in chip |
| CN201323560Y (en) * | 2008-12-30 | 2009-10-07 | 天津南大强芯半导体芯片设计有限公司 | High-capacity switch driving circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007122814A (en) * | 2005-10-28 | 2007-05-17 | Oki Electric Ind Co Ltd | Semiconductor integrated circuit and leak current reduction method |
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Patent Citations (3)
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|---|---|---|---|---|
| CN100541577C (en) * | 2005-09-20 | 2009-09-16 | 三星移动显示器株式会社 | The organic light emitting display of scan drive circuit and this scan drive circuit of use |
| CN101540599A (en) * | 2008-03-21 | 2009-09-23 | 广芯电子技术(上海)有限公司 | Analog switch control circuit in chip |
| CN201323560Y (en) * | 2008-12-30 | 2009-10-07 | 天津南大强芯半导体芯片设计有限公司 | High-capacity switch driving circuit |
Non-Patent Citations (3)
| Title |
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| JP特开2007-122814A 2007.05.17 |
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Effective date of registration: 20230410 Address after: Room 2013, No. 2 Factory Building, East Side of North Section of Lu Xin Road, Xinta Community, Lili Town, Wujiang District, Suzhou City, Jiangsu Province, 215000 Patentee after: SUZHOU XINKUAN ELECTRONIC SCIENCE & TECHNOLOGY CO.,LTD. Address before: 215123 No. 199 benevolence Road, Suzhou Industrial Park, Jiangsu, China Patentee before: SOOCHOW University |
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Effective date of registration: 20231106 Address after: Room 606-4, Building 1, Jinji Lake Avenue, Suzhou Industrial Park, Suzhou, China (Jiangsu) Pilot Free Trade Zone, 215000, Jiangsu Province Patentee after: SUZHOU KUANWEN ELECTRONIC SCIENCE & TECHNOLOGY Co.,Ltd. Address before: Room 2013, No. 2 Factory Building, East Side of North Section of Lu Xin Road, Xinta Community, Lili Town, Wujiang District, Suzhou City, Jiangsu Province, 215000 Patentee before: SUZHOU XINKUAN ELECTRONIC SCIENCE & TECHNOLOGY CO.,LTD. |