CN102522109A - Power management circuit - Google Patents
Power management circuit Download PDFInfo
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- CN102522109A CN102522109A CN2011104476348A CN201110447634A CN102522109A CN 102522109 A CN102522109 A CN 102522109A CN 2011104476348 A CN2011104476348 A CN 2011104476348A CN 201110447634 A CN201110447634 A CN 201110447634A CN 102522109 A CN102522109 A CN 102522109A
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- storage unit
- management circuit
- power management
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- pmos pipe
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Abstract
The invention discloses a power management circuit, which is connected between an output end of a storage unit and a grounding electrode. The power management circuit is used for controlling the storage unit to obtain preset power voltage so as to realize a work, sleep or data maintaining state, and comprises at least one PMOS (P-channel metal oxide semiconductor) tube, substrates of the PMOS tubes are connected with a power end VCC, source electrodes of the PMOS tubes are connected with the output end of the storage unit, drain electrodes of the PMOS tubes are connected with the grounding electrode, a grid electrode and the drain electrode of each PMOS tube are communicated with each other when the storage unit is in the data maintaining state, and the grid electrode and the drain electrode of each PMOS tube are not communicated with each other when the storage unit is in the work or sleep state. By the aid of the power management circuit, power consumption of a storage circuit is reduced, simultaneously, data retention capacity can be improved, and rail-to-rail voltage of the storage unit is increased relatively under the condition of reducing voltage VCC of the power end.
Description
Technical field
The present invention relates to a kind of electric power management circuit, be specifically related to a kind of electric power management circuit that is applied to storage unit.
Background technology
Along with improving constantly of CMOS technological level, and constantly the dwindling of minimum feature size, threshold voltage constantly reduces, and memory device demonstrates two very important problems: leakage current constantly increase and steady state (SS) under the losing of data.If can not take in above problem, logic error, disabler will certainly appear in some cases.
At present the power consumption that produces of storer is occupied important proportion in SOC (System on Chip) chip power-consumption, and along with the progress of technology, will account for bigger ratio, so the problem of power consumption of memory has caused widely and payes attention to.In order to reduce power consumption of memory, its key is to reduce leakage current.Meanwhile, in order better to guarantee the performance of storer, also should improve the ability that data are kept.The technology of now this two large problems being taked is on memory circuitry, to connect an electric power management circuit.
Electric power management circuit in the existing storer mainly contains header and two kinds of structures of footer, joins illustrated in figures 1 and 2 respectively.Header and footer electric power management circuit be respectively by the conducting of drawing PMOS pipe or pull-down NMOS pipe in the signal control with close, thereby realize operate as normal and the dormant state of memory.Header and footer electric power management circuit provide voltage VDD by power supply under the mode of operation or value preserving state that keep the memory value, so under the value preserving state, circuit produces bigger power consumption.
In order to reduce the power consumption in the circuit, take at value preserving state decline low supply voltage, and can guarantee that simultaneously storing value do not lose.Join shown in Figure 3ly, increased PMOS pipe, and its grid is linked to each other with draining, substrate links to each other with source electrode; Effect is equivalent to a diode, under the situation of operate as normal, and the P1 conducting, power supply is that memory provides supply voltage; When the signal signal was high level, P1 closed, and then was communicated with VDD and memory through P2; P2 produces a pressure drop, to memory a relatively low voltage is provided, and makes memory under the value preserving state, reduce power consumption.The input voltage of VDD is also unstable, and the voltage of actual input storage unit can decrease.Because the substrate of P2 links to each other with source electrode, the threshold voltage when making it as diode is also fixed all the time, so under the value preserving state, the reduction of the voltage of VDD can make the rail-to-rail voltage of storage unit reduce.
In view of this, be necessary to provide a kind of novel electric power management circuit.
Summary of the invention
Deficiency to prior art; The technical matters that the present invention solves provides a kind of electric power management circuit; This electric power management circuit is when reducing the memory circuit power consumption; Can also improve the hold facility to data, this electric power management circuit can be so that rail-to-rail voltage becomes big relatively under the situation that power end voltage VCC reduces simultaneously.
For solving the problems of the technologies described above; Technical scheme of the present invention is achieved in that a kind of electric power management circuit; Be connected between the output terminal and earth polar of storage unit, said electric power management circuit obtains predetermined supply voltage to realize work, dormancy or value preserving state respectively, especially in order to the control store unit; Said electric power management circuit comprises at least one PMOS pipe; The substrate of said PMOS pipe connects power end VCC, and the source electrode of said PMOS pipe is connected in the output terminal of said storage unit, and the drain electrode of said PMOS pipe is connected in the earth polar; The said gate pmos utmost point is communicated with when storage unit is in the value preserving state with drain electrode, and the said gate pmos utmost point is not communicated with when storage unit is in work or dormant state with drain electrode.
Preferably, in above-mentioned electric power management circuit, also be connected with transistor between the said gate pmos utmost point and the drain electrode, said transistor through by and conducting be communicated with to realize the not connected sum between the said gate pmos utmost point and the drain electrode respectively.
Preferably, in above-mentioned electric power management circuit, said electric power management circuit comprises two PMOS pipes, is respectively PMOS pipe and the 2nd PMOS pipe, is connected between the output terminal and earth polar of said storage unit after said PMOS pipe and the series connection of the 2nd PMOS pipe.
Preferably; In above-mentioned electric power management circuit; Said electric power management circuit also comprises at least one NMOS pipe, is connected between the output terminal and earth polar of said storage unit after said NMOS pipe and the series connection of said PMOS pipe, and the substrate of said NMOS pipe connects the earth polar; Said NMOS tube grid is communicated with when storage unit is in the value preserving state with drain electrode, and said NMOS tube grid is not communicated with when storage unit is in work or dormant state with drain electrode.
Preferably, in above-mentioned electric power management circuit, also be connected with transistor between said NMOS tube grid and the drain electrode, said transistor through by and conducting be communicated with to realize the not connected sum between said NMOS tube grid and the drain electrode respectively.
The invention has the advantages that:
(1) electric power management circuit obtains predetermined supply voltage to realize work, dormancy or value preserving state respectively in order to the control store unit; When the value preserving state; The effect of PMOS pipe is equivalent to a diode, and this diode has certain threshold voltage, makes the voltage that storage unit obtained reduce; And then reduced power consumption, the value that the voltage that storage unit obtained simultaneously can be preserved storer.
(2) substrate of PMOS pipe connects power end VCC, when the voltage of power end VCC reduces, makes the threshold voltage of PMOS pipe reduce, and when making the value preserving state, it is big that the rail-to-rail voltage of storage unit becomes relatively, thereby can better preserve the value of storage unit.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Shown in Figure 1 is the synoptic diagram of the header structure of electric power management circuit in the prior art;
Shown in Figure 2 is the synoptic diagram of the footer structure of electric power management circuit in the prior art;
Shown in Figure 3 is the structural representation of another electric power management circuit in the prior art;
Shown in Figure 4 is the structural representation of electric power management circuit when the value preserving state in the embodiment of the invention 1;
Shown in Figure 5 is the structural representation of electric power management circuit when the value preserving state in the embodiment of the invention 2;
Shown in Figure 6 is the structural representation of electric power management circuit when the value preserving state in the embodiment of the invention 3.
Embodiment
The object of the invention is: in order to reduce the power consumption of storage unit under the value preserving state; Hope reduces the supply voltage value on the storage unit as far as possible; And under the situation of low pressure value preserving, can make rail-to-rail (RAIL-RAIL) value relatively large, thereby better preserve the value of storage unit.So in the design of storage unit, relate to the electric power management circuit technology, to improve the performance of storage unit.
To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out detailed description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, the every other embodiment that those of ordinary skills are obtained under the prerequisite of not making creative work belongs to the scope that the present invention protects.
Three kinds of circuit in following examples all design with the principle of footer circuit.
Embodiment 1
Join Fig. 4 at present, the structure and the principle of work of the electric power management circuit 10 that is used for storage unit memory is described.Electric power management circuit 10 is connected between the output terminal and earth polar of storage unit, and electric power management circuit 10 obtains predetermined supply voltage to realize work, dormancy or value preserving state respectively in order to the control store unit.
Electric power management circuit 10 comprises 11 and NMOS pipes 12 of a PMOS pipe, is connected between the output terminal and earth polar of storage unit after PMOS pipe 11 and 12 series connection of NMOS pipe.During duty, PMOS pipe 11 and the 12 equal conductings of NMOS pipe, the voltage of storage unit is power end VCC voltage; During dormant state, PMOS pipe 11 all ends with NMOS pipe 12, and the voltage of storage unit is zero.
The substrate of PMOS pipe 11 connects power end VCC, and the drain electrode of PMOS pipe 11 is connected in the earth polar, is connected with transistor (figure does not show) between the grid of PMOS pipe 11 and the drain electrode, and this transistor is PMOS pipe or NMOS pipe.When storage unit is in the value preserving state; This transistor turns; To realize the diode action of PMOS pipe 11, when storage unit was in dormancy or duty, this transistor ended; The grid of PMOS pipe 11 is controlled its conducting through the input of logic control signal and is ended, and then realizes on-off action.
The substrate of NMOS pipe 12 connects the earth polar; The source electrode of NMOS pipe 12 is connected with the source electrode of PMOS pipe 11; The drain electrode of NMOS pipe 12 is connected in the output terminal of storage unit, is connected with transistor (figure does not show) between the grid of NMOS pipe 12 and the drain electrode, and this transistor is PMOS pipe or NMOS pipe.When storage unit is in the value preserving state, this transistor turns, to realize the diode action of NMOS pipe 12, when storage unit was in dormancy or duty, this transistor ended, and NMOS pipe 11 is through conducting with by realizing on-off action.
When storage unit is in the value preserving state, be communicated with between the grid of PMOS pipe 11 and the drain electrode, make the effect of PMOS pipe 11 be equivalent to a diode; Be communicated with between the grid of NMOS pipe 12 and the drain electrode, make the effect of NMOS pipe 12 also be equivalent to a diode.Two diodes are connected between storage unit and the earth polar; And all has certain threshold voltage; Make this moment voltage that storage unit obtained less than the voltage of power end VCC, thereby play the effect that reduces power consumption, the value that the voltage that storage unit obtained simultaneously can be preserved storer.
When the voltage of power end VCC reduced, the also corresponding reduction of underlayer voltage of PMOS pipe 11 made the lining bias-voltage of PMOS pipe 11 reduce, thereby makes the also corresponding reduction of threshold voltage V1 of PMOS pipe 11.At this moment, the source voltage of NMOS pipe 12 reduces, and underlayer voltage is constant, make that voltage reduces between source electrode and the substrate of NMOS pipe 12, thereby the threshold voltage V2 of NMOS pipe 12 descends also.The voltage V=VCC-(V1+V2) that storage unit obtained, the voltage accounting of storage unit is that (1-(V1+V2)/VCC) is because when the voltage of power end VCC reduces; V1 and V2 also reduce; So the situation all constant with respect to V1 and V2 (substrate of PMOS pipe 11 is connected with source electrode), voltage V and voltage accounting that storage unit obtained are all relatively large, and promptly the rail-to-rail voltage of storage unit becomes big relatively; Thereby more stable preservation cell value under the state that low-voltage keeps, the performance of raising circuit.
Embodiment 2
Join Fig. 5 at present, the structure and the principle of work of the electric power management circuit 20 that is used for storage unit memory is described.Electric power management circuit 20 is connected between the output terminal and earth polar of storage unit, and electric power management circuit 20 obtains predetermined supply voltage to realize work, dormancy or value preserving state respectively in order to the control store unit.
Electric power management circuit 20 comprises two identical PMOS pipes 21 and 22 (PMOS pipe and the 2nd PMOS pipe), is connected between the output terminal and earth polar of storage unit after PMOS pipe 21 and 22 series connection of PMOS pipe.In other embodiments, the quantity of PMOS pipe also can be set to more than two, to realize the hypotensive effect under the value preserving state.During duty, PMOS manages 21 and 22 equal conductings, and the voltage of storage unit is power end VCC voltage; During dormant state, PMOS pipe 21 and 22 all ends, and the voltage of storage unit is zero.
The substrate of PMOS pipe 22 connects power end VCC, and the drain electrode of PMOS pipe 22 is connected in the earth polar, is connected with transistor (figure does not show) between the grid of PMOS pipe 22 and the drain electrode, and this transistor is PMOS pipe or NMOS pipe.When storage unit is in the value preserving state; This transistor turns; To realize the diode action of PMOS pipe 22, when storage unit was in dormancy or duty, this transistor ended; The grid of PMOS pipe 22 is controlled its conducting through the input of logic control signal and is ended, and then realizes on-off action.
The substrate of PMOS pipe 21 connects power end VCC; The drain electrode of PMOS pipe 21 is connected in the source electrode of PMOS pipe 22; The source electrode of PMOS pipe 21 is connected in the output terminal of storage unit, is connected with transistor (figure does not show) between the grid of PMOS pipe 21 and the drain electrode, and this transistor is PMOS pipe or NMOS pipe.When storage unit is in the value preserving state; This transistor turns; To realize the diode action of PMOS pipe 21, when storage unit was in dormancy or duty, this transistor ended; The grid of PMOS pipe 21 is controlled its conducting through the input of logic control signal and is ended, and then realizes on-off action.
When storage unit is in the value preserving state, be communicated with between the grid of PMOS pipe 21 and the drain electrode, make the effect of PMOS pipe 21 be equivalent to a diode; Be communicated with between the grid of PMOS pipe 22 and the drain electrode, make the effect of PMOS pipe 22 also be equivalent to a diode.Two diodes are connected between storage unit and the earth polar; And all has certain threshold voltage; Make this moment voltage that storage unit obtained less than the voltage of power end VCC, thereby play the effect that reduces power consumption, the value that the voltage that storage unit obtained simultaneously can be preserved storer.
When the voltage of power end VCC reduced, the also corresponding reduction of underlayer voltage of PMOS pipe 21 and 22 made the lining bias-voltage of PMOS pipe 21 and 22 reduce, thereby makes the also corresponding reduction of threshold voltage of PMOS pipe 21 and 22.So the situation all constant (PMOS manage 21 link to each other with source electrode with 22 substrate) with respect to PMOS pipe 21 and 22 threshold voltage; It is big that the rail-to-rail voltage of storage unit becomes relatively; Thereby more stable preservation cell value under the state that low-voltage keeps, the performance of raising circuit.
Embodiment 3
Join Fig. 6 at present, the structure and the principle of work of the electric power management circuit 30 that is used for storage unit memory is described.Electric power management circuit 30 is connected between the output terminal and earth polar of storage unit, and electric power management circuit 30 obtains predetermined supply voltage to realize work, dormancy or value preserving state respectively in order to the control store unit.
Electric power management circuit 30 comprises a PMOS pipe 31, and PMOS pipe 31 is series between the output terminal and earth polar of storage unit.During duty, PMOS manages 31 conductings, and the voltage of storage unit is power end VCC voltage; During dormant state, PMOS pipe 31 ends, and the voltage of storage unit is zero.
The substrate of PMOS pipe 31 connects power end VCC; The drain electrode of PMOS pipe 31 is connected in the earth polar; The source electrode of PMOS pipe 31 is connected in the output terminal of storage unit, is connected with transistor (figure does not show) between the grid of PMOS pipe 31 and the drain electrode, and this transistor is PMOS pipe or NMOS pipe.When storage unit is in the value preserving state; This transistor turns; To realize the diode action of PMOS pipe 31, when storage unit was in dormancy or duty, this transistor ended; The grid of PMOS pipe 31 is controlled its conducting through the input of logic control signal and is ended, and then realizes on-off action.
When storage unit is in the value preserving state, be communicated with between the grid of PMOS pipe 31 and the drain electrode, make the effect of PMOS pipe 31 be equivalent to a diode.Diode is connected between storage unit and the earth polar; Has certain threshold voltage; Make this moment voltage that storage unit obtained less than the voltage of power end VCC, thereby play the effect that reduces power consumption, the value that the voltage that storage unit obtained simultaneously can be preserved storer.
When the voltage of power end VCC reduced, the also corresponding reduction of underlayer voltage of PMOS pipe 31 made the lining bias-voltage of PMOS pipe 31 reduce, thereby makes the also corresponding reduction of threshold voltage of PMOS pipe 31.So manage the situation (substrate of PMOS pipe 31 links to each other with source electrode) of 31 threshold voltage unchanged with respect to PMOS, it is big that the rail-to-rail voltage of storage unit becomes relatively, thus under the state of low-voltage maintenance more stable preservation cell value, the performance of raising circuit.
The invention has the advantages that:
(1) electric power management circuit obtains predetermined supply voltage to realize work, dormancy or value preserving state respectively in order to the control store unit; When the value preserving state; PMOS pipe or the effect of NMOS pipe are equivalent to a diode, and this diode has certain threshold voltage, makes the voltage that storage unit obtained reduce; And then reduced power consumption, the value that the voltage that storage unit obtained simultaneously can be preserved storer.
(2) substrate of PMOS pipe connects power end VCC, when the voltage of power end VCC reduces, makes the threshold voltage of PMOS pipe reduce, and when making the value preserving state, it is big that the rail-to-rail voltage of storage unit becomes relatively, thereby can better preserve the value of storage unit.
To those skilled in the art, obviously the invention is not restricted to the details of above-mentioned example embodiment, and under the situation that does not deviate from spirit of the present invention or essential characteristic, can realize the present invention with other concrete form.Therefore; No matter from which point; All should regard embodiment as exemplary; And be nonrestrictive, scope of the present invention is limited accompanying claims rather than above-mentioned explanation, therefore is intended to the implication of the equivalents that drops on claim and all changes in the scope are included in the present invention.Should any Reference numeral in the claim be regarded as limit related claim.
In addition; Describing according to embodiment though should be appreciated that this instructions, is not that each embodiment only comprises an independently technical scheme; This narrating mode of instructions only is for clarity sake; Those skilled in the art should make instructions as a whole, and the technical scheme among each embodiment also can form other embodiments that it will be appreciated by those skilled in the art that through appropriate combination.
Claims (5)
1. electric power management circuit; Be connected between the output terminal and earth polar of storage unit; Said electric power management circuit obtains predetermined supply voltage to realize work, dormancy or value preserving state respectively in order to the control store unit, it is characterized in that: said electric power management circuit comprises at least one PMOS pipe, and the substrate of said PMOS pipe connects power end VCC; The source electrode of said PMOS pipe is connected in the output terminal of said storage unit; The drain electrode of said PMOS pipe is connected in the earth polar, and the said gate pmos utmost point is communicated with when storage unit is in the value preserving state with drain electrode, and the said gate pmos utmost point is not communicated with when storage unit is in work or dormant state with drain electrode.
2. electric power management circuit according to claim 1 is characterized in that: also be connected with transistor between the said gate pmos utmost point and the drain electrode, said transistor through by and conducting be communicated with to realize the not connected sum between the said gate pmos utmost point and the drain electrode respectively.
3. electric power management circuit according to claim 1; It is characterized in that: said electric power management circuit comprises two PMOS pipes; Be respectively PMOS pipe and the 2nd PMOS pipe, be connected between the output terminal and earth polar of said storage unit after said PMOS pipe and the series connection of the 2nd PMOS pipe.
4. electric power management circuit according to claim 1; It is characterized in that: said electric power management circuit also comprises at least one NMOS pipe; Be connected between the output terminal and earth polar of said storage unit after said NMOS pipe and the series connection of said PMOS pipe; The substrate of said NMOS pipe connects the earth polar, and said NMOS tube grid is communicated with when storage unit is in the value preserving state with drain electrode, and said NMOS tube grid is not communicated with when storage unit is in work or dormant state with drain electrode.
5. electric power management circuit according to claim 4 is characterized in that: also be connected with transistor between said NMOS tube grid and the drain electrode, said transistor through by and conducting be communicated with to realize the not connected sum between said NMOS tube grid and the drain electrode respectively.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011104476348A CN102522109A (en) | 2011-12-28 | 2011-12-28 | Power management circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011104476348A CN102522109A (en) | 2011-12-28 | 2011-12-28 | Power management circuit |
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| CN102522109A true CN102522109A (en) | 2012-06-27 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108073211A (en) * | 2016-11-11 | 2018-05-25 | 中芯国际集成电路制造(上海)有限公司 | A kind of generation circuit and electronic equipment for keeping voltage |
| CN109144158A (en) * | 2018-07-13 | 2019-01-04 | 上海华力集成电路制造有限公司 | The quiescent current supply circuit of IC chip |
| CN109782836A (en) * | 2018-12-27 | 2019-05-21 | 西安紫光国芯半导体有限公司 | It is a kind of for reducing the power supply unit and method of standby leakage current |
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Application publication date: 20120627 |