CN103928051B - A kind of random access memory bit location, random access memory and electronic chip - Google Patents
A kind of random access memory bit location, random access memory and electronic chip Download PDFInfo
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- CN103928051B CN103928051B CN201410145283.9A CN201410145283A CN103928051B CN 103928051 B CN103928051 B CN 103928051B CN 201410145283 A CN201410145283 A CN 201410145283A CN 103928051 B CN103928051 B CN 103928051B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
Abstract
The embodiment of the present invention provides a kind of random access memory bit location, random access memory and electronic chip, is related to field of storage, can solve the problem that the problem of memory reliability and power consumption.The random access memory bit location includes at least one power supply, the first write line, the second write line, write-in bit line, read line, reading bit line, read module, asymmetric memory module and conduction module.The random access memory is made up of the above-mentioned random access memory bit location of predetermined number, and the electronic chip includes the random access memory.The embodiment of the present invention is used to optimize the reliability and power consumption of random access memory.
Description
Technical field
The present invention relates to field of storage, more particularly to a kind of random access memory bit location, random access memory and electronic chip.
Background technology
With the manufacturing lifting of electronic chip technique, transistor size enters quasi- nanometer era, crystal in electronic chip
The integrated level more and more higher of pipe, so as to occur in that the high performance chipses that super large-scale integration is constituted, the high performance chipses
Demand creates the epoch of on-chip system (System on Chip, SoC).
As shown in figure 1, being a kind of eight pipes SRAM commonly used in the prior art（Static Random
Access Memory, SRAM）Bit location（Bit Cell）Structure, such SRAM determined bit position structure one has
Three states, respectively：Hold mode, reading state and write state.Wherein, write-in line traffic control turns on the conducting of transistor,
That is to say on-off action.The data mode of bit line traffic control conducting transistor, such as 0 or 1, specifically：
In hold mode, M1, M2, M3, M4Two phase inverters of head and the tail Opposite direction connection are constituted, by the two phase inverter structures
Into memory cell powered by VDD, write line be in 0 state, i.e., non-selected state, similarly for conducting transistor be also unselected
Select state（State is not turned on）, read bit line and read line be also in low level state, i.e., non-selected state.
In reading state, read line first applies high level, that is to say selection state, M8It is equal to conducting.Meanwhile, read
Bit line temporarily applies of short duration high voltage, that is to say of short duration 1 state.Two M of phase inverter of memory cell2With M4Being responsible for will
Its state for keeping controls M7Conducting whether, such that it is able to by M8Transistor expresses its state value.
In write state, write line is in high level state, i.e. state 1, meanwhile, two bit lines are in complementary shape
State, wherein a high level, state 1, another is low level, state 0.For example, during write storage unit 1, bit line is height
Level, and complementary bit line is then low level；During write storage unit 0, bit line is low level, and complementary bit line is then height
Level.
Because above-mentioned eight pipes SRAM has higher reliability and relatively low power consumption, so above-mentioned eight pipe is static
Random access memory is widely used in high performance chipses, but as chip volume constantly reduces, integrated level more and more higher, property
While constantly being lifted, its power consumption needs the special problem for considering in also increasingly becoming design.In particular with memory
The notable rising of proportion in SoC chip, the requirement of high reliability and low-power consumption for memory is also increasingly apparent therefore right
In the optimization of the reliability and power consumption of memory be problem demanding prompt solution.
The content of the invention
Embodiments of the invention provide a kind of random access memory bit location, random access memory and electronic chip, it is possible to increase
The reliability of memory, and reduce power consumption of memory.
To reach above-mentioned purpose, embodiments of the invention are adopted the following technical scheme that：
First aspect, there is provided a kind of random access memory bit location, the random access memory bit location includes：
At least one power supply, the first write line, the second write line, write-in bit line, read line, reading bit line, reading
Module, asymmetric memory module and conduction module；
Wherein, the data terminal of the read module is electrically connected with the reading bit line, the control end of the read module
Electrically connected with the read line, the reading end of the read module electrically connects with the output end of the asymmetric memory module；
The data terminal of the conduction module is electrically connected with said write bit line, the first control end of the conduction module with
The first write line electrical connection, the second control end of the conduction module is electrically connected with second write line, the conducting
The write-in end of module electrically connects with the input of the asymmetric memory module；
At least one power supply is electrically connected with the power supply interface of the read module.
With reference in a first aspect, in the first possible implementation, the asymmetric memory module includes：First is anti-phase
Device and the second phase inverter;The output end of first phase inverter is electrically connected with the input of second phase inverter, and described second
The output end of phase inverter is electrically connected with the input of first phase inverter；
Wherein, area of the area of second phase inverter more than first phase inverter.
With reference to the first possible implementation of first aspect, in second possible implementation, described first
Phase inverter includes the first transistor and transistor seconds, and second phase inverter includes the first transistor and transistor seconds；
The source ground of the first transistor, the grid of the first transistor is electric with the grid of the transistor seconds
Connection, the first transistor drain electrode is electrically connected with the drain electrode of the transistor seconds, the source electrode of the transistor seconds and institute
State power supply interface electrical connection；
The source ground of the third transistor, the grid of the third transistor is electric with the grid of the 4th transistor
Connection, third transistor drain electrode is electrically connected with the drain electrode of the 4th transistor, the source electrode of the 4th transistor and institute
State power supply interface electrical connection；
Wherein, the grid of the first transistor and the tie point of the grid of the transistor seconds are described first anti-phase
The input of device, the drain electrode of the first transistor is the defeated of first phase inverter with the tie point of the drain electrode of the transistor seconds
Go out end；The grid of the third transistor and the input that the tie point of the grid of the 4th transistor is second phase inverter
End, the drain electrode of third transistor and the output end that the tie point of the drain electrode of the 4th transistor is second phase inverter；
The grid of the first transistor is the asymmetric storage mould with the tie point of the grid of the transistor seconds
The input of block, the drain electrode of the third transistor is the asymmetric storage with the tie point of the drain electrode of the 4th transistor
The output end of module.
With reference to second possible implementation of first aspect, in the third possible implementation, when it is described extremely
When a few power supply is a power supply, the electric contact of the source electrode of the source electrode of the transistor seconds and the 4th transistor is constituted
The power supply interface, the power supply interface and one power electric connection；
When at least one power supply includes the first power supply and second source, the source electrode of the transistor seconds is used as institute
First power supply interface and first power electric connection of power supply interface are stated, the source electrode of the 4th transistor is used as the power supply
Second power supply interface of interface is electrically connected with the second source.
With reference to any one in the third possible implementation of first aspect to first aspect, in the 4th kind of possibility
Implementation in, the conduction module includes：5th transistor and the 6th transistor；
The grid of the 5th transistor as the conduction module first control end, the 5th transistor
Source electrode is electrically connected with the drain electrode of the 6th transistor, and the drain electrode of the 5th transistor and the source electrode of the 6th transistor are electric
Connection, the grid of the 6th transistor as the conduction module the second control end, the source electrode of the 5th transistor with
The tie point of the drain electrode of the 6th transistor as the conduction module write-in end, the drain electrode of the 5th transistor and institute
State the 6th transistor source electrode tie point as the conduction module data terminal.
With reference to any one in the 4th kind of possible implementation of first aspect to first aspect, in the 5th kind of possibility
Implementation in, the read module includes：7th transistor and the 8th transistor；
The source electrode of the 7th transistor as the read module data terminal, the grid conduct of the 7th transistor
The reading end of the read module, the drain electrode of the 7th transistor is electrically connected with the drain electrode of the 8th transistor, and described
The source ground of the drain electrode of eight transistors, the grid of the 8th transistor as the read module control end.
A kind of second aspect, there is provided random access memory, including：Predetermined number such as the 5th of first aspect to first aspect
Plant any one the random access memory bit location in possible implementation.
The third aspect, there is provided a kind of electronic chip, it is characterised in that the electronic chip includes：
Random access memory as described in second aspect.
The embodiment of the present invention provides a kind of random access memory bit location, random access memory and electronic chip, the random storage
Device bit location include at least one power supply, the first write line, the second write line, write-in bit line, read line, read bit line,
Read module, asymmetric memory module and conduction module；Wherein, the data terminal of read module is electrically connected with bit line is read, and is read
The control end of modulus block is electrically connected with read line, and the reading end of read module electrically connects with the output end of asymmetric memory module；
The data terminal of conduction module is electrically connected with write-in bit line, and the first control end of conduction module is electrically connected with the first write line, is led
Second control end of logical module is electrically connected with the second write line, the input for writing end and asymmetric memory module of conduction module
Electrical connection；At least one power supply is electrically connected with the power supply interface of read module.Compared with prior art, the embodiment of the present invention is provided
Random access memory bit location in asymmetric memory module can improve the voltage margin of random access memory bit location, so as to
The reliability of random access memory bit location is enough improved, and prior art compares the double write-in bit lines for being used, and the present invention is real
Only one write-in bit line in the random access memory bit location of example offer is provided, power consumption can be reduced.
Brief description of the drawings
Technical scheme in order to illustrate more clearly the embodiments of the present invention, below will be in embodiment or description of the prior art
The required accompanying drawing for using is briefly described, it should be apparent that, drawings in the following description are only some realities of the invention
Example is applied, for those of ordinary skill in the art, on the premise of not paying creative work, can also be according to these accompanying drawings
Obtain other accompanying drawings.
A kind of structural representation of eight pipes SRAM bit location that Fig. 1 is provided for prior art；
Fig. 2 is a kind of structural representation of random access memory bit location provided in an embodiment of the present invention；
Fig. 3 is a kind of structural representation of random access memory bit location provided in an embodiment of the present invention；
Fig. 4 is the phase inverter connection effect of asymmetric memory module in random access memory bit location provided in an embodiment of the present invention
Fruit schematic diagram；
Fig. 5 is the structural representation of another random access memory bit location provided in an embodiment of the present invention；
Fig. 6 is the output voltage of asymmetric memory module in a kind of random access memory bit location provided in an embodiment of the present invention
Simulated effect figure compared to existing technology.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
The embodiment of the present invention provides a kind of random access memory bit location 1, as shown in Fig. 2 random access memory bit location 1 is wrapped
Include：
At least one power supply 11, the first write line 12, the second write line 13, write-in bit line 14, read line 15, reading ratio
Special line 16, read module 17, asymmetric memory module 18 and conduction module 19；
Wherein, the data terminal 171 of read module 17 is electrically connected with bit line 16 is read, the control end 172 of read module 17
Electrically connected with read line 15, the reading end 173 of read module 17 electrically connects with the output end 181 of asymmetric memory module 18；
The data terminal 191 of conduction module 19 is electrically connected with write-in bit line 14, the first control end 192 of conduction module 19 with
First write line 12 is electrically connected, and the second control end 193 of conduction module 19 is connected with the second write line electricity 13, conduction module 19
Write-in end 194 electrically connects with the input 182 of asymmetric memory module 18；
At least one power supply 11 is electrically connected with the power supply interface 183 of asymmetric memory module 18.
The embodiment of the present invention provides a kind of random access memory bit location, and the random access memory bit location includes at least one electricity
Source, the first write line, the second write line, write-in bit line, read line, reading bit line, read module, asymmetric memory module
And conduction module；Wherein, the data terminal of read module is electrically connected with bit line is read, control end and the read line electricity of read module
Connection, the reading end of read module electrically connects with the output end of asymmetric memory module；The data terminal of conduction module compares with write-in
Special line electrical connection, the first control end of conduction module is electrically connected with the first write line, second control end and second of conduction module
Write line is electrically connected, and the write-in end of conduction module electrically connects with the input of asymmetric memory module；At least one power supply and reading
The power supply interface electrical connection of modulus block.Compared with prior art, in random access memory bit location provided in an embodiment of the present invention
Asymmetric memory module can improve the voltage margin of random access memory bit location such that it is able to improve random access memory bit location
Reliability, and prior art compares double write-in bit lines for being used, random access memory provided in an embodiment of the present invention
Only one write-in bit line, can reduce power consumption in unit.
In order that those skilled in the art can be more clearly understood that technical scheme provided in an embodiment of the present invention, lead to below
Specific embodiment is crossed, a kind of random access memory bit location 2 provided in an embodiment of the present invention is described in detail, such as Fig. 3 institutes
Show, the random access memory bit location 2 includes：
At least one power supply 21, the first write line 22, the second write line 23, write-in bit line 24, read line 25, reading ratio
Special line 26, read module 27, asymmetric memory module 28 and conduction module 29；Second write line 23 is mutual for the first write line 22
Mend write line；
Wherein, the data terminal 271 of read module 27 is electrically connected with bit line 26 is read, the control end 272 of read module 27
Electrically connected with read line 25, the reading end 273 of read module 27 electrically connects with the output end 281 of asymmetric memory module 28；
The data terminal 291 of conduction module 29 is electrically connected with write-in bit line 24, the first control end 292 of conduction module 29 with
First write line 22 is electrically connected, and the second control end 293 of conduction module 29 is connected with the second write line electricity 23, conduction module 29
Write-in end 294 electrically connects with the input 282 of asymmetric memory module 28；
At least one power supply 21 is electrically connected with the power supply interface 283 of asymmetric memory module 28.
Wherein, as shown in figure 3, asymmetric memory module 28 includes：The first transistor M1, transistor seconds M2, the 3rd crystalline substance
Body pipe M3 and the 4th transistor M4.
The source ground of the first transistor M1, the grid of the first transistor M1 is electrically connected with the grid of transistor seconds M2,
The first transistor M1 drain electrodes are electrically connected with the drain electrode of transistor seconds M2, source electrode and the electricity of power supply interface 283 of transistor seconds M2
Connection；
The source ground of third transistor M3, the grid of third transistor M3 is electrically connected with the grid of the 4th transistor M4,
Third transistor M3 drain electrodes are electrically connected with the drain electrode of the 4th transistor M4, source electrode and the electricity of power supply interface 283 of the 4th transistor M4
Connection；
Above-mentioned the first transistor M1 and transistor seconds M2 constitutes the first phase inverter, third transistor M3 and the 4th transistor
M4 constitutes the second phase inverter, and the output end of the first phase inverter is electrically connected with the input of the second phase inverter, the second phase inverter
Output end is electrically connected with the input of the first phase inverter；Wherein, it is exemplary, the face of third transistor M3 and the 4th transistor M4
Area of the product much larger than the first transistor M1 and transistor seconds M2, such as W/L of third transistor M3 and the 4th transistor M4
It is 10 times of the first transistor M1 and W/L of transistor seconds M2（W/L is the width/height of transistor channel）, therefore second is anti-
Area of the area of phase device more than the first phase inverter.The annexation of the first phase inverter and the second phase inverter can be as shown in Figure 4.
Certainly, the multiple of the W/L of the W/L and the first transistor M1 and transistor seconds M2 of third transistor M3 and the 4th transistor M4 can
To be arranged as required to, including but not limited to this.
Wherein, the grid of the first transistor M1 and the input that the tie point of the grid of transistor seconds M2 is the first phase inverter
End, the drain electrode of the first transistor M1 and the output end that the tie point of the drain electrode of transistor seconds M2 is the first phase inverter；3rd is brilliant
The tie point of the grid of body pipe M3 and the grid of the 4th transistor M4 is the input of the second phase inverter, the leakage of third transistor M3
Pole and the output end that the tie point of the drain electrode of the 4th transistor M4 is the second phase inverter.
In addition, the grid of the first transistor M1 is asymmetric memory module 28 with the tie point of the grid of transistor seconds M2
Input 282, the tie point of drain electrode with the drain electrode of the 4th transistor M4 of third transistor M3 is asymmetric memory module 28
Output end 281.
As shown in figure 3, conduction module 29 includes：5th transistor M5 and the 6th transistor M6；
The grid of the 5th transistor M5 as conduction module 29 the first control end 292, the source electrode of the 5th transistor M5 with
The drain electrode electrical connection of the 6th transistor M6, the drain electrode of the 5th transistor M5 is electrically connected with the source electrode of the 6th transistor M6, and the 6th is brilliant
The grid of body pipe M6 as conduction module 29 the second control end 293, the source electrode of the 5th transistor M5 and the 6th transistor M6's
The tie point of drain electrode as conduction module 29 write-in end 294, drain electrode and the source electrode of the 6th transistor M6 of the 5th transistor M5
Tie point as conduction module 29 data terminal 291.
As shown in figure 3, read module 27 includes：7th transistor M7 and the 8th transistor M8；
The source electrode of the 7th transistor M7 as read module 27 data terminal 271, the grid of the 7th transistor M7 is used as reading
The reading end 273 of modulus block 27, the drain electrode of the 7th transistor M7 is electrically connected with the drain electrode of the 8th transistor M8, the 8th transistor M8
Drain electrode source ground, the grid of the 8th transistor M8 as read module 27 control end 272.
In addition, optional, the power supply interface 283 of asymmetric memory module 28 can both access a power supply, it is also possible to connect
Enter two power supplys, specifically, as shown in figure 3, to access schematic diagram of the power supply using single-voltage-supply cmos：
The electric contact of the source electrode of the source electrode of transistor seconds M2 and the 4th transistor M4 constitutes power supply interface 283, and power supply connects
Mouth 283 is electrically connected with a power supply 21.
Or, as shown in figure 5, to access the schematic diagram that two power supplys are powered using twin voltage：
The source electrode of transistor seconds M2 is electrically connected as the first power supply interface 283a and the first power supply 21a of power supply interface 283
Connect, the source electrode of the 4th transistor M is electrically connected as the second power supply interface 283b of power supply interface 283 with second source 21b.
It should be noted that random access memory bit location 2 also has three states, including：Hold mode, read operation and write
Enter operation, specific operation principle is as follows：
In hold mode, asymmetric memory module 28 is powered by VDD（Can also be multiple VDD）, the first write line 22
0 state, i.e., non-selected state are in the second write line 23.Equally, it is also non-selected for the transistor in conduction module 29
State, write-in bit line 24 is also low level, and read line 25 and reading bit line 26 are also all to be not powered on pressure condition.
In read operation, read line 25 increases level, i.e. 1 state first, and then the 8th transistor M8 is on shape
State.Due to the source ground of the 8th transistor M8, the drain electrode that now the 7th transistor M7 is connected with the 8th transistor M8 is in low
Level state.When the temporarily addition high level of bit line 26 is read, the second of the 4th transistor M4 and third transistor M3 compositions
Phase inverter（Big phase inverter）Output valve be connected to the grid of the 7th transistor M7, that is, control the conducting state of the 7th transistor M7.
When high level, the 7th transistor M7 is turned on then, and it is exactly low level to read the output of bit line 26, that is to say complementary state.If
When the output of second phase inverter is low level, the 7th transistor M7 is not turned on, then read bit line 26 then or high level state.
In write operation, the line of the first write line 22 carries out high level operation, meanwhile, the second write line 23 carries out low level
Operation.Since so, the 5th transistor M5 and the 6th transistor M6 all in opening, asymmetric memory module is write
The value for entering can carry out assignment transmission by writing 24 couples of the 5th transistor M5 and the 6th transistor M6 of bit line.
Further, as shown in fig. 6, being asymmetric memory module 28, relative to existing skill under 85%VDD supply voltages
The output voltage analogous diagram of the hold mode under eight pipe SRAM bit location 180nm techniques of art.
Wherein, X-axis and Y-axis represent the output electricity of end to end two phase inverters in random access memory bit location respectively
Pressure.Wherein, curve 1（Curve with triangle as node）With curve 2（Curve with ellipse as node）Represent asymmetric storage mould
Two output voltages of phase inverter of block 28（Wherein, curve 1 is the output voltage of the first phase inverter, and curve 2 is the second phase inverter
Output voltage）, curve 3 and curve 4 represent in eight pipe SRAM bit locations in the prior art two phase inverters
Output voltage.By curve 2 as can be seen that in the hold state, because the area of the second phase inverter expands, it can normal work
Voltage range is also significantly greater than two phase inverters in eight pipe SRAM bit locations in the prior art, it can be seen that this hair
The asymmetric memory module 28 of the use in bright embodiment enables to random access memory bit location in the stability of hold mode
It is improved.
In addition, as shown in figure 5, the asymmetric memory module 28 for being constituted with the phase inverter of asymmetric size herein is improved and kept
While reliability under state, supply voltage can also be separated, so as to realize low voltage power supply.Optionally, different process, no
With the phase inverter of size, and different size of threshold voltage can all influence be produced on the actual numerical value of lower power consumption.Such as, root
Understood according to Fig. 6, under the technique of 180nm, while random access memory bit location normal work is kept, VDD1 can be down to
93% VDD, VDD2 can be down to 91%VDD（VDD is default normal voltage）, so as to reduce power consumption.Also, according to double
Power voltage supply, in write operation, the first write line 22 and the second write line 23 can separate supply voltage to write line, so that
In the case of not influenceing normal work, the voltage of the first write line 22 and the second write line 23 can be reduced, it is exemplary, according to
Fig. 6 understands that the voltage of the first write line 22 and the second write line 23 can be reduced to 76%VDD, therefore, it is possible to reduce power consumption, together
When, the voltage for writing bit line can also be reduced, exemplary, can be reduced to 84.5%VDD.Meanwhile, institute compared to existing technology
The double write-in bit lines for using, only one write-in bit line, energy in random access memory bit location provided in an embodiment of the present invention
Enough reduce power consumption.Certainly, the present embodiment is the percentage that exemplary illustration voltage can be reduced, and does not represent Ben Fa
Bright beneficial effect is confined to the effect indicated by these numerical value.
Finally, with regard to reliability when reading, typically limited by reading static noise（Static Noise Margin,
SNM）Come what is weighed, optionally, can be by adjusting M1, M3, the size of M7 and M8 corresponding reads static noise improving its
Limit, the size of the 4th transistor M4 and third transistor M3 is greater than the 7th transistor M7 and the 8th transistor for not increasing size
The size of M8, so as to improve read when Read-SNM, that is, improve its reading when by property.
Therefore, in sum, compared with prior art, it is non-in random access memory bit location provided in an embodiment of the present invention
Symmetrical storage module can improve the voltage margin of random access memory bit location such that it is able to improve random access memory bit location
Reliability, and asymmetric memory module is as a result of asymmetric phase inverter, it is possible to realizing that twin voltage is powered such that it is able to
Supply voltage is reduced in the case where operation is not influenceed, power consumption can be saved, while in the case where twin voltage is powered, depositing at random
The power supply of reservoir bit location is also different from the power supply of write line, read line and bit line such that it is able to reduces write line and writes
The voltage for entering bit line saves power consumption, in addition, compared to existing technology compared to the double write-in bit lines for being used, the embodiment of the present invention
Only one write-in bit line, can further reduce power consumption in the random access memory bit location of offer.
The embodiment of the present invention also provides a kind of random access memory 3, and random access memory 3 includes：Predetermined number it is above-mentioned random
Memory bitcell 1 or random access memory bit location 2.
The embodiment of the present invention also provides a kind of electronic chip 4, and the electronic chip 4 includes above-mentioned random access memory 3.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although
The present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those within the art that：It still may be used
Modified with to the technical scheme described in foregoing embodiments, or equivalent is carried out to which part technical characteristic；
And these modification or replace, do not make appropriate technical solution essence depart from various embodiments of the present invention technical scheme spirit and
Scope.
Claims (7)
1. a kind of random access memory bit location, it is characterised in that the random access memory bit location includes：
At least one power supply, the first write line, the second write line, write-in bit line, read line, read bit line, read module,
Asymmetric memory module and conduction module；
Wherein, the data terminal of the read module is electrically connected with the reading bit line, the control end of the read module and institute
Read line electrical connection is stated, the reading end of the read module electrically connects with the output end of the asymmetric memory module；
The data terminal of the conduction module is electrically connected with said write bit line, the first control end of the conduction module with it is described
First write line is electrically connected, and the second control end of the conduction module is electrically connected with second write line, the conduction module
Write-in end electrically connected with the input of the asymmetric memory module；
At least one power supply is electrically connected with the power supply interface of the asymmetric memory module；
The asymmetric memory module includes：First phase inverter and the second phase inverter；The output end of first phase inverter and institute
The input electrical connection of the second phase inverter is stated, the output end of second phase inverter is electrically connected with the input of first phase inverter
Connect；
Wherein, the breadth length ratio of transistor is all higher than the breadth length ratio of transistor in first phase inverter in second phase inverter.
2. random access memory bit location according to claim 1, it is characterised in that
First phase inverter includes the first transistor and transistor seconds, and second phase inverter includes third transistor and the
Four transistors；
The source ground of the first transistor, the grid of the first transistor is electrically connected with the grid of the transistor seconds
Connect, the first transistor drain electrode is electrically connected with the drain electrode of the transistor seconds, the source electrode of the transistor seconds with it is described
Power supply interface is electrically connected；
The source ground of the third transistor, the grid of the third transistor is electrically connected with the grid of the 4th transistor
Connect, third transistor drain electrode is electrically connected with the drain electrode of the 4th transistor, the source electrode of the 4th transistor with it is described
Power supply interface is electrically connected；
Wherein, the grid of the first transistor and the tie point of the grid of the transistor seconds are first phase inverter
Input, the drain electrode of the first transistor and the output that the tie point of the drain electrode of the transistor seconds is first phase inverter
End；The grid of the third transistor and the input that the tie point of the grid of the 4th transistor is second phase inverter
End, the drain electrode of third transistor and the output end that the tie point of the drain electrode of the 4th transistor is second phase inverter；
The grid of the first transistor is the asymmetric memory module with the tie point of the grid of the transistor seconds
Input, the drain electrode of the third transistor is the asymmetric memory module with the tie point of the drain electrode of the 4th transistor
Output end.
3. random access memory bit location according to claim 2, it is characterised in that
When at least one power supply is a power supply, the source electrode of the source electrode of the transistor seconds and the 4th transistor
Electric contact constitute the power supply interface, the power supply interface and one power electric connection；
When at least one power supply includes the first power supply and second source, the source electrode of the transistor seconds is used as the confession
First power supply interface of electrical interface and first power electric connection, the source electrode of the 4th transistor is used as the power supply interface
The second power supply interface electrically connected with the second source.
4. the random access memory bit location according to claims 1 to 3 any one, it is characterised in that the conduction module
Including：5th transistor and the 6th transistor；
The grid of the 5th transistor as the conduction module first control end, the source electrode of the 5th transistor
Drain electrode with the 6th transistor is electrically connected, and drain electrode and the source electrode of the 6th transistor of the 5th transistor are electrically connected
Connect, the grid of the 6th transistor as the conduction module the second control end, the source electrode of the 5th transistor and institute
State the 6th transistor drain electrode tie point as the conduction module write-in end, the drain electrode of the 5th transistor with it is described
The tie point of the source electrode of the 6th transistor as the conduction module data terminal.
5. the random access memory bit location according to claims 1 to 3 any one, it is characterised in that the read module
Including：7th transistor and the 8th transistor；
The source electrode of the 7th transistor as the read module data terminal, the grid of the 7th transistor is used as described
The reading end of read module, the drain electrode of the 7th transistor is electrically connected with the drain electrode of the 8th transistor, and the described 8th is brilliant
The source ground of the drain electrode of body pipe, the grid of the 8th transistor as the read module control end.
6. a kind of random access memory, it is characterised in that the random access memory includes：Predetermined number such as claim 1 to 5 times
Random access memory bit location described in meaning one.
7. a kind of electronic chip, it is characterised in that the electronic chip includes：
Random access memory as claimed in claim 6.
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| CN201410145283.9A CN103928051B (en) | 2014-04-11 | 2014-04-11 | A kind of random access memory bit location, random access memory and electronic chip |
| PCT/CN2014/095322 WO2015154530A1 (en) | 2014-04-11 | 2014-12-29 | Random access memory bit cell, random access memory and electronic chip |
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| CN101999147A (en) * | 2009-05-25 | 2011-03-30 | 松下电器产业株式会社 | Semiconductor memory device |
| CN201918172U (en) * | 2011-01-24 | 2011-08-03 | 中国电子科技集团公司第五十八研究所 | Asymmetrical structure configured SRAM (static random access memory) applicable to FPGA (field programmable gate array) circuits |
| CN102467961A (en) * | 2010-11-09 | 2012-05-23 | 香港科技大学 | Static random access memory and method of controlling the same |
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| CN103489914B (en) * | 2012-06-12 | 2016-01-20 | 香港科技大学 | There is static random-access memory and the control method thereof of non-symmetric transistor |
| CN102779837B (en) * | 2012-08-15 | 2015-04-08 | 中国科学院上海微系统与信息技术研究所 | Six-transistor static random access memory unit and manufacturing method thereof |
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| CN101999147A (en) * | 2009-05-25 | 2011-03-30 | 松下电器产业株式会社 | Semiconductor memory device |
| CN102467961A (en) * | 2010-11-09 | 2012-05-23 | 香港科技大学 | Static random access memory and method of controlling the same |
| CN201918172U (en) * | 2011-01-24 | 2011-08-03 | 中国电子科技集团公司第五十八研究所 | Asymmetrical structure configured SRAM (static random access memory) applicable to FPGA (field programmable gate array) circuits |
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