CN103928051A - Random access memory bit cell, random access memory and electronic chip - Google Patents
Random access memory bit cell, random access memory and electronic chip Download PDFInfo
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- CN103928051A CN103928051A CN201410145283.9A CN201410145283A CN103928051A CN 103928051 A CN103928051 A CN 103928051A CN 201410145283 A CN201410145283 A CN 201410145283A CN 103928051 A CN103928051 A CN 103928051A
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- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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Abstract
The embodiment of the invention provides a random access memory bit cell, a random access memory and an electronic chip, belonging to the field of storages, and aiming at solving the problems of reliability and power consumption of the memory. The random access memory bit cell comprises at least one power supply, a first write-in wire, a second write-in wire, a write-in bit wire, a reading wire, a reading bit wire, a reading module, an asymmetrical storage module and a conduction module. The random access memory consists of the random access memory bit cells with preset number; the electronic chip comprises the random access memory. The reliability and the power consumption of the random access memory can be optimized.
Description
Technical field
The present invention relates to field of storage, relate in particular to a kind of random access memory bit location, random access memory and electronic chip.
Background technology
Along with the manufacturing lifting of electronic chip technique, transistor size enters accurate nanometer era, in electronic chip, transistorized integrated level is more and more higher, thereby there is the high performance chips that VLSI (very large scale integrated circuit) forms, the demand of this high performance chips has brought up the epoch of SOC (system on a chip) (System on Chip, SoC).
As shown in Figure 1, a kind of eight pipe static RAM (Static Random Access Memory conventional in prior art, SRAM) bit location (Bit Cell) structure, this type of static RAM determined bit position structure one has three states, be respectively: hold mode, reading state and write state.Wherein, write the conducting of line traffic control turn-on transistor, that is to say on-off action.Bit line is controlled the data mode of turn-on transistor, as 0 or 1, concrete:
When hold mode, M
1, M
2, M
3, M
4form two phase inverters of head and the tail Opposite direction connection, the storage unit consisting of these two phase inverters is powered by VDD, write lambda line in 0 state, it is non-selected state, for turn-on transistor, be also non-selected state (not conducting state) equally, read bit line and read line also all in low level state, i.e. non-selected state.
When reading state, read line first applies high level, that is to say selection mode, M
8be equal to conducting.Meanwhile, read bit line and temporarily apply of short duration high voltage, that is to say of short duration 1 state.The M of two phase inverters of storage unit
2with M
4be responsible for the state of its maintenance to control M
7conducting whether, thereby can be by M
8transistor is expressed its state value.
When write state, write lambda line in high level state, state 1, and meanwhile, two bit lines are in complementary state, a high level wherein, state 1, another root is low level, state 0.For example, during write storage unit 1, bit line is high level, and complementary bit line is low level; During write storage unit 0, bit line is low level, and complementary bit line is high level.
Because above-mentioned eight pipe static RAM have higher reliability and lower power consumption, so above-mentioned eight pipe static RAM are widely used in high performance chips, but along with chip volume constantly reduces, integrated level is more and more higher, when performance constantly promotes, its power consumption also more and more becomes the problem that needs special consideration in design.Particularly along with the remarkable rising of storer proportion on SoC chip, also day by day obvious for the high reliability of storer and the requirement of low-power consumption, for the reliability of storer and the optimization of power consumption, be therefore problem demanding prompt solution.
Summary of the invention
Embodiments of the invention provide a kind of random access memory bit location, random access memory and electronic chip, can improve the reliability of storer, and reduce power consumption of memory.
For achieving the above object, embodiments of the invention adopt following technical scheme:
First aspect, provides a kind of random access memory bit location, and described random access memory bit location comprises:
At least one power supply, first writes that lambda line, second is write lambda line, write bit line, read line, read bit line, read module, asymmetric memory module and conduction module;
Wherein, the data terminal of described read module with described in read bit line and be electrically connected to, the control end of described read module is electrically connected to described read line, the end that reads of described read module is electrically connected to the output terminal of described asymmetric memory module;
The data terminal of described conduction module is electrically connected to said write bit line, the first control end of described conduction module and described first is write lambda line and is electrically connected to, the second control end of described conduction module and described second is write lambda line and is electrically connected to, and the end that writes of described conduction module is electrically connected to the input end of described asymmetric memory module;
Described at least one power supply is electrically connected to the power supply interface of described read module.
In conjunction with first aspect, in the possible implementation of the first, described asymmetric memory module comprises: the first phase inverter and the second phase inverter; The output terminal of described the first phase inverter is electrically connected to the input end of described the second phase inverter, and the output terminal of described the second phase inverter is electrically connected to the input end of described the first phase inverter;
Wherein, the area of described the second phase inverter is greater than the area of described the first phase inverter.
In conjunction with the possible implementation of the first of first aspect, in the possible implementation of the second, described the first phase inverter comprises the first transistor and transistor seconds, and described the second phase inverter comprises the first transistor and transistor seconds;
The source ground of described the first transistor, the grid of described the first transistor is electrically connected to the grid of described transistor seconds, described the first transistor drain electrode is electrically connected to the drain electrode of described transistor seconds, and the source electrode of described transistor seconds is electrically connected to described power supply interface;
Described the 3rd transistorized source ground, described the 3rd transistorized grid is electrically connected to described the 4th transistorized grid, described the 3rd transistor drain is electrically connected to described the 4th transistorized drain electrode, and described the 4th transistorized source electrode is electrically connected to described power supply interface;
Wherein, the tie point of the grid of described the first transistor and the grid of described transistor seconds is the input end of described the first phase inverter, and the tie point of the drain electrode of the first transistor and the drain electrode of described transistor seconds is the output terminal of described the first phase inverter; The tie point of described the 3rd transistorized grid and described the 4th transistorized grid is the input end of described the second phase inverter, and the tie point of the 3rd transistorized drain electrode and described the 4th transistorized drain electrode is the output terminal of described the second phase inverter;
The tie point of the grid of described the first transistor and the grid of described transistor seconds is the input end of described asymmetric memory module, the output terminal that the tie point of described the 3rd transistorized drain electrode and described the 4th transistorized drain electrode is described asymmetric memory module.
In conjunction with the possible implementation of the second of first aspect, in the third possible implementation, when described at least one power supply is a power supply, the electric contact of the source electrode of described transistor seconds and described the 4th transistorized source electrode forms described power supply interface, and described power supply interface is electrically connected to a described power supply;
When described at least one power supply comprises the first power supply and second source, the source electrode of described transistor seconds is electrically connected to described the first power supply as the first power supply interface of described power supply interface, and described the 4th transistorized source electrode is electrically connected to described second source as the second power supply interface of described power supply interface.
In conjunction with first aspect, to any one in the third possible implementation of first aspect, in the 4th kind of possible implementation, described conduction module comprises: the 5th transistor and the 6th transistor;
Described the 5th transistorized grid is as described first control end of described conduction module, described the 5th transistorized source electrode is electrically connected to described the 6th transistorized drain electrode, described the 5th transistorized drain electrode is electrically connected to described the 6th transistorized source electrode, described the 6th transistorized grid is as the second control end of described conduction module, the tie point of described the 5th transistorized source electrode and described the 6th transistorized drain electrode is as the end that writes of described conduction module, the tie point of described the 5th transistorized drain electrode and described the 6th transistorized source electrode is as the data terminal of described conduction module.
In conjunction with first aspect, to any one in the 4th kind of possible implementation of first aspect, in the 5th kind of possible implementation, described read module comprises: the 7th transistor and the 8th transistor;
Described the 7th transistorized source electrode is as the data terminal of described read module, described the 7th transistorized grid is as the end that reads of described read module, described the 7th transistorized drain electrode is electrically connected to described the 8th transistorized drain electrode, the source ground of described the 8th transistorized drain electrode, described the 8th transistorized grid is as the control end of described read module.
Second aspect, provides a kind of random access memory, comprising: predetermined number if first aspect is to any one random access memory bit location in the 5th kind of possible implementation of first aspect.
The third aspect, provides a kind of electronic chip, it is characterized in that, described electronic chip comprises:
Random access memory as described in second aspect.
The embodiment of the present invention provides a kind of random access memory bit location, random access memory and electronic chip, and this random access memory bit location comprises that at least one power supply, first writes that lambda line, second is write lambda line, write bit line, read line, read bit line, read module, asymmetric memory module and conduction module; Wherein, the data terminal of read module is electrically connected to reading bit line, and the control end of read module is electrically connected to read line, and the end that reads of read module is electrically connected to the output terminal of asymmetric memory module; The data terminal of conduction module with write bit line and be electrically connected to, the first control end of conduction module and first is write lambda line and is electrically connected to, the second control end of conduction module and second is write lambda line and is electrically connected to, and the end that writes of conduction module is electrically connected to the input end of asymmetric memory module; At least one power supply is electrically connected to the power supply interface of read module.Compared with prior art, asymmetric memory module in the random access memory bit location that the embodiment of the present invention provides can improve the voltage margin of random access memory bit location, thereby can improve the reliability of random access memory bit location, and prior art is compared adopted two bit lines that write, in the random access memory bit location that the embodiment of the present invention provides, only have one to write bit line, can reduce power consumption.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of the embodiment of the present invention, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The structural representation of a kind of eight pipe static RAM bit locations that Fig. 1 provides for prior art;
The structural representation of a kind of random access memory bit location that Fig. 2 provides for the embodiment of the present invention;
The structural representation of a kind of random access memory bit location that Fig. 3 provides for the embodiment of the present invention;
In the random access memory bit location that Fig. 4 provides for the embodiment of the present invention, the phase inverter of asymmetric memory module connects effect schematic diagram;
The structural representation of the another kind of random access memory bit location that Fig. 5 provides for the embodiment of the present invention;
The output voltage of asymmetric memory module simulated effect figure compared to existing technology in a kind of random access memory bit location that Fig. 6 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of random access memory bit location 1, and as shown in Figure 2, random access memory bit location 1 comprises:
At least one power supply 11, first writes that lambda line 12, second is write lambda line 13, write bit line 14, read line 15, read bit line 16, read module 17, asymmetric memory module 18 and conduction module 19;
Wherein, the data terminal 171 of read module 17 is electrically connected to reading bit line 16, and the control end 172 of read module 17 is electrically connected to read line 15, and the end 173 that reads of read module 17 is electrically connected to the output terminal 181 of asymmetric memory module 18;
The data terminal 191 of conduction module 19 with write bit line 14 and be electrically connected to, first control end 192 and first of conduction module 19 is write lambda line 12 and is electrically connected to, second control end 193 and second of conduction module 19 is write lambda line electricity 13 and is connected, and the end 194 that writes of conduction module 19 is electrically connected to the input end 182 of asymmetric memory module 18;
At least one power supply 11 is electrically connected to the power supply interface 183 of asymmetric memory module 18.
The embodiment of the present invention provides a kind of random access memory bit location, and this random access memory bit location comprises that at least one power supply, first writes that lambda line, second is write lambda line, write bit line, read line, read bit line, read module, asymmetric memory module and conduction module; Wherein, the data terminal of read module is electrically connected to reading bit line, and the control end of read module is electrically connected to read line, and the end that reads of read module is electrically connected to the output terminal of asymmetric memory module; The data terminal of conduction module with write bit line and be electrically connected to, the first control end of conduction module and first is write lambda line and is electrically connected to, the second control end of conduction module and second is write lambda line and is electrically connected to, and the end that writes of conduction module is electrically connected to the input end of asymmetric memory module; At least one power supply is electrically connected to the power supply interface of read module.Compared with prior art, asymmetric memory module in the random access memory bit location that the embodiment of the present invention provides can improve the voltage margin of random access memory bit location, thereby can improve the reliability of random access memory bit location, and prior art is compared adopted two bit lines that write, in the random access memory bit location that the embodiment of the present invention provides, only have one to write bit line, can reduce power consumption.
In order to make those skilled in the art can more clearly understand the technical scheme that the embodiment of the present invention provides, below by specific embodiment, a kind of random access memory bit location 2 that the embodiment of the present invention is provided is elaborated, and as shown in Figure 3, this random access memory bit location 2 comprises:
At least one power supply 21, first writes that lambda line 22, second is write lambda line 23, write bit line 24, read line 25, read bit line 26, read module 27, asymmetric memory module 28 and conduction module 29; Second to write lambda line 23 be that lambda line is write in the first complementation of writing lambda line 22;
Wherein, the data terminal 271 of read module 27 is electrically connected to reading bit line 26, and the control end 272 of read module 27 is electrically connected to read line 25, and the end 273 that reads of read module 27 is electrically connected to the output terminal 281 of asymmetric memory module 28;
The data terminal 291 of conduction module 29 with write bit line 24 and be electrically connected to, first control end 292 and first of conduction module 29 is write lambda line 22 and is electrically connected to, second control end 293 and second of conduction module 29 is write lambda line electricity 23 and is connected, and the end 294 that writes of conduction module 29 is electrically connected to the input end 282 of asymmetric memory module 28;
At least one power supply 21 is electrically connected to the power supply interface 283 of asymmetric memory module 28.
Wherein, as shown in Figure 3, asymmetric memory module 28 comprises: the first transistor M1, transistor seconds M2, the 3rd transistor M3 and the 4th transistor M4.
The source ground of the first transistor M1, the grid of the first transistor M1 is electrically connected to the grid of transistor seconds M2, and the first transistor M1 drain electrode is electrically connected to the drain electrode of transistor seconds M2, and the source electrode of transistor seconds M2 is electrically connected to power supply interface 283;
The source ground of the 3rd transistor M3, the grid of the 3rd transistor M3 is electrically connected to the grid of the 4th transistor M4, and the 3rd transistor M3 drain electrode is electrically connected to the drain electrode of the 4th transistor M4, and the source electrode of the 4th transistor M4 is electrically connected to power supply interface 283;
Above-mentioned the first transistor M1 and transistor seconds M2 form the first phase inverter, the 3rd transistor M3 and the 4th transistor M4 form the second phase inverter, and the output terminal of the first phase inverter is electrically connected to the input end of the second phase inverter, the output terminal of the second phase inverter is electrically connected to the input end of the first phase inverter; Wherein, exemplary, the area of the 3rd transistor M3 and the 4th transistor M4 is much larger than the area of the first transistor M1 and transistor seconds M2, for example the W/L of the 3rd transistor M3 and the 4th transistor M4 is 10 times (width/height that W/L is transistor channel) of the W/L of the first transistor M1 and transistor seconds M2, therefore the area of the second phase inverter is greater than the area of the first phase inverter.The annexation of the first phase inverter and the second phase inverter can be as shown in Figure 4.Certainly, the multiple of the W/L of the W/L of the 3rd transistor M3 and the 4th transistor M4 and the first transistor M1 and transistor seconds M2 can arrange as required, includes but not limited to this.
Wherein, the tie point of the grid of the grid of the first transistor M1 and transistor seconds M2 is the input end of the first phase inverter, and the tie point of the drain electrode of the drain electrode of the first transistor M1 and transistor seconds M2 is the output terminal of the first phase inverter; The tie point of the grid of the grid of the 3rd transistor M3 and the 4th transistor M4 is the input end of the second phase inverter, and the tie point of the drain electrode of the drain electrode of the 3rd transistor M3 and the 4th transistor M4 is the output terminal of the second phase inverter.
In addition, the tie point of the grid of the grid of the first transistor M1 and transistor seconds M2 is that the drain electrode of input end 282, the three transistor M3 of asymmetric memory module 28 and the tie point of the drain electrode of the 4th transistor M4 are the output terminal 281 of asymmetric memory module 28.
As shown in Figure 3, conduction module 29 comprises: the 5th transistor M5 and the 6th transistor M6;
The grid of the 5th transistor M5 is as the first control end 292 of conduction module 29, the source electrode of the 5th transistor M5 is electrically connected to the drain electrode of the 6th transistor M6, the drain electrode of the 5th transistor M5 is electrically connected to the source electrode of the 6th transistor M6, the grid of the 6th transistor M6 is as the second control end 293 of conduction module 29, the tie point of the drain electrode of the source electrode of the 5th transistor M5 and the 6th transistor M6 holds the tie point of the drain electrode of 294, the five transistor M5 and the source electrode of the 6th transistor M6 as the data terminal 291 of conduction module 29 as writing of conduction module 29.
As shown in Figure 3, read module 27 comprises: the 7th transistor M7 and the 8th transistor M8;
The source electrode of the 7th transistor M7 is as the data terminal 271 of read module 27, the grid of the 7th transistor M7 holds 273 as reading of read module 27, the drain electrode of the 7th transistor M7 is electrically connected to the drain electrode of the 8th transistor M8, the source ground of the drain electrode of the 8th transistor M8, the grid of the 8th transistor M8 is as the control end 272 of read module 27.
In addition, optional, the power supply interface 283 of asymmetric memory module 28 both can access a power supply, also can access two power supplys, concrete, as shown in Figure 3, and for accessing the schematic diagram of single-voltage-supply cmos for a power acquisition:
The electric contact of the source electrode of the source electrode of transistor seconds M2 and the 4th transistor M4 forms power supply interface 283, and power supply interface 283 is electrically connected to a power supply 21.
Or, as shown in Figure 5, for accessing the schematic diagram of two power voltage supplies for two power acquisitions:
The source electrode of transistor seconds M2 is electrically connected to the first power supply 21a as the first power supply interface 283a of power supply interface 283, and the source electrode of the 4th transistor M is electrically connected to second source 21b as the second power supply interface 283b of power supply interface 283.
It should be noted that, random access memory bit location 2 also has three states, comprising: hold mode, read operation and write operation, and concrete principle of work is as follows:
When hold mode, asymmetric memory module 28 is by VDD power supply (can be also a plurality of VDD), and first writes lambda line 22 and second writes lambda line 23 in 0 state, i.e. non-selected state.Equally, for the transistor in conduction module 29, be also non-selected state, writing bit line 24 is also low level, read line 25 and to read bit line 26 be all also making alive state not.
When read operation, first read line 25 adds high level, i.e. 1 state, and then the 8th transistor M8 is in conducting state.Due to the source ground of the 8th transistor M8, the drain electrode that now the 7th transistor M7 is connected with the 8th transistor M8 is in low level state.When reading bit line 26 and temporarily add high level, the output valve of the second phase inverter that the 4th transistor M4 and the 3rd transistor M3 form (large phase inverter) is linked the grid of the 7th transistor M7, controls the conducting state of the 7th transistor M7.When high level,, reading bit line 26 outputs is exactly low level, that is to say complementary state in the 7th transistor M7 conducting.If when the second phase inverter output is low level, the 7th not conducting of transistor M7, reads 26 of bit lines or high level state.
When write operation, first writes lambda line 22 lines carries out high level operation, and meanwhile, second writes lambda line 23 carries out low level operation.Like this, the 5th transistor M5 and the 6th transistor M6 all in opening, the value that write asymmetric memory module can carry out assignment transmission by writing 24 couples of the 5th transistor M5 of bit line and the 6th transistor M6.
Further, as shown in Figure 6, be asymmetric memory module 28, under 85%VDD supply voltage, with respect to eight of prior art, manage the output voltage analogous diagram of the hold mode under static RAM bit location 180nm techniques.
Wherein, X-axis and Y-axis represent respectively the output voltage of end to end two phase inverters in random access memory bit location.Wherein, curve 1(be take the curve that triangle is node) and curve 2(take the curve that ellipse is node) represent asymmetric memory module 28 two phase inverters output voltage (wherein, curve 1 is the output voltage of the first phase inverter, curve 2 is output voltages of the second phase inverter), the output voltage of two phase inverters in eight pipe static RAM bit locations in curve 3 and curve 4 expression prior aries.By curve 2, can be found out, under hold mode, enlarged areas due to the second phase inverter, its voltage range that can normally work is also obviously greater than in prior art two phase inverters in eight pipe static RAM bit locations, and the asymmetric memory module 28 of the employing in the embodiment of the present invention can make random access memory bit location be improved in the stability of hold mode as can be seen here.
In addition, as shown in Figure 5, in the reliability that the asymmetric memory module 28 forming at this phase inverter by asymmetric size improves under hold mode, all right separated supply voltage, thus realize low voltage power supply.Optionally, different process, the phase inverter of different sizes, and the threshold voltage of different sizes all can exert an influence to the actual numerical value of power-dissipation-reduced.Such as, known according to Fig. 6, under the technique of 180nm, when keeping the normal work of random access memory bit location, VDD1 can be down to 93% VDD, and it is default normal voltage that VDD2 can be down to 91%VDD(VDD), thereby reduced power consumption.And, if adopt two power voltage supplies, write lambda line when write operation, first write lambda line 22 and second write lambda line 23 can separated supply voltage, thereby in the situation that not affecting normal work, can reduce by first and write the voltage that lambda line 22 and second is write lambda line 23, exemplary, known according to Fig. 6, first writes lambda line 22 and second writes the voltage of lambda line 23 and can be reduced to 76%VDD, therefore can reduce power consumption, simultaneously, the voltage that writes bit line also can reduce, exemplary, can be reduced to 84.5%VDD.Meanwhile, what adopted compared to existing technology two writes bit line, in the random access memory bit location that the embodiment of the present invention provides, only has one to write bit line, can reduce power consumption.Certainly, the present embodiment is the exemplary number percent that voltage can reduce that illustrates, and does not represent that beneficial effect of the present invention is confined to the indicated effect of these numerical value.
Finally, reliability when reading, normally by reading static noise limit (Static Noise Margin, SNM) weigh, optional, can be by adjusting M1, M3, the size of M7 and M8 improves it and reads accordingly static noise limit, the size of the 4th transistor M4 and the 3rd transistor M3 is greater than does not increase the 7th transistor M7 of size and the size of the 8th transistor M8, thereby has improved the Read-SNM when reading, and when namely having improved it and reading, leans on property.
Therefore, in sum, compared with prior art, asymmetric memory module in the random access memory bit location that the embodiment of the present invention provides can improve the voltage margin of random access memory bit location, thereby can improve the reliability of random access memory bit location, and asymmetric memory module is owing to having adopted asymmetric phase inverter, so can realize two power voltage supplies, thereby the situation decline low suppling voltage of operation can not affected, can save power consumption, simultaneously the in the situation that of two power voltage supply, the power supply of random access memory bit location with write lambda line, the power supply of read line and bit line is also different, thereby can reduce the voltage saving power consumption of writing lambda line and writing bit line, in addition, compare compared to existing technology adopted two bit lines that write, in the random access memory bit location that the embodiment of the present invention provides, only have one to write bit line, can further reduce power consumption.
The embodiment of the present invention also provides a kind of random access memory 3, and random access memory 3 comprises: above-mentioned random access memory bit location 1 or the random access memory bit location 2 of predetermined number.
The embodiment of the present invention also provides a kind of electronic chip 4, and this electronic chip 4 comprises above-mentioned random access memory 3.
Finally it should be noted that: above embodiment only, in order to technical scheme of the present invention to be described, is not intended to limit; Although the present invention is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (8)
1. a random access memory bit location, is characterized in that, described random access memory bit location comprises:
At least one power supply, first writes that lambda line, second is write lambda line, write bit line, read line, read bit line, read module, asymmetric memory module and conduction module;
Wherein, the data terminal of described read module with described in read bit line and be electrically connected to, the control end of described read module is electrically connected to described read line, the end that reads of described read module is electrically connected to the output terminal of described asymmetric memory module;
The data terminal of described conduction module is electrically connected to said write bit line, the first control end of described conduction module and described first is write lambda line and is electrically connected to, the second control end of described conduction module and described second is write lambda line and is electrically connected to, and the end that writes of described conduction module is electrically connected to the input end of described asymmetric memory module;
Described at least one power supply is electrically connected to the power supply interface of described asymmetric memory module.
2. random access memory bit location according to claim 1, is characterized in that, described asymmetric memory module comprises: the first phase inverter and the second phase inverter; The output terminal of described the first phase inverter is electrically connected to the input end of described the second phase inverter, and the output terminal of described the second phase inverter is electrically connected to the input end of described the first phase inverter;
Wherein, the area of described the second phase inverter is greater than the area of described the first phase inverter.
3. random access memory bit location according to claim 2, is characterized in that,
Described the first phase inverter comprises the first transistor and transistor seconds, and described the second phase inverter comprises the 3rd transistor and the 4th transistor;
The source ground of described the first transistor, the grid of described the first transistor is electrically connected to the grid of described transistor seconds, described the first transistor drain electrode is electrically connected to the drain electrode of described transistor seconds, and the source electrode of described transistor seconds is electrically connected to described power supply interface;
Described the 3rd transistorized source ground, described the 3rd transistorized grid is electrically connected to described the 4th transistorized grid, described the 3rd transistor drain is electrically connected to described the 4th transistorized drain electrode, and described the 4th transistorized source electrode is electrically connected to described power supply interface;
Wherein, the tie point of the grid of described the first transistor and the grid of described transistor seconds is the input end of described the first phase inverter, and the tie point of the drain electrode of the first transistor and the drain electrode of described transistor seconds is the output terminal of described the first phase inverter; The tie point of described the 3rd transistorized grid and described the 4th transistorized grid is the input end of described the second phase inverter, and the tie point of the 3rd transistorized drain electrode and described the 4th transistorized drain electrode is the output terminal of described the second phase inverter;
The tie point of the grid of described the first transistor and the grid of described transistor seconds is the input end of described asymmetric memory module, the output terminal that the tie point of described the 3rd transistorized drain electrode and described the 4th transistorized drain electrode is described asymmetric memory module.
4. random access memory bit location according to claim 3, is characterized in that,
When described at least one power supply is a power supply, the electric contact of the source electrode of described transistor seconds and described the 4th transistorized source electrode forms described power supply interface, and described power supply interface is electrically connected to a described power supply;
When described at least one power supply comprises the first power supply and second source, the source electrode of described transistor seconds is electrically connected to described the first power supply as the first power supply interface of described power supply interface, and described the 4th transistorized source electrode is electrically connected to described second source as the second power supply interface of described power supply interface.
5. according to the random access memory bit location described in claim 1 to 4 any one, it is characterized in that, described conduction module comprises: the 5th transistor and the 6th transistor;
Described the 5th transistorized grid is as described first control end of described conduction module, described the 5th transistorized source electrode is electrically connected to described the 6th transistorized drain electrode, described the 5th transistorized drain electrode is electrically connected to described the 6th transistorized source electrode, described the 6th transistorized grid is as the second control end of described conduction module, the tie point of described the 5th transistorized source electrode and described the 6th transistorized drain electrode is as the end that writes of described conduction module, the tie point of described the 5th transistorized drain electrode and described the 6th transistorized source electrode is as the data terminal of described conduction module.
6. according to the random access memory bit location described in claim 1 to 5 any one, it is characterized in that, described read module comprises: the 7th transistor and the 8th transistor;
Described the 7th transistorized source electrode is as the data terminal of described read module, described the 7th transistorized grid is as the end that reads of described read module, described the 7th transistorized drain electrode is electrically connected to described the 8th transistorized drain electrode, the source ground of described the 8th transistorized drain electrode, described the 8th transistorized grid is as the control end of described read module.
7. a random access memory, is characterized in that, described random access memory comprises: the random access memory bit location as described in claim 1 to 6 any one of predetermined number.
8. an electronic chip, is characterized in that, described electronic chip comprises:
Random access memory as claimed in claim 7.
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| CN201410145283.9A CN103928051B (en) | 2014-04-11 | 2014-04-11 | A kind of random access memory bit location, random access memory and electronic chip |
| PCT/CN2014/095322 WO2015154530A1 (en) | 2014-04-11 | 2014-12-29 | Random access memory bit cell, random access memory and electronic chip |
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| WO2015154530A1 (en) * | 2014-04-11 | 2015-10-15 | 华为技术有限公司 | Random access memory bit cell, random access memory and electronic chip |
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