WO2014026458A1

WO2014026458A1 - Six-transistor static random access memory unit and manufacturing method thereof

Info

Publication number: WO2014026458A1
Application number: PCT/CN2012/087700
Authority: WO
Inventors: 陈静; 伍青青; 罗杰馨; 柴展; 余涛; 王曦
Original assignee: 中国科学院上海微系统与信息技术研究所
Priority date: 2012-08-15
Filing date: 2012-12-27
Publication date: 2014-02-20
Also published as: CN102779837A; CN102779837B

Abstract

The present invention relates to the technical field of memory design and manufacturing. Provided are a six-transistor static random access memory unit and manufacturing method thereof, the memory unit comprising two phase-inverters and a transmission gate; each phase-inverter consists of a structurally symmetric NMOS transistor and a structurally symmetric PMOS transistor connected to each other; the transmission gate consists of two NMOS transistors having asymmetric source and drain structures; the source structure of the NMOS transistor having asymmetric source and drain structures is provided with a pocket region and a lightly doped drain (LDD) region, and the drain structure is not provided with a pocket region or an LDD region. The present invention employs a transmission gate N-type transistor having an asymmetric structure, and eliminates the asymmetry caused by the LDD region and the pocket region of the drain without changing device processing technique, additionally increasing the layout size, or reducing the service life of a device, thus achieving electrical asymmetry obviously superior to the existing structures. The present invention has a simple process and reduced cost, and is suitable for industrial production.

Description

Six-transistor static random access memory unit and manufacturing method thereof

Technical field

The invention belongs to the technical field of memory design and manufacturing, and in particular relates to a six-transistor static random access memory unit and a manufacturing method thereof. Background technique

The memory is divided into flash memory (DRAM), dynamic random access memory (DRAM) and static random access memory (SRAM). The static random access memory is the first choice for critical system memory modules, such as CPU and Cache between main memory, etc. Although static memory has a larger footprint than other memories at the same storage capacity, it cannot be replaced by other new memories in the case of fast read and write.

At present, the commonly used static random access memory cells mainly adopt a six-transistor type, and are composed of two pull-up P-type transistors, two pull-down N-type transistors, and two transfer gate N-type transistors. The word line controls the switches of the two transfer gate N-type transistors, which are written or read by the bit lines to store data. When designing a six-transistor static random access memory cell, it is necessary to consider both the memory signal strength (ie, the magnitude of the read current) and the read and write stability of the memory. After the sub-100nm process, write failure has become the main cause of static memory failure. Therefore, how to enhance the write stability of static random access memory cells has always been a major consideration for memory designers.

In the case of SRAM read and write operations, the conductivity requirements of the two pass gate N-type transistors are different. During the read operation, the current flows from the drain to the source. In order not to destroy the signal, the conductivity of the N-type transistor is required to be relatively weak. In the write operation, the current flows from the source to the drain, in order to ensure stability. Writing a signal requires two transmission gates. The N-type transistor has a relatively high conductivity. Therefore, from the device itself, the transmission gate N-type transistor needs to be made a source-drain asymmetric structure. At present, some asymmetric structures have been proposed, including asymmetric Halo process, oblique injection Halo process, asymmetric Spacer process and electrical stress leading to asymmetry, etc. These programs or process changes, or the degree of asymmetry is not enough, or the device Its own service life has an impact. In view of this, in order to enhance the write stability of a six-transistor static random access memory cell, the present invention proposes a novel memory structure using a novel asymmetric transfer gate N-type transistor, which ensures that the existing process is not changed and the device lifetime is not affected. Under the premise, it will cause obvious asymmetry as much as possible, so as to effectively enhance the stability of the write operation of the static random access memory unit. Summary of the invention

In view of the above disadvantages of the prior art, an object of the present invention is to provide a six-transistor static random access memory cell and a method for fabricating the same, which are used to solve the problem that the six-transistor static random access memory cell in the prior art is not highly asymmetric. Write instability, or to increase the device's asymmetry, resulting in a shortened device lifetime.

To achieve the above and other related objects, the present invention provides a six-transistor static random access memory unit, the memory unit comprising at least:

a first inverter, comprising a first PMOS transistor and a first NMOS transistor;

a second inverter, comprising a second PMOS transistor and a second NMOS transistor;

The transmission gate is composed of a third NMOS transistor and a fourth NMOS transistor;

The source of the third NMOS transistor is simultaneously connected to the output end of the first inverter and the input end of the second inverter, the gate is connected to the word line of the memory, and the drain is connected to the bit line of the memory. ;

The source of the fourth NMOS transistor is simultaneously connected to the input end of the first inverter and the output end of the second inverter, the gate is connected to the word line of the memory, and the drain line is connected to the bit line of the memory;

The source structures of the third NMOS transistor and the fourth NMOS transistor have a pocket region and a shallow doped extension region, and the drain structure has no pocket region and a shallow doped extension region.

In the six-transistor static random access memory cell of the present invention, at the same voltage, the current flowing from the drain to the source of the third NMOS transistor and the fourth NMOS transistor is smaller than the current flowing from the source to the drain.

In the six-transistor static random access memory cell of the present invention, the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are all transistors having a source-drain structure symmetrical.

In the six-transistor static random access memory cell of the present invention, the fabrication substrate of the six-transistor static random access memory cell is a bulk silicon substrate or a silicon-on-insulator substrate.

The present invention also provides a method for fabricating a six-transistor static random access memory cell, the method of fabrication comprising at least the following steps:

1) providing a semiconductor substrate, and defining an active region in the semiconductor substrate, forming a shallow trench isolation trench around the active region;

2) forming an N-type well implant region in the semiconductor substrate by an ion implantation process according to a position of the active region, and forming a first P-type well implant region and a second P on both sides of the N-type well implant region Type well injection zone;

3) forming a first NMOS transistor and a third NMOS transistor in the first P-type well implant region, and forming a first PMOS transistor and a second PMOS transistor in the N-type well implant region, in the second P a second NMOS transistor and a fourth NMOS transistor are formed in the well-well region, wherein the source and drain structures of the first and second NMOS transistors, the first and second PMOS transistors each have a pocket region and a shallow doped extension region The source structure of the third and fourth NMOS transistors has a pocket region and a shallow doped extension region, and the drain structure does not have a pocket region and a shallow doped extension region; 4) Make a metal connection to complete the production of the storage unit.

In the method for fabricating the six-transistor static random access memory cell of the present invention, the step 3) includes the steps: 3-

1) forming a first gate across the first P-type well implant region and the N-type well implant region, and a second gate across the N-well implant region and the second P-type well implant region, Forming a third gate and a fourth gate at predetermined positions of the first P-type well implant region and the second P-type well implant region; 3-2) fabricating a mask and performing the first ion implantation, Forming first and second NMOS transistors, pocket regions of the source and drain structures of the first and second PMOS transistors, and shallow doping extension regions, and forming a pocket region of the source structures of the third and fourth NMOS transistors and shallow doping An extension region; 3-3) forming sidewall structures on the first, second, third, and fourth gates, respectively, and then forming first, second, third, and fourth NMOS transistors by using a self-aligned process; a source and a drain of the first and second PMOS transistors, wherein the first NMOS transistor and the first PMOS transistor share a first gate, and the second NMOS transistor and the second PMOS transistor share a first Two grids.

In the method of fabricating the six-transistor static random access memory cell of the present invention, the drain of the first NMOS transistor is shared with the source of the third NMOS transistor, and the drain of the second NMOS transistor and the fourth The sources of the NMOS transistors are shared.

In the step 4) of the method for fabricating the six-transistor static random access memory cell of the present invention, the first NMOS transistor and the first PMOS transistor are interconnected to form a first inverter, and the second NMOS transistor and the The second PMOS transistors are interconnected to form a second inverter, and the source of the third NMOS transistor is simultaneously connected to the output of the first inverter and the input of the second inverter, and the gate is connected. a word line of the memory, a drain connected to the bit line of the memory, a source of the fourth NMOS transistor being simultaneously connected to an input end of the first inverter and an output end of the second inverter, the gate connection memory The word line, the bit line of the drain connection memory is not.

In the method of fabricating the six-transistor static random access memory cell of the present invention, the semiconductor substrate is a bulk silicon substrate or a silicon-on-insulator substrate.

As described above, the six-transistor static random access memory cell of the present invention and the method for fabricating the same have the following beneficial effects: the memory cell includes two inverters and a transfer gate, and the inverter comprises a symmetrical NMOS transistor and The structure is composed of symmetrical PMOS transistor interconnections, and the transmission gate is composed of two NMOS transistors whose source/drain structure is asymmetric, and the source structure of the source-drain structure asymmetric NMOS transistor has a pocket region and a shallow doped extension region, and The drain structure does not have a pocket region and a shallow doped extension region. The invention adopts a transmission gate N-type transistor with an asymmetric structure, and the asymmetry introduced by removing the shallow doped extension region (LDD) and the pocket of the drain does not change the processing technology of the device, and does not add an additional layout. The device lifetime is not compromised, and the resulting electrical asymmetry is significantly better than existing structures. The invention has simple process, is beneficial to reduce cost, and is suitable for industrial production. DRAWINGS

1 is a schematic diagram showing the circuit principle of a six-transistor static random access memory cell of the present invention.

2 is a schematic view showing the structure of a symmetrical MOS transistor of a six-transistor static random access memory cell of the present invention. 3 is a schematic diagram showing the structure of an NMOS transistor in which the source-drain structure of the six-transistor static random access memory cell of the present invention is asymmetric.

Figure 4 is a schematic diagram showing the structure of a method for fabricating a six-transistor static random access memory cell of the present invention.

Figure 5 is a block diagram showing the structure presented in the step 2) of the method for fabricating a six-transistor static random access memory cell of the present invention.

6 to 7 are schematic diagrams showing the structure presented in the step 3) of the method for fabricating the six-transistor static random access memory cell of the present invention.

Figure 8 is a diagram showing the electrical characteristics of a six-transistor static random access memory cell of the present invention. Component label description

10 first inverter

101 first PMOS transistor

102 first NMOS transistor

11 second inverter

111 second PMOS transistor

112 second NMOS transistor

12 third NMOS transistor

13 fourth NMOS transistor

141 Storage Node Q

142 storage node Q_Bar

20a, 20b 20c and 20d active areas

21 first P-well injection region

22 N-well injection zone

23 second P-well injection region

103 first grid 131 fourth grid embodiment

The embodiments of the present invention are described below by way of specific specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The invention may be practiced or applied in various other specific embodiments, and the details of the invention may be variously modified or changed without departing from the spirit and scope of the invention.

Please refer to Figure 1 to Figure 8. It should be noted that the illustrations provided in this embodiment merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, instead of the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component's type, number and proportion can be a random change, and its component layout can be more complicated. Example 1

As shown in FIG. 1 to FIG. 3, the present invention provides a six-transistor static random access memory unit, the memory unit including at least:

The first inverter 10 is composed of a first PMOS transistor 101 and a first NMOS transistor 102;

The second inverter 11 is composed of a second PMOS transistor 111 and a second NMOS transistor 112;

The transmission gate is composed of a third NMOS transistor 12 and a fourth NMOS transistor 13;

The source of the third NMOS transistor 12 is simultaneously connected to the output end of the first inverter 10 and the input end of the second inverter 11, the gate is connected to the word line of the memory, and the drain is connected to the memory. Bit line

The source of the fourth NMOS transistor 13 is simultaneously connected to the input end of the first inverter 10 and the output end of the second inverter 11, the gate is connected to the word line of the memory, and the drain is connected to the bit of the memory. Line not

The source structures of the third NMOS transistor 12 and the fourth NMOS transistor 13 have a pocket region and a shallow doped extension region, and the drain structure has no pocket region and a shallow doped extension region. That is, the third NMOS transistor 12 and the fourth NMOS transistor 13 have a source-drain asymmetric structure, and the effect is that the third NMOS transistor 12 and the fourth NMOS transistor 13 are from the drain to the source at the same voltage. The current flowing out is less than the current flowing from the source to the drain.

In this embodiment, the sources of the first PMOS transistor 101 and the second PMOS transistor 111 are connected to the power supply VDD, and the drains are respectively connected to the drains of the first NMOS transistor 102 and the second NMOS transistor 112, as a reverse The output end of the phase device, the gates of the first PMOS transistor 101 and the second PMOS transistor 111 respectively An NMOS transistor 102 and a second NMOS transistor 112 are connected to each other as an input terminal of the inverter, and the sources of the first NMOS transistor 102 and the second NMOS transistor 112 are grounded to implement the first inverter 10 and The function of the second inverter 11.

In this embodiment, the first PMOS transistor 101, the second PMOS transistor 111, the first NMOS transistor 102, and the second NMOS transistor 112 are all transistors having a source-drain structure symmetrical; of course, in other embodiments, The structure of the first PMOS transistor 101, the second PMOS transistor 111, the first NMOS transistor 102, and the second NMOS transistor 112 can be changed as needed, and only the normal operation of the inverter is required.

In this embodiment, the fabrication substrate of the six-transistor static random access memory cell is a bulk silicon substrate or a silicon-on-insulator substrate. Of course, in other embodiments, the fabrication substrate of the six-transistor static random access memory cell may also be any desired substrate such as a germanium substrate, a silicon germanium substrate or a silicon carbide substrate.

Now, the write data "0" of the six-transistor static random access memory cell of the present invention is taken as an example to describe the write phase of data: when the word line WL is active high, the third NMOS transistor 12 of the transfer gate is omitted. Both PG1) and the fourth NMOS transistor 13 (hereinafter hereinafter omitted as PG2) are turned on, and the write data "0" is changed to "0" and "1" by the write circuit to be loaded to the bit line (BL) and the bit line, respectively. On (BL_bar), the storage nodes Q141 and Q_Barl42 are finally brought to the state "0" and the state "1". Since the transmission gate transistor has strong reverse conduction capability, the voltage division at both ends is also small, so that the state "0" potential of the storage node Q141 can be sufficiently low without causing the memory cell state to be inverted, that is, the stability of the write state is ensured. ;

Now, the readout phase of the data is described by taking the read data "0" of the six-transistor static random access memory cell of the present invention as an example: the bit line (BL) and the bit line non (BL_bar) are first pre-pulled to a high potential, and then The word line WL is active high, and the transfer gate NMOS transistors PG1 and PG2 are both on. Since the storage node Q141 is at a low potential at this time, the bit line (BL) is charged to the storage node Q141 through the turned-on PG1, and the Q potential is raised. , and the bit line BL potential drops, by sensing the potential difference between the two bit lines, that is, the readable data "0". Since the transmission gate transistor has a weak forward conduction capability, the voltage division at both ends is also large, so that the state of the Q point "0" potential is not excessively pulled up, causing the memory cell state to be reversed, that is, the read state is stabilized. Sex. Example 2

Referring to FIG. 2 to FIG. 3 and FIG. 4 to FIG. 7 , the method for fabricating a six-transistor static random access memory cell is provided. The manufacturing method includes at least the following steps:

As shown in FIG. 4, step 1) is first performed to provide a semiconductor substrate, and active regions 20a, 20b, 20c, and 20d are defined in the semiconductor substrate, and shallow trenches are formed around the active region. Isolation slot (not shown); specifically, predetermined The active regions 20a, 20b, 20c, and 20d are defined, and then shallow trenches are etched around the active regions, and finally the shallow trenches are filled with an insulating material to form the shallow trench isolation trenches. In this embodiment, the semiconductor substrate is a bulk silicon substrate or a silicon-on-insulator substrate, and the insulating material is silicon dioxide.

As shown in FIG. 5, step 2) is then performed to form an N-type well implant region 22 in the semiconductor substrate by an ion implantation process according to the positions of the active regions 20a, 20b, 20c, and 20d, and in the N-type A first P-type well implant region 21 and a second P-type well implant region 23 are formed on both sides of the well implant region 22, wherein the N-type well implant region 22 is used to prepare the first PMOS transistor 101 and the second PMOS transistor 111. The first P-type well implant region 21 is used to prepare a first NMOS transistor 102 and a third NMOS transistor 12, and the second P-type well implant region 23 is used to prepare a second NMOS transistor 112 and a fourth NMOS transistor 13. . In this embodiment, the P-type ions are boron and the N-type ions are phosphorus.

As shown in FIG. 2 to FIG. 3 and FIG. 6 to FIG. 7 , step 3) is followed to form a first NMOS transistor 102 and a third NMOS transistor 12 in the first P-type well implant region 21 to be implanted in the N-type well. a first PMOS transistor 101 and a second PMOS transistor 111 are formed in the region 22, and a second NMOS transistor 112 and a fourth NMOS transistor 13 are formed in the second P-type well implant region 23, wherein the first and second The source and drain structures 307, 308 of the NMOS transistors 102, 112, the first and second PMOS transistors 101, 111 each have a pocket region and shallow doped extension regions 302, 303, 304, 305, the third and fourth NMOS The source structure 407 of the transistors 12, 13 has a pocket region 402 and a shallow doped extension region 404, and the drain structure 408 has no pocket regions and shallow doped extension regions.

In this embodiment, the step 3) includes the steps of:

3-1) forming a first gate 103 spanning the first P-type well implant region 21 and the N-type well implant region 22, and across the N-type well implant region 22 and the second P-type well implant region a second gate 113 of 23, and a third gate 121 and a fourth gate 131 are formed at predetermined positions of the first P-type well implant region 21 and the second P-type well implant region 23;

3-2) fabricating a mask and performing a first ion implantation to form a pocket region of the source-drain structure of the first NMOS transistor 102, the second NMOS transistor 112, the first PMOS transistor 101, and the second PMOS transistor 111, and shallow doping a hetero-extension region, and forming a pocket region of the source structure of the third NMOS transistor 12 and the fourth NMOS transistor 13 and a shallow doped extension region;

3-3) forming sidewall structures 306, 406 on the first, second, third, and fourth gates 103, 113, 121, and 131, respectively, and then forming the first, second, and second by using a self-alignment process Third, the fourth NMOS transistors 102, 112, 12, 13 and the first and second PMOS transistors 101, 111 of the source and drain 307, 308, 407, 408, wherein the first NMOS transistor 102 and the The first PMOS transistor 101 shares the first gate 103, and the second NMOS transistor 112 and the second PMOS transistor 111 share the second gate 113. In this embodiment, the first The drain of one NMOS transistor 102 is shared with the source of the third NMOS transistor 12, and the drain of the second NMOS transistor 112 is shared with the source of the fourth NMOS transistor 13. The structures of the first and second PMOS transistors 101 and 111 and the first and second NMOS transistors 102 and 112 are as shown in FIG. 2, and the structures of the third and fourth NMOS transistors 12 and 13 are as shown in FIG. .

Finally, step 4) is made of metal wiring to complete the fabrication of the memory unit.

Specifically, the first NMOS transistor 102 and the first PMOS transistor 101 are interconnected to form a first inverter 10, and the second NMOS transistor 112 and the second PMOS transistor 111 are interconnected to form a second reverse. The phase of the third NMOS transistor 12 is simultaneously connected to the output end of the first inverter 10 and the input end of the second inverter 11, the gate is connected to the word line of the memory, and the drain Connecting a bit line of the memory, the source of the fourth NMOS transistor 13 is simultaneously connected to the input end of the first inverter 10 and the output end of the second inverter 11, and the gate is connected to the word line of the memory, The bit line of the drain connection memory is not.

The process steps of the method for fabricating the six-transistor static random access memory cell of the present invention are identical to those of the prior art, and there is no additional layout expenditure, and the purpose of enhancing the stability of read and write operations of the memory cell is achieved in the most economical manner.

Figure 8 shows the transfer characteristics of a six-transistor static random access memory cell of the present invention, wherein forward current 501 is defined as being from the drain to the source, and reverse current 502 is defined as being from the source to the drain. It can be seen that by removing the drain-doped extension LDD and the pocket Pocket, very significant asymmetry results can be achieved. Since there is no drain LDD, when the device is in forward operation (ie, write operation), hot carriers generated by impact ionization cannot be injected into the gate oxide and can only be injected into the sidewall wall, thereby weakening the stress damage of the device and prolonging the The life of the device.

In summary, in the six-transistor static random access memory cell of the present invention and the method of fabricating the same, the memory cell includes two inverters and a transfer gate, the inverter is symmetrical by a structurally symmetric NMOS transistor and structure The PM0S transistor is composed of an interconnection, the transmission gate is composed of two source-drain structure asymmetric NMOS transistors, and the source-drain structure asymmetric NMOS transistor has a source structure with a pocket region and a shallow doped extension region, and the drain The pole structure does not have a pocket and a shallow doped extension. The invention adopts a transmission gate N-type transistor with an asymmetric structure, and the asymmetry introduced by removing the shallow doped extension region (LDD) and the pocket region (Pocket) of the drain does not change the processing technology of the device, and does not add an additional layout. The device lifetime is not compromised, and the resulting electrical asymmetry is significantly better than existing structures. The invention has simple process, is beneficial to reduce cost, and is suitable for industrial production. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above-described embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications or variations of the above-described embodiments may be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, All equivalent modifications or changes made by those skilled in the art without departing from the spirit and scope of the invention will be covered by the appended claims.

Claims

The present invention provides a six-transistor static random access memory unit, wherein the memory unit comprises at least:

The source structures of the third NMOS transistor and the fourth NMOS transistor have a pocket region and a shallow doped extension region, and the drain structure has no pocket region and a shallow doped extension region. The six-transistor static random access memory cell according to claim 1, wherein: at the same voltage, the current flowing from the drain to the source of the third NMOS transistor and the fourth NMOS transistor is less than from the source The current flowing out of the drain. The six-transistor static random access memory cell of claim 1, wherein: the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, and the second NMOS transistor are transistors having a symmetrical source-drain structure. The six-transistor static random access memory cell of claim 1, wherein: the fabricated substrate of the six-transistor static random access memory cell is a bulk silicon substrate or a silicon-on-insulator substrate. A method for fabricating a six-transistor static random access memory cell, characterized in that: the manufacturing method comprises at least the following steps:

2) forming an N-type well implant region in the semiconductor substrate by an ion implantation process according to a position of the active region, and forming a first P-type well implant region and a second P on both sides of the N-type well implant region Type well injection zone; 3) forming a first NMOS transistor and a third NMOS transistor in the first P-type well implant region, and forming a first PMOS transistor and a second PMOS transistor in the N-well implant region, in the second P a second NMOS transistor and a fourth NMOS transistor are formed in the well-well region, wherein the source and drain structures of the first and second NMOS transistors, the first and second PMOS transistors have a pocket region and a shallow doped extension region The source structure of the third and fourth NMOS transistors has a pocket region and a shallow doped extension region, and the drain structure does not have a pocket region and a shallow doped extension region;

4) Make a metal connection to complete the production of the storage unit. The method of fabricating a six-transistor static random access memory cell according to claim 5, wherein: the step 3) comprises the steps of:

3-1) forming a first gate across the first P-type well implant region and the N-type well implant region, and a second gate spanning the N-well implant region and the second P-type well implant region a third gate and a fourth gate are formed at predetermined positions of the first P-type well implant region and the second P-type well implant region;

3-2) fabricating a mask and performing a first ion implantation to form a pocket region and a shallow doped extension region of the first and second NMOS transistors, the source and drain structures of the first and second PMOS transistors, and forming a third a pocket region of the source structure of the fourth NMOS transistor and a shallow doped extension region;

3-3) forming a sidewall structure on the first, second, third, and fourth gates, respectively, and then forming a first, second, third, and fourth NMOS transistor and a first a source and a drain of the second PMOS transistor, wherein the first NMOS transistor and the first PMOS transistor share a first gate, and the second NMOS transistor and the second PMOS transistor share a second gate . The method of fabricating a six-transistor static random access memory cell according to claim 6, wherein: a drain of the first NMOS transistor is shared with a source of the third NMOS transistor, and a second NMOS transistor The drain is shared with the source of the fourth NMOS transistor. The method of fabricating a six-transistor static random access memory cell according to claim 5, wherein: in the step 4), the first NMOS transistor and the first PMOS transistor are interconnected to form a first inverter The second NMOS transistor and the second PMOS transistor are interconnected to form a second inverter, and a source of the third NMOS transistor is simultaneously connected to an output end of the first inverter and the second reverse An input end of the phase transistor, the gate is connected to the word line of the memory, the drain is connected to the bit line of the memory, and the source of the fourth NMOS transistor is simultaneously connected to the input end of the first inverter and the second inversion Output of the device, word line connected to the gate, memory connected to the drain The bit line is not. The method of fabricating a six-transistor static random access memory cell according to claim 5, wherein: the semiconductor substrate is a bulk silicon substrate or a silicon-on-insulator substrate.