CN103579118B - The method that the write redundancy of SRAM is improved - Google Patents
The method that the write redundancy of SRAM is improved Download PDFInfo
- Publication number
- CN103579118B CN103579118B CN201310492066.2A CN201310492066A CN103579118B CN 103579118 B CN103579118 B CN 103579118B CN 201310492066 A CN201310492066 A CN 201310492066A CN 103579118 B CN103579118 B CN 103579118B
- Authority
- CN
- China
- Prior art keywords
- transistor
- sram
- pulled
- nmos device
- pmos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 42
- 239000011241 protective layer Substances 0.000 claims abstract description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 18
- 230000008569 process Effects 0.000 claims abstract description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 230000003446 memory effect Effects 0.000 claims abstract description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 10
- 239000010703 silicon Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000001459 lithography Methods 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 238000002347 injection Methods 0.000 claims abstract description 4
- 239000007924 injection Substances 0.000 claims abstract description 4
- 230000035882 stress Effects 0.000 claims description 36
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 29
- 229920005591 polysilicon Polymers 0.000 claims description 29
- 230000000694 effects Effects 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 13
- 230000003068 static effect Effects 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 230000008646 thermal stress Effects 0.000 claims description 3
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- 238000002679 ablation Methods 0.000 abstract description 5
- 238000010304 firing Methods 0.000 description 5
- 230000006872 improvement Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7847—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate using a memorization technique, e.g. re-crystallization under strain, bonding on a substrate having a thermal expansion coefficient different from the one of the region
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The method that the write redundancy of a kind of SRAM is improved, including: step S1: silicon-based substrate is provided, and forms shallow trench isolation；Step S2: form nmos device and as the PMOS device pulled up transistor；Step S3: carry out source and drain injection, and deposited silicon nitride protective layer at nmos device and source area and drain region as the PMOS device pulled up transistor；Step S4: carry out source and drain annealing process to nmos device with as the PMOS device pulled up transistor；Step S5: etching removes silicon nitride protective layer.The present invention is by when preparing stress memory effect art lithography version; the PMOS device region pulled up transistor is made to be capped with nmos device; in stress memory effect technique; pulling up transistor and nmos device is all covered by silicon nitride protective layer, carry out source and drain annealing process afterwards, the hole mobility pulled up transistor is lowered; thus increase the equivalent resistance pulled up transistor; in ablation process, reduce secondary nodal point current potential, thus improve its write redundancy.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to the write redundancy of a kind of SRAM
The method that degree improves.
Background technology
SRAM (Static Random Access Memory, SRAM) is deposited as quasiconductor
A class staple product in reservoir, in the high speed data exchange systems such as computer, communication, multimedia
To being widely applied.
Normally, the domain of the SRAM of described below 90nm includes source region, polysilicon gate,
And three levels of contact hole, and in described layout area, forming control pipe respectively, described control pipe is
Nmos device；Lower trombone slide (Pull Down MOS), described lower trombone slide is nmos device；Upper trombone slide
(Pull Up MOS), described upper trombone slide is PMOS device.But, at existing SRAM
In, described in the equivalent resistance that pulls up transistor less, and then cause the write redundancy of described static memory
Degree (Write Margin) is less.Seek the equivalent resistance pulled up transistor described in a kind of increase, to improve
The method of the write redundancy of described SRAM become this area problem demanding prompt solution it
One.
Therefore the problem existed for prior art, this case designer by being engaged in the industry experience for many years,
Actively study improvement, then have the side that the write redundancy of a kind of SRAM of the present invention is improved
Method.
Summary of the invention
The present invention be directed in prior art, pulling up transistor of described traditional SRAM
Equivalent resistance is less, and then causes the write redundancy (Write Margin) of described static memory less
The method that the write redundancy improvement of a kind of SRAM is provided etc. defect.
For realizing the purpose of the present invention, the present invention provides the write redundancy of a kind of SRAM to change
Kind method, described method includes:
Perform step S1: silicon-based substrate is provided, and in described silicon-based substrate, forms the isolation of described shallow trench；
Perform step S2: interval forms described nmos device and described work between described shallow trench is isolated
For the PMOS device pulled up transistor；
Perform step S3: in source area and the drain region of described nmos device, and described as pull-up
After the source area of the PMOS device of transistor and drain region carry out source and drain injection, and at described NMOS device
The described silicon-based substrate side that differs from of part and described PMOS device deposits described silicon nitride protective layer；
Perform step S4: to described nmos device and described as the PMOS device pulled up transistor
Carry out source and drain annealing process；
Perform step S5: etching removes described silicon nitride protective layer.
Alternatively, when preparing described stress memory effect art lithography version so that described in pull up transistor
PMOS device region be not switched on, and capped as described nmos device, described upper crystal pulling
The silicon nitride protective layer in territory, body area under control is not etched removing.
Alternatively, to described nmos device with described carry out source as the PMOS device pulled up transistor
Leakage annealing process, in described silicon nitride protective layer, the polysilicon gate of described nmos device and sidewall, institute
State and between the polysilicon gate as the PMOS device pulled up transistor and sidewall, produce thermal stress and internal stress
Effect.
Alternatively, the memory of described stress effect is on the polysilicon gate and described conduct of described nmos device
In the polysilicon gate of the PMOS device of pull transistor, described stress direction is perpendicular to described static random and deposits
Reservoir face.
Alternatively, when etching removes described silicon nitride protective layer, described stress effect is remembered at described NMOS
The polysilicon gate of device, and conducts as in the polysilicon gate of the PMOS device pulled up transistor with described
To the raceway groove of described cmos semiconductor device.
Alternatively, the described stress in conduction extremely described cmos semiconductor device channel is described for being perpendicular to
The compressive stress on SRAM surface and the tensile stress along device channel direction.
Alternatively, memory at the polysilicon gate of described nmos device with described as pulling up transistor
In the polysilicon gate of PMOS device, and the stress effect conducted to described cmos semiconductor device channel
Should, the electron mobility of described nmos device will be improved.
Alternatively, memory at the polysilicon gate of described nmos device with described as pulling up transistor
In the polysilicon gate of PMOS device, and the stress effect conducted to described cmos semiconductor device channel
Should, using reducing the described carrier mobility as the PMOS device pulled up transistor, increase on described
The equivalent resistance of pull transistor, improves the write redundancy of described SRAM.
In sum, the present invention is by when preparing described stress memory effect art lithography version so that institute
State the PMOS device region pulled up transistor to be capped with described nmos device, in stress memory effect
In technique, described in pull up transistor PMOS device and described nmos device is all protected by described silicon nitride
Layer covers, and carries out source and drain annealing process afterwards, described in the hole mobility that pulls up transistor be lowered, from
And the equivalent resistance pulled up transistor described in increasing, in the ablation process of described SRAM,
Reduce the current potential of described secondary nodal point, thus improve the write redundancy of described SRAM.
Accompanying drawing explanation
Fig. 1 show the write schematic equivalent circuit of SRAM of the present invention；
Fig. 2 show the method flow diagram that the write redundancy of SRAM of the present invention is improved；
Fig. 3 (a)～Fig. 3 (c) show the write redundancy improvement of SRAM of the present invention
Interim structural representation；
Fig. 4 (a)～Fig. 4 (b) show the present invention pull up transistor firing current reduce before and after simulation
Comparative result figure.
Detailed description of the invention
By describing the technology contents of the invention, structural feature in detail, being reached purpose and effect, under
Face is incited somebody to action in conjunction with the embodiments and coordinates accompanying drawing to be described in detail.
Refer to Fig. 1, Fig. 1 and show the write schematic equivalent circuit of SRAM of the present invention.
Write redundancy (Write Margin) is the important of the described static random access memory cell write performance of measurement
Parameter.In the write equivalent circuit of described SRAM, it is assumed that described primary nodal point 1 stores
Data are electronegative potential (i.e. storage data be " 0 "), described secondary nodal point 2 store data be high potential (i.e.
Storage data are " 1 "), nonrestrictive enumerate, such as, write high potential to described primary nodal point 1, to
Described secondary nodal point 2 writes electronegative potential, and before write activity, described first bit line 3 can be paramount by preliminary filling
Current potential, described second bit line 4 can be charged to electronegative potential in advance；When write starts, described wordline 5 is opened,
Owing to the data of described primary nodal point 1 initial storage are electronegative potential, therefore when described original state, described
Pulling up transistor and 6 open, described pull-down transistor 7 is closed.
In described SRAM ablation process, pull up transistor 6 and described control due to described
Transistor 8 is all opened, and the current potential of the most described secondary nodal point 2 is no longer high potential " 1 ", and is in another
Intermediate potential.As those skilled in the art, it is readily appreciated that ground, described intermediate potential is by described upper crystal pulling
The equivalent resistance of body pipe 6 and described control transistor 8 determines.In order to complete write activity, described second
The intermediate potential of node 2 is necessarily less than certain numerical value, i.e. described control transistor 8 and described upper crystal pulling
The equivalent resistance of body pipe 6 is necessarily less than certain numerical value.It is apparent that described intermediate potential is the lowest, then described
The write redundancy of SRAM is the biggest.Therefore, by increase described in pull up transistor 6 etc.
Effect resistance, can reduce the intermediate potential of described secondary nodal point 2, and then improve the storage of described static random
The write redundancy of device.
Refer to Fig. 2, Fig. 3 (a)～Fig. 3 (c), Fig. 2 show SRAM of the present invention it
The method flow diagram that write redundancy is improved.Fig. 3 (a)～Fig. 3 (c) show static random of the present invention
The interim structural representation that the write redundancy of memorizer is improved.Nonrestrictive enumerate, such as at 45nm
In following technique, the method that the write redundancy of described SRAM is improved includes:
Perform step S1: silicon-based substrate 91 is provided, and in described silicon-based substrate 91, forms described shallow ridges
Groove isolation 92；
Perform step S2: interval forms described nmos device 93 He between described shallow trench isolation 92
Described as the PMOS device 94 pulled up transistor；
Perform step S3: in source area 931 and the drain region 932 of described nmos device 93, and
After the source area 941 of described PMOS device 94 and drain region 942 carry out source and drain injection, and described
Described silicon-based substrate 91 side that differs from of nmos device 93 and described PMOS device 94 deposits described nitrogen
SiClx protective layer 95；
Perform step S4: described nmos device 93 and described PMOS device 94 are carried out source and drain and moves back
Ignition technique；
Perform step S5: etching removes described silicon nitride protective layer 95.
As those skilled in the art, it is readily appreciated that ground, in described step S4, to described NMOS
Device 93 and described PMOS device 94 carry out source and drain annealing process, it will at described silicon nitride protective layer
95, the polysilicon gate 933 of described nmos device 93 and sidewall 934, described PMOS device 94 it
Producing thermal stress and internal stress effect between polysilicon gate 943 and sidewall 944, described stress effect is remembered
Polysilicon gate 933 and the polysilicon gate 943 of described PMOS device 94 at described nmos device 93
In, described stress direction is perpendicular to described SRAM surface.
Performing described step S5, when etching removes described silicon nitride protective layer 95, described stress effect is still
Remember the polysilicon gate of the polysilicon gate 933 at described nmos device 93 and described PMOS device 94
In 943, and conduct to the raceway groove of described cmos semiconductor device.Wherein, conduction extremely described CMOS
Described stress in semiconductor device channel be perpendicular to described SRAM surface compressive stress and
Tensile stress along device channel direction.
It is apparent that memory is in the polysilicon gate 933 of described nmos device 93 and described PMOS device
In the polysilicon gate 943 of 94, and the stress effect conducted to described cmos semiconductor device channel,
The electron mobility of described nmos device 93 will be improved, on the other hand reduce described PMOS device
The carrier mobility of 94, the equivalent resistance pulled up transistor described in increase, improves described static random and deposits
The write redundancy of reservoir.
As the detailed description of the invention of the present invention, in order to described nmos device and described PMOS device
All produce stress effect, it is preferable that when preparing described stress memory effect art lithography version so that institute
State PMOS device 94 region pulled up transistor to be not switched on, and quilt as described nmos device
Cover, therefore in stress memory effect technique, described in pull up transistor and described nmos device is all by institute
State silicon nitride protective layer 95 to cover, described in the hole mobility that pulls up transistor be lowered, thus increase institute
State the equivalent resistance pulled up transistor, in the ablation process of described SRAM, reduce described
The current potential of secondary nodal point 2, thus improve the write redundancy of described SRAM.
Referring to Fig. 4 (a), Fig. 4 (b), Fig. 4 (a) show the present invention and pulls up transistor firing current
Analog result figure before reduction.Fig. 4 (b) show the present invention pull up transistor firing current reduce after write
Enter the analog result figure of redundancy.From Fig. 4 (a), Fig. 4 (b), nonrestrictive enumerate, pin
To 45nm SRAM, after the firing current pulled up transistor described in reducing, described static state with
Write redundancy 10b of machine memorizer relatively described in the firing current that pulls up transistor reduce before write redundancy
Degree 10a improves 10mV.
In sum, the present invention is by when preparing described stress memory effect art lithography version so that institute
State the PMOS device region pulled up transistor to be capped with described nmos device, in stress memory effect
In technique, described in pull up transistor and described nmos device all covered by described silicon nitride protective layer, it
After carry out source and drain annealing process, described in the hole mobility that pulls up transistor be lowered, thus increase described
The equivalent resistance pulled up transistor, in the ablation process of described SRAM, reduces described
The current potential of two nodes, thus improve the write redundancy of described SRAM.
Those skilled in the art it will be appreciated that the most without departing from the spirit or scope of the present invention, can
The present invention is carried out various modifications and variations.Thus, if any amendment or modification fall into appended right and want
When asking in the protection domain of book and equivalent, it is believed that the present invention contains these amendment and modification.
Claims (8)
1. the method that the write redundancy of a SRAM is improved, it is characterised in that described side
Method includes:
Perform step S1: silicon-based substrate is provided, and in described silicon-based substrate, forms shallow trench isolation；
Perform step S2: interval forms crystal pulling in nmos device and conduct between described shallow trench is isolated
The PMOS device of body pipe；
Perform step S3: in source area and the drain region of described nmos device, and described as pull-up
After the source area of the PMOS device of transistor and drain region carry out source and drain injection, and at described NMOS device
Part and described differ from described silicon-based substrate side deposited silicon nitride as the PMOS device pulled up transistor
Protective layer；
Perform step S4: to described nmos device and described as the PMOS device pulled up transistor
Carry out source and drain annealing process；
Perform step S5: etching removes described silicon nitride protective layer.
2. the method that the write redundancy of SRAM as claimed in claim 1 is improved, it is special
Levying and be, described method also includes preparing stress memory effect art lithography version, uses described stress memory
During effect art lithography version so that described in the PMOS device region that pulls up transistor be not switched on, and with
Described nmos device is the most capped, described in the pull up transistor silicon nitride protective layer in region be not etched
Remove.
3. the method that the write redundancy of SRAM as claimed in claim 1 is improved, it is special
Levy and be, described nmos device and described PMOS device are carried out source and drain annealing process, at described nitrogen
SiClx protective layer, the polysilicon gate of described nmos device and sidewall, described as pulling up transistor
Thermal stress and internal stress effect is produced between polysilicon gate and the sidewall of PMOS device.
4. the method that the write redundancy of SRAM as claimed in claim 3 is improved, it is special
Levying and be, the memory of described stress effect is in the polysilicon gate of described nmos device and crystal pulling in described conduct
In the polysilicon gate of the PMOS device of body pipe, described stress direction is perpendicular to described SRAM
Surface.
5. the method that the write redundancy of SRAM as claimed in claim 4 is improved, it is special
Levying and be, when etching removes described silicon nitride protective layer, described stress effect is remembered at described NMOS device
The polysilicon gate of part, and conducts extremely as in the polysilicon gate of the PMOS device pulled up transistor with described
In the raceway groove of cmos semiconductor device, wherein, described cmos semiconductor device includes described NMOS
Device and as the PMOS device pulled up transistor.
6. the method that the write redundancy of SRAM as claimed in claim 5 is improved, it is special
Levying and be, the described stress in conduction to described cmos semiconductor device channel is for being perpendicular to described static state
The compressive stress on random access memory surface and the tensile stress along device channel direction.
7. the method that the write redundancy of SRAM as claimed in claim 5 is improved, it is special
Levy and be, remember at the polysilicon gate of described nmos device with described as the PMOS pulled up transistor
In the polysilicon gate of device, and the stress effect conducted to described cmos semiconductor device channel, will
Improve the electron mobility of described nmos device.
8. the method that the write redundancy of SRAM as claimed in claim 5 is improved, it is special
Levy and be, remember at the polysilicon gate of described nmos device with described as the PMOS pulled up transistor
In the polysilicon gate of device, and the stress effect conducted to described cmos semiconductor device channel, will
Reduce the described carrier mobility as the PMOS device pulled up transistor, increase described upper crystal pulling
The equivalent resistance of pipe, improves the write redundancy of described SRAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310492066.2A CN103579118B (en) | 2013-10-18 | 2013-10-18 | The method that the write redundancy of SRAM is improved |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310492066.2A CN103579118B (en) | 2013-10-18 | 2013-10-18 | The method that the write redundancy of SRAM is improved |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103579118A CN103579118A (en) | 2014-02-12 |
| CN103579118B true CN103579118B (en) | 2016-11-02 |
Family
ID=50050595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310492066.2A Active CN103579118B (en) | 2013-10-18 | 2013-10-18 | The method that the write redundancy of SRAM is improved |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103579118B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113611672A (en) * | 2021-06-18 | 2021-11-05 | 联芯集成电路制造(厦门)有限公司 | Method for forming semiconductor element |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7223647B2 (en) * | 2004-11-05 | 2007-05-29 | Taiwan Semiconductor Manufacturing Company | Method for forming integrated advanced semiconductor device using sacrificial stress layer |
| US7795644B2 (en) * | 2007-01-04 | 2010-09-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuits with stress memory effect and fabrication methods thereof |
| US20120280324A1 (en) * | 2010-11-03 | 2012-11-08 | Texas Instruments Incorporated | Sram structure and process with improved stability |
| CN102655122A (en) * | 2012-04-16 | 2012-09-05 | 上海华力微电子有限公司 | Method for improving reading redundancy of SRAM (static random access memory) |
| CN102655124A (en) * | 2012-04-16 | 2012-09-05 | 上海华力微电子有限公司 | Method for improving reading redundancy of static random access memory |
| CN102738084B (en) * | 2012-05-04 | 2014-09-03 | 上海华力微电子有限公司 | Method for improving write redundancy of high SRAM (static random access memory) |
| CN102779837B (en) * | 2012-08-15 | 2015-04-08 | 中国科学院上海微系统与信息技术研究所 | Six-transistor static random access memory unit and manufacturing method thereof |
-
2013
- 2013-10-18 CN CN201310492066.2A patent/CN103579118B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN103579118A (en) | 2014-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4906353B2 (en) | SRAM array, SRAM cell, microprocessor, SRAM memory, and method of forming the same | |
| US20140001562A1 (en) | Integrated Circuit Having FinFETS with Different Fin Profiles | |
| Fahey et al. | Stress-induced dislocations in silicon integrated circuits | |
| US9312263B2 (en) | Static random access memory cell and forming method thereof | |
| CN102738084B (en) | Method for improving write redundancy of high SRAM (static random access memory) | |
| CN103579118B (en) | The method that the write redundancy of SRAM is improved | |
| US11114548B2 (en) | Semiconductor device having source and drain in active region and manufacturing method for same | |
| CN103325788A (en) | Eight-transistor static random access memory unit | |
| CN102655122A (en) | Method for improving reading redundancy of SRAM (static random access memory) | |
| SG141429A1 (en) | Thyristor-based sram and method using quasi-planar finfet process for the fabrication thereof | |
| CN107302000B (en) | SRAM memory and forming method thereof | |
| CN102683287B (en) | Method for improving write margin of static random access memory (SRAM) | |
| CN102610574B (en) | Method for improving reading redundancy rate of static random access memory | |
| CN103579243B (en) | SRAM and write redundancy ameliorative way in embedded germanium silicon technology | |
| CN106158866A (en) | A kind of SRAM device and electronic installation thereof | |
| CN103579244B (en) | The method that SRAM and write redundancy thereof are improved | |
| CN102709252B (en) | Method for improving read-out redundancy of static random access memory | |
| Feng et al. | Vertical Channel Transistor (VCT) as Access Transistor for Future 4F 2 DRAM Architecture | |
| CN102655124A (en) | Method for improving reading redundancy of static random access memory | |
| CN103579245A (en) | Static random access memory in hybrid orientation technology and method for improving write margin | |
| CN102693944A (en) | Method for improving read redundancy of static random access memory | |
| Aoulaiche et al. | Origin of wide retention distribution in 1T Floating Body RAM | |
| CN103606536B (en) | Improve the method for the write redundancy of static random access memory | |
| CN102683288B (en) | Method for improving read-out redundancy of static random access memory | |
| CN102655123B (en) | Method for improving reading redundancy of static random access memory |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |