CN103606536B - Improve the method for the write redundancy of static random access memory - Google Patents
Improve the method for the write redundancy of static random access memory Download PDFInfo
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- CN103606536B CN103606536B CN201310491576.8A CN201310491576A CN103606536B CN 103606536 B CN103606536 B CN 103606536B CN 201310491576 A CN201310491576 A CN 201310491576A CN 103606536 B CN103606536 B CN 103606536B
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- 230000003068 static effect Effects 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000007943 implant Substances 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 28
- 229920005591 polysilicon Polymers 0.000 claims abstract description 28
- 229910021478 group 5 element Inorganic materials 0.000 claims abstract description 27
- 238000010304 firing Methods 0.000 claims abstract description 17
- 238000002679 ablation Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 6
- 230000000694 effects Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005303 weighing Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
Abstract
Improve a method for the write redundancy of static random access memory, comprising: step S1: before polysilicon gate etching technique, group-v element pre-implant is carried out to the control grid of nmos device of transistor and the grid of the nmos device of pull-down transistor; Step S2: group-v element pre-implant is carried out to the grid of the PMOS device pulled up transistor.The present invention by carrying out group-v element pre-implant to the grid of nmos device, to regulate cmos device threshold voltage and described firing current; Group-v element pre-implant is carried out to the grid of the PMOS device pulled up transistor, the relative doping concentration of the polysilicon gate pulled up transistor is reduced, thus the dead resistance of increase polysilicon gate and polysilicon gate exhaust phenomenon, the firing current pulled up transistor is caused to reduce, and then in static random access memory ablation process, increase the equivalent resistance pulled up transistor, reduce the current potential of Section Point, improve the write redundancy of static random access memory.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of method improving the write redundancy of static random access memory.
Background technology
Static random access memory (StaticRandomAccessMemory, SRAM), as the class staple product in semiconductor memory, is widely used in the high speed data exchange systems such as computer, communication, multimedia.
Normally, the domain of the static random access memory of described below 90nm includes source region, polysilicon gate, and contact hole three levels, and distinguishes formation control pipe in described layout area, and described control valve is nmos device; Lower trombone slide (PullDownMOS), described lower trombone slide is nmos device; Upper trombone slide (PullUpMOS), described upper trombone slide is PMOS device.But, in existing static random access memory, described in the equivalent resistance that pulls up transistor less, and then cause the write redundancy (WriteMargin) of described static random access memory less.Seek the equivalent resistance pulled up transistor described in a kind of increase, become one of this area problem demanding prompt solution with the method for the write redundancy improving described static random access memory.
Therefore for prior art Problems existing, this case designer is by means of being engaged in the industry experience for many years, and active research improves, so there has been a kind of method improving the write redundancy of static random access memory of the present invention.
Summary of the invention
The present invention be directed in prior art, the equivalent resistance pulled up transistor of described traditional static random access memory is less, and then causes the defects such as the write redundancy (WriteMargin) of described static random access memory is less to provide a kind of method improving the write redundancy of static random access memory.
For realizing the object of the present invention, the invention provides a kind of method improving the write redundancy of static random access memory, described method comprises:
Perform step S1: before polysilicon gate etching technique, group-v element pre-implant is carried out to the grid of the grid of the nmos device of described control transistor and the nmos device of described pull-down transistor;
Perform step S2: group-v element pre-implant is carried out to the grid of the described PMOS device pulled up transistor.
Alternatively, described method is applied to below 45nm technique.
Alternatively, group-v element pre-implant is carried out to the grid of the grid of the nmos device of described control transistor and the nmos device of described pull-down transistor, regulate described cmos device threshold voltage (V to reach
t) and described firing current (I
on) object.
Alternatively, group-v element pre-implant is carried out to the grid of the described PMOS device pulled up transistor, the relative doping concentration of the polysilicon gate pulled up transistor described in making reduces, thus increase the dead resistance of described polysilicon gate and polysilicon gate exhausts phenomenon, the firing current pulled up transistor described in causing reduces, in described static random access memory ablation process, the equivalent resistance pulled up transistor described in increasing, reduce the current potential of described Section Point, thus improve the write redundancy of described static random access memory.
Alternatively, when preparing the polysilicon gate pre-implant reticle of the nmos device of described control transistor and the nmos device of described pull-down transistor, the region that pulls up transistor described in making is opened, while group-v element pre-implant is carried out to the grid of nmos device, complete and group-v element pre-implant is carried out to the grid of described PMOS device.
In sum, the present invention, by before polysilicon gate etching technique, carries out group-v element pre-implant to the grid of the grid of the nmos device of described control transistor and the nmos device of described pull-down transistor, regulates described cmos device threshold voltage (V to reach
t) and described firing current (I
on) object; Group-v element pre-implant is carried out to the grid of the described PMOS device pulled up transistor, the relative doping concentration of the polysilicon gate pulled up transistor described in making reduces, thus increase the dead resistance of described polysilicon gate and polysilicon gate exhausts phenomenon, the firing current pulled up transistor described in causing reduces, and then in described static random access memory ablation process, the equivalent resistance pulled up transistor described in increasing, reduce the current potential of described Section Point, improve the write redundancy of described static random access memory.
Accompanying drawing explanation
Figure 1 shows that the write schematic equivalent circuit of static random access memory of the present invention;
Figure 2 shows that the present invention improves the flow chart of the method for static random access memory write redundancy;
Fig. 3 (a) ~ Fig. 3 (b) be depicted as the present invention pull up transistor firing current reduce before and after analog result comparison diagram.
Embodiment
By describe in detail the invention technology contents, structural feature, reached object and effect, coordinate accompanying drawing to be described in detail below in conjunction with embodiment.
Refer to Fig. 1, Figure 1 shows that the write schematic equivalent circuit of static random access memory of the present invention.Write redundancy (WriteMargin) is the important parameter weighing described static random access memory cell write performance.In the write equivalent electric circuit of described static random access memory, assuming that it is electronegative potential (namely storing data for " 0 ") that described first node 1 stores data, it is high potential (namely storing data for " 1 ") that described Section Point 2 stores data, nonrestrictively to enumerate, such as write high potential to described first node 1, write electronegative potential, before write activity to described Section Point 2, described first bit line 3 can by preliminary filling to high potential, and described second bit line 4 can be charged to electronegative potential in advance; Write start time, described wordline 5 is opened, because the data of described first node 1 initial storage are electronegative potential, therefore when described initial condition, described in pull up transistor and 6 to open, described pull-down transistor 7 is closed.
In described static random access memory ablation process, due to described pull up transistor 6 and described control transistor 8 all open, then the current potential of described Section Point 2 is no longer high potential " 1 ", and is in another intermediate potential.As those skilled in the art, easy understand ground, described intermediate potential is by the equivalent resistance decision of described pull up transistor 6 and described control transistor 8.In order to complete write activity, the intermediate potential of described Section Point 2 must be less than certain numerical value, that is, described control transistor 8 and described pull up transistor 6 equivalent resistance must be less than certain numerical value.Significantly, described intermediate potential is lower, then the write redundancy of described static random access memory is larger.Therefore, by pull up transistor described in increasing 6 equivalent resistance, the intermediate potential of described Section Point 2 can be reduced, and then improve the write redundancy of described static random access memory.
Refer to Fig. 2, and Fig. 1 is consulted in combination, Figure 2 shows that the present invention improves the flow chart of the method for static random access memory write redundancy.Nonrestrictively enumerate, such as, in described below 45nm technique, the method for described raising static random access memory write redundancy comprises:
Perform step S1: before polysilicon gate etching technique, group-v element pre-implant is carried out to the grid of the grid of the nmos device of described control transistor and the nmos device of described pull-down transistor;
Perform step S2: group-v element pre-implant is carried out to the grid of the described PMOS device pulled up transistor.
As those skilled in the art, easy understand ground, in the present invention, carries out group-v element pre-implant to the grid of the grid of the nmos device of described control transistor and the nmos device of described pull-down transistor, regulates described cmos device threshold voltage (V to reach
t) and described firing current (I
on) object; Group-v element pre-implant is carried out to the grid of the described PMOS device pulled up transistor, the relative doping concentration of the polysilicon gate pulled up transistor described in making reduces, thus increasing the dead resistance of described polysilicon gate and polysilicon gate exhausts phenomenon, the firing current pulled up transistor described in causing reduces.Therefore in described static random access memory ablation process, the equivalent resistance pulled up transistor described in increasing, reduces the current potential of described Section Point 8, thus improves the write redundancy of described static random access memory.
As the specific embodiment of the present invention, in order to the grid of the grid of the nmos device to described control transistor and the nmos device of described pull-down transistor carries out group-v element pre-implant, and group-v element pre-implant is carried out to the grid of the PMOS device of described pull-down transistor, preferably, when preparing the polysilicon gate pre-implant reticle of described NMOS, the region that pulls up transistor described in making is opened, while group-v element pre-implant is carried out to the grid of nmos device, can complete and group-v element pre-implant is carried out to the grid of described PMOS device
Refer to Fig. 3 (a), Fig. 3 (b), Fig. 3 (a) be depicted as the present invention pull up transistor firing current reduce before analog result figure.Fig. 3 (b) be depicted as the present invention pull up transistor firing current reduce after write redundancy analog result figure.From Fig. 3 (a), Fig. 3 (b), nonrestrictively to enumerate, for 45nm static random access memory, after the firing current that pulls up transistor described in reducing, the write redundancy 10b of described static random access memory comparatively described in pull up transistor 6 firing current reduction before write redundancy 10a improve 10mV.
In sum, the present invention, by before polysilicon gate etching technique, carries out group-v element pre-implant to the grid of the grid of the nmos device of described control transistor and the nmos device of described pull-down transistor, regulates described cmos device threshold voltage (V to reach
t) and described firing current (I
on) object; Group-v element pre-implant is carried out to the grid of the described PMOS device pulled up transistor, the relative doping concentration of the polysilicon gate pulled up transistor described in making reduces, thus increase the dead resistance of described polysilicon gate and polysilicon gate exhausts phenomenon, the firing current pulled up transistor described in causing reduces, and then in described static random access memory ablation process, the equivalent resistance pulled up transistor described in increasing, reduce the current potential of described Section Point, improve the write redundancy of described static random access memory.
Those skilled in the art all should be appreciated that, without departing from the spirit or scope of the present invention, can carry out various modifications and variations to the present invention.Thus, if when any amendment or modification fall in the protection range of appended claims and equivalent, think that these amendment and modification are contained in the present invention.
Claims (4)
1. improve a method for the write redundancy of static random access memory, it is characterized in that, described method comprises:
Perform step S1: before polysilicon gate etching technique, group-v element pre-implant is carried out to the control grid of nmos device of transistor and the grid of the nmos device of pull-down transistor;
Perform step S2: group-v element pre-implant is carried out to the grid of the PMOS device pulled up transistor, the relative doping concentration of the polysilicon gate pulled up transistor described in making reduces, thus increase the dead resistance of described polysilicon gate and polysilicon gate exhausts phenomenon, the firing current pulled up transistor described in causing reduces, in described static random access memory ablation process, the equivalent resistance pulled up transistor described in increasing, reduce the current potential of Section Point, thus improve the write redundancy of described static random access memory.
2. the method improving the write redundancy of static random access memory as claimed in claim 1, it is characterized in that, described method is applied to below 45nm technique.
3. the method improving the write redundancy of static random access memory as claimed in claim 2, it is characterized in that, group-v element pre-implant is carried out to the grid of the grid of the nmos device of described control transistor and the nmos device of described pull-down transistor, regulates cmos device threshold voltage (V to reach
t) and firing current (I
on) object.
4. the method improving the write redundancy of static random access memory as claimed in claim 1, it is characterized in that, when preparing the polysilicon gate pre-implant reticle of the nmos device of described control transistor and the nmos device of described pull-down transistor, the region that pulls up transistor described in making is opened, while group-v element pre-implant is carried out to the grid of nmos device, complete and group-v element pre-implant is carried out to the grid of described PMOS device.
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| CN103606536B true CN103606536B (en) | 2016-03-23 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446719A (en) * | 2011-09-08 | 2012-05-09 | 上海华力微电子有限公司 | Method for increasing writing speed of floating body dynamic random access memory |
| CN102832110A (en) * | 2012-05-22 | 2012-12-19 | 上海华力微电子有限公司 | Method for improving static random access memory reading redundancy |
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| US8859302B2 (en) * | 2011-02-28 | 2014-10-14 | International Business Machines Corporation | Structure and method for adjusting threshold voltage of the array of transistors |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102446719A (en) * | 2011-09-08 | 2012-05-09 | 上海华力微电子有限公司 | Method for increasing writing speed of floating body dynamic random access memory |
| CN102832110A (en) * | 2012-05-22 | 2012-12-19 | 上海华力微电子有限公司 | Method for improving static random access memory reading redundancy |
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