CN103579244B - The method that SRAM and write redundancy thereof are improved - Google Patents
The method that SRAM and write redundancy thereof are improved Download PDFInfo
- Publication number
- CN103579244B CN103579244B CN201310491853.5A CN201310491853A CN103579244B CN 103579244 B CN103579244 B CN 103579244B CN 201310491853 A CN201310491853 A CN 201310491853A CN 103579244 B CN103579244 B CN 103579244B
- Authority
- CN
- China
- Prior art keywords
- silicon
- drain region
- transistor
- source area
- based substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 50
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 50
- 239000010703 silicon Substances 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 50
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 38
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 230000006835 compression Effects 0.000 claims abstract description 16
- 238000007906 compression Methods 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 230000009467 reduction Effects 0.000 claims abstract description 5
- 238000002347 injection Methods 0.000 claims description 14
- 239000007924 injection Substances 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 13
- 229910052732 germanium Inorganic materials 0.000 claims description 12
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 12
- 230000003068 static effect Effects 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 11
- 230000008569 process Effects 0.000 claims description 11
- 238000002360 preparation method Methods 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 5
- 230000000694 effects Effects 0.000 abstract description 8
- 238000010304 firing Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000002679 ablation Methods 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A kind of SRAM, including: silicon-based substrate；The shallow trench isolation being arranged in silicon-based substrate；Nmos device；PMOS device, arranges silicon germanium lattice structure in the source area and drain region of PMOS device；Pull up transistor, for PMOS semiconductor, in the source area pulled up transistor, drain region, be not provided with silicon germanium lattice structure.The present invention, by arranging silicon germanium lattice structure in the source area, drain region of PMOS device, increases the compression in described PMOS device raceway groove, thus reaches to improve the effect of the hole mobility of described PMOS device；By being not provided with described silicon germanium lattice structure in the source area pulled up transistor described, drain region, the compression on channel direction that pulls up transistor described in making reduces, the carrier mobility pulled up transistor described in reduction, the equivalent resistance pulled up transistor described in increase, and then improve described SRAM write redundancy.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of SRAM and write superfluous
The method that remaining is improved.
Background technology
SRAM (Static Random Access Memory, SRAM) is deposited as semiconductor
A class staple product in reservoir, in the high speed data exchange systems such as computer, communication, multimedia
To being widely applied.
Normally, the domain of the SRAM of described below 90nm includes source region, polysilicon gate,
And three levels of contact hole, and in described layout area, forming control pipe respectively, described control pipe is
Nmos device；Lower trombone slide (Pull Down MOS), described lower trombone slide is nmos device；Upper trombone slide
(Pull Up MOS), described upper trombone slide is PMOS device.But, at existing SRAM
In, described in the equivalent resistance that pulls up transistor less, and then cause the write redundancy of described static memory
Degree (Write Margin) is less.Seek the equivalent resistance pulled up transistor described in a kind of increase, to improve
The method that the write redundancy of described SRAM is improved has become this area problem demanding prompt solution
One of.
Therefore the problem existed for prior art, this case designer by being engaged in the industry experience for many years,
Actively study improvement, then have a kind of SRAM of the present invention and write redundancy thereof to improve
Method.
Summary of the invention
The present invention be directed in prior art, pulling up transistor of described traditional SRAM
Equivalent resistance is less, and then causes the write redundancy (Write Margin) of described static memory less
A kind of SRAM is provided etc. defect.
The present invention is also an object that in prior art, on described traditional SRAM
The equivalent resistance of pull transistor is less, and then causes the write redundancy (Write of described static memory
Margin) defect such as less provides a kind of method of write redundancy improvement of SRAM.
For realizing the purpose of the present invention, the present invention provides a kind of SRAM, described static random
Memory includes: silicon-based substrate, and interval is provided for the shallow ridges of electrical isolation in described silicon-based substrate
Groove is isolated；Nmos device, is arranged between the isolation of described shallow trench, the grid of described nmos device
Being arranged in described silicon-based substrate, the source area of described nmos device, drain region are separately positioned on described
In the silicon-based substrate of grid both sides, and it is not provided with described in source area, the drain region of described nmos device
Silicon germanium lattice structure；PMOS device, is arranged between the isolation of described shallow trench, described PMOS device
Grid be arranged in described silicon-based substrate, the source area of described PMOS device, drain region are respectively provided with
In the silicon-based substrate of described grid both sides, and set in the source area and drain region of described PMOS device
Put described silicon germanium lattice structure；Pull up transistor, described in pull up transistor as PMOS semiconductor, and set
Put between described shallow trench is isolated, described in the grid that pulls up transistor be arranged in described silicon-based substrate,
The described source area that pulls up transistor, drain region are separately positioned in the silicon-based substrate of described grid both sides,
And source area, the drain region pulled up transistor described is not provided with described silicon germanium lattice structure.
For realizing the another purpose of the present invention, the present invention provides the write redundancy of a kind of SRAM
The method that degree improves, described method includes:
Perform step S1: provide silicon-based substrate, and in described silicon-based substrate interval be provided for electrically every
From shallow trench isolation；
Perform step S2: nmos device, described NMOS device are set between described shallow trench is isolated
The grid of part is arranged in described silicon-based substrate, and the source area of described nmos device, drain region set respectively
Put in the silicon-based substrate of described grid both sides, in the source area, drain region of described nmos device not
Form described silicon germanium lattice structure；
Perform step S3: PMOS device, described PMOS device are set between described shallow trench is isolated
Grid be arranged in described silicon-based substrate, the source area of described PMOS device, drain region are respectively provided with
In the silicon-based substrate of described grid both sides, and set in the source area and drain region of described PMOS device
Put described silicon germanium lattice structure；
Perform step S4: arrange and pull up transistor between described shallow trench is isolated, described in pull up transistor
For PMOS semiconductor, described in the grid that pulls up transistor be arranged in described silicon-based substrate, described pull-up
The source area of transistor, drain region are separately positioned in the silicon-based substrate of described grid both sides, on described
Described silicon germanium lattice structure it is formed without in the source area of pull transistor, drain region.
Alternatively, the preparation method of described silicon germanium lattice structure farther includes:
In described PMOS device preparation process, before described source area, drain region injection technology,
Described PMOS device is carried out germanium injection, it is achieved source area, drain region decrystallized, to form an ultra shallow
Knot；
By annealing process, form germanium silicon lattice structure in described source area, drain region.
Alternatively, germanium injection technology and annealing are not carried out in the source area that pulls up transistor described in, drain region
Technique, to be formed without described silicon germanium lattice structure.
Alternatively, arrange in the source area of PMOS device of described SRAM, drain region
Described silicon germanium lattice structure, increases the compression in described PMOS device raceway groove, thus reaches to improve institute
State the hole mobility of PMOS device.
Alternatively, it is not provided with described silicon Germanium lattice knot in the source area that pulls up transistor to described, drain region
Structure so that described in pull up transistor compression on channel direction reduce, pull up transistor described in reduction
Carrier mobility, increase described in the equivalent resistance that pulls up transistor, and then improve described static state
Random access memory write redundancy.
The present invention, by arranging silicon germanium lattice structure in the source area, drain region of PMOS device, increases
Compression in described PMOS device raceway groove, thus reach to improve the hole migration of described PMOS device
The effect of rate；By being not provided with described silicon Germanium lattice in the source area pulled up transistor described, drain region
Structure so that described in pull up transistor compression on channel direction reduce, reduce described upper crystal pulling
The carrier mobility of pipe, the equivalent resistance pulled up transistor described in increase, and then improve described static state with
Machine memory write redundancy.
Accompanying drawing explanation
Fig. 1 show the write schematic equivalent circuit of SRAM of the present invention；
Fig. 2 show the NMOS of SRAM of the present invention, PMOS, the structure that pulls up transistor
Schematic diagram；
Fig. 3 show the method flow diagram that the write redundancy of SRAM of the present invention is improved；
Fig. 4 (a)～Fig. 4 (b) show the present invention pull up transistor firing current reduce before and after simulation
Comparative result figure.
Detailed description of the invention
By describing the technology contents of the invention, structural feature in detail, being reached purpose and effect, under
Face is incited somebody to action in conjunction with the embodiments and coordinates accompanying drawing to be described in detail.
Refer to Fig. 1, Fig. 1 and show the write schematic equivalent circuit of SRAM of the present invention.
Write redundancy (Write Margin) is the important of the described static random access memory cell write performance of measurement
Parameter.In the write equivalent circuit of described SRAM, it is assumed that described first node 1 stores
Data are electronegative potential (i.e. storage data be " 0 "), described Section Point 2 store data be high potential (i.e.
Storage data are " 1 "), nonrestrictive enumerate, such as, write high potential to described first node 1, to
Described Section Point 2 writes electronegative potential, and before write activity, described first bit line 3 can be paramount by preliminary filling
Current potential, described second bit line 4 can be charged to electronegative potential in advance；When write starts, described wordline 5 is opened,
Owing to the data of described first node 1 initial storage are electronegative potential, therefore when described original state, described
Pulling up transistor and 6 open, described pull-down transistor 7 is closed.
In described SRAM ablation process, pull up transistor 6 and described control due to described
Transistor 8 is all opened, and the current potential of the most described Section Point 2 is no longer high potential " 1 ", and is in another
Intermediate potential.As those skilled in the art, it is readily appreciated that ground, described intermediate potential is by described upper crystal pulling
The equivalent resistance of body pipe 6 and described control transistor 8 determines.In order to complete write activity, described second
The intermediate potential of node 2 is necessarily less than certain numerical value, i.e. described control transistor 8 and described upper crystal pulling
The equivalent resistance of body pipe 6 is necessarily less than certain numerical value.It is apparent that described intermediate potential is the lowest, then described
The write redundancy of SRAM is the biggest.Therefore, by increase described in pull up transistor 6 etc.
Effect resistance, can reduce the intermediate potential of described Section Point 2, and then improve the storage of described static random
The write redundancy of device.
Refer to Fig. 2, Fig. 2 and show the NMOS of SRAM of the present invention, PMOS, pull-up
The structural representation of transistor.Described SRAM 9 includes: silicon-based substrate 91, and described
In silicon-based substrate 91, interval is provided for the shallow trench isolation 92 of electrical isolation；Nmos device 93, if
Putting between described shallow trench isolation 92, the grid 931 of described nmos device 93 is arranged on described silicon
On base substrate 91, the source area 932 of described nmos device 93, drain region 933 are separately positioned on institute
State in the silicon-based substrate 91 of grid 931 both sides；PMOS device 94, is arranged on the isolation of described shallow trench
Between 92, the grid 941 of described PMOS device 94 is arranged in described silicon-based substrate 91, described PMOS
The source area 942 of device 94, drain region 943 are separately positioned on the silicon-based substrate of described grid 941 both sides
In 91, and silicon Germanium lattice is set in the source area 942 and drain region 943 of described PMOS device 94
Structure 95；Pull up transistor 96, described in pull up transistor 96 for PMOS semiconductor, and be arranged on institute
State shallow trench isolation 92 between, described in pull up transistor 96 grid 961 be arranged on described silicon-based substrate
On 91, described in pull up transistor 96 source area 962, drain region 963 be separately positioned on described grid 961
In the silicon-based substrate 91 of both sides.
As those skilled in the art, it is readily appreciated that ground, such as in below 65nm technique, quiet in the present invention
The source area 942 of the PMOS device 94 of state random access memory, drain region 943 arrange silicon Germanium lattice knot
Structure 95, can produce compression in described PMOS device 94 raceway groove, thus reach to improve described PMOS
The hole carrier mobility of device 94, to improve the performance of PMOS device 94.Wherein, described silicon
The preparation method of germanium lattice structure 95 includes: first, at described PMOS device 94 preparation process
In, before described source area 942, drain region 943 injection technology, described PMOS device 94 is carried out
Germanium inject, it is achieved source area 942, drain region 943 decrystallized, to form ultra-shallow junctions；Then, pass through
Annealing process, forms germanium silicon lattice structure 95 in described source area 942, drain region 943.On the other hand,
Compression in described raceway groove can reduce the mobility of electronics, therefore does not carry out institute at described nmos device 93
State germanium injection technology and annealing process.I.e. in source area 932, the drain region 933 of described nmos device 93
Inside it is formed without described silicon germanium lattice structure 95.
In the present invention, described in pull up transistor 96 for PMOS semiconductor, and pull up transistor described
It is not provided with described silicon germanium lattice structure 95, i.e. on described in the source area 962 of 96, drain region 963
The source area 962 of pull transistor 96, drain region 963 do not carry out germanium injection technology and annealing process so that
Described 96 compression on channel direction that pull up transistor reduce, and pull up transistor 96 described in reduction
Carrier mobility, pull up transistor described in increase 96 equivalent resistance, and then improve described static random
Memory write redundancy.
Refer to Fig. 3, and combine the write showing SRAM of the present invention refering to Fig. 2, Fig. 3
The method flow diagram that redundancy is improved.The method bag that the write redundancy of described SRAM is improved
Include:
Perform step S1: silicon-based substrate 91 is provided, and is spaced in described silicon-based substrate 91 and is provided for
The shallow trench isolation 92 of electrical isolation；
Perform step S2: nmos device 93, described NMOS are set between described shallow trench isolation 92
The grid 931 of device 93 is arranged in described silicon-based substrate 91, the source area of described nmos device 93
932, in drain region 933 is separately positioned on the silicon-based substrate 91 of described grid 931 both sides, at described NMOS
Device 93 does not carry out described germanium injection technology and annealing process, i.e. at the source electrode of described nmos device 93
Described silicon germanium lattice structure 95 it is formed without in district 932, drain region 933；
Perform step S3: PMOS device 94, described PMOS are set between described shallow trench isolation 92
The grid 941 of device 94 is arranged in described silicon-based substrate 91, the source area of described PMOS device 94
942, in drain region 943 is separately positioned on the silicon-based substrate 91 of described grid 941 both sides, and described
The source area 942 of PMOS device 94 and drain region 943 arrange described silicon germanium lattice structure 95；
Wherein, the preparation method of described silicon germanium lattice structure 95 includes: first, in described PMOS device
In 94 preparation process, before described source area 942, drain region 943 injection technology, to described PMOS
Device 94 carries out germanium injection, it is achieved source area 942, drain region 943 decrystallized, to form ultra-shallow junctions；
Then, by annealing process, germanium silicon lattice structure 95 is formed in described source area 942, drain region 943.
On the other hand, the compression in described raceway groove can reduce the mobility of electronics, therefore at described nmos device
93 do not carry out described germanium injection technology and annealing process.I.e. described nmos device 93 source area 932,
Described silicon germanium lattice structure 95 it is formed without in drain region 933.
Perform step S4: arrange between described shallow trench isolation 92 and pull up transistor 96, described pull-up
Transistor 96 is PMOS semiconductor, described in pull up transistor 96 grid 961 be arranged on described silica-based
On substrate 91, described in pull up transistor 96 source area 962, drain region 963 be separately positioned on described grid
In the silicon-based substrate 91 of both sides, pole 961, described in pull up transistor 96 source area 962, drain region 963
Inside be not provided with described silicon germanium lattice structure 95, i.e. to described pull up transistor 96 source area 962, leakage
Polar region 963 does not carry out germanium injection technology and annealing process.
As those skilled in the art, it is readily appreciated that ground, at the PMOS of SRAM of the present invention
The source area 942 of device 94, drain region 943 arrange silicon germanium lattice structure 95, described PMOS can be increased
Compression in device 94 raceway groove, thus reach to improve the hole mobility of described PMOS device 94
Effect.In the present invention, described in pull up transistor 96 for PMOS semiconductor, and on described crystal pulling
Described embedded germanium silicon 95 it is not provided with so that described pull-up in the source area 962 of pipe 96, drain region 963
The transistor 96 compression on channel direction reduces, reduce described in pull up transistor 96 carrier
Mobility, increase described in pull up transistor 96 equivalent resistance, and then improve described static random and deposit
Reservoir write redundancy.
Referring to Fig. 4 (a), Fig. 4 (b), Fig. 4 (a) show the present invention and pulls up transistor firing current
Analog result figure before reduction.Fig. 4 (b) show the present invention pull up transistor firing current reduce after write
Enter the analog result figure of redundancy.From Fig. 4 (a), Fig. 4 (b), nonrestrictive enumerate, pin
To 45nm SRAM, pull up transistor described in reducing by 96 firing current after, described quiet
Write redundancy 10b of state random access memory relatively described in pull up transistor 96 firing current reduce before write
Enter redundancy 10a and improve 10mV.
In sum, the present invention is by arranging silicon Germanium lattice in the source area, drain region of PMOS device
Structure, increases the compression in described PMOS device raceway groove, thus reaches to improve described PMOS device
The effect of hole mobility；By being not provided with institute in the source area pulled up transistor described, drain region
State silicon germanium lattice structure so that described in pull up transistor compression on channel direction reduce, reduce institute
State the carrier mobility pulled up transistor, the equivalent resistance pulled up transistor described in increase, and then improve
Described SRAM write redundancy.
Those skilled in the art it will be appreciated that the most without departing from the spirit or scope of the present invention, can
The present invention is carried out various modifications and variations.Thus, if any amendment or modification fall into appended right and want
When asking in the protection domain of book and equivalent, it is believed that the present invention contains these amendment and modification.
Claims (6)
1. a SRAM, it is characterised in that described SRAM includes:
Silicon-based substrate, and interval is provided for the shallow trench isolation of electrical isolation in described silicon-based substrate；
Nmos device, is arranged between the isolation of described shallow trench, and the grid of described nmos device is arranged
In described silicon-based substrate, the source area of described nmos device, drain region are separately positioned on described grid
In the silicon-based substrate of both sides, and it is not provided with silicon Germanium lattice in source area, the drain region of described nmos device
Structure；
PMOS device, is arranged between the isolation of described shallow trench, and the grid of described PMOS device is arranged
In described silicon-based substrate, the source area of described PMOS device, drain region are separately positioned on described grid
In the silicon-based substrate of both sides, and described SiGe is set in the source area and drain region of described PMOS device
Lattice structure；
Pull up transistor, described in pull up transistor as PMOS semiconductor, and be arranged on described shallow trench every
Between from, described in the grid that pulls up transistor be arranged in described silicon-based substrate, described in pull up transistor it
Source area, drain region are separately positioned in the silicon-based substrate of described grid both sides, and crystal pulling on described
The source area of pipe, drain region are not provided with described silicon germanium lattice structure.
2. the method that the write redundancy of SRAM as claimed in claim 1 is improved,
It is characterized in that, described method includes:
Perform step S1: provide silicon-based substrate, and in described silicon-based substrate interval be provided for electrically every
From shallow trench isolation；
Perform step S2: nmos device, described NMOS device are set between described shallow trench is isolated
The grid of part is arranged in described silicon-based substrate, and the source area of described nmos device, drain region set respectively
Put in the silicon-based substrate of described grid both sides, in the source area, drain region of described nmos device not
Form described silicon germanium lattice structure；
Perform step S3: PMOS device, described PMOS device are set between described shallow trench is isolated
Grid be arranged in described silicon-based substrate, the source area of described PMOS device, drain region are respectively provided with
In the silicon-based substrate of described grid both sides, and set in the source area and drain region of described PMOS device
Put described silicon germanium lattice structure；
Perform step S4: arrange and pull up transistor between described shallow trench is isolated, described in pull up transistor
For PMOS semiconductor, described in the grid that pulls up transistor be arranged in described silicon-based substrate, described pull-up
The source area of transistor, drain region are separately positioned in the silicon-based substrate of described grid both sides, on described
Described silicon germanium lattice structure it is formed without in the source area of pull transistor, drain region.
3. the method that the write redundancy of SRAM as claimed in claim 2 is improved, it is special
Levy and be, described in pull up transistor source area, do not carry out germanium injection technology and annealing process in drain region,
To be formed without described silicon germanium lattice structure.
4. the method that the write redundancy of SRAM as claimed in claim 2 is improved, it is special
Levying and be, the preparation method of the silicon germanium lattice structure of described PMOS device farther includes:
In described PMOS device preparation process, before described source area, drain region injection technology,
Described PMOS device is carried out germanium injection, it is achieved source area, drain region decrystallized, to form an ultra shallow
Knot；
By annealing process, form germanium silicon lattice structure in described source area, drain region.
5. the method that the write redundancy of SRAM as claimed in claim 4 is improved, it is special
Levy and be, described to the source area of PMOS device of described SRAM, drain region are arranged
Silicon germanium lattice structure, increases the compression in described PMOS device raceway groove, thus it is described to reach raising
The hole mobility of PMOS device.
6. the method that the write redundancy of SRAM as claimed in claim 4 is improved, it is special
Levy and be, in the source area that pulls up transistor to described, drain region, be not provided with described silicon germanium lattice structure,
The compression on channel direction that pulls up transistor described in making reduces, the load pulled up transistor described in reduction
Stream transport factor, increase described in the equivalent resistance that pulls up transistor, and then improve described static random
Memory write redundancy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310491853.5A CN103579244B (en) | 2013-10-18 | 2013-10-18 | The method that SRAM and write redundancy thereof are improved |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310491853.5A CN103579244B (en) | 2013-10-18 | 2013-10-18 | The method that SRAM and write redundancy thereof are improved |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103579244A CN103579244A (en) | 2014-02-12 |
| CN103579244B true CN103579244B (en) | 2016-08-17 |
Family
ID=50050650
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310491853.5A Active CN103579244B (en) | 2013-10-18 | 2013-10-18 | The method that SRAM and write redundancy thereof are improved |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103579244B (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6984564B1 (en) * | 2004-06-24 | 2006-01-10 | International Business Machines Corporation | Structure and method to improve SRAM stability without increasing cell area or off current |
| KR100714479B1 (en) * | 2006-02-13 | 2007-05-04 | 삼성전자주식회사 | Semiconductor integrated circuit device and method for fabricating the same |
| DE102008045034B4 (en) * | 2008-08-29 | 2012-04-05 | Advanced Micro Devices, Inc. | Forward current adjustment for transistors fabricated in the same active region by locally providing an embedded strain-inducing semiconductor material in the active region |
| CN102655122A (en) * | 2012-04-16 | 2012-09-05 | 上海华力微电子有限公司 | Method for improving reading redundancy of SRAM (static random access memory) |
| CN102683289B (en) * | 2012-05-04 | 2014-04-02 | 上海华力微电子有限公司 | Method for improving writing redundancy of static random access memory |
| CN102738084B (en) * | 2012-05-04 | 2014-09-03 | 上海华力微电子有限公司 | Method for improving write redundancy of high SRAM (static random access memory) |
| CN102693944A (en) * | 2012-05-10 | 2012-09-26 | 上海华力微电子有限公司 | Method for improving read redundancy of static random access memory |
-
2013
- 2013-10-18 CN CN201310491853.5A patent/CN103579244B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN103579244A (en) | 2014-02-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8897067B2 (en) | Nonvolatile memory cells and methods of making such cells | |
| CN103515434B (en) | MOS transistor and forming method thereof, SRAM memory cell circuit | |
| CN102779837B (en) | Six-transistor static random access memory unit and manufacturing method thereof | |
| Lin et al. | Transient and Thermal Analysis on Disturbance Immunity for 4$\mathrm {F}^{2} $ Surrounding Gate 1T-DRAM With Wide Trenched Body | |
| CN103515435A (en) | MOS transistor and formation method thereof, and SRAM memory cell circuit | |
| CN106783856A (en) | Semiconductor devices | |
| Han et al. | Surround gate transistor with epitaxially grown Si pillar and simulation study on soft error and rowhammer tolerance for DRAM | |
| CN102738084B (en) | Method for improving write redundancy of high SRAM (static random access memory) | |
| CN103579244B (en) | The method that SRAM and write redundancy thereof are improved | |
| Damrongplasit et al. | Comparative study of uniform versus supersteep retrograde MOSFET channel doping and implications for 6-T SRAM yield | |
| CN105761740A (en) | Restoring circuit for improving negative bias temperature instability of memory control circuit | |
| CN104576536B (en) | A kind of semiconductor devices and its manufacture method and electronic installation | |
| CN102655122A (en) | Method for improving reading redundancy of SRAM (static random access memory) | |
| TWI615923B (en) | Non-volatile sram memory cell and non-volatile semiconductor memory device | |
| CN103579243B (en) | SRAM and write redundancy ameliorative way in embedded germanium silicon technology | |
| CN103514943B (en) | SRAM (Static Random Access Memory) cell as well as circuit and method of forming same | |
| CN103579118B (en) | The method that the write redundancy of SRAM is improved | |
| CN102610574B (en) | Method for improving reading redundancy rate of static random access memory | |
| CN102709252B (en) | Method for improving read-out redundancy of static random access memory | |
| CN100517720C (en) | Sram device and method for manufacturing the same | |
| CN102683289B (en) | Method for improving writing redundancy of static random access memory | |
| CN102683287B (en) | Method for improving write margin of static random access memory (SRAM) | |
| CN103999194B (en) | With the capacity coupled nonvolatile memory device of vertical drain-to-gate | |
| CN102693944A (en) | Method for improving read redundancy of static random access memory | |
| CN103579245A (en) | Static random access memory in hybrid orientation technology and method for improving write margin |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |