CN106158866A

CN106158866A - A kind of SRAM device and electronic installation thereof

Info

Publication number: CN106158866A
Application number: CN201510157884.6A
Authority: CN
Inventors: 张弓
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Corp
Priority date: 2015-04-03
Filing date: 2015-04-03
Publication date: 2016-11-23
Anticipated expiration: 2035-04-03
Also published as: CN106158866B

Abstract

The present invention provides a kind of SRAM device and electronic installation thereof, described SRAM device has the matrix structure being made up of multiple sram cells, described sram cell includes at least one PU transistor being connected in parallel and the 2nd PU transistor, a wherein said PU transistor includes that control gate, the grid of described control gate are connected to write word line WWL；Described 2nd PU transistor includes that work grid, described work grid are connected to wordline WL.According to the present invention, on the premise of not increasing the quantity of fin of the quantity of fin of PU transistor and increase PD transistor and PG transistor, while effectively the described SRAM device of lifting writes tolerance limit, improve data and keep stability, static noise margin is not affected.

Description

A kind of SRAM device and electronic installation thereof

Technical field

The present invention relates to semiconductor fabrication process, in particular to a kind of SRAM device and Its electronic installation.

Background technology

Static RAM (SRAM) as a kind of important memory device by extensively Be applied to during numeral designs with communicating circuit, itself because have that power consumption is little, that to read fast reading fast etc. is excellent Put and be widely used in the storage of data.

SRAM device has the matrix structure being made up of multiple sram cells, typically Sram cell includes six metal-oxide-semiconductors (i.e. having 6T structure) as shown in Figure 1A, wherein Pull-down transistor (PD) and store elementary cell to the control of bit line (Bit Line) for reading and writing System switch (PG) is usually NMOS, and pull up transistor (PU) is PMOS, a pair PU CMOS inverter is constituted with PD.In order to reduce the chip area that sram cell takies, During design sram cell domain, as shown in Figure 1B, the fin of usual PU, PD and PG (Fin) quantitative relation of 100 is PU:PD:PG=1:1:1.But, held by read-write noise Limit is analyzed and is understood, and the sram cell of PU:PD:PG=1:1:1 has relatively low static noise to be held Limit and write tolerance limit, in order to solve this problem, during design sram cell domain, needing β Value (PD/PG) is set as not less than 1.2, is set as γ-value (PG/PU) not less than 1.5. Prior art generally improves β value by the quantitative relation changing the fin of PU, PD and PG And γ-value, such as, design sram cell domain time, as shown in Figure 1 C, PU, PD and The quantitative relation of the fin 101 of PG is PU:PD:PG=1:2:2, and its drawback is to increase SRAM Chip area and the data of reduction sram cell that unit takies keep stability (α value (PU/PD) less than 1).

It is, therefore, desirable to provide a kind of sram cell, to solve the problems referred to above.

Summary of the invention

For the deficiencies in the prior art, the present invention provides a kind of SRAM device, described SRAM Device has the matrix structure being made up of multiple sram cells, and described sram cell includes At least one PU transistor being connected in parallel and the 2nd PU transistor, wherein said first PU transistor includes that control gate, the grid of described control gate are connected to write word line WWL；Institute State the 2nd PU transistor and include that work grid, described work grid are connected to wordline WL.

In one example, described sram cell also includes at least one PD transistor and at least One PG transistor.

In one example, the PU transistor being connected in parallel described in and the 2nd PU crystal The drain electrode of pipe and source electrode are connected respectively to drain power V_ddDrain electrode with described PD transistor.

In one example, described sram cell has 6T structure, in described 6T structure The quantitative relation of fin of PU transistor, PD transistor and PG transistor be PU:PD: PG=1:2:2 or PU:PD:PG=1:4:2.

In one example, as described WWL=1, described WL=0, α value is 1；When When described WWL=0, described WL=1, γ-value is 2.

In one example, a described PU transistor and described 2nd PU transistor are fin Sheet transistor npn npn, both share same fin.

In one embodiment, the present invention also provides for a kind of electronic installation, described electronic installation bag Include described SRAM device.

According to the present invention, do not increasing the quantity of fin of PU transistor and increasing PD crystal On the premise of the quantity of the fin of pipe and PG transistor, effectively promote described SRAM device While writing tolerance limit, improve data and keep stability.

Accompanying drawing explanation

The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Attached Figure shows embodiments of the invention and description thereof, is used for explaining the principle of the present invention.

In accompanying drawing:

Figure 1A is the circuit diagram of existing sram cell；

Figure 1B is the domain of the PU:PD:PG=1:1:1 of the sram cell shown in Figure 1A Schematic diagram；

Fig. 1 C is the domain of the PU:PD:PG=1:2:2 of the sram cell shown in Figure 1A Schematic diagram；

Fig. 2 is the circuit diagram of the sram cell that the present invention proposes；

Fig. 3 is the schematic diagram of the domain of the sram cell shown in Fig. 2；

Fig. 4 is the schematic diagram of another domain of the sram cell shown in Fig. 2.

Detailed description of the invention

In the following description, a large amount of concrete details is given to provide to the present invention more Understand thoroughly.It is, however, obvious to a person skilled in the art that the present invention Can be carried out without these details one or more.In other example, in order to keep away Exempt to obscure with the present invention, technical characteristics more well known in the art are not described.

In order to thoroughly understand the present invention, detailed step will be proposed in following description, in order to The SRAM device of explaination present invention proposition and electronic installation thereof.Obviously, the execution of the present invention It is not limited to the specific details that the technical staff of semiconductor applications is familiar with.The present invention's is preferable Embodiment is described in detail as follows, but in addition to these describe in detail, the present invention can also have Other embodiments.

It should be appreciated that term ought be used in this manual " to comprise " and/or " including " Time, it indicates and there is described feature, entirety, step, operation, element and/or assembly, but Do not preclude the presence or addition of other features one or more, entirety, step, operation, element, Assembly and/or combinations thereof.

[exemplary embodiment one]

It is PU:PD to solve the quantitative relation of the fin of existing PU, PD and PG: The 6T structure sram cell of PG=1:2:2 has poor data and keeps the problem of stability, The present invention proposes a kind of sram cell, as in figure 2 it is shown, with existing 6T structure SRAM Unit is compared (seeing Figure 1A), and PU transistor increases by a control gate, and this control gate is connected to The work grid of write word line WWL, PU transistor are still attached to wordline WL, PU transistor Drain electrode and source electrode be still connected respectively to drain power V_ddDrain electrode with PD transistor.

When designing sram cell domain as shown in Figure 2, as it is shown on figure 3, the fin of PU The quantity of 300 is 1, and the quantity of the fin 301 of PD and PG is 2；PU transistor increases One control gate, this control gate is connected to write word line WWL, and the work grid of PU transistor connect To wordline WL, when write word line there is high level i.e. WWL=1, wordline WL has low level I.e. during WL=0, the fin 300 of PU is divided into two, and being equivalent to quantity is 2, now, α Value (PU/PD) is 1, and this sram cell has good data and keeps stability；When writing When wordline has low level i.e. WWL=0, wordline WL has high level i.e. WL=1, PU The quantity of fin 300 remain as 1, now, γ-value (PG/PU) is 2, this SRAM Unit has higher writes tolerance limit.

Owing to the quantity of the fin 301 of PD and PG is 2, β value (PD/PG) is 1, Therefore, the static noise margin of this sram cell does not changes.In order to make this SRAM Unit has higher static noise margin, when designing this sram cell domain, such as Fig. 4 Shown in, make the quantity of the fin 402 of PD be 4, the quantity of the fin 403 of PG is 2, Now, β value (PD/PG) is 2, and the static noise of this sram cell can be substantially improved Tolerance limit.

According to the present invention, do not increasing the quantity of fin of PU and increasing the fin of PD and PG On the premise of the quantity of sheet, while effectively the described SRAM device of lifting writes tolerance limit, improve Data keep stability, the most not affect static noise margin.

Conventional fin transistors manufacturing process is used to form this sram cell, as example, Its processing step includes: providing Semiconductor substrate, the constituent material of Semiconductor substrate can use Unadulterated monocrystal silicon, monocrystal silicon etc. doped with impurity；Formed on a semiconductor substrate and firmly cover Film layer, form that described hard mask layer can use that those skilled in the art are familiar with various suitably Technique, such as chemical vapor deposition method, the material of described hard mask layer can be nitride, Preferably silicon nitride；Pattern described hard mask layer, formed and be used for etching Semiconductor substrate with at it The mask of upper formation fin；Etching Semiconductor substrate is to be formed on fin；Employing wet method is lost Carving technology removes described mask；Isolation structure is formed at the two ends of fin；Two ends shape at fin Become epitaxial material as source/drain；Grid structure, grid are formed in the both sides of fin and top Electrode structure includes that the gate dielectric of stacking from bottom to top, gate material layers and grid are sheltered firmly Layer；The offset side wall against grid structure is formed in grid structure both sides；Removal is positioned at fin two The offset side wall of side；Sequentially form on a semiconductor substrate and there is the contact that can produce stress characteristics Hole etching stopping layer and interlayer dielectric layer, perform cmp to expose the top of grid structure Portion；Remove grid structure, the groove stayed is formed high k-metal gate structure, this knot Structure includes the high k dielectric layer of stacking from bottom to top, cover layer, workfunction layers, barrier layer And metal material layer；Form another interlayer dielectric layer, then, shape in above-mentioned interlayer dielectric layer Become to connect top and the contact hole of pole, described source/drain region of described metal gate structure, pass through Described contact hole, in the top of the described metal gate structure exposed and pole, described source/drain region Upper formation self-aligned silicide, filler metal (usually tungsten) is the company of being formed in described contact hole The interconnecting metal layer connecing enforcement back end fabrication and formed connects with described self-aligned silicide Touch plug；Form multiple interconnecting metal layer, generally use dual damascene process to complete；Formed Metal pad, wire bonding during for implementing device encapsulation.

[exemplary embodiment two]

The present invention also provides for a kind of electronic installation, and it includes such as exemplary embodiment of the present one institute The SRAM device described.Described electronic installation can be mobile phone, panel computer, notebook Computer, net book, game machine, television set, VCD, DVD, navigator, photographing unit, Video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment, it is also possible to It is any intermediate products including described semiconductor device.Described electronic installation, owing to employing Described semiconductor device, thus there is better performance.

The present invention is illustrated by above-described embodiment, but it is to be understood that, above-mentioned Embodiment is only intended to citing and descriptive purpose, and is not intended to limit the invention to described Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that the present invention not office It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repair Change, within these variants and modifications all fall within scope of the present invention.The present invention's Protection domain is defined by the appended claims and equivalent scope thereof.

Claims

1. a SRAM device, described SRAM device has by multiple sram cells The matrix structure constituted, described sram cell includes that at least one PU being connected in parallel is brilliant Body pipe and the 2nd PU transistor, a wherein said PU transistor includes control gate, described The grid of control gate is connected to write word line WWL；Described 2nd PU transistor includes work grid, Described work grid are connected to wordline WL.

SRAM device the most according to claim 1, it is characterised in that described SRAM Unit also includes at least one PD transistor and at least one PG transistor.

SRAM device the most according to claim 2, it is characterised in that described parallel connection The PU transistor connected and the drain electrode of the 2nd PU transistor and source electrode are connected respectively to Lou Pole power supply V_ddDrain electrode with described PD transistor.

SRAM device the most according to claim 2, it is characterised in that described SRAM Unit has 6T structure, PU transistor, PD transistor and the PG in described 6T structure The quantitative relation of the fin of transistor is PU:PD:PG=1:2:2 or PU:PD: PG=1:4:2.

SRAM device the most according to claim 1, it is characterised in that when described When WWL=1, described WL=0, α value is 1；As described WWL=0, described WL=1 Time, γ-value is 2.

SRAM device the most according to claim 1, it is characterised in that described first PU transistor and described 2nd PU transistor are fin type transistors, and both share same fin Sheet.

7. an electronic installation, described electronic installation includes such as institute arbitrary in claim 1-6 The SRAM device stated.