CN105845680B - A kind of semiconductor devices and its manufacturing method and electronic device - Google Patents
A kind of semiconductor devices and its manufacturing method and electronic device Download PDFInfo
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- CN105845680B CN105845680B CN201510019318.9A CN201510019318A CN105845680B CN 105845680 B CN105845680 B CN 105845680B CN 201510019318 A CN201510019318 A CN 201510019318A CN 105845680 B CN105845680 B CN 105845680B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 86
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 230000005540 biological transmission Effects 0.000 claims abstract description 69
- 238000000034 method Methods 0.000 claims description 32
- 239000000758 substrate Substances 0.000 claims description 26
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- 239000000463 material Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
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- 238000001259 photo etching Methods 0.000 description 2
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- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- 230000003068 static effect Effects 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0891—Source or drain regions of field-effect devices of field-effect transistors with Schottky gate
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66848—Unipolar field-effect transistors with a Schottky gate, i.e. MESFET
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
- H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
The present invention provides a kind of semiconductor devices and its manufacturing method and electronic device, is related to technical field of semiconductors.The semiconductor devices includes sram cell, wherein the sram cell includes: as the first PMOS transistor and the second PMOS transistor, the first NMOS transistor as pull-down transistor and the second NMOS transistor to pull up transistor and as the third NMOS transistor and the 4th NMOS transistor of transmission gate transistor, wherein, in each transmission gate transistor, source electrode and drain electrode is relative to the asymmetric setting of gate structure.Semiconductor devices of the invention due to include sram cell in transmission gate transistor source electrode and drain electrode relative to the asymmetric setting of gate structure, have better read noise tolerance and write noise margin compared with the existing technology.For manufacturing above-mentioned semiconductor device, semiconductor devices obtained equally has the above advantages the manufacturing method of semiconductor devices of the invention.Electronic device of the invention includes above-mentioned semiconductor device, is equally had the above advantages.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacturing method and electronics
Device.
Background technique
As using electronic communication technology as the continuous development of the Modern high-tech industry of representative, world's IC industry is total
For the output value to develop per year over 30% speed, Static RAM (SRAM) is extensive as a kind of important memory device
Applied in number and communicating circuit design.SRAM is a kind of important component in logic circuit, because having small power consumption, is read
The advantages that speed is high and the storage for being widely used in data.
A kind of circuit structure of existing 6T type sram cell is as shown in Figure 1A, including 6 fin (Fin) transistors, i.e.,
First PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, the second NMOS transistor N2, the 3rd NMOS
Transistor N3, the 4th NMOS transistor N4.Wherein, the first PMOS transistor P1 and the first NMOS transistor N1 constitutes the first CMOS
Transistor 101 (that is, the drain electrode of the first PMOS transistor P1 is connected with the drain electrode of the first NMOS transistor N1, the first PMOS crystal
The grid of pipe P1 is connected with the grid of the first NMOS transistor N1), the second PMOS transistor P2 and the second NMOS transistor N2 structure
At the second CMOS transistor 102 (that is, the drain electrode of the second PMOS transistor P2 is connected with the drain electrode of the second NMOS transistor N2,
The grid of two PMOS transistor P2 is connected with the grid of the second NMOS transistor N2).The input terminal of first CMOS transistor 101 with
The output end of second CMOS transistor 102 is connected, the output end of the first CMOS transistor 101 and the second CMOS transistor 102
Input terminal is connected；The source electrode of the source electrode of first PMOS transistor P1 and the second PMOS transistor P2 are connected to supply voltage Vdd,
The source electrode of the source electrode of first NMOS transistor N1 and the second NMOS transistor N2 are connected to supply voltage Vss.
Wherein, the source electrode of third NMOS transistor N3 is connected with bit line BL, the drain electrode of drain electrode and the first PMOS transistor P1
It is connected, grid is connected with wordline WL.The source electrode of 4th NMOS transistor N4 is connected with the drain electrode of the second PMOS transistor, grid with
Wordline WL is connected, drain electrode and another bit lineIt is connected.
In the circuit structure of above-mentioned sram cell, P1 and P2 are to pull up transistor (PU), and N1 and N2 are lower crystal pulling
Pipe, N3 and N4 are transmission gate transistor (PG).Wherein the quantity ratio of PU, PD and PG are 1:1:1.Wherein, transmission gate transistor N3
It is as shown in Figure 1B with the schematic domain structure of N4, including source electrode 201, drain electrode 202 and gate structure 203, wherein 201 He of source electrode
Drain electrode 202 is symmetrical arranged in the two sides of gate structure 203.That is, source electrode 201 and drain electrode 202 shape is identical and size also phase
Together.
In the sram cell, since β ratio is PD/PG=1, thus lead to read noise tolerance (the read noise of difference
margin).And according to using planar structure transistor sram cell data, β ratio should be not less than 1.2.At this
In sram cell, due to γ ratio (γ ratio) be PG/PU=1, thus cause difference write noise margin (write
margin).And according to using planar structure transistor sram cell data, γ ratio should be not less than 1.5.Namely
It says, the sram cell of existing above structure has that write capability is poor because γ ratio is relatively low.
It is more existing for improve α ratio, the method for β ratio or γ ratio and its there are the problem of it is as follows: (1) pass through
The quantity of selection fin transistor is set as 1 to improve α ratio, β ratio or γ ratio, such as by the quantity ratio of PU, PD and PG:
2:1 or 1:2:2 or 1:2:3 etc..However, this method will cause area loss, and it will lead to the holding stability at the end Vss
The loss of (Hold stability), α ratio (PU/PD) < 1.(2) improve α ratio by optimization tri- kinds of devices of PU, PD and PG
Rate, β ratio or γ ratio.However, this method can make technique become extremely complex.(3) by being set for tri- kinds of devices of PU, PD and PG
Different injection conditions is set to improve α ratio, β ratio or γ ratio.But this method will lead to logical device and can not match
The target of SRAM device causes to need to increase more exposure masks.(4) the crucial ruler of polysilicon is adjusted by exposure mask or photoetching process
It is very little so as to improve α ratio, β ratio or γ ratio.However, this method will cause the process window loss of photoetching process.
It can be seen that the sram cell of existing above structure causes read noise tolerance poor because β ratio is relatively low
And there is a problem of that write capability is poor because γ ratio is relatively low, and existing various methods can not effectively solve it is above-mentioned
Problem.Therefore, in order to solve the above technical problems, it is necessary to propose a kind of new sram cell, energy is write with improve sram cell
Power.
Summary of the invention
In view of the deficiencies of the prior art, the present invention proposes a kind of semiconductor devices and its manufacturing method and electronic device, can
So that sram cell better read noise tolerance (read noise margin) and writes noise with having compared with the existing technology
Tolerance (write margin).
One embodiment of the present of invention provides a kind of semiconductor devices comprising sram cell, wherein the sram cell
It include: as the first PMOS transistor and the second PMOS transistor to pull up transistor, as the first NMOS of pull-down transistor
Transistor and the second NMOS transistor and third NMOS transistor and the 4th NMOS transistor as transmission gate transistor,
Wherein, in each transmission gate transistor, source electrode and drain electrode is relative to the asymmetric setting of gate structure.
It in an example, include source electrode, drain and gate as the third NMOS transistor of transmission gate transistor
Structure, wherein the source electrode exists with the gate structure to be overlapped, and overlapping, institute is not present with the gate structure for the drain electrode
State that source electrode is identical with the shape of the drain electrode, and the area of the source electrode is greater than the area of the drain electrode.
It in an example, include source electrode, drain and gate as the 4th NMOS transistor of transmission gate transistor
Structure, wherein the drain electrode exists with the gate structure to be overlapped, and there is no overlapping, institutes for the source electrode and the gate structure
State that source electrode is identical with the shape of the drain electrode, and the area of the source electrode is less than the area of the drain electrode.
In an example, grid knot of the source electrode and drain electrode of the transmission gate transistor prior to the transmission gate transistor
It is configured to, also, the source electrode and drain electrode of the transmission gate transistor is to be formed respectively by doping in situ.
In an example, described pull up transistor, the pull-down transistor and the transmission gate transistor be fin
Field effect transistor.
Illustratively, in the sram cell, first PMOS transistor and the first NMOS transistor constitute first
CMOS transistor, second PMOS transistor and second NMOS transistor constitute the second CMOS transistor, wherein described
The input terminal of first CMOS transistor is connected with the output end of second CMOS transistor, first CMOS transistor it is defeated
Outlet is connected with the input terminal of second CMOS transistor；The source electrode of first PMOS transistor and the 2nd PMOS are brilliant
The source electrode of body pipe is connected to supply voltage Vdd, the source electrode of first NMOS transistor and second NMOS transistor
Source electrode is connected to supply voltage Vss；The source electrode of the third NMOS transistor is connected with bit line, the third NMOS transistor
Drain electrode be connected with the drain electrode of first PMOS transistor, the grid of the third NMOS transistor is connected with wordline；It is described
The source electrode of 4th NMOS transistor is connected with the drain electrode of second PMOS transistor, the grid of the 4th NMOS transistor with
Wordline is connected, and the drain electrode of the 4th NMOS transistor is connected with another bit line.
Another embodiment of the present invention provides a kind of manufacturing method of semiconductor devices, the semiconductor devices includes
Sram cell, the sram cell include the transmission gate transistor of N-type, the method comprise the steps that
Step S101: it is formed in the first electrode position tool of the transmission gate transistor of quasi- formation on a semiconductor substrate
There is the first mask layer of the first opening, is performed etching using first mask layer with formation and institute in the semiconductor substrate
State the corresponding first groove of the first opening；
Step S102: the first electrode that the transmission gate transistor is formed in the first groove is entrained in by original position；
Step S103: it is formed in the second electrode position of the transmission gate transistor of quasi- formation on the semiconductor substrate
The second mask layer with the second opening is set, is performed etching using second mask layer to be formed in the semiconductor substrate
Second groove corresponding with second opening；
Step S104: being entrained in the second electrode that the transmission gate transistor is formed in the second groove by original position,
Wherein the area of the second electrode is greater than the area of the first electrode；
Step S105: forming gate structure on the semiconductor substrate, wherein the gate structure and first electricity
Pole exists overlapping and there is no overlapping with the second electrode；
Wherein, the first electrode is source electrode, and the second electrode is drain electrode；Alternatively, the first electrode is drain electrode, institute
Stating second electrode is source electrode.
Illustratively, the source electrode is identical with the shape of the drain electrode.
Illustratively, in the step S101, before forming first mask layer, to the semiconductor substrate into
Row etching is to form fin structure.
Illustratively, further include following steps between the step S104 and the step S105:
There are the first electrode and the side of the second electrode to carry out at planarization the formation of the semiconductor substrate
Reason；
And/or carry out thermal anneal process.
Yet another embodiment of the present invention provides a kind of electronic device, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part, wherein the semiconductor devices includes sram cell, the sram cell includes: as upper crystal pulling
The first PMOS transistor and the second PMOS transistor of pipe, the first NMOS transistor as pull-down transistor and the 2nd NMOS are brilliant
Body pipe and third NMOS transistor and the 4th NMOS transistor as transmission gate transistor, wherein in each transmission
In door transistor, source electrode and drain electrode is relative to the asymmetric setting of gate structure.
The source electrode and drain electrode phase of semiconductor devices of the invention due to the transmission gate transistor in included sram cell
Setting asymmetric for gate structure, therefore there is better read noise tolerance compared with the existing technology and write noise margin.This
For manufacturing above-mentioned semiconductor device, semiconductor devices obtained equally has above-mentioned the manufacturing method of the semiconductor devices of invention
Advantage.Electronic device of the invention includes above-mentioned semiconductor device, thus is equally had the above advantages.
Detailed description of the invention
Following drawings of the invention is incorporated herein as part of the present invention for the purpose of understanding the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing:
Figure 1A is a kind of existing schematic diagram of the circuit structure of sram cell；
Figure 1B is the schematic diagram of the domain structure of the transmission gate transistor in existing sram cell；
Fig. 2A is the schematic diagram of the circuit structure of the sram cell in the semiconductor devices of one embodiment of the present of invention；
Fig. 2 B is the version of a transmission gate transistor of sram cell in the semiconductor devices of one embodiment of the present of invention
The schematic diagram of graph structure；
Fig. 2 C is another transmission gate transistor of sram cell in the semiconductor devices of one embodiment of the present of invention
The schematic diagram of domain structure；
The system of Fig. 3 A, Fig. 3 B, Fig. 3 C, Fig. 3 D, the semiconductor devices that Fig. 3 E and Fig. 3 F are another embodiment of the invention
Make the schematic diagram of the structure of the correlation step formation of method.
Specific embodiment
In the following description, a large amount of concrete details are given so as to provide a more thorough understanding of the present invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid confusion with the present invention, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.On the contrary, provide these embodiments will make it is open thoroughly and completely, and will fully convey the scope of the invention to
Those skilled in the art.
The purpose of term as used herein is only that description specific embodiment and not as limitation of the invention.Make herein
Used time, " one " of singular, "one" and " described/should " be also intended to include plural form, unless the context clearly indicates separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related listed item and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution of the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however other than these detailed descriptions, this
Invention can also have other embodiments.
The embodiment of the present invention provides a kind of semiconductor devices comprising sram cell.In the following, having referring to Fig. 2A and Fig. 2 B
Body describes the sram cell of the embodiment of the present invention.Wherein, Fig. 2A is in the semiconductor devices of one embodiment of the present of invention
The schematic diagram of the circuit structure of sram cell；Fig. 2 B is one of sram cell in the semiconductor devices of one embodiment of the present of invention
The schematic diagram of the domain structure of a transmission gate transistor；Fig. 2 C is that SRAM is mono- in the semiconductor devices of one embodiment of the present of invention
The schematic diagram of the domain structure of another transmission gate transistor of member.
As shown in Figure 2 A, the circuit structure of sram cell included by the semiconductor devices of one embodiment of the present of invention and existing
There is technology (Figure 1A) identical, is 6T type sram cell.The circuit structure of the sram cell is as shown in Figure 2 A, including 6 fin
(Fin) transistor, i.e. the first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, the 2nd NMOS crystal
Pipe N2, third NMOS transistor N3, the 4th NMOS transistor N4.Wherein, the first PMOS transistor P1 and the first NMOS transistor
N1 constitutes the first CMOS transistor 101 (that is, the drain electrode and the drain electrode phase of the first NMOS transistor N1 of the first PMOS transistor P1
Even, the grid of the first PMOS transistor P1 is connected with the grid of the first NMOS transistor N1), the second PMOS transistor P2 and second
NMOS transistor N2 constitutes the second CMOS transistor 102 (that is, the drain electrode of the second PMOS transistor P2 and the second NMOS transistor N2
Drain electrode be connected, the grid of the second PMOS transistor P2 is connected with the grid of the second NMOS transistor N2).First CMOS transistor
101 input terminal is connected with the output end of the second CMOS transistor 102, the output end and second of the first CMOS transistor 101
The input terminal of CMOS transistor 102 is connected；The source electrode of the source electrode of first PMOS transistor P1 and the second PMOS transistor P2 connect
It is connected to supply voltage Vdd, the source electrode of the source electrode of the first NMOS transistor N1 and the second NMOS transistor N2 are connected to power supply electricity
Press Vss.
Wherein, the source electrode of third NMOS transistor N3 is connected with bit line BL, the drain electrode of drain electrode and the first PMOS transistor P1
It is connected, grid is connected with wordline WL.The source electrode of 4th NMOS transistor N4 is connected with the drain electrode of the second PMOS transistor, grid with
Wordline WL is connected, drain electrode and another bit lineIt is connected.
In the circuit structure of above-mentioned sram cell, P1 and P2 are to pull up transistor (PU), and N1 and N2 are lower crystal pulling
Pipe, N3 and N4 are transmission gate transistor (PG).Wherein the quantity ratio of PU, PD and PG are 1:1:1.
In the sram cell of the present embodiment and one of the prior art the difference is that, in transmission gate transistor N3 and N4
In, and not as good as the prior art (as shown in Figure 1B), source electrode and drain electrode is symmetrical arranged in the two sides of gate structure.Namely
It says, the respective source electrode and drain electrode of transmission gate transistor N3 and transmission gate transistor N4 are non-relative to its respective gate structure
It is symmetrical arranged.
Specifically, in the structure of transmission gate transistor of the present embodiment (N3 or N4) a kind of, in source electrode and drain electrode one
In the presence of overlapping, the other of source electrode and drain electrode then (exists centainly with gate structure there is no overlapping for person and gate structure
Distance).It is overlapped for example, source electrode exists with gate structure, draining, it is overlapping to be not present with gate structure, or in contrast.
Further, in a kind of structure of transmission gate transistor of the present embodiment, the shape of source electrode and drain electrode is still kept
It is identical.But there is the area of overlapping source electrode or drain electrode greater than there is no overlapping drain electrodes or source with grid with gate structure
The area of pole.
Illustratively, in the semiconductor devices of one embodiment of the present of invention in sram cell, a transmission gate crystal
The domain structure of pipe is as shown in Figure 2 B, and the domain structure of another transmission gate transistor is then as shown in Figure 2 C.
As shown in Figure 2 B, the structure of a transmission gate transistor (such as N3) includes source electrode 301, drain electrode 302 and grid knot
Structure 303, wherein source electrode 301 and gate structure 303 exist overlapping, and there is no overlapping with gate structure 303 for drain electrode 302.Wherein, source
Pole 301 and the shape of drain electrode 302 are identical (such as being rectangle), and the area of source electrode 301 is greater than the area of drain electrode 302.
As shown in Figure 2 C, the structure of another transmission gate transistor (such as N4) includes source electrode 401, drain electrode 402 and grid
Structure 403 overlaps wherein drain electrode 402 exists with gate structure 403, and there is no overlapping for source electrode 401 and gate structure 403.Wherein,
Source electrode 401 and the shape of drain electrode 402 are identical (such as being rectangle), and the area of source electrode 401 is less than the area of drain electrode 402.
In the present embodiment, since the source electrode and drain electrode of transmission gate transistor N3 and N4 are relative to its respective gate structure
Asymmetric setting, thus transmission gate transistor N3 and N4 compared with the existing technology in structure have different firing currents
(Ion), and then the β ratio and γ ratio of sram cell can be improved, making sram cell compared with the existing technology has preferably
Read noise tolerance and write noise margin.
For example, the electric current Ion from small drain electrode 301 to big source electrode 302 can be than existing in the structure shown in Fig. 3 B
Technology improves 5%；In the structure shown in Fig. 3 C, the electric current Ion from big drain electrode 402 to small source electrode 401 can be than existing
Technology reduces by 40%.Emulation discovery is carried out to using the sram cell of the two structures, the sram cell is compared with the existing technology
With better read noise tolerance and write noise margin.Wherein, β ratio is improved to 1.4, γ ratio phase from 1 compared with the prior art
1.05 are improved to from 1 for the prior art.
In short, source electrode of the semiconductor devices of the present embodiment due to the transmission gate transistor in included sram cell
With drain electrode relative to the asymmetric setting of gate structure, therefore there is better read noise tolerance compared with the existing technology and write noise
Tolerance.
Another embodiment of the present invention provides a kind of manufacturing methods of semiconductor devices, for manufacturing above-mentioned semiconductor
Device.Wherein, Fig. 3 A to Fig. 3 F is the correlation step shape of the manufacturing method of the semiconductor devices of another embodiment of the invention
At structure schematic diagram.This method relates generally to the manufacturing process of transmission gate transistor in sram cell.
As shown in Fig. 3 A to Fig. 3 F, the manufacturing method of the semiconductor devices of the present embodiment includes the following steps:
Step A1: semiconductor substrate 500 is provided, semiconductor substrate 500 is performed etching to form fin structure 5001, such as
Shown in Fig. 3 A.
Wherein, semiconductor substrate 500 can be the various feasible linings such as monocrystalline substrate, multicrystalline silicon substrate, SOI substrate
Bottom.The method for forming fin structure 5001 can be the existing various feasible methods such as dry etching.By forming fin knot
Structure 5001, can make the transistor to be formed is fin FET.
Step A2: the source electrode position that the transmission gate transistor of quasi- formation is formed in semiconductor substrate 500 has first
First mask layer 600 of opening, is performed etching using the first mask layer 600 to be formed in semiconductor substrate and be opened with described first
The corresponding first groove 5010 of mouth, as shown in Figure 3B.
Wherein, the first mask layer 600 can be various feasible structures, such as the first mask layer 600 includes silicon nitride layer
With photoresist layer disposed thereon.When forming first groove 5010, used lithographic method can be dry etching, wet process
The various feasible methods such as etching.
Step A3: by the source electrode 501 in situ for being entrained in formation transmission gate transistor in the first groove 5010, such as scheme
Shown in 3C.
Wherein, material used in doping in situ may include silicon nitride or other suitable materials.
Step A4: the drain locations that the transmission gate transistor of quasi- formation is formed in semiconductor substrate 500 have second
Second mask layer 700 of opening, is performed etching using the second mask layer 700 to be formed in semiconductor substrate and be opened with described second
The corresponding second groove 5020 of mouth, as shown in Figure 3D.
Wherein, the second mask layer 700 can be various feasible structures, such as the second mask layer 700 includes silicon nitride layer
With photoresist layer disposed thereon.When forming second groove 5020, used lithographic method can be dry etching, wet process
The various feasible methods such as etching.
Step A5: by the drain electrode 502 in situ for being entrained in formation transmission gate transistor in the second groove 5020, wherein
The area of drain electrode 502 is greater than the area of source electrode 501, as shown in FIGURE 3 E.
Wherein, material used in doping in situ may include silicon nitride or other suitable materials.
Step A6: forming gate structure 503 in semiconductor substrate 500, and wherein gate structure 503 and drain electrode 502 exist
It overlaps and is not present and overlaps with source electrode 501, as illustrated in Figure 3 F.
Illustratively, gate structure 503 may include grid and gate lateral wall etc..The method for forming gate structure 503,
Existing various feasible methods can be used, are not defined herein.
In addition, can also include the following steps: between the step A5 and step A6 of the present embodiment
There is the side of source electrode and drain electrode to carry out planarization process the formation of semiconductor substrate 500；
And/or carry out thermal anneal process.
Wherein, planarization process can guarantee that the gate structure being subsequently formed has better yield.Thermal anneal process is then
The ion distribution in the source electrode and drain electrode formed through doping in situ can be improved, improve the performance of semiconductor devices.
About the specific structure of finally formed transmission gate transistor and the specific structure of semiconductor devices, it is referred to
The embodiment of the structure about semiconductor devices of front, no longer repeats one by one herein.
In the above-described embodiments, drain electrode can also be formed in step A3, source electrode is formed in step A5, i.e., in most end form
At transmission gate transistor in, the area of source electrode is greater than the area of drain electrode.It is brief for description, by what is formed in step A3
Source electrode or drain electrode are referred to as first electrode, and the drain electrode or source electrode formed in step A5 is referred to as second electrode.Wherein, in the biography of formation
In defeated door transistor, the area of second electrode is greater than the area of first electrode, and gate structure domain second electrode exist it is overlapping but
(that is, the source electrode and drain electrode of transmission gate transistor is relative to the asymmetric setting of its gate structure) is not overlapped with first electrode.
During executing above-mentioned steps A1 to A5, it is formed simultaneously transmission gate transistor N3 and N4.Also, it is usually also same
When form other transistors of sram cell, such as the P1 and P2 that pulls up transistor, pull-down transistor N1 and N2.Further, it is also possible to
Be formed simultaneously in semiconductor devices other devices, such as transistor, diode etc. in addition to sram cell, herein and without
It limits.The specific implementation of other component is formed simultaneously into A5 about step A1, those skilled in the art is referring to existing
Technology may be implemented, and details are not described herein again.
The semiconductor devices of the manufacturing method manufacture of semiconductor devices according to an embodiment of the present invention, due to included
The source electrode and drain electrode of transmission gate transistor in sram cell is relative to the asymmetric setting of gate structure, therefore relative to existing skill
Art has better read noise tolerance and writes noise margin.
Yet another embodiment of the present invention provides a kind of electronic device, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, which is semiconductor devices as described above.The electronic building brick can be point
Any electronic building bricks such as vertical device, integrated circuit.
Illustratively, the semiconductor devices includes sram cell, wherein the sram cell includes: as upper crystal pulling
The first PMOS transistor and the second PMOS transistor of pipe, the first NMOS transistor as pull-down transistor and the 2nd NMOS are brilliant
Body pipe and third NMOS transistor and the 4th NMOS transistor as transmission gate transistor, wherein in each transmission
In door transistor, source electrode and drain electrode is relative to the asymmetric setting of gate structure.
The electronic device of the present embodiment can be mobile phone, tablet computer, laptop, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment can also be
Any intermediate products including above-mentioned semiconductor device.
The electronic device of the embodiment of the present invention due to having used above-mentioned semiconductor devices, thus equally has above-mentioned excellent
Point.
The present invention has been explained by the above embodiments, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, is not intended to limit the invention to the scope of the described embodiments.Furthermore those skilled in the art
It is understood that the present invention is not limited to the above embodiments, introduction according to the present invention can also be made more kinds of member
Variants and modifications, all fall within the scope of the claimed invention for these variants and modifications.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of semiconductor devices, which is characterized in that including sram cell, wherein the sram cell includes: as upper crystal pulling
The first PMOS transistor (P1) and the second PMOS transistor (P2) of body pipe, the first NMOS transistor as pull-down transistor
(N1) and the second NMOS transistor (N2) and brilliant as the third NMOS transistor (N3) of transmission gate transistor and the 4th NMOS
Body pipe (N4), wherein in each transmission gate transistor, source electrode and drain electrode is relative to the asymmetric setting of gate structure, institute
The source electrode and the drain electrode for stating transmission gate transistor are formed prior to the gate structure of the transmission gate transistor, also, institute
The source electrode and the drain electrode for stating transmission gate transistor are to be formed respectively by doping in situ, the source electrode and the drain electrode
Shape is identical, area is different.
2. semiconductor devices as described in claim 1, which is characterized in that the 3rd NMOS as transmission gate transistor is brilliant
Body pipe includes source electrode (301), drain electrode (302) and gate structure (303), wherein the source electrode and the gate structure have friendship
Folded, the drain electrode is not present with the gate structure to be overlapped, and the area of the source electrode is greater than the area of the drain electrode.
3. semiconductor devices as described in claim 1, which is characterized in that the 4th NMOS as transmission gate transistor is brilliant
Body pipe includes source electrode (401), drain electrode (402) and gate structure (403), wherein the drain electrode exists with the gate structure hands over
Folded, the source electrode and the gate structure are not present and overlap, and the area of the source electrode is less than the area of the drain electrode.
4. semiconductor devices as described in claim 1, which is characterized in that it is described pull up transistor, the pull-down transistor with
And the transmission gate transistor is fin FET.
5. semiconductor devices as described in claim 1, which is characterized in that in the sram cell, the first PMOS is brilliant
Body pipe and the first NMOS transistor constitute the first CMOS transistor (101), second PMOS transistor and the 2nd NMOS
Transistor constitutes the second CMOS transistor (102), wherein the input terminal of first CMOS transistor and the 2nd CMOS are brilliant
The output end of body pipe is connected, and the output end of first CMOS transistor is connected with the input terminal of second CMOS transistor；
The source electrode of first PMOS transistor and the source electrode of second PMOS transistor are connected to supply voltage Vdd, institute
The source electrode of the source electrode and second NMOS transistor of stating the first NMOS transistor is connected to supply voltage Vss；
The source electrode of the third NMOS transistor is connected with bit line, the drain electrode of the third NMOS transistor and the first PMOS
The drain electrode of transistor is connected, and the grid of the third NMOS transistor is connected with wordline；
The source electrode of 4th NMOS transistor is connected with the drain electrode of second PMOS transistor, the 4th NMOS transistor
Grid be connected with wordline, the drain electrode of the 4th NMOS transistor is connected with another bit line.
6. a kind of manufacturing method of semiconductor devices, which is characterized in that the semiconductor devices includes sram cell, the SRAM
Unit includes the transmission gate transistor of N-type, the method comprise the steps that
Step S101: the first electrode position of the transmission gate transistor of quasi- formation is formed on semiconductor substrate (500)
The first mask layer (600) with the first opening, is performed etching in the semiconductor substrate using first mask layer
Form first groove (5010) corresponding with first opening；
Step S102: the first electrode that the transmission gate transistor is formed in the first groove is entrained in by original position；
Step S103: it is formed in the second electrode position tool of the transmission gate transistor of quasi- formation on the semiconductor substrate
There is the second mask layer (700) of the second opening, is performed etching using second mask layer with the shape in the semiconductor substrate
At second groove (5020) corresponding with second opening；
Step S104: being entrained in the second electrode (502) that the transmission gate transistor is formed in the second groove by original position,
Wherein the area of the second electrode is greater than the area of the first electrode, the shape of the first electrode and the second electrode
It is identical；
Step S105: forming gate structure (503) on the semiconductor substrate, wherein the gate structure and second electricity
Pole exists overlapping and there is no overlapping with the first electrode；
Wherein, the first electrode is source electrode, and the second electrode is drain electrode；Alternatively, the first electrode is drain electrode, described the
Two electrodes are source electrode.
7. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that in the step S101, in shape
Before first mask layer, the semiconductor substrate is performed etching to form fin structure (5001).
8. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that in the step S104 and the step
Further include following steps between rapid S105:
There is the side of the first electrode and the second electrode to carry out planarization process the formation of the semiconductor substrate；
And/or carry out thermal anneal process.
9. a kind of electronic device, which is characterized in that including semiconductor devices and the electronics group being connected with the semiconductor devices
Part, wherein the semiconductor devices includes sram cell, wherein the sram cell includes: as first to pull up transistor
PMOS transistor and the second PMOS transistor, the first NMOS transistor as pull-down transistor and the second NMOS transistor, with
And third NMOS transistor and the 4th NMOS transistor as transmission gate transistor, wherein in each transmission gate crystal
Guan Zhong, source electrode and drain electrode is relative to the asymmetric setting of gate structure, the source electrode of the transmission gate transistor and the drain electrode
Gate structure prior to the transmission gate transistor is formed, also, the source electrode of the transmission gate transistor and the drain electrode
It is to be formed respectively by doping in situ, the source electrode is identical with the shape of the drain electrode, area is different.
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| US15/947,525 US10431588B2 (en) | 2015-01-14 | 2018-04-06 | Semiconductor device, related manufacturing method, and related electronic device |
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| CN108987399A (en) * | 2017-06-05 | 2018-12-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and its manufacturing method |
| CN115942739B (en) * | 2023-01-19 | 2023-07-14 | 合肥晶合集成电路股份有限公司 | SRAM device and manufacturing method thereof |
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| US5631863A (en) * | 1995-02-14 | 1997-05-20 | Honeywell Inc. | Random access memory cell resistant to radiation induced upsets |
| JP3279453B2 (en) * | 1995-03-20 | 2002-04-30 | シャープ株式会社 | Non-volatile random access memory |
| US6674101B2 (en) * | 2001-06-01 | 2004-01-06 | Furukawa Electric Co Ltd | GaN-based semiconductor device |
| US7432142B2 (en) * | 2004-05-20 | 2008-10-07 | Cree, Inc. | Methods of fabricating nitride-based transistors having regrown ohmic contact regions |
| US20080308864A1 (en) * | 2007-06-18 | 2008-12-18 | United Microelectronics Corp. | Asymmetrical mos transistor and fabrication method thereof and devices using the same |
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| KR101952570B1 (en) * | 2011-05-13 | 2019-02-27 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method of manufacturing the same |
| JP6013685B2 (en) * | 2011-07-22 | 2016-10-25 | 株式会社半導体エネルギー研究所 | Semiconductor device |
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