TWI624061B - Semiconductor device and method for fabricating the same - Google Patents

Abstract

In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode traversing the active fin, and a first impurity region formed on the active fin on the first At the first side of the gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at the second side of the first gate electrode. At least a part of the second impurity region is not formed in an epitaxial layer.

Description

Semiconductor device and manufacturing method thereof See related applications

This application is the 10th U.S. Patent Application No. 61 / 810,348 filed on April 10, 2013 and filed at the Korean Intellectual Property Office on July 8, 2013. -2013-0079824 Korean Patent Application, and all rights and interests are derived from these cases in accordance with 35 USC119, the content of each case is the entirety and hereby incorporated by reference.

Technical field

An exemplary embodiment relates to a semiconductor device and / or a method of manufacturing the semiconductor device.

2. Narration of related technologies

Recently, semiconductor devices tend to have high-speed operation characteristics accompanied by low voltage, and manufacturing methods of semiconductor devices tend to achieve improved integration.

The improved integration of the device causes a short-channel effect on a field-effect transistor (FET) system, which is one of the many semiconductor device components. Therefore, in order to overcome this shortcoming, we actively implement Study of Fin Fin Field-Effect Transistors (fin FETs) for Channels in Two-dimensional Space Structures.

Summary of invention

At least one embodiment is related to a semiconductor device.

In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode passing through the active fin, and a first impurity region formed on the active fin. One of the gate electrodes is on the first side. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on a second side of one of the first gate electrodes on the active fin. At least a part of the second impurity region is not formed in an epitaxial layer.

In one embodiment, the entirety of the second impurity region is not formed in an epitaxial layer.

In an embodiment, the second impurity region has an upper surface located at the same height as an upper surface of a portion of the active fins through which the gate electrode passes.

In one embodiment, the second impurity region has a larger width in the longitudinal direction of the active fin than the first impurity region. In an embodiment, the semiconductor device further includes a first contact point electrically connected to the first impurity region; and a second contact point electrically connected to the second impurity region with an end opposite to the first gate. Electrode. In one embodiment, the upper surface of the first impurity region is higher than the upper surface of a portion of the active fins traversed by the gate electrode.

In an embodiment, the semiconductor device further includes a first Two gate electrodes cross the active fin, and a third impurity region is formed on the active fin on a first side of one of the second gate electrodes. Here, the first impurity region is formed on the active fin on a second side of one of the second gate electrodes.

In one embodiment, the semiconductor device further includes a second gate electrode crossing the active fin, and a third impurity region is formed on the active fin on a first side of the second gate electrode. And one of the first gate electrodes on the second side. Here, the second impurity region is formed on the active fin on a second side of one of the second gate electrodes.

In one embodiment, the semiconductor device further includes a conductor electrically connected to the second and third impurity regions.

In one embodiment, the second impurity region includes a first portion and a second portion. The first portion is formed in a second epitaxial layer portion, and the second portion is not formed in an epitaxial layer. In one embodiment, the second impurity region has a larger width in the longitudinal direction of the active fin than the first first impurity region. The first portion is opposite to the first gate electrode at an end of the second impurity region. Here, the semiconductor device further includes a first contact point electrically connected to the first impurity region, and a second contact point electrically connected to the first portion of the second impurity region. In one embodiment, the upper surface of the first portion is higher than the upper surface of the active fins traversed by the first gate electrode. In one embodiment, the upper surface of the first impurity region is higher than the upper surface of the active fins traversed by the first gate electrode. In another embodiment, the upper surface of the first impurity region and the upper surface of the first portion are the same height. in In one embodiment, the second impurity region includes a third portion. The third portion is located near the second impurity region with respect to the first gate electrode, and the third portion is formed in a third epitaxial layer portion formed on the active fin. The upper surface of the first portion and the upper surface of the third portion are located at the same height. In an embodiment, the upper surface of the first portion is higher than the upper surface of the active fins traversed by the first gate electrode, and the upper surface of the third portion is higher than the A gate electrode traverses the upper surface of the active fin.

In one embodiment, the semiconductor device further includes an etch stop layer formed on the second portion.

In one embodiment, the semiconductor device further includes a second gate electrode crossing the active fin, and a third impurity region is formed on the active fin on a first side of the second gate electrode. . Here, the first impurity region is formed on the active fin on a second side of one of the second gate electrodes.

In one embodiment, the semiconductor device further includes a second gate electrode crossing the active fin, and a third impurity region is formed on the active fin on a first side of the second gate electrode. And a second side of one of the first gate electrodes. Here, the second impurity region is formed on the active fin on a second side of one of the second gate electrodes. In one embodiment, the semiconductor device further includes a conductor electrically connected to the second and third impurity regions.

At least one embodiment is related to a method for manufacturing a semiconductor device.

In one embodiment, the method includes forming a first gate electrode across an active fin protruding from a substrate. The first gate electrode has a first side and a second side. The method further includes forming an etch stop layer on the active fin on the second side of the first gate electrode, and etching the active fin to form a first trench in the active fin on the first gate. On the first side of the electrode, an epitaxial layer is formed on the active fin using the first gate electrode and the etch stop layer as a mask, so that a first epitaxial layer partially fills the first trench, A doping operation is performed to form a first impurity region in a portion of the first epitaxial layer portion, and a second impurity region is formed in the active fin at the second side of the first gate electrode.

In one embodiment, the method further includes: forming an insulating layer on the substrate, and forming first and second contact holes in the insulating layer. The first contact hole exposes part of the first impurity region and the second contact hole exposes part of the second impurity region. The method further includes forming first and second contact points in the first and second contact holes, respectively, so that the first contact point is electrically connected to the first impurity region and the second contact point is electrically grounded. Connected to the second impurity region.

In one embodiment, the etch stop layer exposes a first portion of the active fin on a second side of the first gate electrode, and an etching operation forms a second trench on the first portion. The action of forming an epitaxial layer forms a second epitaxial layer portion in the second trench, and the action is performed on a second impurity region of the second epitaxial layer portion forming portion.

In one embodiment, the second epitaxial layer is partially near the second impurity region with respect to the first gate electrode.

In an embodiment, the second epitaxial layer portion is located at a distal end of the second impurity region with respect to the first gate electrode.

In one embodiment, the action of forming an epitaxial layer forms the first and second epitaxial layer portions so that the upper surface of the first epitaxial layer portion and the second epitaxial layer portion are above The surface is higher than the upper surface of the active fin.

In one embodiment, the operation of forming an etch stop layer forms the etch stop layer to cover the entirety of the active fins to be formed in the second impurity region.

In one embodiment, the second impurity region has a width larger than that of the first impurity region in the longitudinal direction of the active fin.

In one embodiment, the performing action includes performing a first ion implantation, forming a mask to cover the substrate so that the etch stop layer is exposed, and performing a second ion implantation.

In an embodiment, the method further includes removing the etch stop layer.

1‧‧‧ semiconductor device

2‧‧‧ semiconductor device

3‧‧‧ semiconductor device

4‧‧‧ semiconductor device

5‧‧‧ semiconductor device

6‧‧‧ semiconductor device

7‧‧‧ semiconductor device

8‧‧‧ semiconductor device

9‧‧‧ semiconductor device

10‧‧‧Semiconductor device

11‧‧‧Semiconductor device

12‧‧‧semiconductor device

13‧‧‧semiconductor device

14‧‧‧semiconductor device

19‧‧‧ Trench

20‧‧‧Epitaxial layer

30‧‧‧ Impurity area

32‧‧‧Interface layer

34‧‧‧Gate insulation

36‧‧‧ Work Function Metal

38‧‧‧Gate Metal

40‧‧‧Gate insulation

42‧‧‧ the first impurity region

43‧‧‧ the first impurity region

44‧‧‧Second impurity region

44a‧‧‧The first sub-impurity region

44b‧‧‧Second sub-impurity region

46‧‧‧Virtual impurity region

47‧‧‧Virtual Impurity Region

48‧‧‧Virtual impurity region

48a‧‧‧First virtual impurity region

48b‧‧‧Second virtual impurity region

50‧‧‧Gate electrode

52‧‧‧Virtual gate electrode

54‧‧‧Virtual gate electrode

60‧‧‧ spacer

70‧‧‧ first contact point

80‧‧‧ Etch stop layer

90‧‧‧ second contact point

92‧‧‧ connecting line

94‧‧‧ connecting line

110‧‧‧Deep trench isolation

120‧‧‧ Shallow trench isolation

125‧‧‧ contact well

130‧‧‧ well

210‧‧‧The first active fin

220‧‧‧Second Active Fin

230‧‧‧ third active fin

240‧‧‧Fourth active fin

251‧‧‧first gate electrode (first gate line)

252‧‧‧Second gate electrode

253‧‧‧Third gate electrode (third gate line)

254‧‧‧Fourth gate electrode

261‧‧‧ Contact

271‧‧‧Wire

272‧‧‧Wire

300‧‧‧ contact point

302‧‧‧contact point

304‧‧‧contact point

306‧‧‧contact point

308‧‧‧contact point

310‧‧‧contact point

312‧‧‧contact point

314‧‧‧contact point

316‧‧‧contact point

318‧‧‧contact point

320‧‧‧ contact points

322‧‧‧contact point

324‧‧‧contact point

326‧‧‧contact point

340‧‧‧Interlayer dielectric layer

350‧‧‧ Intermediate Dielectric Layer ILD

352‧‧‧contact point

354‧‧‧contact point

356‧‧‧Wiring

361‧‧‧ Contact

410‧‧‧Logical Area

411‧‧‧first transistor

412‧‧‧Third transistor

420‧‧‧SRAM formation area

421‧‧‧Second transistor

422‧‧‧Fourth transistor

900‧‧‧ wireless communication device

910‧‧‧ Display

911‧‧‧antenna

913‧‧‧Receiver (RCVR)

915‧‧‧Transmitter (TMTR)

920‧‧‧ Digital Section

922‧‧‧Video Processor

924‧‧‧Application Processor

926‧‧‧controller / multi-core processor

928‧‧‧display processor

930‧‧‧Central Processing Unit

932‧‧‧External Bus Interface (EBI)

934‧‧‧ modem processor

940‧‧‧External memory

1000‧‧‧ Computing System

1002‧‧‧Central Processing Unit (CPU)

1004‧‧‧System memory

1006‧‧‧Display

1010‧‧‧Graphics System

1011‧‧‧Graphics Processing Unit (GPU)

1012‧‧‧Graphics Memory

1013‧‧‧Display Controller

1014‧‧‧ Graphic interface

1015‧‧‧Graphics Memory Controller

1100‧‧‧Electronic system

1110‧‧‧ Controller

1120‧‧‧Input / Output Device (I / O)

1130‧‧‧Memory device

1140‧‧‧ interface

1150‧‧‧Bus

1200‧‧‧ Tablet

1300‧‧‧ Notebook

1400‧‧‧Smartphone

AB‧‧‧active substrate

BL‧‧‧bit line

BLb‧‧‧ Complementary Bit Line

BR‧‧‧ Ballast resistor

BR1‧‧‧ ballast resistor

BR2‧‧‧ ballast resistor

DA‧‧‧Installation Area

DT‧‧‧Drive Transistor

DTR1‧‧‧The first virtual transistor

DTR2‧‧‧Second Virtual Transistor

F‧‧‧ Active Fin

F1‧‧‧ Active Fin

F2‧‧‧Active Fin

F3‧‧‧Active Fin

F4‧‧‧Active Fin

F5‧‧‧Active Fin

F6‧‧‧Active Fin

F7‧‧‧Active Fin

F8‧‧‧Active Fin

F9‧‧‧ Active Fin

G1‧‧‧Gate electrode

G2‧‧‧Gate electrode

G3‧‧‧Gate electrode

G4‧‧‧Gate electrode

G5‧‧‧Gate electrode

GC‧‧‧Gate contact

GR‧‧‧ retainer

GRC‧‧‧ ground contact

INV1‧‧‧Inverter

INV2‧‧‧Inverter

MR‧‧‧Memory cell array area

MS‧‧‧Mask

PD1‧‧‧First pull-down transistor

PD2‧‧‧Second pull-down transistor

PS1‧‧‧First pass transistor (first selection transistor)

PS2‧‧‧Second Path Transistor (Second Selection Transistor)

PT‧‧‧pass transistor

PU1‧‧‧The first pull-up transistor

PU2‧‧‧Second pull-up transistor

RBL‧‧‧Read bit line

RWL‧‧‧Read Character Line

S1‧‧‧ Top surface

S2‧‧‧upper surface

S3‧‧‧upper surface

SB‧‧‧ substrate

SMC1‧‧‧SRAM memory cell area

SMC2‧‧‧SRAM memory cell area

TR1‧‧‧First transistor

TR2‧‧‧Second transistor

TR3‧‧‧Third transistor

TR4‧‧‧Fourth transistor

TR5‧‧‧Fifth transistor

TR6‧‧‧Sixth transistor

Vcc‧‧‧ Power Supply Node

VDD‧‧‧ Power Supply Node

Vss‧‧‧ Ground Node

VSS‧‧‧ ground node

W1‧‧‧Width

W2‧‧‧Width

WL‧‧‧Character Line

WWL‧‧‧write character line

The above and other features and advantages of the exemplary embodiment will become more apparent by describing its preferred embodiment in detail with reference to the attached drawings: FIG. 1 is a diagram of a semiconductor device according to the first embodiment. Conceptual plan; Figure 2A is a cross-sectional view taken along the line IIA-IIA of FIG. 1 and FIG. 2B is a cross-sectional view taken along the line IIB-IIB of FIG. 1; 3 is a circuit diagram of a semiconductor device according to the first embodiment; FIGS. 4A-4B are graphs illustrating the operation of the semiconductor device according to the first embodiment; and FIG. 5 is a circuit diagram according to the second embodiment. Conceptual plan drawing of a semiconductor device; FIG. 6 is a cross-sectional view drawn along the line VI-VI of FIG. 5; FIG. 7 is a conceptual plan drawing of a semiconductor device according to the third embodiment; and FIG. 7 is a cross-sectional view taken along the line VIII-VIII; FIG. 9 is a circuit diagram of a semiconductor device according to the third embodiment; FIG. 10 is a conceptual plan view of a semiconductor device according to the fourth embodiment; FIG. 11 FIG. 12 is a cross-sectional view taken along line XI-XI of FIG. 10; FIG. 12 is a cross-sectional view of a semiconductor device according to a fifth embodiment; and FIG. 13 is a cross-sectional view of a semiconductor device according to a sixth embodiment. 14 is a cross-sectional view of a semiconductor device according to a seventh embodiment; FIG. 15 is a conceptual plan view of a semiconductor device according to an eighth embodiment; FIG. 16 is a line extending along the line XVI-XVI of FIG. 15 Draw Section FIG. 17 is a circuit diagram of a semiconductor device according to the eighth embodiment; FIG. 18 is a circuit diagram of a semiconductor device according to the ninth embodiment; and FIG. 19A is a concept of a semiconductor device according to the tenth embodiment. FIG. 19B is a cross-sectional view drawn along the line XIXB-XIXB of FIG. 19A; FIG. 20A is a circuit diagram of a semiconductor device according to an eleventh embodiment; and FIG. 20B is a semiconductor device shown in FIG. 20A FIG. 21 is a conceptual plan view of a semiconductor device according to a twelfth embodiment; FIG. 22 is a circuit diagram of the first SRAM memory cell of FIG. 21; and FIG. 23 is a plan diagram of the first SRAM memory cell of FIG. FIG. 24 illustrates a semiconductor device according to a thirteenth embodiment; FIG. 25 illustrates a semiconductor device according to a fourteenth embodiment; FIG. 26 is a block flow diagram of a wireless communication device including a semiconductor device according to an exemplary embodiment FIG. 27 is a block flow diagram of a computing system including a semiconductor device according to an exemplary embodiment; FIG. 28 is a block diagram of an electronic system including a semiconductor device according to an exemplary embodiment Process; Figure 29 to 31 illustrate based semiconductor device according to some aspects of the exemplary embodiments may be applied where the semiconductor system; 32 to 34B illustrate intermediate procedure steps in a method for manufacturing a semiconductor device according to one embodiment; FIGS. 35A to 35B illustrate a method for manufacturing a semiconductor device according to another embodiment. FIG. 36 illustrates intermediate procedure steps in a method for manufacturing a semiconductor device according to another embodiment; and FIG. 37 illustrates a method for manufacturing a semiconductor device according to another embodiment. Intermediate procedure steps within the method.

Detailed description of the preferred embodiment

The advantages and features of these exemplary implementations will be more readily understood with reference to the following detailed description and accompanying drawings. However, these exemplary implementation patterns are implemented in many different forms and should not be construed as being limited to the implementation patterns set forth therein. Rather, these embodiments are provided so that this disclosure will be more dense and complete and will fully convey the concepts of the invention to those of ordinary skill in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity.

It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on the other element or layer. It is either directly connected to another element or layer, or intervening elements or layers may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. Generally, similar reference numbers refer to similar elements. in this way As used on premises, the term "and / or" includes any and all combinations of one or more of the associated listed items.

Terms of spatial relativity, such as: "below", "below", "lower", "above", "upper", etc., are used here to easily describe an element or The relationship of a feature relative to another element or feature is illustrated in the drawing. It will be understood that these spatial relative terms are intended to encompass different orientations of the device in use and operation, in addition to the orientations described in the drawings. For example, if the device in the drawing is turned over, elements described as "under other elements or features" and "under other elements or features" will then be oriented "above other elements or features." Thus, the exemplary term "below" can encompass both the directions above and below. The device is otherwise oriented (rotated 90 degrees or in other directions) and the relative descriptions of the spaces used here are interpreted accordingly.

The terms "a" and "the" and similar designated objects used in describing the context of the present invention (especially the scope of the following patent application) are interpreted as including "singular" and "plural" Both, unless otherwise indicated here or clearly contradicted in the text. The terms "including," "having," "including," and "containing" are to be construed as unrestricted (ie, meaning "including, but not limited to), unless otherwise specified.

It will be understood that, although the terms first, second, etc. are used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element, a first part, or a first part discussed below may be referred to as a second element, a second part, or a second part without Deviations from the teachings of the exemplary implementation.

Exemplary embodiments are described with reference to perspective views, cross-sectional views, and / or plan views. Therefore, the shapes of these model drawings are modified according to manufacturing technology and / or allowable amount. That is, such implementation aspects are not intended to limit the scope of the exemplary implementation aspects, but include all changes and modifications resulting from changes in manufacturing methods. Therefore, the regions shown in the drawings are described in summary form, and the shapes of these regions are presented by way of illustration only and not as a limitation.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It is noted that the use of any or all of the examples, or the exemplary wording provided herein is intended merely to better describe those exemplary implementations and is not a limitation on the scope of the invention unless otherwise specified . Further, unless otherwise defined, all terms defined in commonly used dictionaries should not be interpreted excessively.

Hereinafter, a semiconductor device according to a first embodiment will be described with reference to FIGS. 1 to 4B.

FIG. 1 is a conceptual plan view of a semiconductor device according to a first embodiment. FIG. 2A is a cross-sectional view taken along line IIA-IIA of FIG. 1 and FIG. 2B is a line taken along line IIB-IIB of FIG. 1. In the drawn cross-sectional view, FIG. 3 is a circuit diagram of the semiconductor device according to the first embodiment, and FIGS. 4A-4B are graphs illustrating the operation of the semiconductor device according to the first embodiment.

First, referring to FIGS. 1 to 2B, the semiconductor device 1 includes an active fin F, a gate electrode 50, a first impurity region 42, and a second impurity region 44.

The active fin F is formed to protrude from a substrate SB and extends in a first direction (for example, in the X-axis direction). Here, the active fin F is formed by etching a portion of the substrate SB. That is, the substrate SB and the active fin F include the same material, but the aspect of the exemplary embodiment is not limited thereto. The active fin F is also formed by other methods. For example, in some embodiments, the active fin F is formed by allowing an epitaxial layer to be grown on the substrate SB independently and etching the grown epitaxial layer.

In some embodiments, as shown in FIG. 2B, the active substrates AB separated by deep trench isolation (DTI) (110 of FIG. 19B) are formed on the substrate SB, and The active fin F is formed on the active substrate AB. The active fins F are separated by shallow trench isolation (STI) 120, but the aspect of the exemplary implementation aspect is not limited thereto. However, the active substrate AB may not be formed. That is, in some other exemplary embodiments, the active fin F is directly formed on the substrate SB.

In some implementations, as shown, the active fins F are formed by grouping each of the active fins F. That is, the two active fins F are formed on one of the active substrates AB. The active fins F are arranged in this manner because they are formed by etching the active substrate AB using two dummy spacers, but the aspect of the exemplary implementation aspect is not limited thereto. The arrangement of the active fins F is modified in various ways.

In the illustrated embodiment, the cross section of the active fin F The shape is tapered so that the width of the active fin F gradually increases from top to bottom, but the aspect of the exemplary embodiment is not limited thereto. In some embodiments, the active fin F is modified to have a rectangular cross section. In addition, in some other embodiments, the cross-sectional shape of the active fin F is chamfered. That is, the corners of the active fin F are circular.

For example, the substrate SB is a semiconductor substrate. The substrate SB10 is made of one or more semiconductor materials, such as: Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs, and InP. For example, the active substrate AB is made of a semiconductor material. In some embodiments, the substrate SB and the active substrate AB include the same material.

Meanwhile, in some embodiments, the substrate SB is an insulating substrate. In detail, the substrate SB is a silicon on insulator (SOI) substrate. Here, the active fin F and the active substrate AB are formed by forming a single crystal silicon on a buried oxide layer used as a substrate SB and patterning the single crystal silicon. In this example, the active fin F and the active substrate AB are epitaxial layers. The use of an SOI substrate system advantageously reduces the delay time during operation of the semiconductor device 1.

The gate electrode 50 may extend through the second direction of the active fin F (for example, in the Y-axis direction). A gate insulating layer 40 is formed under the gate electrode 50. In other words, the gate insulating layer 40 is disposed between the active fin F and the gate electrode 50. The gate insulating layer 40 extends in the second direction (for example, in the Y-axis direction), like the gate electrode 50.

For example, the gate insulation layer 40 includes a high dielectric material (for example, k is greater than 3.9). In some embodiments, the gate insulating layer 40 includes, for example, HfO ₂ , Al ₂ O ₃ , ZrO ₂ , or TaO ₂ , but the aspect of the exemplary embodiment is not limited thereto.

Although not specifically shown, an interface layer is further prepared between the gate insulating layer 40 and the active fin F to avoid poor interface characteristics between the gate insulating layer 40 and the active fin F . The interface layer includes a low-dielectric material layer having a dielectric constant (k) of 9 or less, for example, a silicon oxide layer (k ≒ 4) or a silicon oxynitride layer (k ≒ 4 ~ 8). , Based on the content of oxygen and nitrogen atoms). Alternatively, the interface layer may include a silicate, or a combination of layers as described above.

The gate electrode 50 includes a conductive material. In some exemplary embodiments, the gate electrode 50 includes a highly conductive metal, but the aspect of the exemplary embodiment is not limited thereto. That is, in some other embodiments, the gate electrode 50 is made of a non-metal such as polycrystalline silicon.

A spacer 60 is disposed on at least one side of the gate electrode 50. In detail, as shown in FIG. 2A, the spacer 60 is formed on both sides of the gate electrode 50. The spacer 60 includes at least one of a nitride layer and an oxynitride layer. In FIG. 2A, one side surface of the spacer 60 is curved, but the aspect of the exemplary embodiment is not limited thereto. The shape of the spacer 60 is modified in various ways. For example, in some embodiments, unlike the illustrated embodiment, the spacer 60 is modified to have the shape of the letter "I" or the shape of the letter "L".

A trench 19 is disposed on at least one side of the gate electrode 50 for the first transistor TR1. In detail, as shown in FIG. 2A, the trenches 19 are disposed on both sides of the gate electrode 50 for the first transistor. TR1. The trench 19 is formed by etching the active fins F on both sides of the gate electrode 50.

An epitaxial layer 20 is formed in the trench 19. In detail, the epitaxial layer 20 is formed to fill the trench 19. In some embodiments, the epitaxial layer 20 fills the trench 19 sufficiently by performing an epitaxial generation process on the trench 19. Therefore, the upper surface of the epitaxial layer 20 is formed to be higher than the upper surface of the trench 19. In addition, in some embodiments, the upper surface of the epitaxial layer 20 is formed higher than the lower surface of the gate electrode 50, as shown in FIG. 2A. That is, the upper surface of the epitaxial layer 20 is higher than the upper surface of the active fin F.

The epitaxial layer 20 improves the operating performance of the first and second transistors (TR1 and TR2). For example, when the first and second transistors (TR1 and TR2) are NMOS transistors, the epitaxial layer 20 includes a material for applying tensile stress to the channel, such as SiC. Meanwhile, for example, when the first and second transistors (TR1 and TR2) are PMOS transistors, the epitaxial layer 20 includes a material for applying compressive stress to the channel, such as SiGe.

An impurity region 30 is formed inside the epitaxial layer 20 or inside the active fin F. In the following description, the impurity region 30 according to the embodiment will be described with respect to the second transistor TR2, but the aspect of the exemplary embodiment is not limited thereto. This exemplary embodiment is also applied to other types of transistors (eg, TR1).

A first impurity region 42 is formed on one side of the gate electrode 50 of the second transistor TR2 and a second impurity region 44 is formed on The other side of the gate electrode 50. The first and second impurity regions 42 and 44 are a source region and a drain region of the second transistor TR2. For example, when the conductivity types of the first and second impurity regions 42 and 44 are N-type, the second transistor TR2 is an NMOS transistor. Meanwhile, for example, when the conductivity type of the first and second impurity regions 42 and 44 is a P-type, the second transistor TR2 is a PMOS transistor.

In some embodiments, the first impurity region 42 is a source region of the second transistor TR2 and the second impurity region 44 is a drain region of the second transistor TR2, but the exemplary embodiment This aspect is not limited to this.

In this embodiment, the first impurity region 42 is a standard impurity region and the second impurity region 44 is an extended impurity region. In other words, the width W2 of the second impurity region 44 in the first or longitudinal direction (for example: X-axis direction) is larger than the first impurity region in the first or longitudinal direction (for example: X-axis direction) The width W1 of 42. When the second impurity region 44 is an extended impurity region, it performs a ballast resistance (BR) function. In this example, the same bipolar junction transistor (BJT) includes the first impurity region 42, the active fin F, and the second impurity region 44, and the second transistor TR2 An electrostatic discharge (ESD) function is performed to block the application of a sharp surge to a second contact point 90, which will be described in detail later.

A proximal portion and a terminal portion of the second impurity region 44 are formed in the epitaxial layer 20 and other portions of the second impurity region 44 are formed in the active fin F, such as As shown. Here, formed in the main An upper surface S2 of one of the second impurity regions 44 in the movable fin F is formed at substantially the same height as the upper surface S1 of the active fin F having the gate electrode 50 disposed thereon. In this way, the upper surface S2 of the second impurity region 44 formed in the active fin F is formed to be substantially the same height as the upper surface S1 of the active fin F with the gate electrode 50 disposed thereon. Because the trenches 19 and the epitaxial layer 20 are not formed in the corresponding regions by an etch stop layer 80, they will be described in detail later.

Meanwhile, as shown, the upper surface of the second impurity region 44 formed in the epitaxial layer 20 is formed to be higher than the upper surface S2 of the second impurity region 44 formed in the active fin F. In addition, as shown, the upper surface of the second impurity region 44 formed in the epitaxial layer 20 is formed at substantially the same height as the upper surface of the first impurity region 42 formed in the epitaxial layer 20. Office. That is, in this embodiment, the first impurity region 42 and the second impurity region 44 are formed as extended impurity regions higher than the lower surface of the gate electrode 50.

In some embodiments, the first and second impurity regions 42 and 44 are formed to overlap the spacer 60. In detail, as shown, the first and second impurity regions 42 and 44 may be rolled around the lower portion of the spacer 60, but the aspect of the exemplary implementation aspect is not limited thereto. The first and second impurity regions 42 and 44 are modified to have various shapes.

The etch stop layer 80 is formed on the upper surface S2 of the second impurity region 44 formed in the active fin F. In some embodiments, the etch stop layer 80 includes the same material as the spacer 60. That is, when the spacer 60 is formed of, for example, a nitride layer, the etching The stop layer 80 is also formed of a nitride layer. In addition, when the spacer 60 is formed of an oxynitride layer, the etch stop layer 80 is also formed of an oxynitride layer. As such, the etch stop layer 80 and the spacer 60 include the same material because they are formed at the same time, but the aspect of the exemplary embodiment is not limited thereto. Alternatively, the etch stop layer 80 is formed by various methods.

In detail, in some other embodiments, although not specifically shown, the etching stop layer 80 is formed simultaneously with a cover layer formed on the gate electrode 50. In addition, in some other embodiments, the etch stop layer 80 is also formed at the same time as a passive device (eg, a resistor, a capacitor, etc.), rather than an active device, such as: Transistors TR1 and TR2.

The first contact point 70 is electrically connected to the first impurity region 42. The second contact point 90 is electrically connected to the second impurity region 44. For example, the second contact point 90 is electrically connected to an end portion of the second impurity region 44. In some embodiments, for example, the first contact point 70 is a source contact of the second transistor TR2 and the second contact point 90 is a drain contact of the second transistor TR2, but the The aspect of the exemplary implementation aspect is not limited to this.

As shown, the second impurity region 44 electrically connected to the second contact point 90 is formed in the epitaxial layer 20. In detail, the second impurity region 44 electrically connected to the second contact point 90 is formed in the epitaxial layer 20 that partially fills the trench 19 at the end of the second impurity region 44, but this exemplary The implementation aspect is not limited to this. Formed as the second contact The shape of the area at point 90 is modified in various ways.

At the same time, the etch stop layer 80 is also formed on the other side of the second impurity region 44 electrically connected to the second contact point 90. The second contact point 90 allows the trench 19 and the epitaxial layer 20 to be partially formed only in a region where the etch stop layer 80 is not formed, and an upper surface of the second impurity region 44 formed in the active fin F. The etch stop layer 80 formed on S2 together.

In this embodiment, when the second transistor TR2 operates, the first contact point 70 and the active fin F are connected to a ground voltage GND, as shown in FIG. 3. An I / O signal or a power supply voltage VDD is applied to the second contact point 90. A desired gate voltage is applied to the gate electrode 50 via a gate contact point GC.

As described above, in the second transistor TR2, the extended second impurity region 44 serves as a ballast resistor BR. In addition, because the first impurity region 42, the active fin F, and the second impurity region 44 constitute a bipolar junction transistor (BJT), as shown in FIGS. 4A-4B, in the second transistor TR2 However, even if the voltage applied to the second contact point 90 generally increases suddenly as shown in FIG. 4A (for example, to a large amount of voltage V1), the driving current does not increase suddenly, as shown in FIG. 4B. In other words, an electrostatic discharge (ESD) function is performed to block a sharp surge from being applied to the second contact point 90. Therefore, in the second transistor TR2, the extended second impurity region 44 performs an important function when the second transistor TR2 performs an ESD operation.

In order to form an extended second impurity region 44, the trench 19 is first formed through the extended second impurity region 44. When the epitaxial layer 20 is formed in the trench 19 through an epitaxial growth process, the second The width W2 of the mass region 44 is relatively large, and the epitaxial layer 20 is not formed flat. In this example, the impurity region 30 formed in the epitaxial layer 20 is not formed evenly. Therefore, if the impurity region 30 is not formed flat, the second contact point 90 is not electrically connected to the impurity region 30 to be continuously opened.

Therefore, in the semiconductor device 1 according to this embodiment, the trench 19 and the epitaxial layer 20 are not formed to completely penetrate the extended second impurity region 44, but only the etching stop layer 80 is used in the epitaxial layer. The region where the crystal layer 20 is formed is partially formed (for example, a region adjacent to the channels of the transistors TR1 and TR2). Therefore, it is possible to avoid a situation where the impurity region 30 is formed unevenly, thereby electrically connecting the second contact point 90 to an impurity region (eg, the second impurity region 44) in a reliable manner. Therefore, the reliability of the semiconductor device 1 can be improved.

Next, a semiconductor device according to a second embodiment will be described with reference to FIGS. 5 and 6.

FIG. 5 is a conceptual plan view of a semiconductor device according to a second embodiment, and FIG. 6 is a cross-sectional view taken along a line VI-VI of FIG. 5. The following description will focus only on the differences between this embodiment and the previous embodiment.

5 and FIG. 6, the semiconductor device 2 according to the second embodiment is different from the semiconductor device 1 (FIG. 2A) according to the first embodiment in that the etch stop layer (FIG. 80) in 2A is removed during the manufacturing process of forming the semiconductor device 2.

That is, in the semiconductor device 2, the etch stop layer (80 in FIG. 2A) is no longer on the upper surface S2 of the second impurity region 44 formed in the active fin F. In this example, the upper surface S2 of the second impurity region 44 formed in the active fin F is substantially the same as the upper surface S1 of the active fin F having the gate electrode 50 disposed thereon.

Here, because the second contact point 90 and the extended second impurity region 44 are electrically connected in a reliable manner, the yield of the semiconductor device 2 can be improved.

Next, a semiconductor device according to a third embodiment will be described with reference to FIGS. 7 to 9.

FIG. 7 is a conceptual plan view of a semiconductor device according to the third embodiment, FIG. 8 is a cross-sectional view drawn along the line VIII-VIII of FIG. 7, and FIG. 9 is a view according to the third embodiment Circuit diagram of a semiconductor device. For the sake of brevity, the following description will focus on the differences between this embodiment and the previous embodiment.

First, referring to FIG. 7 and FIG. 8, the semiconductor device 3 according to this embodiment further includes a dummy gate electrode 52 in a second direction parallel to the gate electrode 50 (for example, in a Y-axis direction). extend. The dummy gate electrode 52 forms a dummy transistor DTR.

Here, an extended second impurity region 44 includes a first sub-impurity region 44a disposed on one side of the virtual gate electrode 52 and a second sub-impurity region 44b disposed on the other side of the virtual gate electrode 52. And is separated from the first sub-impurity region 44a.

At the same time, the first sub-impurity region 44 a and the spaced apart second sub-impurity region 44 b are electrically connected to each other via a connection line 92.

In some embodiments, the width of the first sub-impurity region 44a and the width of the second sub-impurity region 44b are different from each other. In detail, as shown, the width of the first sub-impurity region 44a in the longitudinal direction is larger than the width of the second sub-impurity region 44b.

Meanwhile, in some embodiments, as shown, the first sub-impurity region 44 a is formed in the active fin F, and the second sub-impurity region 44 b is formed in a region filling the trench 19. In the epitaxial layer 20. Therefore, the upper surface of the second sub-impurity region 44b is higher than the upper surface of the first sub-impurity region 44a. Meanwhile, the upper surface S2 of the first sub-impurity region 44a is formed at substantially the same height as the upper surface S1 of the active fin F having the gate electrode 50 disposed thereon. In addition, the upper surface S2 of the first sub-impurity region 44 a is also formed at substantially the same height as the upper surface of the active fin F having the dummy gate electrode 52.

In the illustrated embodiment, the first sub-impurity region 44 a having a second contact point 90 is formed in the active fin F. Therefore, as described above, there is no risk that the first sub-impurity region 44a and the second contact point 90 are open due to inconsistent generation of the epitaxial layer 20, thereby improving the yield of the semiconductor device 3.

Meanwhile, in this embodiment, when the second transistor TR2 is operated, the first contact point 70 and the active fin F are connected to a ground voltage GND, as shown in FIG. 9. An I / O signal or a power supply voltage VDD is applied to the second contact point 90. A desired (or, alternatively, a predetermined) gate voltage is applied to the gate electrode 50 via a gate contact point GC.

In some embodiments, when the second transistor TR2 is operated At this time, the dummy gate electrode 52 is floating, but the aspect of the exemplary implementation aspect is not limited thereto. The virtual gate electrode 52 operates in a variety of ways. For example, in some other embodiments, when the second transistor TR2 is operated, a power supply voltage VDD is applied to the virtual gate electrode 52.

In the semiconductor device 3 according to this embodiment, the first sub-impurity region 44a and the connection line 92 electrically connecting the first sub-impurity region 44a to the second sub-impurity region 44b are used as ballast resistors BR1 and BR2 . That is, the first sub-impurity region 44a forms a first ballast resistor BR1, and the connection line 92 electrically connecting the first sub-impurity region 44a to the second sub-impurity region 44b forms a second ballast resistor BR2. . Therefore, compared to the previous implementation, the ballast resistors BR1 and BR2 increase the amount of ballast resistors.

At the same time, the first impurity region 42, the active fin F, and the second sub-impurity region 44b constitute a bipolar junction transistor (BJT). The first sub-impurity region 44a constitutes another bipolar junction transistor (BJT).

Therefore, the second transistor TR2 included in the semiconductor device 3 improves the ESD function.

Next, a semiconductor device according to a fourth embodiment will be described with reference to FIGS. 10 and 11.

FIG. 10 is a conceptual plan view of a semiconductor device according to a fourth embodiment, and FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. 10. For the sake of brevity, the following description will focus on the differences between this embodiment and the previous embodiment.

10 and FIG. 11, a semiconductor device according to this embodiment The 4 series further includes first and second dummy gate electrodes 52 and 54 extending in a second direction (eg, in a Y-axis direction) parallel to the gate electrode 50. The first dummy gate electrode 52 forms a first dummy transistor DTR1 and the second dummy gate electrode 54 forms a second dummy transistor DTR2.

Here, an extended second impurity region 44 includes a first sub-impurity region 44a disposed on one side of the second virtual gate electrode 54 and a second sub-impurity region 44b disposed on the first virtual gate electrode. The other side of 52 is separated from the first sub-impurity region 44a. At the same time, a dummy impurity region 46 is disposed between the first dummy gate electrode 52 and the second dummy gate electrode 54.

As described above, the first sub-impurity region 44 a included in the second impurity region 44 is disposed on one side of the second dummy gate electrode 54, and the dummy impurity region 46 is disposed on the first Between the dummy gate electrode 52 and the second dummy gate electrode 54, the second sub-impurity region 44 b included in the extended second impurity region 44 is disposed between the gate electrode 50 and the first dummy gate. Between the electrode electrodes 52, the first impurity region 42 is disposed on the other side of the gate electrode 50.

At the same time, the first sub-impurity region 44 a and the second sub-impurity region 44 b separated from each other are electrically connected to each other via a connection line 94.

In some embodiments, the width of the first sub-impurity region 44a and the width of the second sub-impurity region 44b are different from each other. In detail, as shown, the width of the first sub-impurity region 44a in the longitudinal direction is larger than the width of the second sub-impurity region 44b.

Meanwhile, in some embodiments, as shown, the first sub-impurity region 44 a is formed in the active fin F, and the second sub-impurity region 44 b is formed in a region filling the trench 19. In the epitaxial layer 20. Therefore, the upper surface of the second sub-impurity region 44b is higher than the upper surface of the first sub-impurity region 44a. Meanwhile, the upper surface S2 of the first sub-impurity region 44a is formed at substantially the same height as the upper surface S1 of the active fin F having the gate electrode 50 disposed thereon. In addition, the upper surface S2 of the first sub-impurity region 44 a is also formed at substantially the same height as the upper surface of the active fin F having the dummy gate electrode 52.

In the illustrated embodiment, the first sub-impurity region 44 a having a second contact point 90 is formed in the active fin F. Therefore, as described above, there is no risk that the first sub-impurity region 44a and the second contact point 90 are open due to the inconsistent generation of the epitaxial layer 20, thereby improving the yield of the semiconductor device 4.

Meanwhile, as shown, a part of the dummy impurity region 46 is formed in the epitaxial layer 20 and another part of the dummy impurity region 46 is formed in the active fin F. That is, as shown, a part of the upper surface of the dummy impurity region 46 is higher than a part of the upper surface of the dummy impurity region 46. In this embodiment, the dummy impurity region 46 has the shape described here because the tail of an etch stop layer (80 of FIG. 36) is disposed on the first and second portions during the manufacturing process of the semiconductor device 4. Between the dummy gate electrodes 52 and 54, which will be described in detail later.

Next, a semiconductor device according to a fifth embodiment will be described with reference to FIG. 12.

FIG. 12 is a cross-sectional view of a semiconductor device according to a fifth embodiment. The following description will focus on the differences between this embodiment and the previous embodiment.

Referring to FIG. 12, in the semiconductor device 5 according to this embodiment, a dummy impurity region 47 has a shape different from that of the dummy impurity region (FIG. 11 to 46) of the semiconductor device 4. In detail, the dummy impurity region 47 formed in the epitaxial layer 20 has a shape such that a part of the dummy impurity region 47 is etched. The dummy impurity region 47 according to this embodiment has such an external shape because a trench 19 and the epitaxial layer 20 are formed in the following state, in this state: the tail of an etch stop layer (80 of FIG. 36) Is disposed between the first and second dummy gate electrodes 52 and 54, but the tail of the etch stop layer 80 is damaged due to the misalignment of the mask when the etch stop layer 80 is removed, which will Details will be described later.

Next, a semiconductor device according to a sixth embodiment will be described with reference to FIG. 13.

FIG. 13 is a cross-sectional view of a semiconductor device according to a sixth embodiment. The following description will focus on the differences between this embodiment and the previous embodiment.

Referring to FIG. 13, in the semiconductor device 6 according to this embodiment, a dummy impurity region 48 includes a first dummy impurity region 48 a and a second dummy impurity region 48 b spaced apart from each other. Here, as shown, the first dummy impurity region 48a is formed in an epitaxial layer 20 and the second dummy impurity region 48b is formed in the active fin F.

Meanwhile, as shown, an etch stop layer 80 is disposed on the first Between a dummy impurity region 48a and the second dummy impurity region 48b. Specifically, the etch stop layer 80 is disposed adjacent to the first dummy impurity region 48 a formed in the epitaxial layer 20.

The dummy impurity region 48 according to this embodiment has a shape other than that described here because a trench 19 and the epitaxial layer 20 are formed in the following state, in this state: an etch stop layer (80 of FIG. 36) The tail portion is disposed between the first and second dummy gate electrodes 52 and 54, but the tail portion of the etch stop layer 80 is removed due to the misalignment of the mask when the etch stop layer 80 is removed. Remove, this will be described in detail later.

Next, a semiconductor device according to a seventh embodiment will be described with reference to FIG. 14.

FIG. 14 is a cross-sectional view of a semiconductor device according to a seventh embodiment. The following description will focus on the differences between this embodiment and the previous embodiment.

Referring to FIG. 14, in the semiconductor device 7 according to this embodiment, for example, a transistor TR2 is formed by a reset process (or a gate subsequent process). Therefore, as shown, a gate insulating layer 34 is configured to extend upwardly along the sidewall of a spacer 60.

Meanwhile, in this embodiment, an interface layer 32 is formed between the gate insulating layer 34 and the active fin F. The interface layer 32 is formed by, for example, thermal oxidation. The interface layer 32 includes a low-dielectric material layer (with a dielectric constant (k) of 9 or less), such as: a silicon oxide layer (k ≒ 4) or a silicon oxynitride layer (k ≒ 4 ~ 8, based on the content of oxygen and nitrogen atoms). Alternatively, the interfacial layer 32 comprises a silicate, or a group of layers as described above. Together.

In the semiconductor device 7 according to this embodiment, a gate electrode system includes a work function metal 36 and a gate metal 38. As described above, when the semiconductor device 7 according to this embodiment is formed by a reset process (or a gate subsequent process), as shown, the work function metal 36 is configured to extend a The side wall of the spacer 60 extends upward.

The work function metal 36 controls the work function and the gate metal 38 fills a space formed by the work function metal 36. The work function metal 36 is formed of a single layer made of metal or has a multilayer structure including a metal nitride layer and a metal. Examples of the metal forming the work function metal 36 include, for example, Al, W, Ti, or a combination thereof, and the metal nitride layer includes TiN, TaN, or a combination thereof, but the exemplary implementation aspect The aspect is not limited to this. The gate metal 38 includes a metal having high conductivity. Examples of the metal include W or Al, but the aspect of the exemplary embodiment is not limited thereto.

Next, a semiconductor device according to an eighth embodiment will be described with reference to FIGS. 15 to 17.

FIG. 15 is a conceptual plan view of a semiconductor device according to the eighth embodiment, FIG. 16 is a cross-sectional view drawn along the line XVI-XVI of FIG. 15, and FIG. 17 is a cross-sectional view according to the eighth embodiment Circuit diagram of a semiconductor device. The following description will focus on the differences between this embodiment and the previous embodiment.

Referring first to FIGS. 15 and 16, in the semiconductor device 8 according to this embodiment, a first impurity region 43 and a second impurity region 44 are both Is to extend the impurity region (for example, extending in the longitudinal direction of the fin F). That is, as shown, the first impurity region 43 is formed to penetrate through the epitaxial layer 20 and the active fin F, and the second impurity region 44 is also formed to penetrate through the epitaxial layer 20 and the active fin. Tablet F. Therefore, the width in the first or longitudinal direction (for example, X-axis direction) of the first impurity region 43 and the width in the first direction (for example, X-axis direction) of the second impurity region 44 Departments are essentially the same as each other. In addition, the upper surface S2 of the second impurity region 44 formed in the active fin F and the upper surface S3 of the first impurity region 43 formed in the active fin F are formed on the gate electrode with the gate electrode. The upper surface S1 of the active fin F disposed on the electrode 50 is substantially the same height.

Here, as shown, an etch stop layer 80 is formed on each of the first and second impurity regions 43 and 44. Of course, as in the semiconductor device of the previous embodiment (FIG. 6-2), the etch stop layer 80 is later removed during the manufacturing process.

In some embodiments, the first impurity region 43 is a source region of a third transistor TR3 and the second impurity region 44 is a drain region of the third transistor TR3. In this embodiment, when the third transistor TR3 is operated, as shown in FIG. 17, the active fin F is connected to a ground voltage GND. An I / O signal or a power supply voltage VDD is applied to the first and second contact points 70 and 90. That is, in some embodiments, the I / O signal is applied to the first contact point 70 and the power supply voltage VDD is applied to the second contact point 90. In addition, in some embodiments, the power supply voltage VDD is applied to the first contact point 70 and the I / O signal is applied to the second contact point 90. In addition, in some implementations In this way, the power supply voltage VDD is applied to both the first contact point 70 and the second contact point 90, or the I / O signal is applied to the first contact point 70 and the second contact point 90. The contact point 90 is both.

Both the extended first impurity region 43 and the extended second impurity region 44 serve as the ballast resistor BR. Therefore, in this aspect, the ballast resistor BR exists in a path connected to the first contact point 70 and also in a path connected to the second contact point 90. A desired (or, alternatively, a predetermined) gate voltage is applied to the gate electrode 50 via a gate contact GC.

Next, a semiconductor device according to a ninth embodiment will be described with reference to FIG. 18.

FIG. 18 is a circuit diagram of a semiconductor device according to a ninth embodiment. The following description will focus on the differences between this embodiment and the previous embodiment.

Referring to FIG. 18, the semiconductor device 9 according to this embodiment includes a stacked transistor. In FIG. 18, the fourth to sixth transistors TR4 to TR6 are sequentially stacked, but the aspect of the exemplary embodiment is not limited thereto. That is, in some other embodiments, the number of stacked transistors is changed.

The transistor system included in the semiconductor devices 1 to 8 according to the above-described embodiments is applied to one of the fourth to sixth transistors TR4 to TR6. For example, a transistor system included in the semiconductor device 1 is applied as the fourth transistor TR4 and the sixth transistor TR6.

Next, a semiconductor device according to a tenth embodiment will be described with reference to the drawings. 19A and FIG. 19B are described.

FIG. 19A is a conceptual plan view of a semiconductor device according to a tenth embodiment, and FIG. 19B is a cross-sectional view drawn along a line XIXB-XIXB of FIG. 19A. The following description will focus on the differences between this embodiment and the previous embodiment.

19A and 19B, the semiconductor device 10 according to this embodiment includes a device area DA and a retainer GR.

At least one of the semiconductor devices 1 to 9 according to the above embodiment is formed on the device area DA. That is, the active fin F formed on the device area DA is used to form a working transistor.

The retainer GR is configured to surround the device area DA. As shown, the retainer GR is connected to a ground contact GRC via a contact well 125.

As shown, each of the device area DA and the retainer GR includes an active substrate AB and an active fin F formed on the active substrate AB. Here, the active substrates AB are separated from each other by a deep trench isolation (DTI) 110 and the active fins F are separated from each other by a shallow trench isolation (STI) 120. For convenience of explanation, in FIG. 19B, only one of the active substrates AB is formed on the device area DA, but the aspect of the exemplary implementation aspect is not limited thereto. In some other embodiments, a plurality of active substrates AB are formed on the device area DA.

As shown, the device area DA and the retainer GR are separated from each other by a deep trench isolation (DTI) 110. At the same time, the active fin F and the retainer GR of the device area DA are arranged in the same well 130. Therefore, the active fins F of the semiconductor devices 1 to 9 according to the above-mentioned embodiments are implemented by The guard ring GR is connected to a ground voltage. In some embodiments, the well 130 is, for example, a P-type well and the contact well 125 is a P + -type well, but the aspect of the exemplary embodiment is not limited thereto.

Next, a semiconductor device according to an eleventh embodiment will be described with reference to FIGS. 20A and 20B.

FIG. 20A is a circuit diagram of a semiconductor device according to an eleventh embodiment, and FIG. 20B is a plan view of the semiconductor device shown in FIG. 20A. The following description will focus on the differences between this embodiment and the previous embodiment.

20A and 20B, the semiconductor device 11 includes a pair of inverters INV1 and INV2 connected in parallel between a power supply node Vcc and a ground node Vss, and connected to the inverters INV1 and INV2. A first pass transistor PS1 and a second pass transistor PS2 at the output node. The first pass transistor PS1 and the second pass transistor PS2 are connected to a bit line BL and a complementary bit line BLb. The gates of the first pass transistor PS1 and the second pass transistor PS2 are connected to a word line WL.

The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 connected to each other in series, and the second inverter INV2 includes a second pull-up transistor PU2 and A second pull-down transistor PD2 is serially connected to each other. The first pull-up transistor PU1 and the second pull-up transistor PU2 are PFET transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 are NFET transistors.

In addition, in order to form a latch circuit, the first inverter INV1 The input node is connected to the output node of the second inverter INV2, and the input node of the second inverter INV2 is connected to the output node of the first inverter INV1.

20A and 20B, a first active fin 210, a second active fin 220, a third active fin 230, and a fourth active fin 240 are separated from each other by a The direction (for example, in one of the upward and downward directions in FIG. 20B) extends lengthwise. The second active fins 220 and the third active fins 230 extend at a smaller length than the first active fins 210 and the fourth active fins 240.

In addition, a first gate electrode 251, a second gate electrode 252, a third gate electrode 253, and a fourth gate electrode 254 are formed in another direction (for example, to the left in FIG. 20B). And rightward direction) extending to traverse the first active fin 210 to the fourth active fin 240. In detail, the first gate electrode 251 completely traverses the first active fin 210 and the second active fin 220, but partially overlaps with the end system of the third active fin 230. The third gate electrode 253 completely traverses the fourth active fin 240 and the third active fin 230, but partially overlaps with the end system of the second active fin 220. The second gate electrode 252 and the fourth gate electrode 254 are formed to cross the first active fin 210 and the fourth active fin 240, respectively.

As shown, the first pull-up transistor PU1 is defined near the intersection of the first gate electrode 251 and the second active fin 220, and the first pull-down transistor PD1 is defined in the Near the intersection of the first gate electrode 251 and the first fin F1, and the first pass transistor PS1 is defined near the intersection of the second gate electrode 252 and the first active fin 210 Neighbourhood. The second pull-up transistor PU2 is defined near the intersection of the third gate electrode 253 and the third active fin 230, and the second pull-down transistor PD2 is defined near the third gate electrode. 253 is near the intersection of the fourth fin 240, and the second pass transistor PS2 is defined near the intersection of the fourth gate electrode 254 and the fourth active fin 240.

Although not specifically shown, the source / drain electrodes are formed at respective intersections of the first to fourth gate electrodes 251-254 and the first to fourth active fins 210, 220, 230, 240. Side, and a plurality of contact points 250 are formed.

The contact 261 is connected to the second active fin 220, a third gate line 253, and a wire 271 in parallel. The same contact 361 is also connected to the third active fin 230, a first gate line 251, and a wire 272 in parallel.

At least one of the transistors included in the semiconductor devices 1 to 10 according to the above-described embodiments may be applied to at least one of the six transistors shown in FIGS. 20A and 20B. For example, a one-bit signal is input to the first and second pass transistors PS1 and PS2, and a power supply voltage is input to the first and second pull-up transistors PU1 and PS1 through a power supply node VCC. PU2. Therefore, if the transistor systems included in the semiconductor devices 1 to 10 according to the above embodiments are applied as the transistors described, an electrostatic discharge (ESD) operation and an improved yield rate can be achieved. Semiconductor device.

Next, a semiconductor device according to a twelfth embodiment will be described with reference to FIGS. 21 to 23.

FIG. 21 is a conceptual plan view of a semiconductor device according to a twelfth embodiment, FIG. 22 is a circuit diagram of the first SRAM memory cell of FIG. 21, and FIG. 23 is a plan diagram of the first SRAM memory cell of FIG. The following description will focus on the differences between this embodiment and the previous embodiment.

In the following description, the exemplary implementation aspect will be described with respect to an example in which an SRAM device is formed in each memory cell array region MR, but the aspect of the exemplary implementation aspect is not limited thereto. In addition, in the following description, the exemplary implementation mode will be described with respect to an example in which an 8T SRAM device including 8 transistors is formed in each memory cell array region MR, but the exemplary implementation The aspect is not limited to this.

First, referring to FIG. 21, a plurality of SRAM memory cell regions SMC1 and SMC2 are arranged on the memory cell array region MR of the semiconductor device 12. As shown in FIG. 21, a plurality of SRAM memory cell regions SMC1 and SMC2 are arranged and arranged in a matrix configuration to have an array configuration.

22, each of the SRAM memory cell regions SMC1 and SMC2 includes a inverter INV1 and INV2 connected in parallel between a power supply node VDD and a ground node VSS, and is connected to the inverter A first selection transistor PS1 and a second selection transistor PS2 at the output nodes of the inverters INV1 and INV2, a driving transistor DT controlled by the output of the first inverter INV1 and connected to the driving transistor DT The output transistor PT of the output node. That is, in this embodiment, each of the SRAM memory cell regions (for example, the first SRAM memory cell region SMC1) includes an SRAM device including eight transistors.

The first selection transistor PS1 and the second selection transistor PS2 are connected to a bit line BL and a complementary bit line BLb. The gates of the first pass transistor PS1 and the second pass transistor PS2 are connected to a write word line WWL.

The first inverter INV1 includes a first pull-up transistor PU1 and a first pull-down transistor PD1 sequentially connected to each other, and the second inverter INV2 includes a second upper transistor sequentially connected to each other. The transistor PU2 is pulled and a second transistor PD2 is pulled down. The first pull-up transistor PU1 and the second pull-up transistor PU2 are PFET transistors, and the first pull-down transistor PD1 and the second pull-down transistor PD2 are NFET transistors.

In addition, in order to form a latch circuit, the input node of the first inverter INV1 is connected to the output node of the second inverter INV2, and the input node of the second inverter INV2 is connected to the via Output node of the first inverter INV1.

The driving transistor DT and the pass transistor PT are used to read data stored in a latch circuit including a first inverter INV1 and a second inverter INV2. A gate of the driving transistor DT is connected to an output node of the first inverter INV1, and a gate of the pass transistor PT is connected to a read word line RWL. As shown, the output of the driving transistor DT is connected to the ground node VSS and the output of the pass transistor PT is connected to a read bit line RBL.

With the circuit configuration, in the semiconductor device 12 according to the embodiment, the data stored in the SRAM device can be taken out through two communication ports (for example, dual communication ports). First, the writing word line WWL, the bit Line BL and the complementary bit line BLb are selected to write data in the latch circuit including the first inverter INV1 and the second inverter INV2, or to read and store in the latch circuit Information. That is, the path formed by the write word line WWL, the bit line BL, and the complementary bit line BLb is used as a first communication port. In addition, the read word line RWL and the read bit line RBL are selected to read data stored in the latch circuit including the first inverter INV1 and the second inverter INV2. That is, the path formed by the read word line RWL and the read bit line RBL is used as a second communication port.

In the aforementioned SRAM device, since the operations of the second communication port and the first communication port are performed independently, the data stored in the latch circuit will not be affected. In other words, the operation of reading data stored in the latch circuit and the operation of writing data to the latch circuit are performed independently.

Next, referring to FIG. 23, each of the SRAM memory cell regions (for example, the first SRAM memory cell region SMC1) includes 9 active fins F1 to F9, 5 gate electrodes G1 to G5, and a plurality of contacts. Points 300, 302, 304, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, and 326.

The first to ninth active fins F1 to F9 are configured to extend in the second direction (for example, in the Y-axis direction).

The first gate electrode G1 overlaps the first to third active fins F1 to F3 and extends in a first direction (for example, in an X-axis direction). The first pull-down transistor PD1 is formed on the first and second active fins F1. And the intersection of F2 and the first gate electrode G1, and the first pull-up transistor PU1 is formed at the intersection of the third active fin F3 and the first gate electrode G1.

The source of the first pull-down transistor PD1 is connected to the second contact point 302. Here, the second contact point 302 is connected to the ground node VSS. The source of the first pull-up transistor PU1 is connected to the fifth contact point 308. Here, the fifth contact point 308 is connected to the power supply node VDD. The drain of the first pull-down transistor PD1 and the drain of the first pull-up transistor PU1 are connected to the first contact point 300. That is, the first pull-down transistor PD1 and the first pull-up transistor PU1 share the first contact point 300.

At the same time, the first selection transistor PS1 is formed at the intersection of the first and second active fins F1 and F2 and the second gate electrode G2. The drain of the first selection transistor PS1 is connected to the first contact point 300. That is, the first pull-down transistor PD1, the first pull-up transistor PU1, and the first selection transistor PS1 share the first contact point 300. The source of the first selection transistor PS1 is connected to the fourth contact point 306. In addition, the fourth contact point 306 is connected to the bit line BL. At the same time, the second gate electrode G2 is connected to the third contact point 304. The third contact point 304 is connected to the write word line WWL.

Here, the first pull-down transistor PD1 and the first selection transistor PS1 are formed by two active fins F1 and F2, and the first pull-up transistor PU1 is formed by an active fin F3. form. Therefore, the first pull-down transistor PD1 and the first selection transistor PS1 are larger in size than the first Pulling transistor PU1 comes big.

The sixth contact point 310 is connected to the first contact point 300 via the third active fin F3. The sixth contact point 310 is connected to the fifth gate electrode G5. The fifth gate electrode G5 extends in the first direction (for example, in the X-axis direction) to cross the fourth to ninth active fins F4 to F9.

The second pull-up transistor PU2 is formed at the intersection of the fourth active fin F4 and the fifth gate electrode G5, and the second pull-down transistor PD2 is formed at the fifth and sixth active fins. The intersections of the sheets F5 and F6 and the fifth gate electrode G5, and the driving transistor DT are formed at the intersections of the seventh to ninth active fins F7-F9 and the fifth gate electrode G5.

As described above, because the first contact point 300 is connected to the fifth gate electrode G5 via the third active fin F3 and the sixth contact point 310, the first pull-up transistor PU1, the first pull-down transistor The outputs of the transistor PD1 and the first selection transistor PS1 are applied to the gates of the second pull-up transistor PU2, the second pull-down transistor PD2, and the driving transistor DT.

The drain of the second pull-up transistor PU2 and the drain of the second pull-down transistor PD2 are connected to the seventh contact point 312 and the fourteenth contact point 326, respectively. In addition, the seventh contact point 312 is connected to the first gate electrode G1. Therefore, the output of the second pull-up transistor PU2 and the output of the second pull-down transistor PD2 are applied to the gates of the first pull-up transistor PU1 and the first pull-down transistor PD1.

The source of the second pull-up transistor PU2 is connected to the eighth contact point 314. In addition, the eighth contact point 314 is connected to the power supply node VDD. Source of the second pull-down transistor PD2 and the driver The source of the transistor DT is connected to the thirteenth contact point 324. In addition, the thirteenth contact point 324 is connected to the ground node VSS.

The second selection transistor PS2 is formed at the intersection of the fifth and sixth active fins F5 and F6 and the third gate electrode G3, and the pass transistor PT is formed at the seventh to ninth Intersections of the active fins F7 to F9 and the fourth gate electrode G4.

The source of the second selection transistor PS2 is connected to the ninth contact point 316. The ninth contact point 316 is connected to the complementary bit line BLb. The drain of the second selection transistor PS2 is connected to the fourteenth contact point 326. As described above, the fourteenth contact point 326 is connected to the seventh contact point 312 via the fourth active fin F4, and the output of the second selection transistor PS2 is applied to the first pull-up transistor. PU1 and the gate of the first pull-down transistor PD1. Meanwhile, as shown, the third gate electrode G3 is connected to the tenth contact point 318. The tenth contact point 318 is connected to the write character bit WWL. In other words, the tenth contact point 318 and the fourth contact point 306 are electrically connected to each other.

The source of the via transistor PT is connected to the eleventh contact point 320. The eleventh contact point 320 is connected to the read bit line RBL. The drain of the pass transistor PT is connected to the drain of the driving transistor DT.

The fourth gate electrode G4 is connected to the twelfth contact point 322. The twelfth contact point 322 is connected to the read word line RWL. In this embodiment, the first SRAM memory cell area SMC1 and the second SRAM memory cell area SMC2 share the twelfth contact point 322 and the first Thirteen contact points 324, but the aspect of the exemplary implementation aspect is not limited to this. For example, in some other embodiments, the first SRAM memory cell area SMC1 and the second SRAM memory cell area SMC2 do not share a contact point, but are connected to the read word through separate contact points. The element line RWL and the ground node VSS.

At the same time, the driving transistor DT and the pass transistor PT are formed by three active fins F7 to F9, the second pull-down transistor PD2 and the second selection transistor PS2 are two active fins F5 And F6, and the second pull-up transistor PU2 is formed by an active fin F4. Therefore, the driving transistor DT and the pass transistor PT are larger in size than the second pull-down transistor PD2 and the second selection transistor PS2, and the second pull-down transistor PD2 and the second selection transistor are larger in size. The crystal PS2 is larger in size than the second pull-up transistor PU2. In other words, in this aspect, the size of the transistor formed at the boundary between the first SRAM memory cell area SMC1 and the second SRAM memory cell area SMC2 will be larger than the distance from the first SRAM memory The transistor size at the boundary between the cell area SMC1 and the second SRAM memory cell area SMC2 is large.

At least one of the transistors included in the semiconductor devices 1 to 10 according to the above-described embodiments is applied as at least one of the six transistors shown in FIGS. 22 to 23.

Next, semiconductor devices according to the thirteenth and fourteenth embodiments will be described with reference to FIGS. 24 and 25.

FIG. 24 illustrates a semiconductor device according to a thirteenth embodiment, and FIG. 25 illustrates a semiconductor device according to a fourteenth embodiment. The following description will Focus on the differences between this implementation and previous implementations.

First, referring to FIG. 24, the semiconductor device 13 according to the thirteenth embodiment includes a logic region 410 and a SRAM formation region 420. A first transistor 411 is disposed on the logic region 410 and a second transistor 421 is disposed on the SRAM formation region 420.

Next, referring to FIG. 25, the semiconductor device 14 according to the fourteenth embodiment includes a logic region 410, and third and fourth transistors 412 and 422 which are different from each other are disposed in the logic region 410. Meanwhile, although not shown individually, the third and fourth transistors 412 and 422 which are different from each other are also arranged in a SRAM formation region.

Here, the first transistor 411 is one of the semiconductor devices 1 to 10 according to the above embodiment, and the second transistor 421 is one of the semiconductor devices 1 to 12 according to the above embodiment. For example, the first transistor 411 is the semiconductor device 1 shown in FIG. 1, and the second transistor 421 is the semiconductor device 12 shown in FIG. 22.

Meanwhile, the third transistor 412 is one of the semiconductor devices 1 to 10 according to the above-mentioned embodiment, and the fourth transistor 422 is one of the semiconductor devices 1 to 10 according to the above-mentioned embodiment.

In FIG. 24, the logic area 410 and the SRAM formation area 420 are exemplified, but the aspect of the exemplary implementation aspect is not limited thereto. For example, the exemplary embodiment also applies to the logical area 410 and areas for forming other types of memories (eg, DRAM, MRAM, RRAM, PRAM, etc.). FIG. 26 is a block flowchart of a wireless communication device including a semiconductor device according to an exemplary embodiment.

Referring to FIG. 26, the wireless communication device 900 is a mobile phone, a smart phone, a telephone receiver, a personal digital assistant (PDA), a notebook computer, an electric game kit, or other types of devices. The wireless communication device 900 adopts code division multiple access (CDMA) and time division multiple access (TDMA), such as Global System for Mobile Communications (GSM), or other types of wireless communication standards.

The wireless communication device 900 provides a two-way communication by a receiving path and a transmitting path. On the receiving path, signals transmitted by one or more base stations are received by an antenna 911 or provided to a receiver (RCVR) 913. The receiver 913 conditions or digitizes the received signal and provides a sample to a digital section 920 for further processing. On the transmission path, a transmitter (TMTR) 915 receives data transmitted from the digital section 920, processes and conditions the data, and generates data to be transmitted to one or more base stations via the antenna 911. Modulate the signal.

The digital section 920 is executed by one or more digital signal processors (DSPs), microprocessors, or reduced instruction set computers (RISC). The digital section 920 is fabricated on one or more special-purpose integrated circuits (ASICs) or other types of ICs.

The digital section 920 includes, for example, various processors and interface units, such as a modem processor 934, a video processor 922, an application processor 924, a display processor 928, a controller / multi-core processor 926, A central processing unit 930 and an external bus interface (EBI) 932.

The video processor 922 executes processing of a graphic application. Generally, the video processor 922 is a module for graphic operation including any number of processing units or any array. A special part of the video processor 922 is And / or software. For example, a controller is implemented by a firmware and / or software module for performing the above functions (eg, steps, functions, etc.). The firmware and / or software code is stored in a memory or executed by a processor (eg, a multi-core processor 926). The memory system is implemented inside or outside the processor.

The video processor 922 executes a software interface, such as an open graphic library (OpenGL) or Direct3D. The central processing unit 930 is accompanied by the video processor 922 to perform a series of graphics processing operations. The controller / multi-core processor 926 includes at least two cores, and the controller / multi-core processor 926 allocates workload to at least two cores according to the workload to be processed and simultaneously processes corresponding tasks. the amount.

In the illustrated embodiment, the application processor 924 is exemplified as a component of the digital section 920, but the aspect of the exemplary embodiment is not limited thereto. In some implementations, the digital section 920 is incorporated into an application processor 924 or an application chip.

The modem processor 934 performs operations required during data transmission between the receiver 913, the transmitter 915, and the digital section 920. The display processor 928 performs operations required to drive the display 910.

The semiconductor devices 1 to 14 according to the above embodiments are used as cache memory or buffer memory for performing operations of the processors 922, 924, 926, 928, 930, and 934.

Next, a description will be given with reference to FIG. Computing system for semiconductor devices.

FIG. 27 is a block flow diagram of a computing system including a semiconductor device according to an exemplary embodiment.

Referring to FIG. 27, the computing system 1000 includes a central processing unit (CPU) 1002, a system memory 1004, a graphics system 1010, and a display 1006.

The CPU 1002 performs operations required to drive the computing system 1000. The system memory 1004 is configured to store data. The system memory 1004 stores data processed by the CPU 1002. The system memory 1004 is used as the working memory of the CPU 1002. The system memory 1004 includes one or more volatile memory devices, such as a double data rate static dynamic random access memory (DDR SDRAM) or a single data transfer rate. Single data rate static dynamic random access memory (SDR SDRAM), and / or one or more non-volatile memory devices, such as: electronic erasable programmable read-only memory (electrical erasable programmable ROM (EEPROM) or flash memory.

One of the semiconductor devices 1 to 14 according to the above embodiment is applied as a component of the system memory 1004.

The graphics system 1010 includes a graphics processing unit (GPU) 1011, a graphics memory 1012, a display controller 1013, a graphics interface 1014, and a graphics memory controller 1015.

The GPU1011 is required for execution of the computing system 1000. Graphic operations. In detail, the GPU 1011 series includes one or more head primitives and uses the combined primitives to perform deduction.

The graphics memory 1012 stores graphics data processed by the GPU 1011 or stores data provided by the GPU 1011. Alternatively, the graphics memory 1012 is used as a working memory of the GPU 1011. One of the semiconductor devices 1 to 6 according to the above embodiment is applied as a part of the graphic memory 1012.

The display controller 1013 controls the display 1006 to display a rendered image structure.

The graphic interface 1014 is defined between the CPU 1002 and the GPU 1011, and the graphic memory controller 1015 provides memory access between the system memory 1004 and the GPU 1011.

Although not shown in FIG. 27, the computing system 1000 includes at least one input device, such as a button, a touch screen, a microphone, and the like, and / or at least one output device, such as a speaker and the like. The computing system 1000 further includes an interface device for exchanging data with an external device in a wired or wireless manner. The interface device includes an antenna or a wired / wireless transceiver.

According to the implementation aspect, the computing system 1000 is a random computing system: a mobile phone, a smart phone, a personal digital assistant (PDA), a desktop computer, a notebook computer, a tablet computer, and the like.

Next, an electronic system including a semiconductor device according to an embodiment will be described with reference to FIG. 28.

FIG. 28 is a circuit diagram of a semiconductor device including a semiconductor device according to an embodiment; Block diagram of the subsystem.

Referring to FIG. 28, the electronic system 1100 includes a controller 1110, an input / output device (I / O) 1120, a memory device 1130, an interface 1140, and a bus 1150. The controller 1110, the I / O 1120, the memory device 1130, and / or the interface 1140 are connected to each other via the bus 1150. The bus 1150 moves through its data corresponding to the path.

The controller 1110 includes at least a microprocessor, a digital signal processor, a microcontroller, and a logic element capable of performing functions similar to these elements. The I / O1120 series includes a small keyboard, a keyboard, a display device, and so on. The memory device 1130 stores data and / or instructions. The interface 1140 performs a function of transmitting data to or receiving data from a communication network. The interface 1140 is wired or wireless. For example, the interface 1140 includes an antenna and / or a wired / wireless transceiver and the like.

Although not shown, the electronic system 1100 further includes high-speed DRAM and / or SRAM as working memory to improve the operation of the controller 1110. Here, as the working memory, one of the semiconductor devices 1 to 6 according to some embodiments is applied. In addition, one of the semiconductor devices 1 to 14 according to some embodiments is prepared in the memory device 1130 or is prepared as a component of the controller 1110 or the I / O 1120.

The electronic system 1100 is applied to a digital assistant (PDA), a portable computer, a tablet computer, a wireless phone, a mobile phone, a digital music player, a memory card, or a wireless environment. Any type of electronic device that sends and / or receives messages.

29 to 31 illustrate exemplary semiconductor systems to which a semiconductor device according to some embodiments may be applied.

FIG. 29 illustrates an example in which a semiconductor device according to an implementation aspect is applied to a tablet computer 1200, and FIG. 30 illustrates an example in which a semiconductor device according to an implementation aspect is applied to a notebook computer 1300, and FIG. 31 illustrates an example in which a semiconductor device according to an embodiment is applied to a smartphone 1400. At least one of the semiconductor devices 1 to 14 according to some embodiments may be applied to a tablet computer, a notebook computer, a smart phone, and the like.

Those skilled in the art will understand that semiconductor devices according to certain implementations can also be applied to other IC devices not described here.

That is, in the illustrated embodiment, only the tablet computer 1200, the notebook computer 1300, and the smart phone 1400 are proposed as examples of the semiconductor system according to the embodiment, but it is not limited thereto.

In some implementations, the semiconductor system can be implemented as a computer, an ultra mobile personal computer (UMPC), a workstation, a small laptop, a personal digital assistant (PDA), and a notebook. Computer, a wireless phone, a mobile phone, an e-book, a mobile multimedia player (PMP), a mobile game console, a navigation device, a black box, a digital camera, a 3D TV, a digital recorder, a Digital audio player, digital video recorder, digital video player, digital video recorder, digital video player, etc.

Next, a description will be given with reference to Figs. A method of implementing a semiconductor device of one aspect.

32 to 34 illustrate intermediate procedure steps in a method for manufacturing a semiconductor device according to certain embodiments.

First, referring to FIG. 32, a gate insulating layer 40 and a gate electrode 50 are sequentially formed on the active fin F. Next, an etch stop layer 80 is formed on one side of the gate electrode 50 of the second transistor TR2, and an extended impurity region is to be formed there. In some embodiments, the spacers 60 on the two sides of the gate electrode 50 and the etch stop layer 80 are formed simultaneously. Therefore, when the spacer 60 is formed of, for example, a nitride layer, the etch stop layer 80 is also formed of a nitride layer.

Next, the trench 19 is formed by etching the active fin F using the formed spacer 60, the gate electrode 50, and the etch stop layer 80 as a mask. Therefore, as shown in FIG. 32, the trench 19 is formed adjacent to the gate electrode 50 or adjacent to the etch stop layer 80.

Next, the epitaxial layer 20 is formed in the trench 19 by using, for example, an epitaxial generation method. Therefore, the epitaxial layer 20 fills the inside of the trench 19 and is formed for a sufficient time. Here, the upper surface of the epitaxial layer 20 becomes higher than the lower surface of the gate electrode 50. At the same time, the epitaxial layer 20 is not formed in a region where the spacer 60, the gate electrode 50 and the etch stop layer 80 are formed.

Next, referring to FIG. 33, an impurity diffusion method is performed on the active fin F by using the gate electrode 50 and the etch stop layer 80 as a mask. In some embodiments, the impurity diffusion method includes a first diffusion method shown in FIG. 33 and a second diffusion method shown in FIG. 34.

First, through the first diffusion method shown in FIG. 33, impurities are diffused into the epitaxial layer 20. Here, the impurity does not diffuse into the active fin F with the etch stop layer 80. In some embodiments, the first diffusion method includes an ion implantation procedure to implant ions into the active fin F with a first energy, but the aspect of the exemplary embodiment is not limited thereto.

Next, referring to FIG. 34A, after the mask MS exposing the etch stop layer 80 is formed, the impurities are diffused into the active fin F through the second diffusion method. Here, the impurity diffuses deeply into the active fin F, as shown in FIG. 34. In some embodiments, the second diffusion method includes an ion implantation procedure to implant ions into the active fins F with a second energy, the second energy being greater than that in the first diffusion method. The first energy used is strong, but the aspect of the exemplary embodiment is not limited thereto.

Thereafter, as shown in FIG. 34B, the mask MS is removed, and an intermediate dielectric layer (ILD) 340 is formed. The ILD 340 is etched to form a contact hole to expose the ends of the first impurity region 42 and the second impurity region 44. The contact points (or contact plugs) 70 and 90 are respectively formed in the contact hole and are electrically connected to the first and second impurity regions 42 and 44 respectively. Therefore, the semiconductor device 1 shown in FIG. 2A is manufactured. It will be appreciated that the diagrams of FIG. 2A and other exemplary implementations do not show that the ILD layer is merely for ease of description. Meanwhile, the semiconductor device 2 shown in FIG. 6 is manufactured by removing the etch stop layer 80 after the method shown in FIG. 34A and before the method shown in FIG. 34B.

Next, a manufacturing basis will be described with reference to FIGS. 35A to 35B. Some other methods of implementing a semiconductor device.

FIG. 35A illustrates intermediate procedure steps in a method for manufacturing a semiconductor device according to certain other implementations.

Referring to FIG. 35A, in the method for manufacturing a semiconductor device according to the embodiment, when the gate electrode 50 is formed on the active fin F, a dummy gate electrode 52 is also formed. Next, an etch stop layer 80 is formed on the dummy gate electrode 52 and the active fin F. In detail, as shown in FIG. 35A, the etch stop layer 80 is formed so that the end of the etch stop layer 80 is disposed at the center of the dummy gate electrode 52.

As in the previous embodiment, an epitaxial layer 20 is formed in the trench 19 after the trench 19 is formed, and an impurity diffusion method is performed. Then, the impurity diffusion method is performed again on the surface of the active fin F from which the etch stop layer 80 is removed. Next, the impurity regions 42 and 44 shown in FIG. 8 are formed. The mask MS was removed and an ILD350 was formed. The ILD350 is etched to form a contact hole to expose the first impurity region 42, the second sub-impurity region 44b, the first sub-impurity region 44b (near the end portion of the second impurity region 44), and the The end portion of the two impurity regions 44. The contact points (or contact plugs) 70, 352, 354, and 90 are respectively formed in the contact hole. The contact points 70, 352, 354, and 90 are respectively electrically connected to the digital portions of the first impurity region 42, the second sub-impurity region 44b, the first sub-impurity region 44a, and the second impurity region. A wiring 356 is also formed on the ILD 350 of the electrical connection contacts 352 and 354. As will be understood, the contact points 352 and 354 and the wiring 356 form the connection line 92. The connection line 92 electrically connects the first sub-impurity region 44a. To the second sub-impurity region 44b, thereby manufacturing the semiconductor device 3 shown in FIG.

Next, a method for manufacturing a semiconductor device according to some other embodiments will be described with reference to FIG. 36.

FIG. 36 illustrates intermediate procedure steps in a method for manufacturing a semiconductor device according to certain other implementations. The following description will focus on the differences between this embodiment and the previous embodiment.

Referring to FIG. 36, in the method for manufacturing a semiconductor device according to the embodiment, when the gate electrode 50 is formed on the active fin F, the first and second dummy gate electrodes 52 and 54 are also Having formed. Next, an etch stop layer 80 is disposed on the second virtual gate electrode 54, but is not disposed on the first virtual gate electrode 52. In detail, as shown in FIG. 36, the etch stop layer 80 is formed so that an end of the etch stop layer 80 is disposed between the first virtual gate electrode 52 and the second virtual gate electrode 54. .

In addition, in a manner similar to the above embodiment, a trench 19 is formed and an epitaxial layer 20 is formed in the trench 19, and an impurity diffusion method is successively performed. Then, the impurity diffusion method is performed again on the surface of the active fin F from which the etch stop layer 80 is removed. Next, the impurity regions 42 and 44 shown in FIG. 11 are formed. Thereafter, an ILD layer, a contact point, and a connection line for electrically connecting the first sub-impurity region 44a and the second sub-impurity region 44b are formed, thereby manufacturing the semiconductor device 3 shown in FIG. 11.

Meanwhile, as described above, if part of the etch stop layer 80 is caused by When the etch stop layer 80 is removed and the mask is misplaced and damaged, the semiconductor device having a shape similar to that of the semiconductor device 5 shown in FIG. 12 is prepared.

Next, a method for manufacturing a semiconductor device according to some other embodiments will be described with reference to FIG. 37.

FIG. 37 illustrates intermediate procedure steps in a method for manufacturing a semiconductor device according to certain other implementations. The following description will focus on the differences between this embodiment and the previous embodiment.

As shown in FIG. 37, when the etch stop layer 80 is at one end of the etch stop layer (80 of FIG. 36), it is disposed in a state between the first and the second virtual gate electrodes 52 and 54. After the removal, part of the etch stop layer 80 is left unremoved based on the dislocation of a mask. The remaining etch stop layer 80 masks the surface of the unexposed active fin F, so that the impurity region shown in FIG. 13 is formed on the active fin F with the etch stop layer 80 formed thereon. in. In other words, the dummy impurity regions 48a and 48b separated from each other are formed between the first dummy transistor DTR1 and the second dummy transistor DTR2.

Although specific exemplary embodiments are shown and described with reference to their exemplary embodiments, those having ordinary knowledge in the technical field will understand that various changes in various forms and details will be made without departing from the scope of the following patent applications Occurs within the context of defining the concept and scope of the invention. What is required is that thinking of this embodiment in a variety of ways is illustrative and not restrictive, and serves as a reference for the scope of the attached patent application, rather than the previous description as indicating the scope of the invention.

Claims (16)

A semiconductor device includes: at least one active fin protruding from a substrate; a first gate electrode crossing the active fin; and a first impurity region formed on the active fin. At a first side of a gate electrode, at least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin; and a second impurity region is formed in the At a second side of one of the first gate electrodes on the active fin, the second impurity region has a width larger than the first impurity region in a longitudinal direction of the active fin, and the second impurity region includes a first Part and a second part, the first part is formed in a second epitaxial layer part, and the second part is not formed in an epitaxial layer; wherein the first part and the second part A portion of the upper surface is substantially coplanar. According to the semiconductor device of claim 1, wherein the second impurity region has an upper surface that is located at the same height as an upper surface of a portion of the active fin that is crossed by the gate electrode. The semiconductor device according to claim 1, further comprising: a first contact point electrically connected to the first impurity region; and a second contact point electrically connected to the second impurity region with respect to One end of the first gate electrode. According to the semiconductor device of claim 1, wherein the first portion is located at an end of the second impurity region opposite to the first gate electrode. The semiconductor device according to claim 4, further comprising: a first contact point electrically connected to the first impurity region; and a second contact point electrically connected to the second impurity region. The first part. The semiconductor device according to claim 4, wherein an upper surface of one of the first portions is higher than an upper surface of the active fin which is traversed by the first gate electrode. According to the semiconductor device of claim 6, wherein an upper surface of one of the first impurity regions is higher than the upper surface of the active fin which is crossed by the first gate electrode. The semiconductor device according to claim 4, wherein the upper surface of the first impurity region and the upper surface of the first portion are at the same height. The semiconductor device according to claim 4, wherein the second impurity region includes a third portion, and the third portion is located at a proximal end of the second impurity region with respect to one of the first gate electrodes, and The third portion is formed in a third epitaxial layer portion on the active fin. For example, the semiconductor device according to claim 9, wherein an upper surface of the first portion and an upper surface of the third portion are at the same height. The semiconductor device according to claim 9, wherein an upper surface of one of the first portions is higher than an upper surface of the active fin which is crossed by the first gate electrode, and one of the third portions The surface is higher than the upper surface of the active fin traversed by the first gate electrode. The semiconductor device according to claim 4, further comprising: an etch stop layer formed on the second portion. The semiconductor device according to claim 4, wherein an upper surface of one of the first portions is at the same height as an upper surface of the active fin which is crossed by the first gate electrode. The semiconductor device according to claim 1, wherein the first portion is located at a proximal end of the second impurity region with respect to one of the first gate electrodes. According to the semiconductor device of claim 14, wherein an upper surface of one of the first portions is higher than an upper surface of the active fin which is crossed by the first gate electrode. The semiconductor device according to claim 15, wherein the upper surface of the first portion and the upper surface of one of the first impurity regions have the same height.