CN105206577B - A kind of semiconductor devices and preparation method thereof and electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof and electronic device Download PDFInfo
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- CN105206577B CN105206577B CN201410256238.0A CN201410256238A CN105206577B CN 105206577 B CN105206577 B CN 105206577B CN 201410256238 A CN201410256238 A CN 201410256238A CN 105206577 B CN105206577 B CN 105206577B
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Abstract
The present invention, which provides a kind of semiconductor devices and preparation method thereof and electronic device, the production method, to be included：Semiconductor substrate is provided, front-end devices on the semiconductor substrate formed with multiple storage units, the storage unit pulls up transistor including at least two, at least two pull-down transistors and at least two transmission gate transistors, wherein, it is described pull up transistor, the pull-down transistor and the transmission gate transistor include grid and gate lateral wall；Asymmetric pocket ion implanting is carried out to two transmission gate transistors in each storage unit.Production method according to the present invention, form the transmission gate transistor of the asymmetric pocket region with different levels of doping, can active balance sram cell writability and read stability between conflict, and then improve the writability and read stability of sram cell, lift the reliability of sram cell.
Description
Technical field
The present invention relates to technical field of semiconductor memory, in particular to a kind of semiconductor devices and preparation method thereof and
Electronic device.
Background technology
With the continuous development of digital integrated electronic circuit, the memory that on piece integrates has become group important in digital display circuit
Into part.SRAM (Static Random Access Memory, static RAM) is with its low-power consumption, high speed
Advantage becomes important component indispensable in on-chip memory.As long as SRAM can preserve data for its power supply, without
Constantly it is refreshed.
Basic SRAM memory cell generally comprises six transistors：2 PU (Pull-up that pull up transistor
Transistor), 2 pull-down transistor PD (Pull-down transistor), 2 transmission transistor PG (Pass-gate
transistor).In the design process of SRAM memory cell, usually to ensure sufficiently large β ratios (Ipd/Ipg electric currents
Than), to obtain sufficiently high static noise margin (static-noise margin, SNM), while require γ ratios (Ipg/
Ipu electric currents ratio) it is sufficiently large, to obtain good writability (writability).Therefore, to the difference of transmission transistor performance
It is required that cause conflicting between the writability of sram cell and read stability.And this conflict is traditional 6T all the time
The bottleneck of SRAM memory cell design.
Therefore, it is necessary to propose a kind of new technical solution, stablized with improving the writability of SRAM memory cell and reading
Property.
The content of the invention
In view of the deficiencies of the prior art, the present invention provides a kind of production method of semiconductor devices, including：
Semiconductor substrate is provided, the front-end devices on the semiconductor substrate formed with multiple storage units are described to deposit
Storage unit pulls up transistor including at least two, at least two pull-down transistors and at least two transmission gate transistors, wherein,
It is described pull up transistor, the pull-down transistor and the transmission gate transistor include grid and gate lateral wall；
Asymmetric pocket ion implanting is carried out to two transmission gate transistors in each storage unit.
Further, the asymmetric pocket ion implanting is noted by small angle inclination ion implanting and wide-angle tilt ion
Enter to combine to realize.
Further, when carrying out the wide-angle tilt ion implanting, by using two transmission gate transistors
The shadowing effect of neighboring gates, only to the semiconductor substrate region on the outside of the neighboring gates of two transmission gate transistors
Injected, the semiconductor substrate region among the neighboring gates is not injected.
Further, when carrying out the small angle inclination ion implanting, it is possible to achieve to two transmission gate transistors
The pocket injection of the semiconductor substrate region on the outside of grid and among the two neighboring transmission gate transistor grid.
Further, formd in the source region close to the transmission gate transistor with highly doped pocket region, close to drain region
Form with low-doped pocket region.
Further, the asymmetric pocket ion implanting uses N-type impurity as injection source.
Further, the N-type impurity is P or As.
Further, before the step of carrying out the asymmetric pocket ion implanting, further include to be formed described in covering each
The step of mask to pull up transistor described in two in storage unit.
Further, the semiconductor devices is static RAM.
The present invention also provides a kind of semiconductor devices, the semiconductor devices includes multiple storage units, and the storage is single
Member pulls up transistor including at least two, at least two pull-down transistors and at least two transmission gate transistors, wherein, every
In a storage unit, described two transmission gate transistors have the asymmetric pocket region of different levels of doping.
Further, the pocket region between the two neighboring transmission gate transistor grid is highly doped pocket region, position
Pocket region on the outside of two transmission gate transistors is highly doped pocket region.
Further, the semiconductor devices is static RAM.
In addition the present invention also provides a kind of electronic device, including above-mentioned semiconductor devices.
In conclusion production method according to the present invention, is injected by implementing asymmetric pocket to transmission gate transistor, made
Transmission gate transistor when carrying out read operation with low saturation current Idsat, while when carrying out write operation with high full
With electric current Idsat, and then the writability and read stability of SRAM memory cell are improved.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A is a kind of existing read circuit figure of 6T SRAM memory cells；
Figure 1B is a kind of existing write operation circuit diagram of 6T SRAM memory cells；
Fig. 2 is that the prior art carries out bowing for pocket injection to the pull-down transistor and transmission gate transistor of SRAM memory cell
View；
Fig. 3 A are the top view of the multiple storage units formed according to the embodiment of the present invention one；
Fig. 3 B are the diagrammatic cross-section according to two transmission gate transistors in Fig. 3 A in elliptical region；
Fig. 4 is the flow chart of method in the embodiment of the present invention one implementation steps successively；
Fig. 5 A are the circuit diagram of the storage unit formed according to the method for the embodiment of the present invention one；
Fig. 5 B are the schematic diagram of the transmission gate transistor formed according to the method for the embodiment of the present invention one.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed structure will be proposed in following description, to explain the skill of the present invention
Art scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention can also have
Other embodiment.
It is as shown in Figure 1A a kind of existing read circuit figure of 6T SRAM memory cells, in read operation, bit line BT
High level VDD is charged to paratope line BC, is then turned off connecting.At this moment access control signal WL is chosen to be increased to VDD,
Open transmission transistor T2 and T3.Without loss of generality, if the storage of B points for 0, then paratope line BC discharges into 0 by T3 and N1.
In read operation, high β ratios and slow PG can be such that node B is in than relatively low level, be conducive to prevent level is excessive from causing
Unit is overturn.
It is as shown in Figure 1B a kind of existing write operation circuit diagram of 6T SRAM memory cells, in write operation, it is assumed that B
Node storage for 0, bit line BT be connected with high level VDD, and paratope line BC is grounded, and node B passes through P1 and T3 electric discharges.Read operation
When, high γ ratios and fast PG can make node B quickly be pulled down to 0, realize the write-in of data.
Therefore, the difference of transmission transistor performance is required, caused between the writability of sram cell and read stability
Conflict.
It is that the prior art carries out mouth to the pull-down transistor PD and transmission gate transistor PG of SRAM memory cell with reference to figure 2
The top view of bag injection, arrow represents the orientation angle of pocket injection in figure.PG points of pull-down transistor PD and transmission gate transistor
The low-doped pocket injection of identical N-type is enjoyed, carries out 4 45 ° of tilt-angle ions injections, therefore pull-down transistor PD and transmission gate crystal
The pocket injection of pipe PG is identical.
Presence in view of the above problems, the present invention proposes a kind of new manufacture method, to balance the writeable of sram cell
Property and conflicting between read stability.
Embodiment one
In the following, the production method of the semiconductor devices of the embodiment of the present invention is done in detail with reference to Fig. 3 A-3B, Fig. 4 and Fig. 5 A-5B
Thin description.
With reference to figure 4, step 401 is performed, there is provided Semiconductor substrate, it is single formed with multiple storages on the semiconductor substrate
The front-end devices of member, what the storage unit included being formed in the Semiconductor substrate at least two pulls up transistor, at least
Two pull-down transistors and at least two transmission gate transistors, wherein, it is described pull up transistor, the pull-down transistor and institute
Stating transmission gate transistor includes grid and gate lateral wall.
Specifically, it is according to the top view of multiple storage units of formation of the embodiment of the present invention, with wherein one with reference to Fig. 3 A
Exemplified by a storage unit.
Semi-conductive substrate is provided, the Semiconductor substrate can be at least one of following material being previously mentioned：Silicon,
Silicon (SSOI) is laminated on silicon-on-insulator (SOI), insulator, is laminated on SiGe (S-SiGeOI) and insulator on insulator
SiGe (SiGeOI) etc..
Go out various active areas defined in the Semiconductor substrate, shallow trench isolation junction is formed with the active area surrounding
Structure；Specifically, active area is first defined, then active area surrounding etches shallow trench again, finally with being filled in the shallow trench
Insulating materials is to form the fleet plough groove isolation structure.
Formed with N-type trap injection region and p-type trap injection region in the Semiconductor substrate.In in the N-type trap injection region
Make at least two to pull up transistor PU, in making at least two pull-down transistor PD and at least two in p-type trap injection region
Transmission gate transistor PG.
Wherein, it is above-mentioned pull up transistor, pull-down transistor and transmission gate transistor include gate structure and gate electrode side
The components such as wall (not indicated in figure).In an example, the gate structure includes the gate dielectric in Semiconductor substrate
Layer, the polysilicon gate on gate dielectric.
Step 402 is performed, two pull-down transistor PD in each storage unit are carried out with pocket ion along the x-axis direction
Injection.
The mask of two PU that pull up transistor in each storage unit of covering is formed, it is then, single to each storage
Two pull-down transistor PD in member carry out pocket ion implanting along the x-axis direction, with the formed below of gate structure edge
Pouch-type doped region (not shown), the pocket ion implanting, as injection source, are made using N-type impurity for example with P or As
To inject source.Can be in the lower section at pull-down transistor PD gate structures edge using inclination injection mode along the x-axis direction, therefore only
Form pouch-type doped region.
Step 403 is performed, asymmetric pocket ion implanting is carried out to two transmission gate transistors in each storage unit.
As shown in Figure 3A, along the y-axis direction asymmetric is carried out to two transmission gate transistor PG in each storage unit
Pocket ion implanting, since ion implanting direction is along the y-axis direction, therefore only transmission gate transistor PG to be injected, no
Pull-down transistor PD can be had an impact.
With reference to wide-angle and small angle inclination ion implanting, asymmetric pocket ion implanting is realized.The pocket ion implanting
Using N-type impurity as injection source, for example with P or As injection source.Two of elliptical region in Fig. 3 B corresponding diagrams 3A
The diagrammatic cross-section of transmission gate transistor, the direction of arrow in Fig. 3 B represent the direction of ion implanting when carrying out pocket ion.Its
In, the first inclination angle a and the second inclination angle b refer to ion implanting direction and the angle perpendicular to the direction of the upper surface of front-end devices.
In the present embodiment, the first inclination angle a selects big inclination angle, can be more than 45 degree, is, for example, 70 degree.By using two transmission
The shadowing effect of the neighboring gates 301 of door transistor, only can be right when carrying out the wide-angle tilt ion implanting of the first inclination angle a
The semiconductor substrate region in the outside of neighboring gates 301 of two transmission gate transistors is injected, will not be to neighboring gates
The semiconductor substrate region among 301 is injected.
In the present embodiment, the second inclination angle b selects small inclination angle, can be less than 45 degree, for example, can be 0 degree.Carry out
During the small angle inclination ion implanting of the second inclination angle b, it is possible to achieve on the outside of two transmission gate transistor grids 301 and phase
The pocket injection of the semiconductor substrate region among adjacent two transmission gate transistor grids 301.
Since the injection of wide-angle pocket and low-angle pocket are injected outside all to the neighboring gates of two transmission gate transistor PG
The semiconductor substrate region of side is injected, therefore in the semiconductor substrate region on the outside of the neighboring gates of transmission transistor PG
Form highly doped pocket region.And a low-angle is only carried out to the region in the Semiconductor substrate among two neighboring gates
Angle-tilt ion is injected, therefore forms low-doped pocket region in the semiconductor substrate region among two neighboring grid.Such as Fig. 5 A
It is shown, it is the circuit diagram of the storage unit formed according to the method for the embodiment of the present invention, Fig. 5 B are to be implemented according to the present invention
The schematic diagram for the transmission gate transistor with asymmetric pocket region that the method for example is formed, as seen from the figure, close to transmission
The source region of door transistor is formd with highly doped pocket region, is formd close to drain region with low-doped pocket region.
The step of grid, drain node or source node form contact hole is additionally included in afterwards, and multiple contact holes are designed
To be square or rectangle in a top view, for being electrically connected, therefore not to repeat here.
The production method of the semiconductor devices of the embodiment of the present invention, can be used for making SRAM memory and other is similar
Semiconductor devices.
The production method of this semiconductor device, forms the transmission gate of the asymmetric pocket region with different levels of doping
Transistor, therefore different source-leakages/drain-source saturation current (Idsat) and threshold voltage (Vt) can be obtained.It can be achieved at the same time
The high threshold voltage of transmission gate transistor (Vt) and when write operation low threshold voltage (Vt) during read operation, and make transmission gate brilliant
Body pipe when carrying out read operation with low saturation current (Idsat), while when carrying out write operation with high saturation current
(Idsat)。
In conclusion production method according to the present invention, the biography of asymmetric pocket region of the formation with different levels of doping
Defeated door transistor, can active balance sram cell writability and read stability between conflict, and then it is mono- to improve SRAM
The writability and read stability of member, lift the reliability of sram cell.
Embodiment two
The embodiment of the present invention two provides a kind of semiconductor devices, which can use in above-described embodiment one
The production method of semiconductor devices is made.
The semiconductor devices of the present embodiment includes multiple storage units, and the storage unit includes crystal pulling at least two
Pipe, at least two pull-down transistors and at least two transmission gate transistors, wherein, it is described in each storage unit
Two transmission gate transistors have the asymmetric pocket region of different levels of doping.
Wherein, exemplarily, the pocket region between the two neighboring transmission gate transistor grid is highly doped mouth
Bag area, the pocket region on the outside of described two transmission gate transistors is highly doped pocket region.
Wherein, the semiconductor devices is static RAM.
The semiconductor devices of the embodiment of the present invention, since the transmission gate of the asymmetric pocket region with different levels of doping is brilliant
Body pipe, therefore conflicting between the writability of active balance sram cell and read stability, and then improve sram cell
Writability and read stability, lift the reliability of sram cell.
Embodiment three
The embodiment of the present invention provides a kind of electronic device, it uses the system of the semiconductor devices according to embodiment one
The semiconductor devices of method manufacture is made, or has used the semiconductor devices described in embodiment two.Due to the use of semiconductor devices
With different device ratios, therefore the electronic device has better performance.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in the range of described embodiment.In addition people in the art
Member is it is understood that the invention is not limited in above-described embodiment, teaching according to the present invention can also be made more kinds of
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of production method of semiconductor devices, including：
Semiconductor substrate, the front-end devices on the semiconductor substrate formed with multiple storage units, the storage list are provided
Member pulls up transistor including at least two, at least two pull-down transistors and at least two transmission gate transistors, wherein, it is described
Pull up transistor, the pull-down transistor and the transmission gate transistor include grid and gate lateral wall；
Asymmetric pocket ion implanting is carried out to two transmission gate transistors in each storage unit, makes described two biographies
The doping concentration of pocket region between defeated door transistor is dense less than the doping of the pocket region on the outside of described two transmission gate transistors
Degree, threshold voltage low during the high threshold voltage and write operation of transmission gate transistor during realizing read operation.
2. according to the method described in claim 1, it is characterized in that, the asymmetric pocket ion implanting passes through small angle inclination
Ion implanting and wide-angle tilt ion implanting are combined to realize.
3. according to the method described in claim 2, it is characterized in that, when carrying out the wide-angle tilt ion implanting, pass through
Using the shadowing effect of the neighboring gates of two transmission gate transistors, only to the adjacent gate of two transmission gate transistors
The semiconductor substrate region on the outside of pole is injected, not to the semiconductor substrate region among the neighboring gates into
Row injection.
, can be with 4. according to the method described in claim 2, it is characterized in that, when carrying out the small angle inclination ion implanting
Realize to described half on the outside of two transmission gate transistor grids and among the two neighboring transmission gate transistor grid
The pocket injection of conductor substrate area.
5. according to the method described in claim 1, it is characterized in that, form tool in the source region close to the transmission gate transistor
There is highly doped pocket region, formd close to drain region with low-doped pocket region.
6. according to the method described in claim 1, it is characterized in that, the asymmetric pocket ion implanting is made using N-type impurity
To inject source.
7. according to the method described in claim 6, it is characterized in that, the N-type impurity is P or As.
8. according to the method described in claim 1, it is characterized in that, carry out the asymmetric pocket ion implanting the step of it
Before, the step of further including the mask to pull up transistor described in be formed in each storage unit of covering two.
9. according to the method described in claim 1, it is characterized in that, the semiconductor devices is static RAM.
10. a kind of semiconductor devices, it is characterised in that the semiconductor devices includes multiple storage units, the storage unit
Pull up transistor including at least two, at least two pull-down transistors and at least two transmission gate transistors, wherein, each
In the storage unit, the doping concentration of the pocket region between described two transmission gate transistors is brilliant less than described two transmission gates
The doping concentration of pocket region on the outside of body pipe is low during the high threshold voltage and write operation of transmission gate transistor during realizing read operation
Threshold voltage.
11. device according to claim 10, it is characterised in that positioned at the two neighboring transmission gate transistor grid it
Between pocket region be low-doped pocket region, the pocket region on the outside of two transmission gate transistors is highly doped pocket region.
12. device according to claim 10, it is characterised in that the semiconductor devices is static random access memory
Device.
13. a kind of electronic device, it is characterised in that including the semiconductor devices described in claim 10.
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| CN105206577B true CN105206577B (en) | 2018-05-04 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112447729A (en) * | 2019-09-04 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| US10950298B1 (en) * | 2020-01-17 | 2021-03-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mixed threshold voltage memory array |
| CN113140515A (en) * | 2021-03-29 | 2021-07-20 | 上海华力集成电路制造有限公司 | Method for adjusting Beta ratio of SRAM |
| CN116631472B (en) * | 2023-07-18 | 2023-10-20 | 全芯智造技术有限公司 | Semiconductor device, method for manufacturing the same, and method for optimizing parameters |
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