CN107785372A - Semiconductor devices and preparation method thereof, electronic installation - Google Patents
Semiconductor devices and preparation method thereof, electronic installation Download PDFInfo
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- CN107785372A CN107785372A CN201610719840.2A CN201610719840A CN107785372A CN 107785372 A CN107785372 A CN 107785372A CN 201610719840 A CN201610719840 A CN 201610719840A CN 107785372 A CN107785372 A CN 107785372A
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Element Separation (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention provides a kind of semiconductor devices and preparation method thereof, electronic installation, and the preparation method is used to make flash memory, and it comprises the steps：Semiconductor substrate is provided, well region is formed in the Semiconductor substrate, and form patterned gate stack and active area hard mask layer on the semiconductor substrate；Ion implanting is compensated to the corner regions of active area, the counterion is identical with the Doped ions of the well region；Using the active area hard mask layer as Semiconductor substrate described in mask etching, to form the groove for being used for forming isolation structure；Fill the groove and form isolation structure.The preparation method to active area corner regions, namely isolation structure corner regions by compensating ion implanting, to compensate the well region Doped ions segregation of such as boron ion, so as to solve thus caused dual hump and electrical leakage problems.The semiconductor devices and electronic installation overcome dual hump and electrical leakage problems.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof, electronics
Device.
Background technology
With the development of manufacture of semiconductor technology, the faster flash of access speed has been developed in terms of storage device
Device (flash memory).Flash memory acts with can repeatedly enter deposit, reading and erasing of row information etc., and be stored in
The characteristic that information will not also disappear after a loss of power, therefore, flash memory has turned into PC and electronic equipment is adopted extensively
A kind of nonvolatile memory.And NAND (NAND gate) fast storages are due to large storage capacity and relatively high property
Can, it is widely used in the field that read/write requires higher.Recently, the capacity of NAND quick-flash memory chip has reached 2GB, and
Size increases sharply.The solid state hard disc of NAND quick-flash memory chip has been developed based on, and has been used as in pocket computer
Storage device.Therefore, in recent years, NAND quick-flash memory is widely used as the storage device in embedded system, also serves as individual
Storage device in computer system.
In advanced NAND shock processings flow (for example, 3X, 2X and following nm technology nodes), due to using autoregistration
STI (shallow trench isolation) etching technics so that well region injection (well implant) needs to implement in the incipient stage, and can not picture
Logic circuit is the same to be implemented after STI flatening process.Because：1) if well region is infused in the laggard of tunnel oxidation
OK, integrity problem, such as GOI TDDB (gate oxides can be caused through the injection of tunneling oxide layer (tunnel oxide)
Reliability testing, the dielectric breakdown with time correlation), it is GOI Vramp (reliability of the gate oxide test, ramp voltage), resistance to
Long property and data are kept.2) as NAND quick-flash memory memory cell is contracted to 3xnm and following technology node, STI depth-to-width ratios
(aspect ratio) is very big, and then the filling of STI spaces becomes increasingly difficult to for this.Therefore, introduce mobility chemical vapor deposition
(FCVD) technique is used for STI filling.But FCVD oxides need to be densified, ensuing densification heat treatment step
Need very high heat budget.In STI fills densification process, serious boron segregation (boron segregation) be present and ask
Topic, which results in the dual hump of device and electrical leakage problems.Fig. 1 shows that the dual hump that high pressure NMOS part has and electric leakage are asked
Topic, even if channel dopant concentration is higher, however it remains this problem.
It is, therefore, desirable to provide a kind of preparation method of new semiconductor devices, to solve the above problems at least in part.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In view of the shortcomings of the prior art, the present invention proposes a kind of preparation method of new semiconductor devices, can overcome
Caused dual hump and electrical leakage problems during NAND quick-flash memory STI makes.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of preparation method of semiconductor devices, is used for
Flash memory is made, it comprises the steps：Semiconductor substrate is provided, forms well region in the Semiconductor substrate, and
Patterned gate stack and active area hard mask layer is formed in the Semiconductor substrate；The corner regions of active area are mended
Ion implanting is repaid, the counterion is identical with the Doped ions of the well region；Carved by mask of the active area hard mask layer
The Semiconductor substrate is lost, to form the groove for being used for forming isolation structure；Fill the groove and form isolation structure.
Further, the counterion injection is carried out with tilting injection mode.
Further, the angle of inclination of counterion injection and the normal perpendicular to the semiconductor substrate surface it
Between angle be 0~15 degree.
Further, the counterion is boron ion.
Further, the Implantation Energy of the boron ion is 0~30keV.
Further, the implantation dosage of the boron ion is 0.5~2E13/cm2。
The preparation method of semiconductor devices proposed by the present invention, by active area corner regions, namely isolation structure angle
Domain of settling in an area compensates ion implanting, thus caused so as to solve to compensate the well region Doped ions segregation of such as boron ion
Dual hump and electrical leakage problems.
Another aspect of the invention provides a kind of semiconductor devices made using the above method, and the semiconductor devices includes：
Semiconductor substrate, the active area separated in the Semiconductor substrate formed with isolation structure and by the isolation structure,
Formed with well region in the active area, formed with gate stack in the Semiconductor substrate of the active area, in the active area
Corner regions form counterion injection region, wherein, counterion and the well region in the counterion injection region
Doped ions are identical.
Further, the counterion is boron ion.
Further, the Implantation Energy of the boron ion is 0~30keV.
Further, the implantation dosage of the boron ion is 0.5~2E13/cm2。
Semiconductor devices proposed by the present invention overcomes dual hump and electrical leakage problems.
Further aspect of the present invention provides a kind of electronic installation, it include semiconductor devices as described above and with it is described partly
The electronic building brick that conductor device is connected.
Electronic installation proposed by the present invention, due to above-mentioned semiconductor device, thus with it is similar the advantages of.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the Id-Vg curves of high pressure NMOS part, wherein dual hump and electrical leakage problems be present；
Fig. 2 shows the step flow chart of the preparation method of semiconductor devices according to an embodiment of the present invention；
Fig. 3 A~Fig. 3 C show that the preparation method of semiconductor devices according to an embodiment of the present invention is implemented respectively successively
Step obtains the diagrammatic cross-section of semiconductor devices；
Fig. 4 shows the high pressure NMOS part of the preparation method formation of semiconductor device according to the invention and current height
Press the Id-Vg curves of nmos device；
Fig. 5 shows the sectional view of semiconductor devices according to an embodiment of the present invention；
Fig. 6 shows the schematic diagram of electronic installation according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated phase from beginning to end
Identical element is represented with reference.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " other members
When part or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be element or layer between two parties.On the contrary, when element be referred to as " on directly existing ... ", " with ... direct neighbor ", " be directly connected to
To " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although art can be used
Language first, second, third, etc. describe various elements, part, area, floor and/or part, these elements, part, area, floor and/or portion
Dividing to be limited by these terms.These terms are used merely to distinguish an element, part, area, floor or part and another
Element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, part, area,
Floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ",
" above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with it is other
The relation of element or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of with
The different orientation of device in operation.For example, if the device upset in accompanying drawing, then, is described as " below other elements "
Or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary term
" ... below " and " ... under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other takes
To) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
As it was previously stated, with the diminution of critical size, it is easily double hunchbacked in the current preparation method of NAND type flash memory
Peak and electrical leakage problems, think that the boron segregation of active area corner regions is dual hump and the leakage of high pressure NMOS part by data analysis
The basic reason of electric problem.
The present invention is based on this, it is proposed that a kind of preparation method of semiconductor devices, for making flash memory, and the making
Method comprises the steps：Step 201, there is provided Semiconductor substrate, well region is formed in the Semiconductor substrate, and described half
Patterned gate stack and active area hard mask layer is formed on conductor substrate；Step 202, the corner regions of active area are carried out
Counterion injects, and the counterion is identical with the Doped ions of the well region；Step 203, with the hard mask of the active area
Layer is Semiconductor substrate described in mask etching, to form the groove for being used for forming isolation structure；Step 204, the groove is filled
Form isolation structure.
The preparation method of semiconductor devices proposed by the present invention, to active area corner regions, namely isolation structure corner region
Domain compensates ion implanting, to compensate the well region Doped ions segregation of such as boron ion, so as to solve thus caused double camels
Peak and electrical leakage problems.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description, to explain this hair
The technical scheme of bright proposition.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, the present invention
There can also be other embodiment.
Embodiment one
Ginseng 3A~Fig. 3 C and Fig. 4 is done in detail to the preparation method of the semiconductor devices of an embodiment of the present invention below
Description.
First, as shown in Figure 3A, there is provided Semiconductor substrate 300, formation well region (does not show in the Semiconductor substrate 300
Go out), patterned gate stack and active area hard mask layer 303, the gate stack are formed in the Semiconductor substrate 300
Including tunnel oxide 301 and floating boom 302.
Wherein, Semiconductor substrate 300 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, Semiconductor substrate 300
Constituent material select monocrystalline silicon.
Well region can be formed by ion implanting, and injection ion is according to well region type.Exemplarily, in the present embodiment,
Semiconductor devices is high-pressure N-shaped semiconductor devices, thus well region injection ion is p-type ion, such as boron ion.
Gate stack includes tunnel oxide 301 and floating boom 302, and it uses structure and forming method system commonly used in the art
Make.Such as tunnel oxide 301 is illustratively silicon oxide layer, it can be by the way that such as (physical vapor be sunk for thermal oxidation method, PVD
Product), CVD (chemical vapor deposition), ALD (ald) the methods of formed.Floating boom 301 exemplarily uses such as polysilicon
Deng semi-conducting material, and by selecting molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low pressure chemical gas
A kind of mutually formation in deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG).
Active area mask layer 303 is made using material commonly used in the art and method, such as active area mask layer 303 can be with
Using hard mask material layers such as oxide, nitride or nitrogen oxides.And pass through PVD (physical vapour deposition (PVD)), CVD (chemistry
Vapour deposition), ALD (ald) the methods of formed.Exemplarily, in the present embodiment, active area mask layer 304 uses
Oxide, such as silica.
Further, gate stack and the graphical of active area mask layer pass through lithographic etch process shape commonly used in the art
Into the shape of gate stack is corresponding with memory cell, the shape and the shape pair of active area and isolation structure of active area mask layer
Should, i.e. active area mask layer masking Semiconductor substrate is used for the region for forming active area, and exposing semiconductor substrate is used to be formed
The region of isolation structure.
Then, as shown in Figure 3 B, ion implanting is compensated to the corner regions of active area, to form counterion injection
Area 304, the counterion are identical with the Doped ions of the well region.
As previously described, because the high fever budget process in follow-up STI filling process can cause the well region of such as boron adulterate from
Sub- segregation problem, and then cause dual hump and electrical leakage problems.Therefore, after completion active area floats and deletes etching, to active area angle
Settle in an area domain, namely the corner regions for the isolation structure being subsequently formed compensate ion implanting, with the corner regions of active area
Form counterion injection region 304, so presence due to counterion injection region 304, even if in follow-up STI filling process
High fever budget process can cause the well region Doped ions segregation problem of such as boron, but due to repaying the presence of ion implanted region 304,
It can reduce or even avoid dual hump and electrical leakage problems caused by the well region Doped ions segregation problem of such as boron.
Further, in order to form counterion injection region 304 in the corner regions of active area, such as arrow institute in Fig. 3 B
Show, counterion injection is carried out with tilting injection mode.Preferably, the angle of inclination of the counterion injection is 0~15 degree
(i.e. with ion implanting direction and the angle between the normal of the semiconductor substrate surface).
Further, as shown in arrow in Fig. 3 B, the injection of the counterion includes opposing gate lamination and active area
The ion implanting that hard mask layer 303 is carried out in an inclined manner from both sides, in other words, the injection of the counterion are included relatively
The ion that the ion implanting and relatively described active area hard mask layer that the active area hard mask layer 303 is tilted to the left are tilted to the right
Injection, it can so be noted with being respectively formed counterion in each active area corner (such as two active area corners in left and right in Fig. 3 B)
Enter area 304.
Further, due to counterion be used for compensate such as boron well region Doped ions segregation problem, thus compensate from
It is sub identical with the Doped ions of the well region.Exemplarily, in the present embodiment, counterion is boron ion.It is also, exemplary
Ground, the Implantation Energy of the boron ion is 0~30keV, and implantation dosage is 0.5~2E13/cm2
Finally, as shown in Figure 3 C, with the active area hard mask layer 303 for Semiconductor substrate 300 described in mask etching, with
Formed for forming the groove of isolation structure, and fill the groove and form isolation structure 305.
Exemplarily, the formation of isolation structure 305 can be completed by following step：
First, it is mask with active area hard mask layer 303, institute is etched by suitable dry etching or wet-etching technology
Semiconductor substrate 300 is stated, to form the groove for being used for forming isolation structure.Exemplarily, the wet-etching technology includes hydrogen
The wet-etching technology of the mixed liquors such as fluoric acid, nitric acid, the dry etch process include the dry etching work of halogen family plasma
Skill, such as chlorine (Cl2) or hydrogen bromide (HBr) plasma dry etch process.
Then, isolated material is filled by suitable depositing operation or fill process in the trench, so as to formed every
From structure 305.Exemplarily, in the present embodiment, isolation structure 305 is fleet plough groove isolation structure, due to the depth-to-width ratio of device
Very big, the process of being preferably filled with can be completed using mobility chemical vapor deposition method fill oxide, and such as preceding institute
State, in addition to the high fever of oxide densification calculates handling process, so that isolated material is densified.
So far, the processing step that method according to embodiments of the present invention is implemented is completed, it is to be understood that the present embodiment
Manufacturing method of semiconductor device not only includes above-mentioned steps, before above-mentioned steps, among or may also include other needs afterwards
The step of.
The preparation method for the semiconductor devices that the present embodiment proposes, by active area corner regions, namely isolation structure
Corner regions compensate ion implanting, to compensate the well region Doped ions segregation of such as boron ion, so as to solve thus to cause
Dual hump and electrical leakage problems.As shown in figure 4, it illustrates the height that the preparation method of semiconductor device according to the invention is formed
Press the Id-Vg curves of nmos device and current high pressure NMOS part, wherein curve 1 be without carry out STI corner regions (namely
Active area corner regions) counterion injection high pressure NMOS part Id-Vg curves, it is double to understand that the device is present from curve 1
Hump and electrical leakage problems.Curve 2 is the preparation method according to the semiconductor devices of the present embodiment, carried out STI corner regions (
That is active area corner regions) counterion injection high pressure NMOS part Id-Vg curves, it was found from curve 2, by active
Area's corner regions form counterion injection region, can overcome the dual hump and electrical leakage problems of high pressure NMOS part
Embodiment two
The present invention also provides a kind of semiconductor devices made using the above method, as shown in figure 5, the semiconductor devices bag
Include：Semiconductor substrate 500, separate in the Semiconductor substrate 500 formed with isolation structure 501 and by the isolation structure
Active area, formed with well region in the active area, formed with gate stack in the Semiconductor substrate of the active area,
The corner regions of the active area form counterion injection region 502, wherein, the counterion in the counterion injection region
It is identical with the Doped ions of the well region.
Wherein, Semiconductor substrate 500 can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, Semiconductor substrate 400
Constituent material select monocrystalline silicon.
Isolation structure 501 can be various suitable isolation structures, such as fleet plough groove isolation structure (STI), and it can lead to
Above-mentioned preparation method provided by the invention is crossed to be formed.Exemplarily, the isolated material filled in isolation structure 501 is oxide.
Well region can be formed by ion implanting, and injection ion is according to well region type.Exemplarily, in the present embodiment,
Semiconductor devices is high-pressure N-shaped semiconductor devices, thus well region injection ion is p-type ion, such as boron ion.
Counterion injection region 502 forms the corner regions in active area, and it can be carried by the above embodiment of the present invention
The preparation method of confession is formed.Counterion in counterion injection region 502, for compensating well region Doped ions in isolation structure
Doped ions segregation problem in 501 filling process, such as boron segregation problem, thus the Doped ions of counterion and the well region
It is identical.Exemplarily, in the present embodiment, the counterion is boron ion.The Implantation Energy of the boron ion be 0~
30keV, implantation dosage are 0.5~2E13/cm2。
Gate stack includes tunnel oxide 503 and floating boom 504, and it uses structure and forming method system commonly used in the art
Make.Such as tunnel oxide 503 is illustratively silicon oxide layer, it can be by the way that such as (physical vapor be sunk for thermal oxidation method, PVD
Product), CVD (chemical vapor deposition), ALD (ald) the methods of formed.Floating boom 504 exemplarily uses such as polysilicon
Deng semi-conducting material, and by selecting molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), low pressure chemical gas
A kind of mutually formation in deposition (LPCVD), laser ablation deposition (LAD) and selective epitaxy growth (SEG).
The semiconductor devices of the present embodiment overcomes dual hump and electrical leakage problems.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic installation, including semiconductor devices and with the semiconductor device
The connected electronic building brick of part.Wherein, the semiconductor devices includes：Semiconductor substrate, in the Semiconductor substrate formed with every
The active area separated from structure and by the isolation structure, formed with well region in the active area, in the active area
Formed with gate stack in Semiconductor substrate, counterion injection region is formed in the corner regions of the active area, wherein, it is described
Counterion in counterion injection region is identical with the Doped ions of the well region.
Wherein, Semiconductor substrate can be at least one of following material being previously mentioned：Si、Ge、SiGe、SiC、
SiGeC, InAs, GaAs, InP or other III/V compound semiconductors, in addition to sandwich construction of these semiconductors composition etc.
Or silicon (SSOI) is laminated for silicon-on-insulator (SOI), on insulator, is laminated SiGe (S-SiGeOI), insulation on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc. on body.As an example, in the present embodiment, the structure of Semiconductor substrate
Into material selection monocrystalline silicon.
Further, the counterion is boron ion.
Further, the Implantation Energy of the boron ion is 0~30keV.
Further, the implantation dosage of the boron ion is 0.5~2E13/cm2。
Wherein, the electronic building brick, can be any electronic building bricks such as discrete device, integrated circuit.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, or
Any intermediate products including the semiconductor devices.
Wherein, Fig. 6 shows the example of mobile phone.The outside of mobile phone 600 is provided with the display portion being included in shell 601
602nd, operation button 603, external connection port 604, loudspeaker 605, microphone 606 etc..
The electronic installation of the embodiment of the present invention, by the semiconductor devices included overcomes dual hump and electrical leakage problems,
Thus there is more preferable yield and performance.Therefore the electronic installation equally has the advantages of similar.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (11)
- A kind of 1. preparation method of semiconductor devices, for making flash memory, it is characterised in that comprise the steps：Semiconductor substrate is provided, well region is formed in the Semiconductor substrate, and is formed on the semiconductor substrate graphical Gate stack and active area hard mask layer；Ion implanting is compensated to the corner regions of active area, the counterion is identical with the Doped ions of the well region；Using the active area hard mask layer as Semiconductor substrate described in mask etching, to form the ditch for being used for forming isolation structure Groove；Fill the groove and form isolation structure.
- 2. the preparation method of semiconductor devices according to claim 1, it is characterised in that the counterion is injected to incline Oblique injection mode is carried out.
- 3. the preparation method of semiconductor devices according to claim 2, it is characterised in that the counterion injection is inclined Rake angle and the angle between the normal of the semiconductor substrate surface are 0~15 degree.
- 4. the preparation method of the semiconductor devices according to claim 1-3, it is characterised in that the counterion be boron from Son.
- 5. the preparation method of semiconductor devices according to claim 4, it is characterised in that the Implantation Energy of the boron ion For 0~30keV.
- 6. the preparation method of semiconductor devices according to claim 4, it is characterised in that the implantation dosage of the boron ion For 0.5~2E13/cm2。
- A kind of 7. semiconductor devices, it is characterised in that including：Semiconductor substrate, formed with isolation in the Semiconductor substrate Structure and the active area separated by the isolation structure, formed with well region in the active area, the half of the active area Formed with gate stack on conductor substrate, counterion injection region is formed in the corner regions of the active area, wherein, the benefit It is identical with the Doped ions of the well region to repay the counterion in ion implanted region.
- 8. semiconductor devices according to claim 7, it is characterised in that the counterion is boron ion.
- 9. the preparation method of semiconductor devices according to claim 8, it is characterised in that the Implantation Energy of the boron ion For 0~30keV.
- 10. the preparation method of semiconductor devices according to claim 8, it is characterised in that the injectant of the boron ion Measure as 0.5~2E13/cm2。
- A kind of 11. electronic installation, it is characterised in that including the semiconductor devices as described in claim 7-10 any one and The electronic building brick being connected with the semiconductor devices.
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| CN111987044A (en) * | 2019-05-21 | 2020-11-24 | 无锡华润微电子有限公司 | Method for manufacturing semiconductor device and semiconductor device |
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