CN111987044B - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN111987044B CN111987044B CN201910421884.0A CN201910421884A CN111987044B CN 111987044 B CN111987044 B CN 111987044B CN 201910421884 A CN201910421884 A CN 201910421884A CN 111987044 B CN111987044 B CN 111987044B
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 230000008569 process Effects 0.000 claims description 27
- 238000005229 chemical vapour deposition Methods 0.000 claims description 18
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 5
- 230000000295 complement effect Effects 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- RCJVRSBWZCNNQT-UHFFFAOYSA-N dichloridooxygen Chemical compound ClOCl RCJVRSBWZCNNQT-UHFFFAOYSA-N 0.000 claims description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 claims 2
- RJNIYSQKLSWQAD-UHFFFAOYSA-N dichloro(oxo)silane Chemical compound Cl[Si](Cl)=O RJNIYSQKLSWQAD-UHFFFAOYSA-N 0.000 claims 1
- 230000005855 radiation Effects 0.000 abstract description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 6
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical compound Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000001066 destructive effect Effects 0.000 description 2
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- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
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- 238000001179 sorption measurement Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Element Separation (AREA)
Abstract
The present application relates to a method for manufacturing a semiconductor device and a semiconductor device. The manufacturing method comprises the following steps: obtaining a substrate, wherein an isolation structure for isolating an active region is formed on the substrate; forming a P-type well region on a substrate; forming an active region on the P-type well region; forming a threshold voltage compensation region at a first side at a boundary of the active region and the isolation structure and a second side opposite to the first side; forming a grid electrode; the active region comprises a source region and a drain region which are formed in the P-type well region; the connection line of the first side and the second side is perpendicular to the conducting channel direction of the active region, and the hole concentration of the threshold voltage compensation region is larger than that of the P-type well region. The threshold voltage compensation areas with higher hole concentration are arranged on the two opposite sides of the junction of the active area and the isolation structure, negative charges induced by radiation in the areas can be neutralized, a multi-threshold channel structure is formed, and the problems that after the device is radiated, the circuit leakage setting device is opened by mistake, the circuit is overturned by mistake and the like can be avoided.
Description
Technical Field
The present application relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
For integrated circuits used in ion radiation environments, such as in space, nuclear power plants, environmental detection, etc., radiation can cause verification damage to the integrated circuits, and therefore, process reinforcement of semiconductor devices is required to improve the radiation resistance of the integrated circuits.
Currently, the mainstream integrated circuits all adopt a CMOS (Complementary Metal Oxide Semiconductor ) architecture, and the CMOS mainly has two types, namely NMOS and PMOS; the ionizing damage caused by radiation mainly forms ionizing positive charges, so that the PMOS can only cause instant speed reduction of an integrated circuit, can not generate destructive results, and can be self-recovered along with the extension of the recombination time. And for NMOS, destructive damage may be formed to the integrated circuit.
The chip manufactured by the traditional standard CMOS integrated circuit manufacturing technology does not have radiation resistance, and the main reason is that the instantaneous threshold voltage drift generated by radiation can cause the problems of electric leakage of an integrated circuit, even false opening of a device, false overturn of the circuit and the like.
Disclosure of Invention
In view of the above, it is necessary to provide a new method for manufacturing a semiconductor device and a semiconductor device.
A method of manufacturing a semiconductor device, comprising:
a substrate is obtained on which an isolation structure for isolating the active region is formed.
An active region is formed on the P-type well region.
A threshold voltage compensation region is formed at a first side at a boundary of the active region and the isolation structure and a second side opposite the first side.
A gate is formed over the region between the source and drain regions.
The active region comprises a source region and a drain region which are formed in the P-type well region; the connecting line of the first side and the second side is perpendicular to the conducting channel direction of the active region, and the hole concentration of the threshold voltage compensation region is larger than that of the P-type well region.
In one embodiment, the gate includes a gate oxide layer formed on the substrate and a polysilicon gate formed on the gate oxide layer, and the step of forming the gate includes forming the gate oxide layer using a chemical vapor deposition process.
In one embodiment, the process temperature of chemical vapor deposition is greater than or equal to 450 degrees celsius and less than or equal to 800 degrees celsius.
In one embodiment, the process gas for chemical vapor deposition includes dichloro-oxide and dichlorosilane.
In one embodiment, the step of forming the gate oxide layer is located after the step of forming the threshold voltage compensation region.
In one embodiment, the threshold voltage compensation region is formed by an ion implantation process, and the ion implanted implant material includes at least one of boron, boron difluoride, and indium.
A semiconductor device, comprising:
a substrate comprising an active region comprising a source region and a drain region.
And the P-type well region is positioned on the substrate.
And the isolation structure is used for isolating the active region.
And the threshold voltage compensation area is arranged on a first side and a second side opposite to the first side at the boundary of the active area and the isolation structure, the connecting line of the first side and the second side is perpendicular to the direction of the conducting channel of the active area, and the hole concentration of the threshold voltage compensation area is larger than that of the P-type well area.
And a gate electrode disposed over the region between the source region and the drain region.
In one embodiment, the isolation structure is a shallow trench isolation structure.
In one embodiment, the active region is surrounded in cross-section by the isolation structure to form a closed pattern, the first side and the second side being opposite sides of the closed pattern.
In one embodiment, the semiconductor device is a complementary metal oxide semiconductor device.
According to the semiconductor device and the manufacturing method thereof, the threshold voltage compensation areas with higher hole concentration are arranged on the two opposite sides of the junction of the active area and the isolation structure, negative charges induced by radiation in the areas can be neutralized, a multi-threshold channel structure is formed, and the problems that after the device is radiated, the circuit leakage setting device is opened by mistake, the circuit is turned over by mistake and the like can be avoided.
Drawings
FIG. 1 is a planar layout of an NMOS;
FIG. 2 is a cross-sectional view of the NMOS of FIG. 1;
FIG. 3 is a schematic cross-sectional view taken along line X-X in FIG. 1;
FIG. 4 is a schematic cross-sectional view taken along line Y-Y in FIG. 1;
FIG. 5 is a flow chart of a method of fabricating a semiconductor device in one embodiment;
FIG. 6 is a flow chart of isolation structure formation in one embodiment;
FIG. 7 is a schematic diagram of a threshold voltage compensation region according to an embodiment;
fig. 8 is a plan layout corresponding to the structure shown in fig. 7.
Detailed Description
In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.
Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. In this way, variations from the illustrated shape due to, for example, manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present application should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present application.
The term "semiconductor" used herein is a technical term commonly used by those skilled in the art, for example, for P-type and N-type impurities, p+ type represents P type with heavy doping concentration, P type with medium doping concentration, P-type represents P type with light doping concentration, n+ type represents N type with heavy doping concentration, N type represents N type with medium doping concentration, and N type represents N type with light doping concentration.
The chip manufactured by the traditional standard CMOS integrated circuit manufacturing technology does not have radiation resistance, and the main reason is that the instantaneous threshold voltage drift generated by radiation can cause the problems of electric leakage of an integrated circuit, even false opening of a device, false overturn of the circuit and the like. The planar layout of a conventional NMOS is shown in fig. 1, and the cross-sectional view thereof is shown in fig. 2.
The structure in fig. 1-2 includes P-well region 102, active region 104, drain region 106, source region 108, gate region 110, contact hole 112, polysilicon gate 114, gate oxide 116, substrate 118, and shallow trench isolation (STI, shallow trench isolation) 120, wherein polysilicon gate 114 and gate oxide 116 together comprise gate region 110 of the device.
Under radiation environment, the filler-silicon dioxide medium in the shallow trench isolation can generate electron-hole pairs, and electrons can run off over the barrier between silicon dioxide and silicon under the condition of obtaining certain activation energy, so that positive charges are left in the STI silicon dioxide medium, and the excessive positive charges can cause adjacent silicon surfaces to be inversely shaped to form leakage channels (see arrow direction in fig. 1), so that the lateral and longitudinal STI isolation of the device is disabled. Because the shallow slot isolation oxide layer mainly generates extra positive charges in the radiation environment, the induced negative charges on the silicon surface are caused, so that the threshold voltage of the device in the boundary area of the active area is greatly reduced, a leakage path is formed, isolation is invalid, and the device is misoperation.
The radiation-affected area is primarily the boundary area between the active region and the isolation structure, and fig. 3 is a schematic cross-sectional view taken along line X-X in fig. 1, including a polysilicon gate 302, a gate oxide 304, a shallow trench isolation structure 306, and a radiation-affected area 308, the shallow trench isolation structure 306 creating additional positive charge in the radiation environment. Fig. 4 is a schematic cross-sectional view taken along line Y-Y of fig. 1, including a polysilicon gate 402, a gate oxide 404, a source region 406, a drain region 408, a shallow trench isolation structure 410, and a radiation-affected region 412; since CMOS is a planar device, the operating current flows laterally, so that only the communication (gate region coverage) region has a threshold voltage effect, and thus the leakage current path is limited to the region shown by the arrow direction in fig. 1.
As shown in fig. 5, the present application provides a method for manufacturing a semiconductor device, comprising:
s102, obtaining a substrate, wherein an isolation structure for isolating the active region is formed on the substrate.
S104, forming a P-type well region on the substrate.
S106, forming an active region on the P-type well region.
S108, forming a threshold voltage compensation area.
A threshold voltage compensation region is formed at a first side at a boundary of the active region and the isolation structure and a second side opposite the first side.
And S110, forming a gate above the region between the source region and the drain region.
In one embodiment, the structure after completion of step S110 may be referred to as fig. 7, and fig. 8 is a plan layout corresponding to the structure shown in fig. 7. Wherein the active region includes a source region 705 and a drain region 707 formed in the P-type well region 703. The threshold voltage compensation region 708 is formed on a first side and a second side opposite to the first side at the boundary between the active region and the isolation structure 710, the connection line between the first side and the second side is perpendicular to the conductive channel direction of the active region, the hole concentration of the threshold voltage compensation region 708 is greater than that of the P-type well region 703, and the threshold voltage compensation region 708 is formed on two sides of the normal threshold voltage region 706. The gate is formed over the region between the source region and the drain region. In the embodiment shown in fig. 7 and 8, the gate includes a gate oxide 704 formed on the substrate and a polysilicon gate 702 formed on the gate oxide 704.
According to the manufacturing method of the semiconductor device, the threshold voltage compensation area with higher hole concentration is additionally arranged on the first side and the second side opposite to the first side at the boundary of the active area and the isolation structure, negative charges induced by radiation in the area can be neutralized, a multi-threshold channel structure is formed, and the problems that after the device is subjected to radiation, a circuit leakage setting device is turned on by mistake, the circuit is turned over by mistake and the like can be avoided.
In one embodiment, the threshold voltage compensation region is formed by an ion implantation process. In one embodiment, the ion implanted implant material comprises at least one of boron, boron difluoride, indium, and the like P-type implant materials.
In one embodiment, as shown in fig. 6, the isolation structure is a shallow trench isolation structure, and the forming of the isolation structure includes the following process steps:
s202, forming an isolation oxide layer.
S204, depositing to form a nitride protection layer.
S206, photoetching and etching to form the shallow trench isolation groove.
S208, forming a trench oxide.
S210, removing the nitride protection layer.
In one embodiment, the step of forming the gate electrode in step S110 includes forming the gate oxide layer 704 using a chemical vapor deposition process.
In the corresponding embodiment of the application, the gate oxide manufacturing process is improved, and the chemical vapor deposition process (CVD, chemical Vapor Deposition) is utilized to replace the conventional furnace tube gate oxide manufacturing process in the current device manufacturing process, so that the low-thermal-budget substrate non-consumption gate oxide is obtained.
In some embodiments, step S108 is to add an additional P-type dopant to the first side of the boundary between the active region and the isolation structure and the second side opposite to the first side (i.e., 708 region in fig. 7) to form a threshold voltage compensation region with a higher hole concentration, so that, in the embodiment in which the step of forming the gate oxide layer follows the step of forming the threshold voltage compensation region, the high temperature process (low temperature film forming defect density, poor compactness and failure to serve as a gate oxide dielectric layer) in the gate oxide manufacturing process may affect the distribution of dopant ions, so that the high doped region diffuses into the channel region, thereby reducing the impurity concentration of the high doped region to cause dopant failure, and causing non-uniformity of channel doping in the normal threshold voltage region and unstable threshold voltage. The gate oxide is manufactured by a chemical vapor deposition process, and the negative influence of the gate oxide process on the doping profile can be reduced because the process can use a lower process temperature than a furnace gate oxide manufacturing process (i.e., thermal oxidation).
Chart 1
As shown in the chart 1, the comparison table of the conventional furnace tube gate oxide manufacturing process and the chemical vapor deposition gate oxide manufacturing process shows that compared with the chemical vapor deposition process, the conventional furnace tube process has extremely high thermal budget, poor film forming compactness and many defects, the inherent strong adsorption capability of silicon dioxide to substrate impurities can seriously affect the multi-threshold channel distribution condition, meanwhile, the furnace tube process needs to consume a silicon substrate when manufacturing an oxide layer, the difficulty of forming multi-threshold voltage in the step S108 is increased, and the chemical vapor deposition process overcomes the problems.
The chemical vapor deposition gate oxide manufacturing process has high defect density and poor compactness due to low-temperature film formation, so that the chemical vapor deposition gate oxide cannot be used as a gate oxide dielectric layer in general. In one embodiment, the process temperature of the chemical vapor deposition gate oxide fabrication process is greater than or equal to 450 degrees celsius and less than or equal to 800 degrees celsius, preferably the process temperature is 780 degrees celsius; in the actual process, the process temperature of the chemical vapor deposition gate oxide manufacturing process can be adjusted according to the product requirement, for example, 500 ℃ and 600 ℃. The process gas for chemical vapor deposition comprises dichloro-silicon dioxide and dichlorosilane, wherein the volume flow ratio of the dichloro-silicon dioxide to the dichlorosilane in the deposition step per unit time is more than or equal to 1.8:1 and less than or equal to 3.5:1.
The present application also provides a semiconductor device including:
a substrate comprising an active region comprising a source region and a drain region;
the P-type well region is positioned on the substrate;
the isolation structure is used for isolating the active area;
the threshold voltage compensation area is arranged on a first side and a second side opposite to the first side at the boundary of the active area and the isolation structure, a connecting line of the first side and the second side is perpendicular to the direction of a conductive channel of the active area, and the hole concentration of the threshold voltage compensation area is larger than that of the P-type well area;
and a gate electrode disposed over the region between the source region and the drain region.
According to the semiconductor device and the manufacturing method thereof, the threshold voltage compensation areas with higher hole concentration are arranged on the two opposite sides of the junction of the active area and the isolation structure, negative charges induced by radiation in the areas can be neutralized, a multi-threshold channel structure is formed, and the problems that after the device is radiated, the circuit leakage setting device is opened by mistake, the circuit is turned over by mistake and the like can be avoided.
In one embodiment, the isolation structure is a shallow trench isolation structure.
In one embodiment, the active region is surrounded in cross-section by the isolation structure to form a closed pattern, the first and second sides being opposite sides of the closed pattern.
In one embodiment, the semiconductor device is a complementary metal oxide semiconductor device.
In one embodiment, the structure of the semiconductor device of the present application may be seen in fig. 7 and 8.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
obtaining a substrate, wherein an isolation structure for isolating an active region is formed on the substrate;
forming a P-type well region on the substrate;
forming an active region on the P-type well region;
forming a threshold voltage compensation region at a first side and a second side opposite the first side of the active region at a boundary with the isolation structure;
forming a gate over the region between the source region and the drain region, the gate including a gate oxide layer formed on the substrate, the step of forming the gate oxide layer being located after the step of forming the threshold voltage compensation region;
wherein the active region includes the source and drain regions formed in the P-type well region; and the connecting line of the first side and the second side is perpendicular to the direction of a conductive channel of the active region, and the hole concentration of the threshold voltage compensation region is larger than that of the P-type well region.
2. The method of claim 1 wherein the gate further comprises a polysilicon gate formed over the gate oxide, the step of forming the gate comprising forming the gate oxide using a chemical vapor deposition process.
3. The method of claim 2, wherein the process temperature of the chemical vapor deposition is greater than or equal to 450 degrees celsius and less than or equal to 800 degrees celsius.
4. The method of claim 2, wherein the process gas for chemical vapor deposition comprises dichloro-oxide and dichlorosilane.
5. The method of claim 4, wherein the volume flow ratio of dichloro-silicon monoxide to dichlorosilane per unit time of the deposition step is 1.8:1 or more and 3.5:1 or less.
6. The method of claim 1, wherein the threshold voltage compensation region is formed by an ion implantation process, the ion implanted implant material comprising at least one of boron, boron difluoride, indium.
7. A semiconductor device, comprising:
a substrate comprising an active region comprising a source region and a drain region;
the P-type well region is positioned on the substrate;
the isolation structure is used for isolating the active area;
the threshold voltage compensation area is arranged on a first side and a second side opposite to the first side at the boundary of the active area and the isolation structure, a connecting line of the first side and the second side is perpendicular to the direction of a conductive channel of the active area, and the hole concentration of the threshold voltage compensation area is larger than that of the P-type well area;
a gate electrode disposed over a region between the source and drain regions; the gate electrode includes a gate oxide layer formed on the substrate, and the step of forming the gate oxide layer is located after the step of forming the threshold voltage compensation region.
8. The device of claim 7, wherein the isolation structure is a shallow trench isolation structure.
9. The device of claim 7, wherein the active region is surrounded in cross-section by the isolation structure to form a closed pattern, the first and second sides being opposite sides of the closed pattern.
10. The device of claim 7, wherein the semiconductor device is a complementary metal oxide semiconductor device.
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