CN105206577A - Semiconductor device and manufacturing method thereof, and electronic apparatus - Google Patents
Semiconductor device and manufacturing method thereof, and electronic apparatus Download PDFInfo
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- CN105206577A CN105206577A CN201410256238.0A CN201410256238A CN105206577A CN 105206577 A CN105206577 A CN 105206577A CN 201410256238 A CN201410256238 A CN 201410256238A CN 105206577 A CN105206577 A CN 105206577A
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, and an electronic apparatus. The manufacturing method includes: a semiconductor substrate is provided, front devices of a plurality of memory cells are formed on the semiconductor substrate, each memory cell comprises at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, wherein the pull-up transistors, the pull-down transistors, and the pass-gate transistors all comprise grid electrodes and grid electrode sidewalls, and asymmetric pocket ion implantation is performed for the two pass-gate transistors of each memory cell. According to the manufacturing method for the semiconductor device, the pass-gate transistors in asymmetric pocket areas with different doping concentrations are formed, the conflict between the writability and the reading stability of an SRAM unit can be effectively balanced, the writability and the reading stability of the SRAM unit are improved, and the reliability of the SRAM unit is improved.
Description
Technical field
The present invention relates to technical field of semiconductor memory, in particular to a kind of semiconductor device and preparation method thereof and electronic installation.
Background technology
Along with the development of digital integrated circuit, memory integrated on sheet has become part important in digital system.SRAM (StaticRandomAccessMemory, static RAM) becomes important component part indispensable in on-chip memory with the advantage of its low-power consumption, high speed.As long as SRAM can preserve data, without the need to constantly refreshing it for its power supply.
Basis SRAM memory cell generally comprises six transistors: 2 PU that pull up transistor (Pull-uptransistor), 2 pull-down transistor PD (Pull-downtransistor), 2 transmission transistor PG (Pass-gatetransistor).In the design process of SRAM memory cell, usually enough large β ratio (Ipd/Ipg current ratio) will be ensured, to obtain sufficiently high static noise margin (static-noisemargin, SNM), require that γ ratio (Ipg/Ipu current ratio) is enough large, to obtain good writability (writability) simultaneously.Therefore, to the different requirements of transmission transistor performance, cause the writability of sram cell and conflicting between read stability.And this conflict is the bottleneck of traditional 6TSRAM memory cell design all the time.
Therefore, be necessary to propose a kind of new technical scheme, to improve writability and the read stability of SRAM memory cell.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising:
Semiconductor substrate is provided, be formed with the front-end devices of multiple memory cell on the semiconductor substrate, described memory cell comprise at least two pull up transistor, at least two pull-down transistors and at least two transmission gate transistors, wherein, pull up transistor described in, described pull-down transistor and described transmission gate transistor include grid and gate lateral wall;
Asymmetric pocket ion implantation is carried out to the described transmission gate transistor of two in each memory cell.
Further, described asymmetric pocket ion implantation is by small angle inclination ion implantation and the incompatible realization of wide-angle tilt ion implanted junction.
Further, when carrying out described wide-angle tilt ion implantation, by utilizing the capture-effect of the neighboring gates of two described transmission gate transistors, only the described semiconductor substrate region outside the neighboring gates of two described transmission gate transistors is injected, the described semiconductor substrate region in the middle of described neighboring gates is not injected.
Further, when carrying out described small angle inclination ion implantation, can realize injecting the pocket of the described semiconductor substrate region outside two described transmission gate transistor grids and in the middle of adjacent two described transmission gate transistor grids.
Further, define in the source region near described transmission gate transistor and there is highly doped pocket region, define near drain region and there is low-doped pocket region.
Further, described asymmetric pocket ion implantation adopts N-type impurity as injection source.
Further, described N-type impurity is P or As.
Further, before the step of carrying out described asymmetric pocket ion implantation, also comprise the step of the mask pulled up transistor described in two that are formed and cover in each described memory cell.
Further, described semiconductor device is static RAM.
The present invention also provides a kind of semiconductor device, described semiconductor device comprises multiple memory cell, described memory cell comprise at least two pull up transistor, at least two pull-down transistors and at least two transmission gate transistors, wherein, in each described memory cell, described two transmission gate transistors have the asymmetric pocket region of different levels of doping.
Further, the pocket region between adjacent two described transmission gate transistor grids is highly doped pocket region, and the pocket region be positioned at outside two described transmission gate transistors is highly doped pocket region.
Further, described semiconductor device is static RAM.
The present invention also provides a kind of electronic installation in addition, comprises above-mentioned semiconductor device.
In sum, according to manufacture method of the present invention, inject by implementing asymmetric pocket to transmission gate transistor, transmission gate transistor is made to have low saturation current Idsat when carrying out read operation, there is high saturation current Idsat simultaneously when carrying out write operation, and then improve writability and the read stability of SRAM memory cell.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A is the read operation circuit diagram of existing a kind of 6TSRAM memory cell;
Figure 1B is the write operation circuit diagram of existing a kind of 6TSRAM memory cell;
Fig. 2 is that prior art carries out the vertical view of pocket injection to the pull-down transistor of SRAM memory cell and transmission gate transistor;
Fig. 3 A is the vertical view of the multiple memory cell according to the embodiment of the present invention one formation;
Fig. 3 B is the generalized section according to the transmission gate transistor of two in elliptical region in Fig. 3 A;
Fig. 4 is the flow chart according to the method in the embodiment of the present invention one successively implementation step;
Fig. 5 A is the circuit diagram of the memory cell formed according to the method for the embodiment of the present invention one;
Fig. 5 B is the schematic diagram of the transmission gate transistor formed according to the method for the embodiment of the present invention one.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
Should be understood that, the present invention can implement in different forms, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiments will expose thoroughly with complete, and scope of the present invention is fully passed to those skilled in the art.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " one ", " one " and " described/to be somebody's turn to do " of singulative is also intended to comprise plural form, unless context is known point out other mode.It is also to be understood that term " composition " and/or " comprising ", when using in this specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other feature, integer, step, operation, element, the existence of parts and/or group or interpolation.When this uses, term "and/or" comprises any of relevant Listed Items and all combinations.
In order to thoroughly understand the present invention, by following description, detailed structure is proposed, to explain technical scheme of the present invention.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Be the read operation circuit diagram of existing a kind of 6TSRAM memory cell as shown in Figure 1A, when read operation, bit line BT and paratope line BC is charged to high level VDD, then disconnects.At this moment access control signal WL is elevated to VDD by selection, opens transmission transistor T2 and T3.Without loss of generality, if the storage of B point is 0, then paratope line BC discharges into 0 by T3 and N1.When read operation, high β ratio and slow PG can make Node B be in lower level, are conducive to preventing the too high unit that causes of level from overturning.
Be the write operation circuit diagram of existing a kind of 6TSRAM memory cell as shown in Figure 1B, when write operation, what suppose that B node stores is 0, and bit line BT is connected with high level VDD, and paratope line BC ground connection, Node B is discharged by P1 and T3.During read operation, high γ ratio and fast PG can make Node B be pulled down to 0 fast, realize the write of data.
Therefore, to the different requirements of transmission transistor performance, cause the writability of sram cell and conflicting between read stability.
With reference to figure 2, for prior art to carry out the vertical view of pocket injection to the pull-down transistor PD of SRAM memory cell and transmission gate transistor PG, in figure, arrow represents the orientation angle that pocket injects.Pull-down transistor PD shares the low-doped pocket of identical N-type and injects with transmission gate transistor PG, carry out 4 45 ° of tilt-angle ion and inject, and therefore the pocket of pull-down transistor PD and transmission gate transistor PG injects is identical.
Existence in view of the above problems, the present invention proposes a kind of new manufacture method, to balance the writability of sram cell and conflicting between read stability.
Embodiment one
Below, be described in detail with reference to the manufacture method of Fig. 3 A-3B, Fig. 4 and Fig. 5 A-5B to the semiconductor device of the embodiment of the present invention.
With reference to figure 4, perform step 401, Semiconductor substrate is provided, be formed with the front-end devices of multiple memory cell on the semiconductor substrate, described memory cell comprises that at least two of being formed in described Semiconductor substrate pull up transistor, at least two pull-down transistors and at least two transmission gate transistors, wherein, pull up transistor described in, described pull-down transistor and described transmission gate transistor include grid and gate lateral wall.
Particularly, with reference to Fig. 3 A, be the vertical view of multiple memory cell formed according to the embodiment of the present invention, for one of them memory cell.
There is provided semi-conductive substrate, described Semiconductor substrate can at least one in following mentioned material: stacked SiGe (S-SiGeOI) and germanium on insulator SiClx (SiGeOI) etc. on stacked silicon (SSOI), insulator on silicon, silicon-on-insulator (SOI), insulator.
In described Semiconductor substrate, define various active area, form fleet plough groove isolation structure with described active area surrounding; Particularly, first define active area, and then active area surrounding etches shallow trench, last with fill insulant in described shallow trench to form described fleet plough groove isolation structure.
N-type trap injection region and P type trap injection region is formed in described Semiconductor substrate.In described N-type trap injection region, make at least two PU that pull up transistor, in P type trap injection region, make at least two pull-down transistor PD and at least two transmission gate transistor PG.
Wherein, above-mentionedly to pull up transistor, pull-down transistor and transmission gate transistor include the parts such as grid structure and gate lateral wall (not indicating in figure).In an example, described grid structure comprises the gate dielectric be positioned in Semiconductor substrate, is positioned at the polysilicon gate on gate dielectric.
Perform step 402, to the pocket ion implantation that the pull-down transistor PD of two in each memory cell carries out along the x-axis direction.
Form the mask of two PU that pull up transistor covered in each described memory cell, then, to the pocket ion implantation that the pull-down transistor PD of two in each memory cell carries out along the x-axis direction, pouch-type doped region (not shown) is formed with the below at grid structure edge, this pocket ion implantation adopts N-type impurity as injection source, such as, adopt P or As injection source.Adopt inclination injection mode along the x-axis direction, therefore only can form pouch-type doped region in the below at pull-down transistor PD grid structure edge.
Perform step 403, asymmetric pocket ion implantation is carried out to the transmission gate transistor of two in each memory cell.
As shown in Figure 3A, to the asymmetric pocket ion implantation that the transmission gate transistor PG of two in each memory cell carries out along the y-axis direction, because ion implantation direction is along the y-axis direction, therefore only can inject transmission gate transistor PG, can not have an impact to pull-down transistor PD.
In conjunction with wide-angle and small angle inclination ion implantation, realize asymmetric pocket ion implantation.This pocket ion implantation adopts N-type impurity as injection source, such as, adopt P or As injection source.The generalized section of two transmission gate transistors of elliptical region in Fig. 3 B corresponding diagram 3A, the direction of arrow in Fig. 3 B represents the direction of ion implantation when carrying out pocket ion.Wherein, the first inclination angle a and the second inclination angle b refers to ion implantation direction and the angle perpendicular to the direction of the upper surface of front-end devices.In the present embodiment, the first inclination angle a selects large inclination angle, can be greater than 45 degree, such as, be 70 degree.By make use of the capture-effect of the neighboring gates 301 of two transmission gate transistors, when carrying out the wide-angle tilt ion implantation of the first inclination angle a, only the described semiconductor substrate region outside the neighboring gates 301 of two transmission gate transistors can be injected, can not the described semiconductor substrate region in the middle of neighboring gates 301 be injected.
In the present embodiment, the second inclination angle b selects little inclination angle, can be less than 45 degree, such as, can be 0 degree.When carrying out the small angle inclination ion implantation of the second inclination angle b, can realize to outside two described transmission gate transistor grids 301 and adjacent two described transmission gate transistor grids 301 in the middle of the pocket of described semiconductor substrate region inject.
To inject due to wide-angle pocket and the injection of low-angle pocket is all injected the semiconductor substrate region outside the neighboring gates of two transmission gate transistor PG, therefore define highly doped pocket region in semiconductor substrate region outside the neighboring gates of transmission transistor PG.And a small angle inclination ion implantation has only been carried out to the region in the Semiconductor substrate of two neighboring gates centres, therefore define low-doped pocket region in the semiconductor substrate region of adjacent two grids centre.As shown in Figure 5A, for the circuit diagram of a memory cell formed according to the method for the embodiment of the present invention, Fig. 5 B is the schematic diagram with the transmission gate transistor of asymmetric pocket region formed according to the method for the embodiment of the present invention, as seen from the figure, define in the source region near transmission gate transistor and there is highly doped pocket region, define near drain region and there is low-doped pocket region.
Also be included in the step that grid, drain node or source node form contact hole afterwards, multiple contact hole is designed to be square or rectangle in a top view, and for electrical connection, therefore not to repeat here.
The manufacture method of the semiconductor device of the embodiment of the present invention, may be used for making SRAM memory and other similar semiconductor device.
The manufacture method of this semiconductor device, defines the transmission gate transistor of the asymmetric pocket region with different levels of doping, therefore can obtain different source-leakages/drain-source saturation current (Idsat) and threshold voltage (Vt).Threshold voltage (Vt) low when the threshold voltage (Vt) that when can realize read operation, transmission gate transistor is high simultaneously and write operation, and make transmission gate transistor have low saturation current (Idsat) when carrying out read operation, there is high saturation current (Idsat) when carrying out write operation simultaneously.
In sum, according to manufacture method of the present invention, form the transmission gate transistor with the asymmetric pocket region of different levels of doping, can the writability of active balance sram cell and conflicting between read stability, and then improve writability and the read stability of sram cell, promote the reliability of sram cell.
Embodiment two
The embodiment of the present invention two provides a kind of semiconductor device, and this semiconductor device can adopt the manufacture method of the semiconductor device in above-described embodiment one to obtain.
The semiconductor device of the present embodiment comprises multiple memory cell, described memory cell comprise at least two pull up transistor, at least two pull-down transistors and at least two transmission gate transistors, wherein, in each described memory cell, described two transmission gate transistors have the asymmetric pocket region of different levels of doping.
Wherein, exemplarily, the pocket region between described adjacent two transmission gate transistor grids is highly doped pocket region, and the pocket region be positioned at outside described two transmission gate transistors is highly doped pocket region.
Wherein, described semiconductor device is static RAM.
The semiconductor device of the embodiment of the present invention, owing to having the transmission gate transistor of the asymmetric pocket region of different levels of doping, therefore the writability of active balance sram cell and conflicting between read stability, and then improve writability and the read stability of sram cell, promote the reliability of sram cell.
Embodiment three
The embodiment of the present invention provides a kind of electronic installation, the semiconductor device that the manufacture method it using the semiconductor device according to embodiment one manufactures, or employs the semiconductor device described in embodiment two.Because the semiconductor device used has different device ratios, therefore this electronic installation has better performance.
This electronic installation can be mobile phone, panel computer, notebook computer, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording pen, any electronic product such as MP3, MP4, PSP or equipment.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (13)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, be formed with the front-end devices of multiple memory cell on the semiconductor substrate, described memory cell comprise at least two pull up transistor, at least two pull-down transistors and at least two transmission gate transistors, wherein, pull up transistor described in, described pull-down transistor and described transmission gate transistor include grid and gate lateral wall;
Asymmetric pocket ion implantation is carried out to the described transmission gate transistor of two in each memory cell.
2. method according to claim 1, is characterized in that, described asymmetric pocket ion implantation is by small angle inclination ion implantation and the incompatible realization of wide-angle tilt ion implanted junction.
3. method according to claim 2, it is characterized in that, when carrying out described wide-angle tilt ion implantation, by utilizing the capture-effect of the neighboring gates of two described transmission gate transistors, only the described semiconductor substrate region outside the neighboring gates of two described transmission gate transistors is injected, the described semiconductor substrate region in the middle of described neighboring gates is not injected.
4. method according to claim 2, it is characterized in that, when carrying out described small angle inclination ion implantation, can realize injecting the pocket of the described semiconductor substrate region outside two described transmission gate transistor grids and in the middle of adjacent two described transmission gate transistor grids.
5. method according to claim 1, is characterized in that, defines have highly doped pocket region in the source region near described transmission gate transistor, defines have low-doped pocket region near drain region.
6. method according to claim 1, is characterized in that, described asymmetric pocket ion implantation adopts N-type impurity as injection source.
7. method according to claim 6, is characterized in that, described N-type impurity is P or As.
8. method according to claim 1, is characterized in that, before the step of carrying out described asymmetric pocket ion implantation, also comprises the step of the mask pulled up transistor described in two that are formed and cover in each described memory cell.
9. method according to claim 1, is characterized in that, described semiconductor device is static RAM.
10. a semiconductor device, it is characterized in that, described semiconductor device comprises multiple memory cell, described memory cell comprise at least two pull up transistor, at least two pull-down transistors and at least two transmission gate transistors, wherein, in each described memory cell, described two transmission gate transistors have the asymmetric pocket region of different levels of doping.
11. devices according to claim 10, is characterized in that, the pocket region between adjacent two described transmission gate transistor grids is highly doped pocket region, and the pocket region be positioned at outside two described transmission gate transistors is highly doped pocket region.
12. devices according to claim 10, is characterized in that, described semiconductor device is static RAM.
13. 1 kinds of electronic installations, is characterized in that, comprise semiconductor device according to claim 10.
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| CN201410256238.0A CN105206577B (en) | 2014-06-10 | 2014-06-10 | A kind of semiconductor devices and preparation method thereof and electronic device |
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| CN112447729A (en) * | 2019-09-04 | 2021-03-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN113140515A (en) * | 2021-03-29 | 2021-07-20 | 上海华力集成电路制造有限公司 | Method for adjusting Beta ratio of SRAM |
| CN113140244A (en) * | 2020-01-17 | 2021-07-20 | 台湾积体电路制造股份有限公司 | Static random access memory device and forming method thereof |
| CN116631472A (en) * | 2023-07-18 | 2023-08-22 | 全芯智造技术有限公司 | Semiconductor device, method for manufacturing the same, and method for optimizing parameters |
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