CN109461732B - Static random access memory unit and manufacturing method thereof - Google Patents

Static random access memory unit and manufacturing method thereof Download PDF

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Publication number
CN109461732B
CN109461732B CN201811212888.XA CN201811212888A CN109461732B CN 109461732 B CN109461732 B CN 109461732B CN 201811212888 A CN201811212888 A CN 201811212888A CN 109461732 B CN109461732 B CN 109461732B
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tube
nmos
pull
pmos
heavily doped
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CN109461732A (en
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陈静
王硕
王本艳
葛浩
柴展
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention provides a static randomMemory cell and method of making the same, where the sources of both the pull-up and pull-down transistors are embedded with tunneling diode structures, can be fabricated without increasing device area (final effective cell area can be less than 7.5 μm) 2 ) The floating body effect, the drain power consumption caused by the parasitic triode effect and the threshold voltage drift of the transistor in the PDSOI device are effectively inhibited, and the noise immunity of the cell is improved. The manufacturing method of the SOI six-transistor SRAM unit also has the advantages of simple manufacturing process, complete compatibility with the existing logic process and the like, and the inside of the unit adopts a central symmetry structure and a sharing structure among the units, so that the unit is convenient to form a storage array, and the period for designing the SRAM chip is shortened.

Description

Static random access memory unit and manufacturing method thereof
Technical Field
The present invention relates to the field of memory design and fabrication, and in particular, to a static random access memory cell and a fabrication method thereof.
Background
With the development of semiconductor processes, the size of transistors has been advanced into deep submicron, and the scale of memory modules is continually expanding in response to performance requirements. In the severe environment in which aerospace electronics operate, memory cells are saturated with radiation from various high-energy particles, and memory cells are more sensitive to high-particle radiation. Conventional memory cells are generally difficult to meet radiation-resistant requirements, and designers often improve upon conventional cells to increase the radiation resistance of the cells.
The single event effect and the total dose effect are the most common and important two of the radiation effects.
When high-energy particles are incident into a sensitive area (for a bulk silicon device, the sensitive area refers to a reverse bias PN junction at the drain end of the sensitive area, and for a silicon-on-insulator device, the body area in a device closing state), the energy of the particles is absorbed by a silicon material, electrons in a valence band can obtain energy to be transited to a conduction band according to a solid energy band theory, and corresponding holes are transited to a position with higher energy downwards in the valence band, so that the electrons and the holes are free moving carriers; the current is formed by directional movement of freely moving carriers due to the existence of an electric field applied by surrounding voltage, but the service life of the carriers is limited, so that the finally formed current is transient current; the transient current causes a voltage drop in the loop within the cell, causing a change in the stored data, an effect of a logic error of the memory cell due to a single particle is called a single particle effect.
The single particle reinforcement method is many, most thinking is to prolong the time of a feedback loop and reduce the influence caused by single particles; if a resistor or a capacitor is added in the loop, an RC loop formed by adding the resistor and the capacitor is also added.
Although passive devices such as a resistor or a capacitor are introduced into the memory cell, the single event resistance effect can be improved, the resistance value of the resistor and the capacitance value of the capacitor are larger in magnitude order, and an additional process is required to manufacture the resistor and the capacitor; moreover, even if these passive devices were fabricated, their area would be intolerable to memory cells, which is a fatal effect for SRAM cells.
Compared with the common bulk silicon process, the SOI technology has small parasitic capacitance, low power consumption, high speed and natural Single-Event-latch-up (SEL) resistance, so that the SOI technology is very suitable for occasions such as System-on-Chips (SoC), low power consumption, radiation resistance and the like; in addition, static random access memory (StaticRandomAccessMemory, SRAM) is widely used in consumer electronics, automotive electronics, processor level one cache and level two cache; therefore, the application of SOI technology to SRAM designs has certain advantages.
The SOI is further classified into a Full-Depleted (FD) SOI and a partial-Depleted (PD) SOI according to the degree of depletion of the MOS body region. For the partially depleted SOI technology, the body region of the MOS transistor is electrically separated from the source region, so that the body region is suspended; in normal operation, the drain electrode potential is higher, electrons of the inversion channel are accelerated by an electric field when moving from the source electrode to the drain electrode, and when moving to a junction close to the drain electrode, the electrons acquire extra energy because of the strongest electric field and collide with atoms on a crystal lattice to form electron-hole pairs; the electron speed is high, and the electron is accelerated to the drain electrode in a short time; however, the hole speed is relatively slow, and the hole moving to the body region is easily recombined by electrons provided by the source along the electric field direction to the low potential regions such as the body region and the source region, and the hole slowly accumulates in the body region due to the floating of the electric potential of the hole, so that the threshold voltage of the MOS tube is directly influenced, and the performance of the MOS tube is changed, namely the floating body effect. In addition, the PD SOI MOS transistor also has parasitic triode effect, namely the source electrode, the body region and the drain electrode of the MOS transistor are N, P and N respectively, which are similar to the emitter electrode, the base electrode and the collector electrode in the triode, namely the MOS transistor parasitizes a natural NPN triode; this base is floating. Generally, when the base electrode has no positive charge, the potential of the base electrode is the same as that of the emitter electrode, so that a triode of the base electrode cannot be conducted; if the floating body effect occurs, when the positive charge of the base electrode is accumulated to a certain extent, the triode is conducted when the potential of the base electrode and the emitter electrode reaches a certain extent, and a phenomenon of large current is generated at the drain electrode. The floating body effect and parasitic triode effect can cause performance variations of the PD SOI SRAM cell, such as increased leakage and reduced noise immunity.
The static random access memory unit commonly used at present mainly adopts six transistor types, and consists of two pull-up P-type transistors, two pull-down N-type transistors and two transmission gate N-type transistors, wherein word lines control the switches of the two transmission gate N-type transistors, and memory data is written in or read out through bit lines, and the six transistors are all common MOS transistors.
Generally, in PD SOI MOS transistors, due to floating body effect and parasitic triode effect, a designer often pulls out the MOS transistor body region (NMOS body region is connected to low potential, i.e. short-circuited with source region potential; PMOS body region is connected to high level), and the potential is kept fixed so as to inhibit both effects; the common body contact is a T-type grid MOS tube and an H-type grid MOS tube, but the area of the common body contact is much higher than that of a non-body contact MOS tube with the same size. If the T-type MOS transistor is directly applied to the SRAM cell, the cell area is increased by about 1 time, and even more (H-type gate is applied).
Therefore, how to provide a static random access memory cell and a manufacturing method thereof can prolong the feedback time of the key storage node of the SRAM cell to external high-energy disturbance, and can effectively inhibit the floating body effect and parasitic triode effect of the MOS transistor on the premise of reducing the area of a chip as much as possible, thereby enhancing the stability of the six-transistor static random access memory cell and reducing the leakage power consumption, and becoming an important technical problem to be solved urgently by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention is directed to providing a static random access memory cell and a method for manufacturing the same, which are used for prolonging the feedback time of an SRAM cell to external disturbance when a key storage node of the SRAM cell is in a hold state, improving the stability of the memory cell, and solving the problems of large occupied area, poor stability, high leakage power consumption and weak noise immunity of the SRAM cell in the prior art.
To achieve the above and other related objects, the present invention provides a static random access memory cell, including at least:
the first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube, the second NMOS pull-down tube, the first NMOS access tube, the second NMOS access tube, the third NMOS access tube and the fourth NMOS access tube;
the grid electrode of the first PMOS pull-up tube is connected with the drain electrode of the second PMOS pull-up tube, the drain electrode of the first PMOS pull-up tube is connected with the grid electrode of the second PMOS pull-up tube, and the source electrode of the first PMOS pull-up tube and the source electrode of the second PMOS pull-up tube are both connected with high level;
the grid electrode of the first NMOS pull-down tube is connected with the source electrode of the second NMOS access tube, the drain electrode of the first NMOS pull-down tube is connected with the drain electrode of the first PMOS pull-up tube and the source electrode of the first NMOS access tube, the grid electrode of the second NMOS pull-down tube is connected with the source electrode of the third NMOS access tube, the drain electrode of the second NMOS pull-down tube is connected with the drain electrode of the second PMOS pull-up tube and the source electrode of the fourth NMOS access tube, and the source electrodes of the first NMOS pull-down tube and the second NMOS pull-down tube are connected with low level;
The source electrode of the first NMOS access tube is connected with the drain electrode of the third NMOS access tube, the drain electrode of the first NMOS access tube is connected with the bit line of the memory cell, the source electrode of the first NMOS access tube is connected with the drain electrode of the first PMOS pull-up tube and the drain electrode of the first NMOS pull-down tube to form a first memory node, and the grid electrodes of the first NMOS access tube and the second NMOS access tube are controlled by word lines;
the source electrode of the fourth NMOS access tube is connected with the drain electrode of the second NMOS access tube, the drain electrode of the fourth NMOS access tube is connected with the inverted bit line of the memory cell, the source electrode of the fourth NMOS access tube is connected with the drain electrode of the second PMOS pull-up tube and the drain electrode of the second NMOS pull-down tube to form a second memory node, and the grid electrode of the third NMOS access tube and the grid electrode of the fourth NMOS access tube are controlled by word lines;
the tunneling diodes are connected between the source electrodes and the body regions of the first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube and the second NMOS pull-down tube; for a PMOS transistor, the source electrode of the PMOS transistor is connected with the anode of the tunneling diode, and the body region of the PMOS transistor is connected with the cathode of the tunneling diode; for an NMOS transistor, its source is connected to the cathode of the tunnel diode and its body is connected to the anode of the tunnel diode.
Optionally, the tunneling diode is formed by connecting a P-type heavily doped anode and an N-type heavily doped cathode.
More optionally, for the PMOS pull-up tube, a P-type heavily doped anode of the tunneling diode is shared with a P-type heavily doped source region of the PMOS pull-up tube, and an N-type heavily doped cathode of the tunneling diode is located at the bottom of the P-type heavily doped source region and is in contact with a body region of the PMOS pull-up tube; for the NMOS pull-down tube, an N-type heavily doped cathode of the tunneling diode is shared with an N-type heavily doped source region of the NMOS pull-down tube, and a P-type heavily doped anode of the tunneling diode is positioned at the bottom of the N-type heavily doped source region and is in contact with a body region of the NMOS pull-down tube.
More optionally, a metal silicide is formed on the P-type heavily doped source region and the N-type heavily doped body contact region.
More optionally, the metal silicide is selected from any one of cobalt silicide and titanium silicide.
More optionally, the static random access memory unit adopts an SOI substrate sequentially comprising a back substrate, a buried insulating layer and a top silicon from bottom to top, and active regions where the transistors are located are isolated by a shallow trench isolation structure penetrating through the top silicon from top to bottom.
More optionally, the first NMOS access tube, the second NMOS access tube, the third NMOS access tube, and the fourth NMOS access tube are one or a combination of several of a common gate NMOS tube, a T-gate NMOS tube, and an H-gate NMOS tube.
To achieve the above and other related objects, the present invention also provides a method for manufacturing a static random access memory cell, where the method at least includes:
1) Providing an SOI substrate which sequentially comprises a back substrate, an insulating buried layer and top silicon from bottom to top, manufacturing a shallow trench isolation structure in the top silicon, and defining an active region;
2) Manufacturing an N well, a first P well and a second P well in the top silicon according to the position of the active region, wherein the N well is positioned between the first P well and the second P well;
3) Manufacturing a first PMOS pull-up tube and a second PMOS pull-up tube in the N well; manufacturing a first NMOS pull-down tube, a first NMOS access tube and a second NMOS access tube in the first P well; manufacturing a second NMOS pull-down tube, a third NMOS access tube and a fourth NMOS access tube in the second P well; the tunneling diodes are connected between the source electrodes and the body regions of the first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube and the second NMOS pull-down tube; for the PMOS pull-up tube, the source electrode of the PMOS pull-up tube is connected with the anode of the tunneling diode, and the body region of the PMOS pull-up tube is connected with the cathode of the tunneling diode; for the NMOS pull-down tube, the source electrode of the NMOS pull-down tube is connected with the cathode of the tunneling diode, and the body region of the NMOS pull-down tube is connected with the anode of the tunneling diode;
4) And manufacturing metal through holes and corresponding metal connecting wires to finish the manufacturing of the static random access memory unit.
More optionally, the tunneling diode is formed by connecting a P-type heavily doped anode and an N-type heavily doped cathode.
More optionally, for the PMOS pull-up tube, a P-type heavily doped anode of the tunneling diode is shared with a P-type heavily doped source region of the PMOS pull-up tube, and an N-type heavily doped cathode of the tunneling diode is located at the bottom of the P-type heavily doped source region and is in contact with a body region of the PMOS transistor; for the NMOS pull-down tube, an N-type heavily doped cathode of the tunneling diode is shared with an N-type heavily doped source region of the NMOS pull-down tube, and a P-type heavily doped anode of the tunneling diode is positioned at the bottom of the N-type heavily doped source region and is in contact with a body region of the NMOS pull-down tube.
Optionally, the step 3) includes the steps of:
31 Forming a grid electrode of the first PMOS pull-up tube and a grid electrode of the second PMOS pull-up tube at the preset position of the N well, forming a grid electrode of the first NMOS pull-down tube at the preset position of the first P well, and forming a grid electrode of the second NMOS pull-down tube at the preset position of the second P well;
32 N-type lightly doping is carried out at preset positions of the first P well and the second P well to form shallow N-type areas of the first NMOS pull-down tube, the second NMOS pull-down tube, the first NMOS access tube, the second NMOS access tube, the third NMOS access tube and the fourth NMOS access tube; p-type light doping is carried out at the preset position of the N well, so that shallow P-type areas of the first PMOS pull-up tube and the second PMOS pull-up tube are formed;
33 Forming a side wall isolation structure around the grid electrode of the first PMOS pull-up tube, the grid electrode of the second PMOS pull-up tube, the grid electrode of the first NMOS pull-down tube and the grid electrode of the second NMOS pull-down tube;
34 N-type heavy doping is carried out in the region above the P-type heavy doping anode in the first P well and the second P well, so that an N-type heavy doping source region of the first NMOS pull-down tube and the second NMOS pull-down tube is formed; and P-type heavy doping is carried out in the region above the N-type heavy doping cathode in the N well, so that P-type heavy doping source regions of the first PMOS pull-up tube and the second PMOS pull-up tube are formed.
Optionally, in the step 34), a mask plate with openings at preset positions of the first and second P-wells is used, and ion implantation is vertically performed through the mask plate to complete the P-type heavy doping or the N-type heavy doping.
More optionally, the concentration of the ion implantation is in the range of 1E15-9E15/cm 2 。
More optionally, in the step 34) or the step 35), the method further includes a step of performing N-type heavy doping at predetermined positions of the first P-well and the second P-well to form drains of the first NMOS pull-down tube, the second NMOS pull-down tube, the first NMOS access tube, the second NMOS access tube, the third NMOS access tube, and the fourth NMOS access tube, and performing P-type heavy doping at predetermined positions of the N-well to form drains of the first PMOS pull-down tube and the second PMOS pull-down tube.
Optionally, in the step 3), a step of forming a metal silicide on the P-type heavily doped source region and the N-type heavily doped source region is further included.
Optionally, forming a metal layer on the P-type heavily doped source region and the N-type heavily doped source region, and performing heat treatment to enable the metal layer to react with Si material below the metal layer to generate the metal silicide.
More optionally, the temperature of the heat treatment is in the range of 700-900 ℃ for 50-70 seconds.
More optionally, the gate of the first PMOS pull-up tube is connected to the drain of the second PMOS pull-up tube, the drain of the first PMOS pull-up tube is connected to the gate of the second PMOS pull-up tube, and the source of the first PMOS pull-up tube and the source of the second PMOS pull-up tube are both connected to a high level;
the grid electrode of the first NMOS pull-down tube is connected with the source electrode of the second access tube, the drain electrode of the first NMOS pull-down tube is connected with the drain electrode of the first PMOS pull-up tube and the source electrode of the first NMOS access tube, the grid electrode of the second NMOS pull-down tube is connected with the source electrode of the third NMOS access tube, the drain electrode of the second NMOS pull-down tube is connected with the drain electrode of the second PMOS pull-up tube and the source electrode of the fourth NMOS access tube, and the source electrodes of the first NMOS pull-down tube and the second NMOS pull-down tube are connected with low level;
The source electrode of the first NMOS access tube is connected with the drain electrode of the third NMOS access tube, the drain electrode of the first NMOS access tube is connected with the bit line of the memory cell, and the grid electrode of the first NMOS access tube and the grid electrode of the second NMOS access tube are controlled by word lines;
the source electrode of the fourth NMOS access tube is connected with the drain electrode of the second NMOS access tube, the drain electrode of the fourth access tube is connected with the bit reversal line of the memory cell, and the grid electrode of the third NMOS access tube and the grid electrode of the fourth NMOS access tube are controlled by word lines.
As described above, the static random access memory cell and the manufacturing method thereof have the following beneficial effects:
the sources of the pull-up transistor and the pull-down transistor of the static random access memory cell are embedded with tunneling diode structures, so that the area of the device is not increased (the final effective cell area can be smaller than 7.5 mu m) 2 ) The floating body effect, the leakage power consumption caused by the parasitic triode effect and the threshold voltage drift of the transistor in the PDSOI device are effectively inhibited, and the noise immunity of the unit is improved; the manufacturing method of the static random access memory unit does not introduce an additional mask plate, is completely compatible with the existing logic process, adopts a central symmetry structure in the unit, is beneficial to matching of the size, threshold voltage and the like of the MOS tube, is beneficial to forming an array, and is convenient for fully customizing an SRAM chip.
Drawings
Fig. 1 is a schematic circuit diagram of a static random access memory cell according to the present invention.
Fig. 2 is a cross-sectional view of a PMOS transistor with a tunnel diode structure embedded in a sram cell according to the present invention.
Fig. 3 is a cross-sectional view of an NMOS transistor with a tunnel diode structure embedded in a sram cell according to the present invention.
Fig. 4 to 6 are schematic diagrams showing a top view structure of an NMOS transistor using a normal gate and a T-gate H-gate, respectively.
Fig. 7-12 are schematic top view structures of the static random access memory cell according to the present invention.
Description of element reference numerals
101. First PMOS pull-up tube
102. First NMOS pull-down tube
201. Second PMOS pull-up tube
202. Second NMOS pull-down tube
301-304 first-fourth NMOS access tube
4. Tunneling diode
41 P-type heavily doped anode
42 N-type heavily doped cathode
5. PMOS transistor embedded with tunneling diode
51 P-type heavily doped source region
52 Body region of PMOS transistor
53 Drain of PMOS transistor
54. Shallow P-type region
6. NMOS transistor embedded with tunneling diode
61 N-type heavily doped source region
62 Body region of NMOS transistor
63 Drain electrode of NMOS transistor
64. Shallow N-type region
7. Metal silicide
8. Back substrate
9. Buried insulating layer
10. Shallow trench isolation structure
11. Gate dielectric layer
12. Polysilicon layer
13. Side wall isolation structure
14. Common grid
15 T-shaped grid
16 H-shaped grid
17. Body contact region
18. Source region
19. Drain region
20a,20b,20c,20d active area
30 N-well
40. First P well and first P well preset position
50. Second P well
60a first grid electrode
60b second gate
60c third grid electrode
60d fourth grid
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-12. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The invention provides a static random access memory cell, and eight transistors are adopted, please refer to fig. 1, which shows a schematic circuit diagram of the static random access memory cell, comprising:
the first PMOS pull-up transistor 101, the second PMOS pull-up transistor 201, the first NMOS pull-down transistor 102, the second NMOS pull-down transistor 202, the first NMOS access transistor 301, the second NMOS access transistor 302, the third NMOS access transistor 303, and the fourth NMOS access transistor 304.
Specifically, the gate of the first PMOS pull-up tube 101 is connected to the drain of the second PMOS pull-up tube 201, the drain of the first PMOS pull-up tube 101 is connected to the gate of the second PMOS pull-up tube 201, and the source of the first PMOS pull-up tube 101 and the source of the second PMOS pull-up tube 201 are both connected to the high level VDD;
the gate of the first NMOS pull-down tube 102 is connected to the source of the second NMOS access tube 302, the drain of the first NMOS pull-down tube 102 is connected to the drain of the first PMOS pull-up tube 101 and the source of the first NMOS access tube 301, the gate of the second NMOS pull-down tube 202 is connected to the source of the third NMOS access tube 303, the drain of the second NMOS pull-down tube 202 is connected to the drain of the second PMOS pull-up tube 201 and the source of the fourth NMOS access tube 304, and the sources of the first NMOS pull-down tube and the second NMOS pull-down tube are both connected to the low level GND;
the source of the first NMOS access tube 301 is connected to the drain of the third NMOS access tube 303, the drain of the first NMOS access tube 301 is connected to the bit line BL of the memory cell, and the gate of the first NMOS access tube 301 and the gate of the second NMOS access tube 302 are controlled by the word line WL;
The source of the fourth NMOS access tube 304 is connected to the drain of the second NMOS access tube 302, the drain of the fourth NMOS access tube 304 is connected to the bit bar line BLB of the memory cell, and the gate of the third NMOS access tube 303 and the gate of the fourth NMOS access tube 304 are controlled by the word line WL.
As shown in fig. 1, the source of the first NMOS access tube 301 is connected to the drain of the first PMOS pull-up tube 101 and the drain of the first NMOS pull-down tube 102 to form a first storage node Q, and the source of the fourth NMOS access tube 304 is connected to the drain of the second PMOS pull-up tube 201 and the drain of the second NMOS pull-down tube 202 to form a second storage node QB.
In particular, in the present embodiment, a tunneling diode 4 is connected between the source and the body of the first PMOS pull-up transistor 101, the second PMOS pull-up transistor 201, the first NMOS pull-down transistor 102 and the second NMOS pull-down transistor 202. One or more transistors selected from the first PMOS pull-up transistor 101, the second PMOS pull-up transistor 201, the first NMOS pull-down transistor 102 and the second NMOS pull-down transistor 202 may be any transistor, and a tunneling diode 4 is connected between the source and the body, which is not limited in this embodiment. For a PMOS transistor, the source is connected to the anode of the tunnel diode 4, and the body is connected to the cathode of the tunnel diode 4; for an NMOS transistor, its source is connected to the cathode of the tunnel diode 4 and its body is connected to the anode of the tunnel diode 4.
As an example, please refer to fig. 2 and 3, wherein fig. 2 shows a cross-sectional view of the PMOS transistor 5 (the first PMOS transistor 11, the second PMOS transistor 21) embedded with the tunnel diode structure, and fig. 3 shows a cross-sectional view of the NMOS transistor 6 (the first NMOS transistor 12, the second NMOS transistor 22) embedded with the tunnel diode structure. As an example, the tunneling diode 4 is formed by connecting a P-type heavily doped anode 41 and an N-type heavily doped cathode 42.
As an example, the static random access memory unit adopts an SOI substrate sequentially comprising a back substrate 8, a buried insulating layer 9 and a top silicon from bottom to top, and active regions where the transistors are located are isolated by a shallow trench isolation structure 10 penetrating through the top silicon from top to bottom. The backing substrate 8 includes, but is not limited to, conventional semiconductor substrates of Si, ge, etc., and may have some type of doping. In this embodiment, the back substrate 8 is a P-type Si substrate, and the buried insulating layer 9 is silicon dioxide.
As shown in fig. 2, for the PMOS transistor, the P-type heavily doped anode 41 of the tunnel diode is shared with the P-type heavily doped source region 51 of the PMOS transistor, the N-type heavily doped cathode 42 of the tunnel diode is located at the bottom of the P-type heavily doped source region 51 and is in contact with the body region 52 of the PMOS transistor, and at the same time, the bottom of the N-type heavily doped cathode 42 is in contact with the buried insulating layer 9.
As shown in fig. 3, for an NMOS transistor, the N-type heavily doped cathode 42 of the tunneling diode is shared with the N-type heavily doped source region 61 of the NMOS transistor, the P-type heavily doped anode 41 of the tunneling diode is located at the bottom of the N-type heavily doped source region 61 and is in contact with the body region 62 of the NMOS transistor, and at the same time, the bottom of the P-type heavily doped anode 41 is in contact with the buried insulating layer 9.
Further, metal silicide 7 is formed on the P-type heavily doped source region 51 and the N-type heavily doped source region 61. The metal silicide 7 includes, but is not limited to, conductive silicide such as cobalt silicide and titanium silicide, which forms ohmic contact with the P-type heavily doped source region 51 or the N-type heavily doped source region 61.
Also shown in fig. 2 and 3 are the drain 53, shallow P-type region 54, gate, and drain 63, shallow N-type region 64, gate of the PMOS transistor and NMOS transistor, respectively. In this embodiment, the gates of the PMOS transistor and the NMOS transistor each include a gate dielectric layer 11 and a polysilicon layer 12 formed on the gate dielectric layer 11. A sidewall isolation structure 13 is further disposed around the gate, and the sidewall isolation structure 13 covers the shallow P-type region 54 or the shallow N-type region 64 partially. In this embodiment, metal silicide 7 is also formed on the upper parts of the drain and gate of the PMOS transistor and the NMOS transistor, so as to reduce the contact resistance between the drain and gate and the extraction electrode.
In the static random access memory unit, the sources of the first PMOS pull-up tube 101, the second PMOS pull-up tube 201, the first NMOS pull-down tube 102 and the second NMOS pull-down tube 202 are embedded with tunneling diode structures, so that the floating body effect, the parasitic triode effect-induced leakage power consumption and the transistor threshold voltage drift in the PD SOI device can be effectively restrained without increasing the unit area, and the noise resistance of the unit is improved.
It should be noted that, in fig. 1, the first NMOS access tube 301, the second NMOS access tube 302, the third NMOS access tube 303, and the fourth NMOS access tube 304 all adopt floating structures (i.e. body is suspended), so that the read speed of the unit performance is faster, the write noise margin is large, and the read noise margin is small.
In other embodiments, at least one of the first NMOS access transistor 301, the second NMOS access transistor 302, the third NMOS access transistor 303, and the fourth NMOS access transistor 304 may be a normal gate NMOS transistor, a T-gate NMOS transistor, or an H-gate NMOS transistor. As shown in fig. 4-6, a top view structure diagram of an NMOS transistor employing a normal gate 14, a T-type gate 15, and an H-type gate 16 is shown, wherein source region 17 and drain region 18 are provided on both sides of the gate, respectively, and body contact region 19 is provided for the T-type gate NMOS and the H-type gate NMOS transistor, respectively. The read speed is low, the write noise margin is low, but the read noise margin is high using cells with body contacts (pick-up tube source, even GND).
The following describes the specific working mode of the static random access memory unit in detail, and the static random access memory unit has three working states:
write state (write "0" data, for example): firstly, pulling down a bit line BL, raising an inverted bit line BLB, then raising a word line WL, conducting a first NMOS access tube 301, and discharging a first storage node Q through the first NMOS access tube 301; the third NMOS access tube 303 is turned on, the fourth NMOS access tube 304 is turned on, the inverted bit line raises the gate voltage of the first NMOS pull-down tube 102 through the third NMOS access tube 303 and the fourth NMOS access tube 304, and then the first storage node Q is further discharged through the first NMOS pull-down tube 102; the inverted bit line BLB charges the second storage node QB through the fourth NMOS access transistor 304, the potential of the first storage node Q decreases, and QB is charged through the first PMOS pull-up transistor 101.
In a read state (taking reading "0" data as an example), firstly raising the bit line BL and the bit line BLB to a high level through a precharge circuit, then raising the word line, conducting the first NMOS access tube 301, discharging the bit line BL to enable the bit line BL to be lowered, and amplifying the potential difference between the bit line BL and the bit line BLB through a sense amplifier to judge that the stored data is "0" data;
Holding state: only the word line WL needs to be pulled down, the first NMOS access transistor 301 and the fourth NMOS access transistor 304 are turned off, so that the data of the bit line BL and the bit bar line BLB do not affect the first storage node Q and the second storage node QB.
Assuming that the data stored in the memory cell is "1" data, that is, the first storage node Q is at a high level, and the second storage node QB is at a low level; word line WL is low; if the high-energy particles bombard the body region of the first NMOS pull-down tube 102, the first NMOS pull-down tube 102 and the second PMOS pull-up tube 201 are in the off state, and the second NMOS pull-down tube 202 and the first PMOS pull-up tube 101 are in the on state; after the high-energy particle bombardment, a transient high current is formed in the body region of the first NMOS pull-down tube 102, and at the moment, a part of current flows to the GMD end at a low point position through the body extraction structure of the body region; another portion of the current causes the first storage node Q to decrease in potential. At this time, on the one hand, the second storage node QB is still at a low potential, the first PMOS pull-up transistor 101 is turned on, and the first storage node Q is charged by the high potential VDD, preventing its potential from decreasing; on the other hand, the source electrode or the drain electrode of the MOS tube connected with the first storage node Q, because the second NMOS access tube 302 is cut off, the equivalent resistance value is in megaohm level, and because the first NMOS access tube 301 connected with the second NMOS access tube 302 is cut off, the grid electrode of the first NMOS access tube is connected with the second NMOS pull-down tube, and the equivalent resistance is higher than the megaohm level by several orders of magnitude, the feedback time of the first NMOS access tube is greatly prolonged, the stability of the holding state of the storage unit is improved, and the reading and writing speeds of the static random storage unit are ensured to be close to those of the traditional six-transistor static random storage unit.
Example two
The invention also provides a manufacturing method of the static random access memory unit, which comprises the following steps:
firstly, step 1) is executed to provide an SOI substrate which sequentially comprises a back substrate, an insulating buried layer and top silicon from bottom to top, shallow trench isolation structures are manufactured in the top silicon, and an active region is defined.
Specifically, as shown in fig. 7, four active regions 20a,20b,20c and 20d are defined, wherein the four active regions 20a,20b,20c and 20d are sequentially arranged, shallow trenches are formed around each active region, and insulating materials are filled in the shallow trenches to form a shallow trench isolation structure. In this embodiment, the insulating material is silicon dioxide.
Step 2) is then performed, as shown in fig. 8, to fabricate an N-well 30, a first P-well 40a and a second P-well 40b in the top silicon according to the position of the active region, wherein the N-well 30 is located between the first P-well 40a and the second P-well 40b.
Specifically, the N-well 30, the first P-well 40a, and the second P-well 40b are formed by an ion implantation method. As an example, the N-well 30 is implanted with phosphorus ions, and the first P-well 40a and the second P-well 40b are implanted with boron ions. The N well is used for manufacturing a PMOS transistor, and a partial area of the N well is used as a body area of the PMOS transistor; the first P well and the second P well are used for manufacturing an NMOS transistor, and a partial area of the first P well and the second P well is used as a body area of the NMOS transistor.
Step 3) is performed, as shown in fig. 9 to 12, to manufacture a first PMOS pull-up transistor 101 and a second PMOS pull-up transistor 201 in the N-well 30; manufacturing a first NMOS pull-down tube 102, a first NMOS access tube 301 and a second NMOS access tube 302 in the first P-well 40 a; a second NMOS pull-down transistor 202, a third NMOS access transistor 303, and a fourth NMOS access transistor 304 are fabricated in the second P-well 40 b; in fig. 10 to 12, the areas where the transistors are located are shown by dashed boxes.
Specifically, a tunneling diode 4 is connected between the source and the body of the first PMOS pull-up transistor 101, the second PMOS pull-up transistor 201, the first NMOS pull-down transistor 102, and the second NMOS pull-down transistor 202; for a PMOS transistor, the source is connected to the anode of the tunnel diode 4, and the body is connected to the cathode of the tunnel diode 4; for an NMOS transistor, its source is connected to the cathode of the tunnel diode 4 and its body is connected to the anode of the tunnel diode 4.
As an example, the tunneling diode 4 is formed by connecting a P-type heavily doped anode 41 and an N-type heavily doped cathode 42. For a PMOS transistor, the P-type heavily doped anode 41 of the tunneling diode 4 is shared with the P-type heavily doped source region 51 of the PMOS transistor, the N-type heavily doped cathode 42 of the tunneling diode 4 is located at the bottom of the P-type heavily doped source region 51 and is in contact with the body region of the PMOS transistor, and at the same time, the bottom of the N-type heavily doped cathode 42 is in contact with the buried insulating layer. For an NMOS transistor, the N-type heavily doped cathode 42 of the tunneling diode 4 is shared with the N-type heavily doped source region 61 of the NMOS transistor, the P-type heavily doped anode 41 of the tunneling diode 4 is located at the bottom of the N-type heavily doped source region 61 and is in contact with the body region of the NMOS transistor, and at the same time, the bottom of the P-type heavily doped anode 41 is in contact with the buried insulating layer.
As an example, said step 3) comprises the steps of:
31 As shown in fig. 9 and 10, a third gate 60c and a fourth gate 60d are formed at predetermined positions in the N-well 30, a first gate 60a is formed at predetermined positions in the first P-well 40a, and a second gate 60b is formed at predetermined positions in the second P-well 40 b; wherein the first gate 60a is a gate of the first NMOS pull-down tube 102, the second gate 60b is a gate of the second NMOS pull-down tube 202, the third gate 60c is a gate of the first PMOS pull-up tube 101, and the second gate 60d is a gate of the second PMOS pull-up tube 201; forming a fifth gate 60e at a predetermined position in the first P-well 40a, and forming a sixth gate 60f at a predetermined position in the second P-well 40 b; the fifth gate 60e is shared by the first NMOS access transistor 301 and the second NMOS access transistor 302; the sixth gate 60f is shared by the third NMOS access tube 303 and the fourth NMOS access tube 304, and the sixth gate 60f has a T-shaped bent portion at the positions of the third NMOS access tube 303 and the fourth NMOS access tube 304, respectively.
More specifically, the first gate 60a, the second gate 60b, the third gate 60c, the fourth gate 60d, the fifth gate 60e, and the sixth gate 60f each include a gate dielectric layer 11 and a polysilicon layer 12 on the gate dielectric layer 11.
32 N-type lightly doping is performed at the preset positions of the first P-well 40a and the second P-well 40b to form shallow N-type regions 401 of the first NMOS pull-down transistor 201, the second NMOS pull-down transistor 202, the first NMOS access transistor 301, the second NMOS access transistor 302, the third NMOS access transistor 303 and the fourth NMOS access transistor 304; p-type lightly doped is performed at a predetermined position of the N-well 30 to form shallow P-type regions (not shown) of the first PMOS pull-up transistor 101 and the second PMOS pull-up transistor 201.
33 A sidewall isolation structure (not shown) is formed around the first gate 60a, the second gate 60b, the third gate 60c, the fourth gate 60d, the fifth gate 60e, and the sixth gate 60 f. The sidewall isolation structure partially covers the shallow P-type region or the shallow N-type region 13.
34 As shown in fig. 11, P-type heavily doped anode 64 of the tunneling diode embedded in the first NMOS transistor 102 and the second NMOS transistor 202 is formed by P-type heavily doping at the preset position of the first P-well 40a and the second P-well 40 b; n-type heavily doping is performed at a predetermined position of the N-well 30 to form an N-type heavily doped cathode 42 embedded in the tunneling diodes of the first PMOS transistor 101 and the second PMOS transistor 201.
Specifically, an open mask is disposed at a preset position of the first P-well 40a and the second P-well 40b, and ion implantation is vertically performed through the mask, so as to complete the P-type heavy doping or the N-type heavy doping. In this embodiment, the concentration of the ion implantation is in the range of 1E15-9E15/cm 2 Preferably 3E15/cm 2 、5E15/cm 2 、7E15/cm 2 The method comprises the steps of carrying out a first treatment on the surface of the The ion concentration peak is made to be close to the lower part of the region where the transistor source region is located by controlling the energy of ion implantation.
35 As shown in fig. 12, N-type heavily doped regions above the P-type heavily doped anode 41 in the first P-well 40a and the second P-well 40b to form N-type heavily doped source regions 61 of the first NMOS transistor 12 and the second NMOS transistor 22; p-type heavy doping is performed in the N-well 30 in a region above the N-type heavy doping cathode 42, forming P-type heavy doping source regions 51 of the first PMOS transistor 11 and the second PMOS transistor 21. P-type heavy doping is performed at the preset positions of the first P-well 40a and the second P-well 40b, so as to form the P-type heavy doped body contact regions of the first NMOS access tube 301, the second NMOS access tube 302, the third NMOS access tube 303 and the fourth NMOS access tube 304.
Specifically, in the step 34) or the step 35), the method further includes the steps of performing N-type heavy doping at predetermined positions of the first P-well 40a and the second P-well 40b to form drains of the first NMOS pull-down transistor 102, the second NMOS pull-down transistor 202, the first NMOS access transistor 301, the second NMOS access transistor 302, the third NMOS access transistor 303 and the fourth NMOS access transistor 304, and sources of the first NMOS access transistor 301, the second NMOS access transistor 302, the third NMOS access transistor 303 and the fourth NMOS access transistor 304, and performing P-type heavy doping at predetermined positions of the N-well to form drains of the first PMOS pull-down transistor 101 and the second PMOS pull-down transistor 201.
Further, the present step further includes a step (not shown) of forming a metal silicide on the P-type heavily doped source region 51 and the N-type heavily doped source region 61.
Specifically, the metal silicide is formed by forming a metal layer on the P-type heavily doped source region 51 and the N-type heavily doped source region 61, and thermally treating the metal layer to react with the Si material thereunder. In this embodiment, the temperature range of the heat treatment is 700-900 ℃ and the time is 50-70 seconds.
Specifically, while forming metal silicide on the P-type heavily doped source region 51 and the N-type heavily doped source region 61, metal silicide may be formed on the upper portions of the drains and gates of the first PMOS pull-up transistor 101, the second PMOS pull-up transistor 201, the first NMOS pull-down transistor 102, and the second NMOS pull-down transistor 202, and metal silicide may be formed on the upper portions of the source drain and the gate of the first NMOS access transistor 301, the second NMOS access transistor 302, the third NMOS access transistor 303, and the fourth NMOS access transistor 304, so as to reduce the contact resistance between the source drain and the gate and the extraction electrode.
And finally, executing the step 4) to manufacture metal through holes and corresponding metal connecting wires so as to finish the manufacture of the static memory unit.
Specifically, the gate of the first PMOS pull-up tube 101 is connected to the drain of the second PMOS pull-up tube 201, the drain of the first PMOS pull-up tube 101 is connected to the gate of the second PMOS pull-up tube 201, and the source of the first PMOS pull-up tube 101 and the source of the second PMOS pull-up tube 201 are both connected to the high level VDD; the grid electrode of the first NMOS pull-down tube 102 is connected with the source electrode of the second NMOS access tube 302, the drain electrode of the first NMOS pull-down tube 102 is connected with the drain electrode of the first PMOS pull-up tube 101 and the source electrode of the first NMOS access tube 301, the grid electrode of the second NMOS pull-down tube 202 is connected with the source electrode of the third NMOS access tube 303, the drain electrode of the second NMOS pull-down tube 202 is connected with the drain electrode of the second PMOS pull-up tube 201 and the source electrode of the fourth NMOS access tube 304, and the source electrodes of the first NMOS pull-down tube and the second NMOS pull-down tube are both connected with the low level GND; the source electrode of the first NMOS access tube 301 is connected with the drain electrode of the third NMOS access tube 303, the drain electrode of the first NMOS access tube 301 is connected with the bit line BL of the memory cell, and the grid electrodes of the first NMOS access tube 301 and the second NMOS access tube 302 are controlled by word lines WL; the source of the fourth NMOS access tube 304 is connected to the drain of the second NMOS access tube 302, the drain of the fourth NMOS access tube 304 is connected to the bit bar line BLB of the memory cell, and the gates of the third NMOS access tube 303 and the fourth NMOS access tube 304 are controlled by the word line WL. The P-type heavily doped body contact region 7 of the first, second, third and fourth NMOS access transistors 301, 302, 303, 304 is connected to GND.
Thus, the manufacture of the static random access memory unit is completed. The manufacturing method of the static random access memory unit does not introduce an extra mask plate, is completely compatible with the existing logic process, adopts a central symmetry structure in the unit, is beneficial to matching of the size, threshold voltage and the like of the MOS tube, is beneficial to forming an array, is convenient for fully customizing an SRAM chip, and is suitable for occasions with harsh unit area, low power consumption and the like.
In summary, in the static random access memory cell of the present invention, the pull-up transistor and the pull-down transistor are embedded with the tunneling diode structure, which can effectively inhibit the floating body effect and parasitic triode effect in the PD SOI device from causing leakage power consumption and transistor threshold voltage drift without increasing the device area, and improve the noise immunity of the cell. The manufacturing method of the SOI six-transistor SRAM unit also has the advantages of simple manufacturing process, complete compatibility with the existing logic process and the like, the inside of the unit adopts a central symmetrical structure, the influence caused by process deviation can be reduced, meanwhile, the unit has a good sharing structure, the effective area of the unit can be reduced, the memory array can be conveniently formed, the area of the memory array is further reduced, and the period for designing the SRAM chip is shortened. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (18)

1. A static random access memory cell, wherein the static random access memory cell comprises at least:
the first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube, the second NMOS pull-down tube, the first NMOS access tube, the second NMOS access tube, the third NMOS access tube and the fourth NMOS access tube;
the grid electrode of the first PMOS pull-up tube is connected with the drain electrode of the second PMOS pull-up tube, the drain electrode of the first PMOS pull-up tube is connected with the grid electrode of the second PMOS pull-up tube, and the source electrode of the first PMOS pull-up tube and the source electrode of the second PMOS pull-up tube are both connected with high level;
the grid electrode of the first NMOS pull-down tube is connected with the source electrode of the second NMOS access tube, the drain electrode of the first NMOS pull-down tube is connected with the drain electrode of the first PMOS pull-up tube and the source electrode of the first NMOS access tube, the grid electrode of the second NMOS pull-down tube is connected with the source electrode of the third NMOS access tube, the drain electrode of the second NMOS pull-down tube is connected with the drain electrode of the second PMOS pull-up tube and the source electrode of the fourth NMOS access tube, and the source electrodes of the first NMOS pull-down tube and the second NMOS pull-down tube are connected with low level;
The source electrode of the first NMOS access tube is connected with the drain electrode of the third NMOS access tube, the drain electrode of the first NMOS access tube is connected with the bit line of the memory cell, the source electrode of the first NMOS access tube is connected with the drain electrode of the first PMOS pull-up tube and the drain electrode of the first NMOS pull-down tube to form a first memory node, and the grid electrodes of the first NMOS access tube and the second NMOS access tube are controlled by word lines;
the source electrode of the fourth NMOS access tube is connected with the drain electrode of the second NMOS access tube, the drain electrode of the fourth NMOS access tube is connected with the inverted bit line of the memory cell, the source electrode of the fourth NMOS access tube is connected with the drain electrode of the second PMOS pull-up tube and the drain electrode of the second NMOS pull-down tube to form a second memory node, and the grid electrode of the third NMOS access tube and the grid electrode of the fourth NMOS access tube are controlled by word lines;
the tunneling diodes are connected between the source electrodes and the body regions of the first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube and the second NMOS pull-down tube; for a PMOS transistor, the source electrode of the PMOS transistor is connected with the anode of the tunneling diode, and the body region of the PMOS transistor is connected with the cathode of the tunneling diode; for an NMOS transistor, its source is connected to the cathode of the tunnel diode and its body is connected to the anode of the tunnel diode.
2. The static random access memory cell of claim 1, wherein: the tunneling diode is formed by connecting a P-type heavily doped anode and an N-type heavily doped cathode.
3. The static random access memory cell of claim 2, wherein: for the PMOS pull-up tube, a P-type heavily doped anode of the tunneling diode is shared with a P-type heavily doped source region of the PMOS transistor, and an N-type heavily doped cathode of the tunneling diode is positioned at the bottom of the P-type heavily doped source region and is contacted with a body region of the PMOS pull-up tube; for the NMOS pull-down tube, an N-type heavily doped cathode of the tunneling diode is shared with an N-type heavily doped source region of the NMOS pull-down tube, and a P-type heavily doped anode of the tunneling diode is positioned at the bottom of the N-type heavily doped source region and is in contact with a body region of the NMOS pull-down tube.
4. A static random access memory cell according to claim 3, wherein: and metal silicide is formed on the upper parts of the P-type heavily doped source regions and the N-type heavily doped source regions.
5. The static random access memory cell of claim 4, wherein: the metal silicide is selected from any one of cobalt silicide and titanium silicide.
6. The static random access memory cell of claim 1, wherein: the static random access memory unit adopts an SOI substrate which sequentially comprises a back substrate, an insulating buried layer and top silicon from bottom to top, and active areas of all transistors are isolated by a shallow trench isolation structure penetrating through the top silicon from top to bottom.
7. The static random access memory cell of claim 1, wherein: the first NMOS access tube, the second NMOS access tube, the third NMOS access tube and the fourth NMOS access tube are one or a combination of a plurality of common grid NMOS tubes, T-shaped grid NMOS tubes or H-shaped grid NMOS tubes.
8. A method of fabricating a static random access memory cell according to any one of claims 1 to 7, comprising the steps of:
1) Providing an SOI substrate which sequentially comprises a back substrate, an insulating buried layer and top silicon from bottom to top, manufacturing a shallow trench isolation structure in the top silicon, and defining an active region;
2) Manufacturing an N well, a first P well and a second P well in the top silicon according to the position of the active region, wherein the N well is positioned between the first P well and the second P well;
3) Manufacturing a first PMOS pull-up tube and a second PMOS pull-up tube in the N well; manufacturing a first NMOS pull-down tube, a first NMOS access tube and a second NMOS access tube in the first P well; manufacturing a second NMOS pull-down tube, a third NMOS access tube and a fourth NMOS access tube in the second P well; the tunneling diodes are connected between the source electrodes and the body regions of the first PMOS pull-up tube, the second PMOS pull-up tube, the first NMOS pull-down tube and the second NMOS pull-down tube; for the PMOS pull-up tube, the source electrode of the PMOS pull-up tube is connected with the anode of the tunneling diode, and the body region of the PMOS pull-up tube is connected with the cathode of the tunneling diode; for the NMOS pull-down tube, the source electrode of the NMOS pull-down tube is connected with the cathode of the tunneling diode, and the body region of the NMOS pull-down tube is connected with the anode of the tunneling diode;
4) And manufacturing metal through holes and corresponding metal connecting wires to finish the manufacturing of the static random access memory unit.
9. The method for manufacturing the static random access memory cell according to claim 8, wherein: the tunneling diode is formed by connecting a P-type heavily doped anode and an N-type heavily doped cathode.
10. The method for manufacturing the static random access memory cell according to claim 9, wherein: for the PMOS pull-up tube, a P-type heavily doped anode of the tunneling diode is shared with a P-type heavily doped source region of the PMOS pull-up tube, and an N-type heavily doped cathode of the tunneling diode is positioned at the bottom of the P-type heavily doped source region and is in contact with a body region of the PMOS pull-up tube; for the NMOS pull-down tube, an N-type heavily doped cathode of the tunneling diode is shared with an N-type heavily doped source region of the NMOS pull-down tube, and a P-type heavily doped anode of the tunneling diode is positioned at the bottom of the N-type heavily doped source region and is in contact with a body region of the NMOS pull-down tube.
11. The method for manufacturing the static random access memory cell according to claim 9, wherein: said step 3) comprises the steps of:
31 Forming a grid electrode of the first PMOS pull-up tube and a grid electrode of the second PMOS pull-up tube at the preset position of the N well, forming a grid electrode of the first NMOS pull-down tube at the preset position of the first P well, and forming a grid electrode of the second NMOS pull-down tube at the preset position of the second P well;
32 N-type lightly doping is carried out at preset positions of the first P well and the second P well to form shallow N-type areas of the first NMOS pull-down tube, the second NMOS pull-down tube, the first NMOS access tube, the second NMOS access tube, the third NMOS access tube and the fourth NMOS access tube; p-type light doping is carried out at the preset position of the N well, so that shallow P-type areas of the first PMOS pull-up tube and the second PMOS pull-up tube are formed;
33 Forming a side wall isolation structure around the grid electrode of the first PMOS pull-up tube, the grid electrode of the second PMOS pull-up tube, the grid electrode of the first NMOS pull-down tube and the grid electrode of the second NMOS pull-down tube;
34 P-type heavy doping is carried out at preset positions of the first P well and the second P well, so that the P-type heavy doping anode is formed; n-type heavy doping is carried out at the preset position of the N well, and the N-type heavy doping cathode is formed;
35 N-type heavy doping is carried out on the region above the P-type heavy doping anode in the first and second P-wells, so as to form N-type heavy doping source regions of the first and second NMOS pull-down tubes; and P-type heavy doping is carried out in the region above the N-type heavy doping cathode in the N well, so that P-type heavy doping source regions of the first PMOS pull-up tube and the second PMOS pull-up tube are formed.
12. The method for manufacturing the static random access memory cell according to claim 11, wherein: in the step 34), a mask plate with openings at preset positions of the first and second P-wells is adopted, and ion implantation is vertically performed through the mask plate to complete the P-type heavy doping or the N-type heavy doping.
13. The method for manufacturing the static random access memory cell according to claim 12, wherein: the concentration of the ion implantation is in the range of 1E15-9E15/cm 2 。
14. The method for manufacturing the static random access memory cell according to claim 11, wherein: in the step 34) or the step 35), the method further includes the step of performing N-type heavy doping at the predetermined positions of the first P-well and the second P-well to form the first NMOS pull-down tube, the second NMOS pull-down tube, the drain of the first NMOS access tube, the second NMOS access tube, the third NMOS access tube, and the fourth NMOS access tube, and the source of the first NMOS access tube, the second NMOS access tube, the third NMOS access tube, and the fourth NMOS access tube, and performing P-type heavy doping at the predetermined positions of the N-well to form the drains of the first PMOS pull-down tube and the second PMOS pull-down tube.
15. The method for manufacturing the static random access memory cell according to claim 10, wherein: in the step 3), a step of forming metal silicide on the P-type heavily doped source region and the N-type heavily doped source region is further included.
16. The method for manufacturing the static random access memory cell according to claim 15, wherein: and forming a metal layer on the P-type heavily doped source region and the N-type heavily doped source region, and performing heat treatment to enable the metal layer to react with Si material below the metal layer to generate the metal silicide.
17. The method for manufacturing the static random access memory cell according to claim 16, wherein: the temperature range of the heat treatment is 700-900 ℃ and the time is 50-70 seconds.
18. The method for manufacturing the static random access memory cell according to claim 8, wherein:
the grid electrode of the first PMOS pull-up tube is connected with the drain electrode of the second PMOS pull-up tube, the drain electrode of the first PMOS pull-up tube is connected with the grid electrode of the second PMOS pull-up tube, and the source electrode of the first PMOS pull-up tube and the source electrode of the second PMOS pull-up tube are both connected with high level;
the grid electrode of the first NMOS pull-down tube is connected with the source electrode of the second NMOS access tube, the drain electrode of the first NMOS pull-down tube is connected with the drain electrode of the first PMOS pull-up tube and the source electrode of the first NMOS access tube, the grid electrode of the second NMOS pull-down tube is connected with the source electrode of the third NMOS access tube, the drain electrode of the second NMOS pull-down tube is connected with the drain electrode of the second PMOS pull-up tube and the source electrode of the fourth NMOS access tube, and the source electrodes of the first NMOS pull-down tube and the second NMOS pull-down tube are connected with low level;
The source electrode of the first NMOS access tube is connected with the drain electrode of the third NMOS access tube, the drain electrode of the first NMOS access tube is connected with the bit line of the memory cell, and the grid electrode of the first NMOS access tube and the grid electrode of the second NMOS access tube are controlled by word lines;
the source electrode of the fourth NMOS access tube is connected with the drain electrode of the second NMOS access tube, the drain electrode of the fourth NMOS access tube is connected with the bit reversal line of the memory cell, and the grid electrode of the third NMOS access tube and the grid electrode of the fourth NMOS access tube are controlled by word lines.
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