CN105489608B - A kind of SOI dual-port sram cell and preparation method thereof - Google Patents
A kind of SOI dual-port sram cell and preparation method thereof Download PDFInfo
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- CN105489608B CN105489608B CN201610008065.XA CN201610008065A CN105489608B CN 105489608 B CN105489608 B CN 105489608B CN 201610008065 A CN201610008065 A CN 201610008065A CN 105489608 B CN105489608 B CN 105489608B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
Abstract
The present invention provides a kind of SOI dual-port sram cell and preparation method thereof, and the unit includes: the first phase inverter, is made of the first PMOS transistor and the first NMOS transistor；Second phase inverter is made of the second PMOS transistor and the second NMOS transistor；Pipe is obtained, is made of the NMOS transistor of third, the four, the 5th and the 6th.In sram cell of the invention, four transistors of the first, second phase inverter of composition are all made of L-type grid, and the bending angle lateral area of L-type grid is equipped with heavy doping body contact zone.The present invention can effectively inhibit the leakage power consumption and transistor threshold voltage drift of floater effect and the initiation of parasitic triode effect in PD SOI device in the case where sacrificing small cell area, improve the noise resisting ability of unit.Manufacturing process of the present invention does not introduce extra mask plate, completely compatible with existing logic process, uses centrosymmetric structure inside unit, not only contributes to the matching such as size and threshold voltage of metal-oxide-semiconductor, also helps to form array, facilitate full custom sram chip.
Description
Technical field
The invention belongs to reservoir designs and production field, it is related to a kind of SOI dual-port sram cell and preparation method thereof.
Background technique
SOI technology is since the invention eighties in last century, it is relative to common bulk silicon technological, the small, function with parasitic capacitance
Anti-single particle latch (Single-Event-Latchup, SEL) ability low, that speed is fast and natural is consumed, so that SOI technology is very suitable
Together in work in system on chip (System-on-Chips, SoC), low-power consumption and the occasions such as anti-radiation；In addition, static random
Memory (Static Random Access Memory, SRAM) is widely used in consumer electronics, automotive electronics, processor one
In grade caching and L2 cache；So SOI technology is applied in SRAM design, there is some superiority.
According to the degree of exhaustion in metal-oxide-semiconductor body area, SOI can further be divided into fully- depleted (Full-Depleted, FD) SOI and
Part depletion (Partially-Depleted, FD) SOI.For part depletion SOI technology, due to its body area of metal-oxide-semiconductor and source region
It electrically separates, it is hanging for leading to body area；In normal work, drain potentials are higher, and the electronics of inversion channel is transported from source electrode
When moving drain electrode, by electric field acceleration, when moving to by close to leakage body knot, at this time because most strong in electric field, electronics obtains volume
Outer energy, and collide to form electron-hole pair with the atom on lattice；Velocity of electrons is fast, in a short period of time by
Accelerate to drain electrode；However cavity speed is relatively slow, and the low potentials such as body area, source region region is slowly moved to along direction of an electric field,
Be moved to body area hole be easy to the electronics provided by source electrode carry out it is compound fall, and when being moved to body area, because of its potential floating
And hole is accumulated gradually in body area, it directly will affect the threshold voltage of metal-oxide-semiconductor, so that metal-oxide-semiconductor performance is made to change, this
It is exactly floater effect.In addition, there are also parasitic triode effects in PD SOI metal-oxide-semiconductor, refer to source electrode, body area and the leakage of metal-oxide-semiconductor
Pole is respectively N, P and N, similar to emitter, base stage and the collector in triode, that is, the parasitic day of metal-oxide-semiconductor
Right NPN triode；This base stage is hanging.Generally, when base stage does not have positive charge, potential and transmitting electrode potential phase
Together, therefore its triode does not turn on；If floater effect occurs, when base stage positive charge is accumulated to a certain extent, base stage and emitter
When potential reaches a certain level, triode can be connected, the phenomenon that drain electrode can generate high current.Floater effect and parasitic three poles
Tube effect will cause the performance change of PD SOI sram cell, such as electric leakage increases, noise resisting ability reduces.
Currently used static random access memory cell includes eight transistor types, by two pull-up P-type transistors, two
It pulls down N-type transistor and four transmission gate N-type transistors is constituted, wordline controls the switch of four transmission gate N-type transistors, passes through
Bit line write-in reads storing data, wherein this eight transistors are all made of common metal-oxide-semiconductor.
Generally, due to floater effect and parasitic triode effect in PD SOI metal-oxide-semiconductor, designer usually can be by metal-oxide-semiconductor
Body area extracts that (NMOS body area is connected to low potential, that is, is shorted with source region potential；PMOS body area is connected to high level), by potential
It is kept fixed to inhibit the two effect；Common body contact is exactly T- type grid metal-oxide-semiconductor and H- type grid metal-oxide-semiconductor, but this and phase
Compared with the non-body of size contacts metal-oxide-semiconductor, area can be higher by very much.If T- type metal-oxide-semiconductor is directly applied to sram cell
In the middle, cellar area will increase 1 times or so, even more (applying H- type grid).
Therefore, a kind of SOI dual-port sram cell and preparation method thereof how is provided, before minimizing chip area
Floater effect, the parasitic triode effect for effectively inhibiting metal-oxide-semiconductor are put, to enhance six-transistor static random access memory unit
Stability and drop low leakage power consumption, become those skilled in the art's important technological problems urgently to be resolved.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of SOI dual-port sram cells
And preparation method thereof, for solving, SOI dual-port sram cell area occupied is larger in the prior art, stability is poor, leakage power consumption
High and weak noise resisting ability problem.
In order to achieve the above objects and other related objects, the present invention provides a kind of SOI dual-port sram cell, the SOI
Dual-port sram cell includes:
First phase inverter is made of the first PMOS transistor and the first NMOS transistor；
Second phase inverter is made of the second PMOS transistor and the second NMOS transistor；
Pipe is obtained, by third NMOS transistor, the 4th NMOS transistor, the 5th NMOS transistor and the 6th NMOS transistor
Composition；The source electrode of the third NMOS tube is connected to the input of the output end and second phase inverter of first phase inverter
End, grid are connected to the write word line of memory, and drain electrode is connected to the write bit line of memory；The source electrode of 4th NMOS transistor
It is connected to the output end of second phase inverter and the input terminal of first phase inverter, grid is connected to writing for memory
Line, what drain electrode was connected to memory writes antiposition line；The source electrode of 5th NMOS tube is connected to the output of first phase inverter
The input terminal of end and second phase inverter, grid are connected to the readout word line of memory, and drain electrode is connected to the sense bit line of memory；
The source electrode of 6th NMOS transistor is connected to the output end of second phase inverter and the input terminal of first phase inverter,
Grid is connected to the readout word line of memory, and drain electrode is connected to the reading antiposition line of memory；
Wherein: first, second PMOS transistor and the first, second NMOS transistor are all made of L-type grid；For NMOS
Transistor, the bending angle lateral areas of L-type grid are equipped with a p-type heavy doping body contact zone, the p-type heavy doping body contact zone with
Body area of NMOS transistor and N-type heavy doping source region have contact with each other where it；For PMOS transistor, the bending of L-type grid
Angle lateral area is equipped with a N-type heavy doping body contact zone, the body of the p-type heavy doping body contact zone and PMOS transistor where it
Area and p-type heavy doping source region have contact with each other.
Optionally, the N-type heavy doping source region and the p-type heavy doping body contact zone top are formed with metal silicide.
Optionally, the p-type heavy doping source region and the N-type heavy doping body contact zone top are formed with metal silicide.
Optionally, any one of the metal silicide in cobalt silicide and titanium silicide.
Optionally, the SOI dual-port sram cell is using from bottom to top successively including backing bottom, insulating buried layer and top layer
The SOI substrate of silicon, by being isolated up and down through the fleet plough groove isolation structure of the top layer silicon between active area where each transistor.
Optionally, the third, at least one in the four, the five, the 6th NMOS transistors use L-type grid NMOS tube.
Optionally, the third, at least one in the four, the five, the 6th NMOS transistors using common grid NMOS tube,
T-type grid NMOS tube or H-type grid NMOS tube.
The present invention also provides a kind of production methods of SOI dual-port sram cell, include the following steps:
S1: one is provided from bottom to top successively including the SOI substrate at backing bottom, insulating buried layer and top layer silicon, in the top layer
Fleet plough groove isolation structure is made in silicon, defines active area；
S2: the position according to the active area makes N trap, the first p-well and the second p-well in the top layer silicon, wherein institute
N trap is stated between first p-well and the second p-well；
S3: the first PMOS transistor and the second PMOS transistor are made in the N trap；It is made in first p-well
First NMOS transistor, third NMOS transistor and the 5th NMOS transistor；The 2nd NMOS crystal is made in second p-well
Pipe, the 4th NMOS transistor and the 6th NMOS transistor；Wherein, first, second PMOS transistor and the first, second NMOS
Transistor is all made of L-type grid；For NMOS transistor, the bending angle lateral area of L-type grid is contacted equipped with a p-type heavy doping body
Area, the p-type heavy doping body contact zone have contact with each other with the body area of NMOS transistor where it and N-type heavy doping source region；It is right
It is equipped with a N-type heavy doping body contact zone in the bending angle lateral area of PMOS transistor, L-type grid, the p-type heavy doping body connects
Touching area has contact with each other with the body area of PMOS transistor where it and p-type heavy doping source region；
S4: production metallic vias and respective metal line, to complete the production of the sram cell.
Optionally, the step S3 comprising steps of
S3-1: the first grid across first p-well and the N trap and the across the N trap and the second p-well is formed
Two grids, and third grid is formed in the first p-well predeterminated position, the 4th grid is formed in the second p-well predeterminated position；
The first grid is shared by first NMOS transistor and first PMOS transistor, and the first grid is distinguished
There is a bending part at first NMOS transistor and first PMOS transistor position；The second grid is described
Second NMOS transistor and second PMOS transistor share, and the second grid is respectively in the 2nd NMOS crystal
There is a bending part at pipe and second PMOS transistor position；
S3-2: carrying out N-type in the first, second p-well predeterminated position and be lightly doped, formed it is described first, second, third,
The shallow n-type area of four, the 5th and the 6th NMOS transistor；P-type is carried out in the N trap predeterminated position to be lightly doped, and forms described the
One, the shallow p type island region of the second PMOS transistor；
S3-3: side wall isolation structure is formed around first, second, third, fourth grid；
S3-4: N-type heavy doping is carried out in the N trap predeterminated position, forms the described of first, second PMOS transistor
N-type heavy doping body contact zone；P-type heavy doping is carried out in the first, second p-well predeterminated position, forms first and second NMOS
The p-type heavy doping body contact zone of transistor.
Optionally, the N-type heavy doping body contact zone is formed using ion implantation and the p-type heavy doping body contacts
Area.
Optionally, the concentration range of the ion implanting is 1E15-9E15/cm2。
It optionally, further include heavily doped in the first, second p-well predeterminated position progress N-type in the step S3-4
It is miscellaneous, formed described first and second, third, the four, the five, the 6th NMOS transistors N-type heavy-doped source drain region the step of, and
P-type heavy doping is carried out in the N trap predeterminated position, forms the p-type heavy-doped source drain region of first, second PMOS transistor
Step.
Optionally, the drain electrode of first NMOS transistor is shared with the source electrode of the third NMOS transistor；Described
The drain electrode of bi-NMOS transistor is shared with the source electrode of the 4th NMOS transistor.
It optionally, further include in the p-type heavy doping source region, N-type heavy doping body contact zone and institute in the step S3
The step of stating N-type heavy doping source region, p-type heavy doping body contact zone top formation metal silicide.
Optionally, by the p-type heavy doping source region, N-type heavy doping body contact zone and the N-type heavy doping source region, P
Metal layer is formed in type heavy doping body contact zone, and being heat-treated reacts the metal layer with the Si material under it, described in generation
Metal silicide.
Optionally, the temperature range of the heat treatment is 700-900 DEG C, and the time is 50-70 seconds.
Optionally, first NMOS transistor and first PMOS transistor are interconnected and form the first phase inverter；It is described
Second NMOS transistor and second PMOS transistor are interconnected and form the second phase inverter；The source electrode of the third NMOS tube connects
To the output end of first phase inverter and the input terminal of second phase inverter, grid is connected to the write word line of memory, leaks
Pole is connected to the write bit line of memory；The source electrode of 4th NMOS transistor be connected to second phase inverter output end and
The input terminal of first phase inverter, grid are connected to the write word line of memory, and what drain electrode was connected to memory writes antiposition line；Institute
The source electrode for stating the 5th NMOS tube is connected to the output end of first phase inverter and the input terminal of second phase inverter, and grid connects
It is connected to the readout word line of memory, drain electrode is connected to the sense bit line of memory；The source electrode of 6th NMOS transistor is connected to institute
The output end of the second phase inverter and the input terminal of first phase inverter are stated, grid is connected to the readout word line of memory, and drain electrode connects
It is connected to the reading antiposition line of memory.
As described above, SOI dual-port sram cell and preparation method thereof of the invention, has the advantages that described
In SOI dual-port sram cell, four transistors for forming the first phase inverter and the second phase inverter are all made of L-type grid；For
NMOS transistor, the bending angle lateral area of L-type grid are equipped with a p-type heavy doping body contact zone, the p-type heavy doping body contact
The body area of NMOS transistor and N-type heavy doping source region have contact with each other where Qu Yuqi；For PMOS transistor, L-type grid
Bending angle lateral area is equipped with a N-type heavy doping body contact zone, the p-type heavy doping body contact zone and PMOS transistor where it
Body area and p-type heavy doping source region have contact with each other.The present invention can (final has in the case where sacrificing small cell area
Effect cellar area is smaller than 4 μm2) effectively inhibit the floater effect in PD SOI device and the leakage of parasitic triode effect initiation
Power consumption and transistor threshold voltage drift, improve the noise resisting ability of unit.And SOI dual-port sram cell of the invention
Production method do not introduce extra mask plate, completely compatible with existing logic process, use centrosymmetric structure inside unit, no
Only be conducive to the matching such as size and threshold voltage of metal-oxide-semiconductor, also help to form array, facilitate full custom sram chip.
Detailed description of the invention
Fig. 1 is shown as the circuit theory schematic diagram of SOI dual-port sram cell of the invention.
The plan structure that Fig. 2 is shown as the NMOS transistor in SOI dual-port sram cell of the invention using L-type grid is shown
It is intended to.
Fig. 3 and Fig. 4 be respectively indicated as the A-A ' of structure shown in Fig. 2 to and B-B ' to cross-sectional view.
Fig. 5-Fig. 7 is respectively indicated as the overlooking structure diagram of the NMOS transistor using common grid, T-type grid and H-type grid.
Fig. 8-Figure 13 is shown as the vertical view that each step is presented in the production method of SOI dual-port sram cell of the invention
Structural schematic diagram.
Component label instructions
1 first phase inverter
101 first PMOS transistors
102 first NMOS transistors
2 second phase inverters
201 second PMOS transistors
202 second NMOS transistors
3 obtain pipe
301 third NMOS transistors
302 the 4th NMOS transistors
303 the 5th NMOS transistors
304 the 6th NMOS transistors
4 N-type heavy doping source regions
401 shallow n-type areas
5 N-type heavy doping drain regions
6 L-type grid
601 gate dielectric layers
602 polysilicon layers
7 p-type heavy doping body contact zones
8 body areas
9 side wall isolation structures
10 metal silicides
11 backing bottoms
12 insulating buried layers
13 fleet plough groove isolation structures
14 common grid
15 T-type grid
16 H-type grid
17 source regions
18 drain regions
19 body contact zones
20a, 20b, 20c, 20d, 20e, 20f active area
30 N traps
30a, 30b, 30c N trap predeterminated position
40 first p-wells
The first p-well predeterminated position of 40a, 40b
50 second p-wells
The second p-well predeterminated position of 50a, 50b
60a first grid
60b second grid
60c third grid
The 4th grid of 60d
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Figure 13.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
The present invention provides a kind of SOI dual-port sram cell, referring to Fig. 1, being shown as the SOI dual-port sram cell
Circuit theory schematic diagram, comprising:
First phase inverter 1 is made of the first PMOS transistor 101 and the first NMOS transistor 102；
Second phase inverter 2 is made of the second PMOS transistor 201 and the second NMOS transistor 202；
Pipe 3 is obtained, by third NMOS transistor 301, the 4th NMOS transistor 302, the 5th NMOS transistor 303 and the 6th
NMOS transistor 304 forms；The source electrode of the third NMOS tube 301 is connected to the output end and described of first phase inverter
The input terminal of two phase inverters, grid are connected to the write word line WL1 of memory, and drain electrode is connected to the write bit line BL1 of memory；It is described
The source electrode of 4th NMOS transistor 302 is connected to the output end of second phase inverter and the input terminal of first phase inverter,
Grid is connected to the write word line WL1 of memory, and what drain electrode was connected to memory writes antiposition line BLB1；5th NMOS tube 303
Source electrode be connected to the output end of first phase inverter and the input terminal of second phase inverter, grid are connected to memory
Readout word line WL2, drain electrode are connected to the sense bit line BL2 of memory；The source electrode of 6th NMOS transistor 304 is connected to described
The input terminal of the output end of two phase inverters and first phase inverter, grid are connected to the readout word line WL2 of memory, drain electrode connection
To the reading antiposition line BLB2 of memory.
As an example, the source electrode of first PMOS transistor 101 and the second PMOS transistor 201 with power end VDD
Connection, drain electrode is connected with the drain electrode of first NMOS transistor 102 and the second NMOS transistor 202 respectively, as phase inverter
Output end.The grid of first PMOS transistor 101 and the second PMOS transistor 201 respectively with the first NMOS crystal
The grid of pipe 102 and the second NMOS transistor 202 is connected, the input terminal as phase inverter.First NMOS transistor 102 and
The source grounding line GND of second NMOS transistor 202, to realize the function of the first phase inverter 1 and the second phase inverter 2.In Fig. 1
Also show the position of the first memory node Q and the second memory node QB.
Particularly, in first phase inverter 1 and the second phase inverter 2, first, second PMOS transistor 101,201
And first, second NMOS transistor 102,202 be all made of L-type grid；For NMOS transistor, the bending angle outside area of L-type grid
Domain is equipped with a p-type heavy doping body contact zone, the p-type heavy doping body contact zone and the body area of NMOS transistor and N-type where it
Heavy doping source region has contact with each other；For PMOS transistor, the bending angle lateral area of L-type grid is equipped with a N-type heavy doping body
Contact zone, the p-type heavy doping body contact zone mutually connect with the body area of PMOS transistor where it and p-type heavy doping source region
Touching.
As an example, referring to Fig. 2, being shown with NMOS transistor (the first, second NMOS transistor of L-type grid
102,202) overlooking structure figure.Fig. 3 and Fig. 4 be respectively indicated as the A-A ' of structure shown in Fig. 2 to and B-B ' to cross-sectional view.As
Example, the SOI dual-port sram cell is using from bottom to top successively including backing bottom 11, insulating buried layer 12 and top layer silicon
SOI substrate, by being isolated up and down through the fleet plough groove isolation structure 13 of the top layer silicon between active area where each transistor.Institute
Stating backing bottom 11 includes but is not limited to the conventional semiconductors substrates such as Si, Ge, and can have the doping of certain type.The present embodiment
In, the backing bottom 11 uses p-type Si substrate, and the insulating buried layer 12 uses silica.
As shown in Figures 2 to 4, the body area 8 of the NMOS transistor is set to the lower section of the L-type grid 6；The NMOS crystal
The N-type heavy doping source region 4 of pipe and N-type heavy doping drain region 5 are respectively arranged on the two sides of 8 front of body area；The p-type heavy doping body
Contact zone 7 be set to the L-type grid 6 bending angle lateral area, and respectively with 8 rear portion of body area and the N-type heavy-doped source
Area 4 is in contact.
Further, the N-type heavy doping source region 4 and 7 top of p-type heavy doping body contact zone are formed with metal silication
Object 10.The metal silicide 10 includes but is not limited to the conductive silicides such as cobalt silicide and titanium silicide, with the N-type heavy doping
Source region 4 and the p-type heavy doping body contact zone 7 form Ohmic contact.
The shallow n-type area 401 of NMOS transistor is also shown in Fig. 3.As an example, the L-type grid 6 include gate dielectric layer
601 and the polysilicon layer 602 that is formed on the gate dielectric layer 601.It is additionally provided with side wall isolation structure 9 around the L-type grid 6,
The side wall isolation structure 9 covers 401 part of shallow n-type area.In the present embodiment, the N-type heavy doping of the NMOS tube is leaked
Area 5 and 6 top of L-type grid are also each formed with metal silicide 10, the contact for reducing drain electrode and between grid and extraction electrode
Resistance.
Fig. 2-Fig. 4 display is using the structural schematic diagram of the NMOS transistor of the L-type grid, for using L-type grid
PMOS transistor, structure is essentially identical with NMOS transistor, only in transistor each region doping type on the contrary, herein no longer
It is illustrated.Likewise, for the PMOS transistor using L-type grid, p-type heavy doping source region and N-type heavy doping body contact zone
Top forms and is also preferably formed with metal silicide.
In SOI dual-port sram cell of the invention, four transistors for forming the first phase inverter and the second phase inverter are equal
Using L-type grid；For NMOS transistor, the bending angle lateral area of L-type grid is equipped with a p-type heavy doping body contact zone, the P
Type heavy doping body contact zone has contact with each other with the body area of NMOS transistor where it and N-type heavy doping source region；For PMOS crystalline substance
Body pipe, the bending angle lateral areas of L-type grid are equipped with a N-type heavy doping body contact zone, the p-type heavy doping body contact zone and its
The body area of place PMOS transistor and p-type heavy doping source region have contact with each other.Wherein, first, second NMOS transistor
Body area contacts and is connected to low level, first, second PMOS with pipe source is obtained by the p-type heavy doping body contact zone
The body area of transistor contacts and is connected to high level with pipe source is obtained by the N-type heavy doping body contact zone, so that this hair
It is bright can (final effective cellar area be smaller than 4 μm in the case where sacrificing small cell area2) effectively inhibit PD SOI
The leakage power consumption and transistor threshold voltage drift that floater effect and parasitic triode effect in device cause, improve unit
Noise resisting ability.
It should be pointed out that in Fig. 1, third NMOS transistor 301, the 4th NMOS crystal used by the acquisition pipe 3
Pipe 302, the 5th NMOS transistor 303 and the 6th NMOS transistor 304 are all made of float structure (area Ji Ti is hanging), unit
The reading rate of energy is very fast, and it is big to write noise margin, and read noise tolerance is small.
In other embodiments, for third NMOS transistor 301, the 4th NMOS crystal used by the acquisition pipe 3
Pipe 302, the 5th NMOS transistor 303 and the 6th NMOS transistor 304, can also at least one use the L-type grid, and pass through
The p-type heavy doping body contact zone of L-type grid bending angle lateral area is set to by the third NMOS transistor 301, the described 4th
The body area of NMOS transistor 302, the 5th NMOS transistor 303 or the 6th NMOS transistor 304 is connected to low level.Certainly, institute
It states in third NMOS transistor 301, the 4th NMOS transistor 302, the 5th NMOS transistor 303 and the 6th NMOS transistor 304
Also but at least one uses common grid NMOS tube, T-type grid NMOS tube or H-type grid NMOS tube.As shown in Figure 5-Figure 7, it shows respectively
It is shown as the overlooking structure figure of the NMOS transistor using common grid 14, T-type grid 15 and H-type grid 16, wherein grid two sides are respectively source
Area 17 and drain region 18 are also respectively provided with body contact zone 19 for T-type grid NMOS and H-type grid NMOS transistor.It is connect using with body
The unit of (obtain and take pipe source or even GND) is touched, reading rate is smaller, it is small to write noise margin, but read noise tolerance is big.
Embodiment two
The present invention also provides a kind of production methods of SOI dual-port sram cell, include the following steps:
Step S1 is first carried out: providing one, successively the SOI including backing bottom, insulating buried layer and top layer silicon is served as a contrast from bottom to top
Bottom makes fleet plough groove isolation structure in the top layer silicon, defines active area.
As an example, as shown in figure 8, defining six active areas 20a, 20b, 20c, 20d, 20e and 20f, wherein this six
Active area 20e, 20a, 20b, 20c, 20d and 20f are successively arranged in parallel, and each active area surrounding is formed with shallow channel, described shallow
Fleet plough groove isolation structure is constituted filled with insulating materials in channel.In the present embodiment, the insulating materials is silica.
Then execute step S2: as shown in figure 9, the position according to the active area made in the top layer silicon N trap 30,
First p-well 40 and the second p-well 50, wherein the N trap 30 is between first p-well 40 and the second p-well 50.
Specifically, forming the N trap and the first, second p-well using ion injection method.As an example, the N trap uses
Phosphonium ion injection, the p-well are injected using boron ion.The N trap is for making PMOS transistor, and partial region is as PMOS
The body area of transistor；First, second p-well is for making NMOS transistor, body of the partial region as NMOS transistor
Area.
Step S3 is executed again: as shown in Figure 10 to Figure 13, the first PMOS transistor 101 and the is made in the N trap 30
Two PMOS transistors 201；The first NMOS transistor 102, third NMOS transistor 301 and are made in first p-well 40
Five NMOS transistors 303；The second NMOS transistor 202, the 4th NMOS transistor 302 and are made in second p-well 50
Six transistors 304；Wherein, Figure 11 is all made of dotted line frame into Figure 13 and shows each transistor region.
Particularly, in first phase inverter 1 and the second phase inverter 2, first, second PMOS transistor 101,201
And first, second NMOS transistor 102,202 be all made of L-type grid；For NMOS transistor, the bending angle outside area of L-type grid
Domain is equipped with a p-type heavy doping body contact zone, the p-type heavy doping body contact zone and the body area of NMOS transistor and N-type where it
Heavy doping source region has contact with each other；For PMOS transistor, the bending angle lateral area of L-type grid is equipped with a N-type heavy doping body
Contact zone, the p-type heavy doping body contact zone mutually connect with the body area of PMOS transistor where it and p-type heavy doping source region
Touching.The bottom of the p-type heavy doping body contact zone and the N-type heavy doping body contact zone is in contact with the insulating buried layer.
As an example, the step S3 comprising steps of
S3-1: as shown in Figures 10 and 11, formed across first p-well 40 and the N trap 30 first grid 60a and
Third grid is formed across the N trap 30 and the second grid 60b of the second p-well 50, and in 40 predeterminated position of the first p-well
60c forms the 4th grid 60d in 50 predeterminated position of the second p-well；The first grid 60a is the first NMOS crystal
Pipe 102 and first PMOS transistor 101 share, and the first grid 60a is respectively in first NMOS transistor
102 and 101 position of the first PMOS transistor at have a bending part；The second grid 60b is the 2nd NMOS brilliant
Body pipe 202 and second PMOS transistor 201 share, and the second grid 60b is respectively in the 2nd NMOS crystal
There is a bending part at pipe 202 and 201 position of the second PMOS transistor；The third grid 60c is the 3rd NMOS
Transistor 301 and the 5th NMOS transistor 303 share；The 4th grid 60d is the 4th NMOS transistor 302
And the 6th NMOS transistor 304 shares.
Specifically, described first, second, third, fourth grid 60a, 60b, 60c, 60d include gate dielectric layer and are located at
Polysilicon layer on the gate dielectric layer.
S3-2: carrying out N-type in first, second p-well 40,50 predeterminated positions and be lightly doped, formed it is described first, second,
The shallow n-type area of third, the four, the five, the 6th NMOS transistors 102,202,301,302,303,304；It is default in the N trap 30
Position carries out p-type and is lightly doped, and forms the shallow p type island region (being unillustrated) of first, second PMOS transistor 101,201.
S3-3: side wall isolation structure is formed around described first, second, third, fourth grid 60a, 60b, 60c, 60d
(being unillustrated).The side wall isolation structure covers the shallow p type island region or shallow n-type area part.
S3-4: as shown in figure 12, carrying out N-type heavy doping in described N trap predeterminated position 30a, 30b, formed it is described first, the
The N-type heavy doping body contact zone of two PMOS transistors 101,201；As shown in figure 13, default in first, second p-well
Position 40b, 50b carry out p-type heavy doping, and the p-type heavy doping body for forming first and second NMOS transistor 102,202 connects
Touch area.
Specifically, forming the N-type heavy doping body contact zone and p-type heavy doping body contact using ion implantation
Area.In the present embodiment, the concentration range of the ion implanting is 1E15-9E15/cm2。
Specifically, as shown in figure 12, it, can also be described first, second when forming the N-type heavy doping body contact zone
P-well predeterminated position 40a, 50a carry out N-type heavy doping, form described first and second, third, the four, the five, the 6th NMOS transistors
102,202,301,302,303,304 N-type heavy-doped source drain region.As shown in figure 13, the p-type heavy doping body contact is being formed
Qu Shi can also carry out p-type heavy doping in the N trap predeterminated position 30c, formed first, second PMOS transistor 101,
201 p-type heavy-doped source drain region.
It should be pointed out that the N-type heavy doping body contact zone, N-type heavy-doped source drain region, p-type heavy doping body contact zone,
The formation sequence in p-type heavy-doped source drain region is adjustable, should not excessively limit the scope of the invention herein.
In the present embodiment, the drain electrode of first NMOS transistor 102 and the source electrode of the third NMOS transistor 301 are total
With；The drain electrode of second NMOS transistor 302 is shared with the source electrode of the 4th NMOS transistor 202.
It further, further include in the p-type heavy doping source region, N-type heavy doping body contact zone and the N in this step
The step of metal silicide is formed at type heavy doping source region, p-type heavy doping body contact zone top (is unillustrated).
Specifically, by the p-type heavy doping source region, N-type heavy doping body contact zone and the N-type heavy doping source region, P
Metal layer is formed in type heavy doping body contact zone, and being heat-treated reacts the metal layer with the Si material under it, described in generation
Metal silicide.In the present embodiment, the temperature range of the heat treatment is 700-900 DEG C, and the time is 50-70 seconds.
Specifically, in the p-type heavy doping source region, N-type heavy doping body contact zone and the N-type heavy doping source region, p-type weight
While adulterating body contact zone top and form metal silicide, can also in first, second PMOS transistor 101,201 and
Metal silicide formed at the drain electrode of the first, second NMOS transistor 102,202 and grid top, and the third, the 4th,
Metal silicide is formed at the source-drain electrode of the five, the 6th NMOS transistors 301,302,303,304 and grid top, to reduce source and drain
Contact resistance between pole and grid and extraction electrode.
Finally execute step S4: production metallic vias and respective metal line, to complete the production of the sram cell.
Specifically, first NMOS transistor 102 is interconnected and form the first reverse phase with first PMOS transistor 101
Device；Second NMOS transistor 202 is interconnected and form the second phase inverter with second PMOS transistor 201；The third
The source electrode of NMOS tube 301 is connected to the output end of first phase inverter and the input terminal of second phase inverter, grid connection
To the write word line of memory, drain electrode is connected to the write bit line of memory；The source electrode of 4th NMOS transistor 302 is connected to institute
The output end of the second phase inverter and the input terminal of first phase inverter are stated, grid is connected to the write word line of memory, and drain electrode connects
Be connected to memory writes antiposition line；The source electrode of 5th NMOS tube 303 is connected to output end and the institute of first phase inverter
The input terminal of the second phase inverter is stated, grid is connected to the readout word line of memory, and drain electrode is connected to the sense bit line of memory；Described
The source electrode of six NMOS transistors 304 is connected to the output end of second phase inverter and the input terminal of first phase inverter, grid
Pole is connected to the readout word line of memory, and drain electrode is connected to the reading antiposition line of memory.
So far, the production of the SOI dual-port sram cell is completed.The system of SOI dual-port sram cell of the invention
Make method and do not introduce extra mask plate, completely compatible with existing logic process, uses centrosymmetric structure inside unit, not only have
Conducive to the size of metal-oxide-semiconductor and threshold voltage etc. matching, also help to form array, facilitate full custom sram chip, be suitable for pair
The occasions such as cellar area harshness, low-power consumption.
In conclusion forming four of the first phase inverter and the second phase inverter in SOI dual-port sram cell of the invention
Transistor is all made of L-type grid；For NMOS transistor, the bending angle lateral area of L-type grid is contacted equipped with a p-type heavy doping body
Area, the p-type heavy doping body contact zone have contact with each other with the body area of NMOS transistor where it and N-type heavy doping source region；It is right
It is equipped with a N-type heavy doping body contact zone in the bending angle lateral area of PMOS transistor, L-type grid, the p-type heavy doping body connects
Touching area has contact with each other with the body area of PMOS transistor where it and p-type heavy doping source region.The present invention can sacrifice smaller list
(final effective cellar area is smaller than 4 μm in the case where elemental area2) effectively inhibit PD SOI device in floater effect with
And leakage power consumption and transistor threshold voltage drift that parasitic triode effect causes, improve the noise resisting ability of unit.And
The production method of SOI dual-port sram cell of the invention does not introduce extra mask plate, list completely compatible with existing logic process
It is first internal using centrosymmetric structure, the matching such as size and threshold voltage of metal-oxide-semiconductor is not only contributed to, also helps to form battle array
Column, facilitate full custom sram chip.So the present invention effectively overcomes various shortcoming in the prior art and has high industrial benefit
With value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (17)
1. a kind of SOI dual-port sram cell, the SOI dual-port sram cell include:
First phase inverter is made of the first PMOS transistor and the first NMOS transistor；
Second phase inverter is made of the second PMOS transistor and the second NMOS transistor；
Pipe is obtained, by third NMOS transistor, the 4th NMOS transistor, the 5th NMOS transistor and the 6th NMOS transistor group
At；
Wherein, the source electrode of the third NMOS tube be connected to first phase inverter output end and second phase inverter it is defeated
Enter end, grid is connected to the write word line of memory, and drain electrode is connected to the write bit line of memory；
The source electrode of 4th NMOS transistor be connected to second phase inverter output end and first phase inverter it is defeated
Enter end, grid is connected to the write word line of memory, and what drain electrode was connected to memory writes antiposition line；
The source electrode of 5th NMOS tube is connected to the output end of first phase inverter and the input terminal of second phase inverter,
Grid is connected to the readout word line of memory, and drain electrode is connected to the sense bit line of memory；
The source electrode of 6th NMOS transistor be connected to second phase inverter output end and first phase inverter it is defeated
Enter end, grid is connected to the readout word line of memory, and drain electrode is connected to the reading antiposition line of memory；
It is characterized by:
First, second PMOS transistor and the first, second NMOS transistor are all made of L-type grid；For NMOS transistor,
The bending angle lateral area of L-type grid is equipped with a p-type heavy doping body contact zone, the p-type heavy doping body contact zone and its place
The body area of NMOS transistor and N-type heavy doping source region have contact with each other；For PMOS transistor, the bending angle outside of L-type grid
Region is equipped with a N-type heavy doping body contact zone, the N-type heavy doping body contact zone and the body area of PMOS transistor and P where it
Type heavy doping source region has contact with each other；So that the effective cellar area of the SOI dual-port sram cell finally is less than 4 μm2。
2. SOI dual-port sram cell according to claim 1, it is characterised in that: the N-type heavy doping source region and described
P-type heavy doping body contact zone top is formed with metal silicide.
3. SOI dual-port sram cell according to claim 1, it is characterised in that: the p-type heavy doping source region and described
N-type heavy doping body contact zone top is formed with metal silicide.
4. SOI dual-port sram cell according to claim 2 or 3, it is characterised in that: the metal silicide is selected from silicon
Change any one in cobalt and titanium silicide.
5. SOI dual-port sram cell according to claim 1, it is characterised in that: the SOI dual-port sram cell is adopted
With the SOI substrate for from bottom to top successively including backing bottom, insulating buried layer and top layer silicon, pass through between active area where each transistor
It is isolated up and down through the fleet plough groove isolation structure of the top layer silicon.
6. SOI dual-port sram cell according to claim 1, it is characterised in that: the third, the four, the five, the 6th
At least one in NMOS transistor uses L-type grid NMOS tube.
7. SOI dual-port sram cell according to claim 1, it is characterised in that: the third, the four, the five, the 6th
At least one in NMOS transistor uses common grid NMOS tube, T-type grid NMOS tube or H-type grid NMOS tube.
8. a kind of production method of SOI dual-port sram cell, which comprises the steps of:
S1: one is provided from bottom to top successively including the SOI substrate at backing bottom, insulating buried layer and top layer silicon, in the top layer silicon
Fleet plough groove isolation structure is made, active area is defined；
S2: the position according to the active area makes N trap, the first p-well and the second p-well in the top layer silicon, wherein the N
Trap is between first p-well and the second p-well；
S3: the first PMOS transistor and the second PMOS transistor are made in the N trap；First is made in first p-well
NMOS transistor, third NMOS transistor and the 5th NMOS transistor；Made in second p-well the second NMOS transistor,
4th NMOS transistor and the 6th NMOS transistor；Wherein, first, second PMOS transistor and the first, second NMOS are brilliant
Body pipe is all made of L-type grid；For NMOS transistor, the bending angle lateral area of L-type grid is contacted equipped with a p-type heavy doping body
Area, the p-type heavy doping body contact zone have contact with each other with the body area of NMOS transistor where it and N-type heavy doping source region；It is right
It is equipped with a N-type heavy doping body contact zone in the bending angle lateral area of PMOS transistor, L-type grid, the N-type heavy doping body connects
Touching area has contact with each other with the body area of PMOS transistor where it and p-type heavy doping source region；So that the SOI dual-port SRAM is mono-
First final effective cellar area is less than 4 μm2；
S4: production metallic vias and respective metal line, to complete the production of the sram cell.
9. the production method of SOI dual-port sram cell according to claim 8, it is characterised in that: the step S3 packet
Include step:
S3-1: forming the first grid across first p-well and the N trap and crosses over the second gate of the N trap and the second p-well
Pole, and third grid is formed in the first p-well predeterminated position, the 4th grid is formed in the second p-well predeterminated position；It is described
First grid is shared by first NMOS transistor and first PMOS transistor, and the first grid is respectively in institute
Stating has a bending part at the first NMOS transistor and first PMOS transistor position；The second grid is described second
NMOS transistor and second PMOS transistor share, and the second grid respectively in second NMOS transistor and
There is a bending part at second PMOS transistor position；
S3-2: carrying out N-type in the first, second p-well predeterminated position and be lightly doped, formed it is described first, second, third, fourth,
The shallow n-type area of 5th and the 6th NMOS transistor；P-type is carried out in the N trap predeterminated position to be lightly doped, formed it is described first, the
The shallow p type island region of two PMOS transistors；
S3-3: side wall isolation structure is formed around first, second, third, fourth grid；
S3-4: N-type heavy doping is carried out in the N trap predeterminated position, forms the N-type of first, second PMOS transistor
Heavy doping body contact zone；P-type heavy doping is carried out in the first, second p-well predeterminated position, it is brilliant to form first and second NMOS
The p-type heavy doping body contact zone of body pipe.
10. the production method of SOI dual-port sram cell according to claim 9, it is characterised in that: use ion implanting
Method forms the N-type heavy doping body contact zone and the p-type heavy doping body contact zone.
11. the production method of SOI dual-port sram cell according to claim 10, it is characterised in that: the ion note
The concentration range entered is 1E15-9E15/cm2。
12. the production method of SOI dual-port sram cell according to claim 9, it is characterised in that: in the step
Further include carrying out N-type heavy doping in the first, second p-well predeterminated position in S3-4, forms described first and second, third, the
Four, the step of N-type heavy-doped source drain region of the five, the 6th NMOS transistors, and p-type weight is carried out in the N trap predeterminated position
The step of doping, the p-type heavy-doped source drain region of formation first, second PMOS transistor.
13. the production method of SOI dual-port sram cell according to claim 12, it is characterised in that: described first
The drain electrode of NMOS transistor is shared with the source electrode of the third NMOS transistor；The drain electrode of second NMOS transistor with it is described
The source electrode of 4th NMOS transistor shares.
14. the production method of SOI dual-port sram cell according to claim 8, it is characterised in that: in the step S3
In, it further include in the p-type heavy doping source region, N-type heavy doping body contact zone and the N-type heavy doping source region, p-type heavy doping body
The step of metal silicide, is formed at contact zone top.
15. the production method of SOI dual-port sram cell according to claim 14, it is characterised in that: by the P
Metal is formed in type heavy doping source region, N-type heavy doping body contact zone and the N-type heavy doping source region, p-type heavy doping body contact zone
Layer, and being heat-treated reacts the metal layer with the Si material under it, generates the metal silicide.
16. the production method of SOI dual-port sram cell according to claim 15, it is characterised in that: the heat treatment
Temperature range be 700-900 DEG C, the time be 50-70 seconds.
17. the production method of SOI dual-port sram cell according to claim 8, it is characterised in that: the first NMOS
Transistor and first PMOS transistor are interconnected and form the first phase inverter；Second NMOS transistor and the 2nd PMOS
Transistor interconnection forms the second phase inverter；The source electrode of the third NMOS tube is connected to output end and the institute of first phase inverter
The input terminal of the second phase inverter is stated, grid is connected to the write word line of memory, and drain electrode is connected to the write bit line of memory；Described
The source electrode of four NMOS transistors is connected to the output end of second phase inverter and the input terminal of first phase inverter, and grid connects
It is connected to the write word line of memory, what drain electrode was connected to memory writes antiposition line；The source electrode of 5th NMOS tube is connected to described
The input terminal of the output end of first phase inverter and second phase inverter, grid are connected to the readout word line of memory, drain electrode connection
To the sense bit line of memory；The source electrode of 6th NMOS transistor is connected to the output end and described of second phase inverter
The input terminal of one phase inverter, grid are connected to the readout word line of memory, and drain electrode is connected to the reading antiposition line of memory.
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| CN108417573B (en) * | 2017-02-10 | 2020-11-03 | 中芯国际集成电路制造(上海)有限公司 | Static memory structure and forming method thereof |
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| CN101206918A (en) * | 2006-12-21 | 2008-06-25 | 松下电器产业株式会社 | Semiconductor memory device |
| CN101931008A (en) * | 2010-07-13 | 2010-12-29 | 中国科学院上海微系统与信息技术研究所 | PD SOI device with body contact structure |
| CN101989604A (en) * | 2009-07-31 | 2011-03-23 | 台湾积体电路制造股份有限公司 | Memory element |
| CN103325788A (en) * | 2013-06-18 | 2013-09-25 | 中国科学院上海微系统与信息技术研究所 | Eight-transistor static random access memory unit |
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| CN101206918A (en) * | 2006-12-21 | 2008-06-25 | 松下电器产业株式会社 | Semiconductor memory device |
| CN101989604A (en) * | 2009-07-31 | 2011-03-23 | 台湾积体电路制造股份有限公司 | Memory element |
| CN101931008A (en) * | 2010-07-13 | 2010-12-29 | 中国科学院上海微系统与信息技术研究所 | PD SOI device with body contact structure |
| CN103325788A (en) * | 2013-06-18 | 2013-09-25 | 中国科学院上海微系统与信息技术研究所 | Eight-transistor static random access memory unit |
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