CN108074930B

CN108074930B - Memory structure and forming method thereof, memory circuit and working method thereof

Info

Publication number: CN108074930B
Application number: CN201611011878.0A
Authority: CN
Inventors: 王楠
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-11-17
Filing date: 2016-11-17
Publication date: 2020-11-27
Anticipated expiration: 2036-11-17
Also published as: CN108074930A

Abstract

The invention provides a memory structure and a forming method thereof, a memory circuit and a working method thereof, wherein the memory structure comprises: a first pull-down transistor having a first channel width; a second pull-down transistor having a third channel width; a first transfer transistor having a second channel width; a second pass transistor having a fourth channel width; the fourth channel width is less than the third channel width; or the second channel width is less than the first channel width; or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width. The memory structure is capable of increasing the static noise capacity of the memory.

Description

Memory structure and forming method thereof, memory circuit and working method thereof

Technical Field

The invention relates to the technical field of semiconductor manufacturing, in particular to a memory structure and a forming method thereof, a memory circuit and a working method thereof.

Background

With the development of information technology, the amount of stored information has increased dramatically. The increase in the amount of stored information has promoted the rapid development of memories, and also has made higher demands on the stability of memories.

A basic Static Random Access Memory (SRAM) relies on six transistors that form two cross-coupled inverters. Each inverter includes: one pull-up transistor, one pull-down transistor, and one access transistor.

In order to obtain sufficient anti-interference capability and read stability, most of the transistors used for forming the memory are Fin-Field-Effect transistors (finfets). In the FinFET transistor, the gate is a 3D structure covering three surfaces of the fin, which can greatly improve circuit control. The application of the FinFET in the memory can improve the data storage stability and the integration level of the memory.

The static noise capacity of the static memory is a main index for measuring the static noise interference resistance of the static memory. The static noise capacity of a static memory is related to the beta ratio of the static memory, which refers to the ratio of the saturation current of the pull-down transistor to the saturation current of the pull-up transistor of the static memory. The saturation current of the transistor is related to the width-length ratio of the transistor, the width-length ratio of the transistor is the ratio of the width of a channel of the transistor to the length of the channel, and the larger the width-length ratio of the transistor is, the larger the saturation current of the transistor is. It can be seen that the ratio of the aspect ratios of the pull-down transistors and the pass transistors can affect the static noise capacity of the static memory.

However, the memory formed by the prior art still has the defects of small reading noise capacity and poor reading stability.

Disclosure of Invention

The invention provides a memory structure and a forming method thereof, a memory circuit and a working method thereof, so as to improve static noise capacity.

To solve the above problems, the present invention provides a memory structure, comprising: a substrate, the substrate comprising: a first pull-down area, a second pull-down area, a first transmission area and a second transmission area; a first pull-down transistor located in a first pull-down region of a substrate, the first pull-down transistor having a first channel width, the first pull-down transistor comprising: the first pull-down gate structure is positioned on the substrate, and the first pull-down source region and the first pull-down drain region are respectively positioned in the substrate on two sides of the first pull-down gate structure and are used for applying a first potential; a second pull-down transistor located in a second pull-down region of the substrate, the second pull-down transistor having a third channel width, the second pull-down transistor comprising: the second pull-down gate structure is positioned on the substrate, and the second pull-down source region and the second pull-down drain region are respectively positioned in the substrate at two sides of the second pull-down gate structure; a first transfer transistor on the first transfer region substrate, the first transfer transistor having a second channel width, the first transfer transistor comprising: the first transmission grid structure is positioned on the substrate, and the first transmission source region and the first transmission drain region are positioned in the substrate on two sides of the first transmission grid structure, and the first transmission source region is electrically connected with the first pull-down drain region; a second pass transistor on a second pass region substrate, the second pass transistor having a fourth channel width, the second pass transistor comprising: a second transfer gate structure on the substrate; the second transmission source region and the second transmission drain region are positioned in the substrate on two sides of the second transmission gate structure, and the second transmission source region is electrically connected with the second pull-down drain region; the fourth channel width is less than the third channel width; or the second channel width is less than the first channel width; or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width; a word line connecting the first transfer gate structure and the second transfer gate structure; a first bit line connected to the first transfer drain region; and a second bit line connected to the second transfer drain region.

Optionally, the first transmission region substrate has a first transmission fin portion, the first transmission gate structure crosses over the first transmission fin portion, and the first transmission source region and the first transmission drain region are respectively located in the first transmission fin portions on two sides of the first transmission gate structure; the second transmission region substrate is provided with a second transmission fin part, the second transmission grid electrode structure stretches across the second transmission fin part, and the second transmission source region and the second transmission drain region are respectively positioned in the second transmission fin parts on two sides of the second transmission grid electrode structure; the first pull-down region substrate comprises a first pull-down fin portion, the first pull-down gate structure stretches across the first pull-down fin portion and is located on partial side wall and top surface of the first pull-down fin portion, and the first pull-down source region and the first pull-down drain region are respectively located in the first pull-down fin portions on two sides of the first pull-down gate structure; the second pull-down region substrate comprises a second pull-down fin portion, the second pull-down gate structure stretches across the second pull-down fin portion and is located on the partial side wall and the top surface of the second pull-down fin portion, and the second pull-down source region and the second pull-down drain region are located in the second pull-down fin portions on two sides of the second pull-down gate structure respectively.

Optionally, the substrate further comprises a first connection region and a second connection region; the first connecting region, the first pull-down region and the first transmission region are in contact with each other, and the second connecting region, the second pull-down region and the second transmission region are in contact; the first connection region substrate includes a first connection fin portion connected with the first pull-down fin portion; the first transmission fin part is connected with the first pull-down fin part; the memory structure further comprises: a first connection gate structure crossing the first connection fin portion, the first connection gate structure being connected to the first transmission gate structure; a first connection source region and a first connection drain region in the first connection fin portion at both sides of the first connection gate structure, the first connection drain region being connected to the first pull-down drain region, the first connection source region not being in contact with the first bit line; the second connection region substrate comprises a second connection fin portion, and the second connection fin portion is connected with the second pull-down fin portion; the second transmission fin part is connected with the second pull-down fin part; the memory structure further comprises: a second connection gate structure crossing the second connection fin portion, the second connection gate structure being connected to the second transmission gate structure; and a second connection source region and a second connection drain region in the second connection fin part at two sides of the second connection gate structure, wherein the second connection drain region is connected with the second pull-down drain region, and the second connection source region is not in contact with the second bit line.

Optionally, the widths of the first pull-down fin portion, the second pull-down fin portion, the first transmission fin portion and the second transmission fin portion are the same, and the heights of the first pull-down fin portion, the second pull-down fin portion, the first transmission fin portion and the second transmission fin portion are the same; the number of the first pull-down fin portions is more than that of the first transmission fin portions, and the number of the second pull-down fin portions is more than that of the second transmission fin portions.

Optionally, the substrate further includes: a first pull-up region and a second pull-up region; the memory structure further comprises: a first pull-up transistor located in a first pull-up region of a substrate; the first pull-up transistor includes: a first pull-up gate structure on the substrate, the first pull-up gate structure being electrically connected to the first pull-down gate structure; the first pull-up drain region and the first pull-up source region are respectively positioned in the substrate on two sides of the first pull-up gate structure, the first pull-up source region is electrically connected with the first pull-down drain region, the first pull-up drain region is used for applying a second potential, and the second potential is greater than the first potential; a second pull-up transistor located in a second pull-up region of the substrate, the second pull-up transistor comprising: the second upper pull-up gate structure is positioned on the substrate and is electrically connected with the second lower pull-down gate structure; and the second pull-up source region and the second pull-up drain region are respectively positioned in the substrates at two sides of the second pull-up gate structure, the second pull-up drain region is electrically connected with the second pull-down drain region, and the second pull-up source region is used for applying the second potential.

Optionally, the substrate includes at least: a first or second split zone; the first shunt area substrate is provided with a first shunt structure, the first shunt structure comprises a first connecting part and a second connecting part, and the first connecting part is used for applying the first potential; the second connecting part is electrically connected with the first bit line, or the memory further comprises a third bit line, and the second connecting part is connected with the third bit line; the second shunt area substrate is provided with a second shunt structure, the second shunt structure comprises a third connecting part and a fourth connecting part, and the third connecting part is used for applying the first potential; the fourth connection portion is electrically connected to the second bit line, or the memory further includes a fourth bit line, and the fourth connection portion is connected to the fourth bit line.

Optionally, the first shunting structure includes: a first shunt transistor comprising a first shunt gate structure on the first shunt region substrate, the first shunt gate structure electrically connected with the first pull-down gate structure; the first shunt source region and the first shunt drain region are respectively positioned in the first shunt area substrates on two sides of the first shunt gate structure, and the first connecting part comprises the first shunt source region; a second shunt transistor, the second shunt transistor comprising: a second shunt gate structure on the second shunt area substrate, the second shunt gate structure electrically connected to the second transfer gate structure; a second shunt source region and a second shunt drain region in the substrate of the second shunt region on two sides of the second shunt gate structure, wherein the second connection portion comprises the second shunt drain region; a first source-drain connection line connecting the second shunt source region and the first shunt drain region; the second shunting structure comprises: a third shunt transistor, the third shunt transistor comprising: a third shunt gate structure located on the third shunt area substrate, the third shunt gate structure being electrically connected to the second pull-down gate structure; a third shunt source region and a third shunt drain region which are respectively positioned in the substrate of the second shunt region at two sides of the third shunt gate structure, wherein the third connecting part comprises the third shunt source region; a fourth shunt transistor, the fourth shunt transistor comprising: a fourth shunt gate structure located on the second shunt area substrate, the fourth shunt gate structure being electrically connected to the second pull-down gate structure; a fourth shunt source region and a fourth shunt drain region which are respectively positioned in the substrate of the second shunt region at two sides of the fourth shunt gate structure, wherein the fourth connecting part comprises the fourth shunt drain region; and the second source-drain connecting line is connected with the fourth shunt source region and the third drain source region.

Accordingly, the present invention also provides a method of forming a memory structure, comprising: providing a substrate, the substrate comprising: a first pull-down area, a second pull-down area, a first transmission area and a second transmission area; forming a first pull-down transistor at the substrate first pull-down region, the first pull-down transistor having a first channel width, the step of forming the first pull-down transistor comprising: forming a first pull-down gate structure on the substrate; respectively forming a first pull-down source region and a first pull-down drain region in the substrate at two sides of the first pull-down gate structure, wherein the first pull-down source region is used for applying a first potential; forming a first transfer transistor on the first transfer region substrate, the first transfer transistor having a second channel width, the forming the first transfer transistor comprising: forming a first transmission grid structure on the substrate, and respectively forming a first transmission source region and a first transmission drain region in the substrate at two sides of the first transmission grid structure, wherein the first transmission source region is electrically connected with the first pull-down drain region; forming a second pull-down transistor in a second pull-down region of the substrate, the second pull-down transistor having a third channel width, the step of forming the second pull-down transistor comprising: forming a second pull-down gate structure on the substrate, and respectively forming a second pull-down source region and a second pull-down drain region in the substrate at two sides of the second pull-down gate structure, wherein the second pull-down gate structure is electrically connected with the first pull-down drain region, the second pull-down drain region is electrically connected with the first pull-down gate structure, and the second pull-down source region is used for applying the first potential; forming a second pass transistor on the second pass region substrate, the second pass transistor having a fourth channel width, the forming the second pass transistor comprising: forming a second transmission grid structure on the substrate, and respectively forming a second transmission source region and a second transmission drain region in the substrate at two sides of the second transmission grid structure, wherein the second transmission source region is electrically connected with the second pull-down drain region; the fourth channel width is less than the third channel width; or the second channel width is less than the first channel width; or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width; forming a word line connecting the first transfer gate structure and the second transfer gate structure after forming the first transfer transistor and the second transfer transistor; forming a first bit line connected to the first transfer drain region; and forming a second bit line connected with the second transmission drain region.

The present invention also provides a memory structure comprising: a substrate including a storage region, a first transfer region, a second transfer region, and a diversion region; the storage structure is positioned in the substrate storage area and comprises a first connecting part, a second connecting part and a grounding part, and the grounding part is used for applying a first potential; a first pass transistor located in the first pass region of the substrate, the first pass transistor comprising: the first transmission grid structure is positioned on the first transmission area substrate, and the first transmission drain area and the first transmission source area are respectively positioned in the substrates at two sides of the first transmission grid structure; a first bit line electrically connected to the first transfer drain region; the second transmission transistor is positioned in a second transmission region of the substrate, the second transmission transistor is positioned on a second transmission grid structure on the substrate of the second transmission region, and a second transmission drain region and a second transmission source region are respectively positioned in the substrate at two sides of the second transmission grid structure, and the second transmission source region is electrically connected with the second connecting part; a word line electrically connected to the first and second transfer gate structures; a second bit line electrically connected to the second transfer drain region; the shunt area at least comprises a first shunt area or a second shunt area, the substrate first shunt area is provided with a first shunt structure, and the first shunt structure comprises: the first shunt input part is used for applying a preset potential, and the first shunt output part is electrically connected with the grounding part; the substrate second shunt region has a second shunt structure comprising: a second shunt input portion for applying the preset potential, and a second shunt output portion electrically connected to the ground portion.

Optionally, the first shunt input is electrically connected to the first bit line; the second shunt input is electrically connected to the second bit line.

Optionally, the method further includes: a third bit line connected to the first shunt input; a fourth bit line connected to the fourth input.

Optionally, the storage area includes: a first pull-down region and a second pull-down region, the memory structure comprising: a first pull-down transistor located in a first pull-down region of the substrate, the first pull-down transistor comprising: a first pull-down gate structure located on the first pull-down region substrate; a first pull-down source region and a first pull-down drain region respectively located in the substrate at two sides of the first pull-down gate structure, the first connection portion including the first pull-down drain region, the ground portion including: the first pull-down source region; a second pull-down transistor located in a second pull-down region of the substrate, the second pull-down transistor comprising: a second pull-down gate structure on the second pull-down region substrate, the second pull-down gate structure being electrically connected to the first pull-down drain region; and the second pull-down source region and the second pull-down drain region are respectively positioned in the substrates at two sides of the second pull-down gate structure, the second pull-down drain region is electrically connected with the first pull-down gate structure, the second connecting part comprises the second pull-down drain region, and the grounding part comprises the second pull-down source region.

Optionally, the first pull-down transistor has a first channel width, the first pass transistor has a second channel width, the second pull-down transistor has a third channel width, and the second pass transistor has a fourth channel width; the fourth channel width is less than the third channel width; or the second channel width is less than the first channel width; or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width.

Optionally, the first transmission region substrate includes a first transmission fin portion, the first transmission gate structure crosses over the first transmission fin portion, the first transmission gate structure is located on a partial sidewall and a top surface of the first transmission fin portion, and the first transmission source region and the first transmission drain region are respectively located in the first transmission fin portions on two sides of the first transmission gate structure; the second transmission region substrate comprises a second transmission fin part, the second transmission gate structure crosses the second transmission fin part, the second transmission gate structure is located on the partial side wall and the top surface of the second transmission fin part, and the second transmission source region and the second transmission drain region are respectively located in the second transmission fin parts on two sides of the second transmission gate structure; the first pull-down region substrate comprises a first pull-down fin portion, the first pull-down gate structure stretches across the first pull-down fin portion, the first pull-down gate structure is located on partial side wall and top surface of the first pull-down fin portion, and the first pull-down source region and the first pull-down drain region are respectively located in the first pull-down fin portions on two sides of the first pull-down gate structure; the second pull-down region substrate comprises a second pull-down fin portion, the second pull-down gate structure crosses over the second pull-down fin portion, the second pull-down gate structure is located on the partial side wall and the top surface of the second pull-down fin portion, and the second pull-down source region and the second pull-down drain region are respectively located in the second pull-down fin portions on two sides of the second pull-down gate structure; the widths of the first pull-down fin portion, the second pull-down fin portion, the first transmission fin portion and the second transmission fin portion are the same, and the heights of the first pull-down fin portion, the second pull-down fin portion, the first transmission fin portion and the second transmission fin portion are the same; the number of the first pull-down fin portions is more than that of the first transmission fin portions, and the number of the second pull-down fin portions is more than that of the second transmission fin portions.

Optionally, the storage area further includes a first pull-up area and a second pull-up area; the memory structure further comprises: a first pull-up load located at a first pull-up region of the substrate, the first pull-up load comprising: a first load input portion for inputting a second potential, the second potential being greater than the first potential; a first load output portion electrically connected to the first pull-down transistor drain region; a second pull-up load located at a second pull-up region of the substrate, the second pull-up load comprising: a second load input section for inputting the second potential; a second load output portion electrically connected with the second pull-down transistor drain region.

Optionally, the first pull-up load includes a first pull-up transistor, and the first pull-up transistor includes: a first pull-up gate structure on the substrate, the first pull-up gate structure being electrically connected to the first pull-down gate structure; the first pull-up drain region and the first pull-up source region are positioned in the substrate on two sides of the first pull-up gate structure, the first load output part comprises the first pull-up source region, and the first load input part comprises the first pull-up drain region; the second load comprises a second pull-up transistor comprising: a second pull-up gate structure on the substrate, the second pull-up gate structure being electrically connected to the second pull-down gate structure; a second pull-up source region and a second pull-up drain region respectively located in the substrate at two sides of the second pull-up gate structure, the second load input portion includes the second pull-up drain region, and the second load output portion includes the second pull-up source region; or, the first pull-up load includes a first pull-up resistor, and the first pull-up resistor includes: a first pull-up doped region and a second pull-up doped region in the substrate, the first load input including the first pull-up doped region, the first load output including the second pull-up doped region; the second pull-up load includes a second pull-up resistor, and the second pull-up resistor includes: and the second load input part comprises the third pull-up doped region, and the second load output part comprises the fourth pull-up doped region.

Optionally, the first shunting structure includes: a first shunt transistor located in a first shunt region of a substrate, the first shunt transistor comprising: a first shunt gate structure located on the first shunt area substrate, the first shunt gate structure being electrically connected to the first pull-down gate structure; the first shunt output part comprises a first shunt source region and a first shunt drain region which are respectively positioned in the first shunt area substrates at two sides of the first shunt gate structure; the first shunting structure further comprises a second shunting transistor located in the first shunting region, the second shunting transistor comprising: a second shunt gate structure located on the first shunt area substrate, the second shunt gate structure electrically connected to the second transfer gate structure; the second shunt source region and the second shunt drain region are respectively positioned in the first shunt region substrate on two sides of the second shunt gate structure, the second shunt source region is electrically connected with the first shunt drain region, and the first shunt input part comprises the second shunt drain region; the second shunting structure comprises: the third shunt transistor is positioned in the substrate second shunt area, and the fourth shunt transistor is positioned in the substrate second shunt area; the third shunt transistor includes: a third shunt gate structure located on the second shunt area substrate, the third shunt gate structure being electrically connected to the second pull-down gate structure; a third shunt source region and a third shunt drain region which are respectively positioned in the substrate of the second shunt region at two sides of the third shunt gate structure, wherein the second shunt output part comprises the third shunt source region; the fourth shunt transistor includes: a fourth shunt gate structure located on the second shunt area substrate, the fourth shunt gate structure being electrically connected to the second transfer gate structure; and the fourth shunt source region and the fourth shunt drain region are respectively positioned in the substrates at two sides of the fourth shunt gate structure, the second shunt input part comprises the fourth shunt drain region, and the fourth shunt source region is electrically connected with the third shunt drain region.

Optionally, the method further includes: a first source line connecting the second shunt source region and the first pull-down source region; a second source line connecting the fourth shunt source region and the second pull-down source region.

Correspondingly, the invention also provides a forming method of the memory structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a storage area, a first transmission area, a second transmission area and a diversion area, and the diversion area at least comprises a first diversion area or a second diversion area; forming a storage structure on the substrate storage area, wherein the storage structure comprises a first connecting part and a second connecting part; forming a first transfer transistor in a first transfer region of the substrate, the step of forming the first transfer transistor comprising: forming a first transmission gate structure on the substrate, and forming a first transmission source region and a first transmission drain region in the substrate on two sides of the first transmission gate structure respectively, wherein the first transmission source region is electrically connected with the first connecting part; forming a second pass transistor in the substrate second pass region, the step of forming the second pass transistor comprising: forming a second transmission gate structure on the substrate, and forming a second transmission drain region and a second transmission source region in the substrate on two sides of the second transmission gate structure respectively, wherein the second transmission source region is electrically connected with the second connecting portion; forming a first shunting structure at the substrate first shunting region; or forming a second shunt structure in the substrate first shunt area; or forming a first shunt structure in the substrate first shunt area and forming a second shunt structure in the substrate first shunt area; the first shunting structure comprises: a first shunt input for inputting a preset potential and a first shunt output for applying a first potential; the second shunting structure comprises: a second shunt input portion for inputting the preset potential and a second shunt output portion for applying the first potential; forming a word line connecting the first transfer gate structure and the second transfer gate structure; forming a first bit line connected to the first transfer drain region; and forming a second bit line connected with the second transmission drain region.

In addition, the present invention also provides a memory circuit comprising: a storage unit, the storage unit comprising: the first connecting end, the second connecting end and the grounding end, wherein the grounding end is used for applying a first electric potential; a first transfer transistor, the first transfer transistor comprising: the first transmission grid, the first transmission source electrode and the first transmission drain electrode, wherein the first transmission source electrode is connected with the first connecting end; a first bit line connected to the first transmission drain; a second pass transistor, the second pass transistor comprising: the second transmission source electrode is connected with the second connecting end; a word line connecting the first and second transfer gates; a second bit line connected to the second transfer drain; the flow dividing unit at least comprises a first flow dividing unit or a second flow dividing unit; the first shunting unit includes: the first shunt output end is connected with the grounding end, and the first shunt input end is used for inputting a preset potential; the second flow dividing unit comprises: the second shunt output end is connected with the grounding end, and the second shunt input end is used for inputting the preset potential.

Optionally, the first shunt input is connected to the first bit line, and the second shunt input is connected to the second bit line.

Optionally, the first shunting unit includes: a first shunt transistor, the first shunt transistor comprising: a first shunt gate connected to the first pull-down gate; the first shunt source electrode is connected with the first shunt output end; the first shunting unit further includes a second shunting transistor, the second shunting transistor including: a second shunt gate connected to the first transfer gate; a second shunt source connected to the first shunt drain; a second shunt drain connected to the first shunt input terminal; the second flow dividing unit comprises: a third shunt transistor, the third shunt transistor comprising: a third shunt gate connected to the second pull-down gate; the third shunt source electrode is connected with the second shunt output end; a fourth shunt transistor, the fourth shunt transistor comprising: a fourth shunt gate connected with the second transfer gate; a fourth shunt source connected to the third shunt drain; a fourth shunt drain connected to the second shunt input.

Optionally, the method further includes: a third bit line connected to the first shunt input; a fourth bit line connected to the second shunt input.

Optionally, the first shunting unit includes: a first shunt transistor, the first shunt transistor comprising: a first shunt gate connected to the first pull-down gate; the first shunt source electrode is connected with the first shunt output end; the first shunt drain electrode is connected with the first shunt input end; the second flow dividing unit comprises: a third shunt transistor, the third shunt transistor comprising: a third shunt gate electrically connected to the second pull-down gate; a third shunt source connected to the second shunt output terminal; and the third shunt drain electrode is connected with the second shunt input end.

Optionally, the storage unit includes: a first pull-down transistor, the first pull-down transistor comprising: a first pull-down gate; a first pull-down drain connected to the first transmission source; a first pull-down source connected to the first potential; a second pull-down transistor, the second pull-down transistor comprising: a second pull-down gate connected to the first pull-down drain; a second pull-down source connected to the first shunt output terminal; a second pull-down drain connected to the first pull-down gate.

Optionally, the storage unit further includes: a first pull-up load, the first pull-up load comprising: a first load input terminal for inputting a second potential, the second potential being greater than the first potential; the first load output end is connected with the drain electrode of the first pull-down transistor; a second pull-up load, the second pull-up load comprising: a second load input terminal for inputting the second potential; and the second load output end is connected with the drain electrode of the second pull-down transistor.

Optionally, the first pull-up load includes a first pull-up transistor, and the first pull-up transistor includes: the first pull-up grid is connected with the first pull-down grid; the first pull-up drain is connected with the first load input end, and the first pull-up source is connected with the first load output end; the second pull-up load comprises a second pull-up transistor comprising: the second pull-up grid is connected with the second pull-down grid; the second pull-up drain is connected with the second load input end; the second pull-up drain is connected with the second load output end; alternatively, the first pull-up load includes a first resistor, and the first resistor includes: the first resistor input end is connected with the first load input end, and the first resistor output end is connected with the first load output end; the second pull-up load is a second resistor, and the second resistor includes: the second resistor input end is connected with the second load input end, and the second resistor output end is connected with the second load output end.

The invention also provides a working method of the memory circuit, which comprises the following steps: providing a memory circuit; applying a first potential to the ground terminal; applying a word line potential on the word line, the word line potential being greater than the first potential; applying an operating potential on the first bit line and the second bit line.

Optionally, the first shunting input terminal is connected to the first bit line; the second shunt input is connected to the second bit line; the step of applying an operating potential on the first bit line and the second bit line comprises: applying preset potentials on the first bit line and the second bit line, wherein the preset potentials interact with a storage unit to form a reading signal; the working method further comprises the following steps: acquiring the read signal through the first word line and the second bit line; the step of acquiring the read signal through the first word line and the second bit line includes: applying a preset potential to the first bit line and the second bit line, wherein the preset potential is greater than the first potential, and the preset potential acts with the memory cell to form a read signal; the read signal is acquired on the third bit line and the fourth bit line.

Optionally, the memory circuit includes: a first shunting unit and a second shunting unit; the memory circuit further comprises: a third bit line connected to the first shunt input terminal; a fourth bit line connected to the second shunt input terminal; the step of applying an operating potential on the first bit line and the second bit line comprises: applying a storage potential on the first bit line and the second bit line to form a storage signal in the memory cell; after forming a storage signal in the memory cell, the operating method further includes: applying a preset potential to the third bit line and the fourth bit line, wherein the preset potential is greater than the first potential, and the preset potential acts with the memory cell to form a read signal; the read signal is acquired on the third bit line and the fourth bit line.

Optionally, the storage unit further includes: a first pull-up load, the first pull-up load comprising: the first load output end is connected with the drain region of the first pull-down transistor; a second pull-up load, the second pull-up load comprising: the second load output end is connected with the drain region of the second pull-down transistor; before applying an operating potential on the first bit line and the second bit line, the operating method further comprises: applying a second potential to the first load input and the second load input, the second potential being greater than the first potential.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the static storage structure provided by the technical scheme of the invention, the width of the second channel is smaller than that of the first channel; or the fourth channel width is less than the third channel width; or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width.

When the second channel width is smaller than the first channel width, the width-to-length ratio of the first transmission transistor is smaller than the width-to-length ratio of the first pull-down transistor, so that the saturation current of the first transmission transistor is smaller than the saturation current of the first pull-down transistor, the ratio of the saturation current of the first pull-down transistor to the saturation current of the first transmission transistor can be increased, and the interference of static noise on a first bit line to the memory structure is reduced.

When the fourth channel width is smaller than the third channel width, the width-to-length ratio of the second transmission transistor is smaller than the width-to-length ratio of the second pull-down transistor, so that the saturation current of the second transmission transistor is smaller than the saturation current of the second pull-down transistor, the ratio of the saturation current of the second pull-down transistor to the saturation current of the second transmission transistor can be increased, and the interference of static noise on a second bit line to the memory structure can be reduced.

When the second channel width is smaller than the first channel width and the fourth channel width is smaller than the third channel width, the width-to-length ratio of the first pass transistor is smaller than the width-to-length ratio of the first pull-down transistor, the width-to-length ratio of the second pass transistor is smaller than the width-to-length ratio of the second pull-down transistor, and further the saturation current of the first pass transistor is smaller than the saturation current of the first pull-down transistor, and the saturation current of the second pass transistor is smaller than the saturation current of the second pull-down transistor, and further the ratio between the saturation current of the first pull-down transistor and the saturation current of the first pass transistor is increased, and the ratio between the saturation current of the second pull-down transistor and the saturation current of the second pass transistor is increased, so that the static noise capacity of the memory can be increased, the interference of static noise to the memory structure is reduced.

Further, the memory structure includes a first shunting structure and a second shunting structure. In the application process of the memory, if the potential at the joint of the first pull-down drain region and the first transmission drain region is low level "0", the first shunt structure is turned on, so that the first bit line can be connected with the first potential, the first potential can be pulled down by the first shunt structure, the potential at the joint of the first pull-down drain region and the first transmission drain region can be prevented from being raised by the potential at the first bit line, and the potential at the joint of the first pull-down drain region and the first transmission drain region can be prevented from being inverted by the potential at the first bit line, so that the interference of static noise on the memory structure can be reduced, and the static noise capacity of the memory structure can be increased.

If the potential at the joint of the second pull-down drain region and the second transmission drain region is low level 0, the second shunt structure is conducted, so that the second bit line can be connected with the second potential, the second potential can be pulled down by the second shunt structure, the potential at the joint of the second pull-down drain region and the second transmission drain region is prevented from being raised by the potential at the second bit line, and the potential at the joint of the second pull-down drain region and the second transmission drain region can be prevented from being inverted by the potential at the second bit line. Therefore, the shunt structure can reduce the interference of static noise to the memory structure and increase the static noise capacity of the memory structure.

In the method for forming the memory provided by the technical scheme of the invention, the width of the fourth channel is smaller than that of the third channel; or the second channel width is less than the first channel width; or the second channel width is smaller than the first channel width, and the fourth channel width is smaller than the third channel width, so that the static noise capacity of the formed memory structure can be increased, and the interference of static noise on the memory structure can be reduced.

In the memory structure provided by the technical scheme of the invention, the memory structure at least comprises a first shunt structure and a second shunt structure. The memory applies a preset potential, which is a high level "1", to the first shunt input portion in a read operation.

When the memory structure comprises a first shunt structure, if the potential of the first connecting part is low level 0, the first shunt structure is conducted, so that the first connecting part is connected with the grounding part. The grounding part can pull down the preset potential through the first shunt structure, so that the influence of the preset voltage on the potential of the first connecting part is reduced, the potential of the first connecting part is prevented from being reversed, and therefore the first shunt structure can reduce the interference of static noise on the first shunt input part on the memory structure.

When the memory structure comprises a second shunt structure, if the potential of the second connecting part is low level 0, the second shunt structure is conducted, so that the second connecting part is connected with the grounding part. The grounding part can pull down the preset potential through the second shunt structure, so that the influence of the preset voltage on the potential of the second connecting part is reduced, the potential of the second connecting part is prevented from being reversed, and the interference of static noise on the second shunt input part on the memory structure can be reduced.

When the memory structure comprises a first shunt structure and a second shunt structure, if the potential of the first connecting part is low level '0' and the potential of the second connecting part is high level '1', the first shunt structure is conducted, and the first shunt structure can reduce the interference of static noise on the first shunt input part to the memory structure; if the potential of the second connection part is low level '0' and the potential of the first connection part is high level '1', the second shunt structure is conducted, and the second shunt structure can reduce the interference of static noise on the second shunt input part to the memory structure. Therefore, the shunt structure can reduce the interference of static noise to the memory and increase the static noise capacity of the memory.

Further, the first shunt input is connected to the first bit line, and the second shunt input is connected to the second bit line. During the reading process of the memory, a preset potential needs to be applied to the first bit line and the second bit line, and the preset potential is a high level "1". If the potential of the first connecting portion is low level "0", and the potential of the second connecting portion is high level "1", the first shunting structure is conducted, and the first bit line is connected with the grounding portion through the first shunting structure, so that the potential of the grounding portion can be pulled down by a preset potential on the first bit line through the first shunting structure, the potential of the first connecting portion is prevented from being raised by the preset potential, the potential of the first connecting portion is prevented from being inverted, and therefore the shunting structure can reduce the interference of static noise on a memory. Similarly, if the potential of the second connection portion is low level "0", and the potential of the first connection portion is high level "1", the second shunting structure is turned on, and the second bit line is connected with the second potential through the second shunting structure, so that the potential of the ground connection portion can pull down the preset potential on the second bit line through the second shunting structure, and further the preset potential is prevented from raising the potential of the second connection portion, and the potential of the second connection portion is prevented from being inverted, and therefore, the shunting structure can reduce the interference of static noise to the memory.

Further, the memory structure further comprises: a third bit line connected to the first shunt input; a fourth bit line connected to the second shunt input. During a read operation of the memory, a preset potential is applied to the third bit line and the fourth bit line. If the potential of the first connecting part is low level '0' and the potential of the second connecting part is high level '1', the first shunt structure is conducted, and the third bit line is connected with the grounding part through the first shunt structure, so that the preset potential is not applied to the first connecting part, the potential of the first connecting part is not raised, the potential of the first connecting part can be prevented from being reversed, and the interference of static noise on the static storage structure can be reduced; if the potential of the second connecting portion is low level '0' and the potential of the first connecting portion is high level '1', the second shunt structure is conducted, and the fourth bit line is connected with the grounding portion through the second shunt structure, so that the preset potential is not applied to the second connecting portion, the potential of the second connecting portion is not raised, and the potential of the second connecting portion can be prevented from being reversed. Therefore, the preset potential is not applied to the first connecting portion and the second connecting portion, so that the preset potential can be prevented from interfering with the potentials of the first connecting portion and the second connecting portion, reading errors are not easy to occur, and therefore the static noise capacity of the memory structure can be increased.

In the method for forming the memory structure provided by the technical scheme of the invention, the memory structure at least comprises a first shunt structure and a second shunt structure, and the memory circuit at least comprises a first shunt unit and a second shunt unit. The first shunt unit can reduce the interference of static noise on the first shunt input end to the memory circuit; the second shunt unit can reduce the interference of static noise on the second shunt input end to the memory circuit, so that the forming method can reduce the interference of the static noise to the memory structure and increase the static noise capacity of the memory structure.

In the memory circuit provided by the technical scheme of the invention, the memory circuit at least comprises a first shunt unit and a second shunt unit. The first shunt unit can reduce the interference of static noise on the first shunt input end to the memory circuit; the second shunt unit can reduce the interference of static noise on the second shunt input end to the memory circuit. It follows that static noise is less disturbing to the memory circuitry, and the static noise capacity of the memory is greater.

In the operating method of the memory circuit provided by the technical scheme of the invention, the memory circuit at least comprises a first shunt unit and a second shunt unit. The first shunt unit can reduce the interference of static noise on the first shunt input end to the memory circuit; the second shunt unit can reduce the interference of static noise on the second shunt input end to the memory circuit. It can be seen that static noise has less interference with the memory circuit, and the static noise capacity of the memory circuit is greater.

Drawings

FIG. 1 is a schematic diagram of a static memory structure;

FIGS. 2 to 5 are schematic structural diagrams illustrating steps of a method for forming a memory structure according to an embodiment of the present invention;

FIGS. 6-10 are schematic structural diagrams illustrating steps of another embodiment of a method for forming a memory structure according to the present invention;

FIG. 11 is a circuit schematic of one embodiment of a memory circuit of the present invention;

FIG. 12 is a circuit schematic of another embodiment of a memory circuit of the present invention.

Detailed Description

The prior art memory structure has many problems, such as a static memory with a small static noise capacity and a poor interference resistance.

The existing memory combined with the prior art analyzes the reasons that the memory has small static noise capacity and poor anti-interference capability:

FIG. 1 is a schematic diagram of a static memory structure.

Referring to fig. 1, the static memory includes: two mirror-symmetrical inverters; the inverter includes: a substrate 100, the substrate 100 comprising: a transmission area 1, a pull-down area 2 and a pull-up area 3; the fin parts 101 are positioned on the substrates of the transmission region 1, the pull-down region 2 and the pull-up region 3, the fin parts 101 of the transmission region 1, the pull-down region 2 and the pull-up region 3 are mutually identical, and the fin parts 101 of the transmission region 1 and the pull-down region 2 are mutually connected; a gate structure 110 crossing the fin 101, wherein the gate structure 110 covers part of the sidewall and the top surface of the fin 101; a source region and a drain region respectively located in the fin portions 101 on two sides of the gate structure 110; a source line connected to the source region; a drain line connected with the drain region, a source line of the transmission region 1, a drain line of the pull-down region 2 and a source line of the pull-up region 3 are connected with each other to form a storage node 10, and a bit line 11 connected with the drain line of the transmission region 1; a gate line 130 connected to the gate structure 110.

During the reading operation of the static memory, a preset potential is applied to the bit line 11, the preset potential is a high level "1", since the static memory has two mirror-symmetric inverters, the static memory includes two storage nodes 10, and the potentials of the two storage nodes 10 are opposite, that is, the potential of one of the two storage nodes 10 is a low level "0", and the storage node 10 with the potential of the low level "0" is a low level node. When a preset potential is applied to the bit line 11 of the transmission area 1 connected to the low-level node, the preset potential easily raises the potential value of the low-level node, so that the potential of the low-level node is easily inverted, and thus an error occurs in a read result. Therefore, the noise capacity of the static memory is low.

To solve the above technical problem, the present invention provides a memory structure, comprising: a substrate, the substrate comprising: a first pull-down area, a second pull-down area, a first transmission area and a second transmission area; a first pull-down transistor located in a first pull-down region of a substrate, the first pull-down transistor having a first channel width, the first pull-down transistor comprising: the first pull-down source region and the first pull-down drain region are respectively positioned in the substrate at two sides of the first pull-down gate structure, and the first pull-down source region is used for being connected with a first potential; a second pull-down transistor located in a second pull-down region of the substrate, the second pull-down transistor having a third channel width, the second pull-down transistor comprising: the second pull-down gate structure is positioned on the substrate, and the second pull-down source region and the second pull-down drain region are respectively positioned in the substrate at two sides of the second pull-down gate structure; a first transfer transistor on the first transfer region substrate, the first transfer transistor having a second channel width, the first transfer transistor comprising: the first transmission grid structure is positioned on the substrate, and the first transmission source region and the first transmission drain region are positioned in the substrate on two sides of the first transmission grid structure and are electrically connected with the first pull-down drain region; a second pass transistor on a second pass region substrate, the second pass transistor having a fourth channel width, the second pass transistor comprising: a second transfer gate structure on the substrate; the second transmission source region and the second transmission drain region are positioned in the substrate on two sides of the second transmission gate structure, and the second transmission source region is electrically connected with the second pull-down drain region; the fourth channel width is less than the third channel width; or the second channel width is less than the first channel width; or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width; a word line connecting the first transfer gate structure and the second transfer gate structure; a first bit line connected to the first transfer drain region; and a second bit line connected to the second transfer drain region.

The static noise capacity of the memory is increased, and the interference of the static noise to the memory structure is small.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 to 5 are schematic structural diagrams of steps of a memory forming method according to an embodiment of the invention.

Referring to fig. 2, a substrate is provided, the substrate comprising: a first pull-down region 212, a second pull-down region 222, a first transmission region 211, and a second transmission region 221.

The first transmission region 211 is a region for forming a first transmission transistor; the first pull-down region 212 is a region subsequently used to form a first pull-down transistor; the second transfer region 221 is a region for forming a second transfer transistor later; the second pull-down region 222 is a region that is subsequently used to form a second pull-down transistor.

In this embodiment, the memory is a static memory, and the substrate is used to form the static memory.

In this embodiment, the substrate further includes: a first pull-up region 213 and a second pull-up region 223. In other embodiments, the substrate may also not include the first pull-up region and the second pull-up region.

The first pull-up region 213 is subsequently used to form a first pull-up load and the second pull-up region 223 is subsequently used to form a second pull-up load. In other embodiments, the substrate may also not include the first and second pull-up regions.

In this embodiment, the substrate includes: a substrate 200 and a fin 201 on the substrate 200 and located on the first transmission region 211, the first pull-down region 212, the first pull-up region 213, the second transmission region 221, the second pull-down region 222, and the first pull-up region 213.

In this embodiment, the fin 201 includes: a first transmission fin portion on the substrate 200 of the first transmission region 211; a second transfer fin portion on the substrate of the second transfer region 221; a first pull-down fin portion on the substrate 200 in the first pull-down region 212; a second pull-down fin portion located on the base 200 of the second pull-down region 222; a first pull-up fin portion on the substrate 200 in the first pull-up region 213; second pull-up fins on the substrate 200 in the second pull-up region 223.

In this embodiment, the first transmission fin portion and the first pull-down fin portion have the same extending direction, and the first transmission fin portion is connected to the first pull-down fin portion. In other embodiments, the first transmission fin and the first pull-down fin may not be connected to each other.

In this embodiment, the second transmission fin portion and the second pull-down fin portion extend in the same direction, and the second transmission fin portion is connected to the second pull-down fin portion. In other embodiments, the second transmitting fin and the second pull-down fin may not be connected to each other.

It should be noted that, in this embodiment, the first channel width is a sum of the number of the first pull-down fin portions multiplied by a width of the first pull-down fin portion and twice a height of the first pull-down fin portion; the second channel width is the sum of the number of the second transmission fin parts multiplied by the width of the second transmission fin parts and twice the height of the second transmission fin parts; the third channel width is the number of the second pull-down fin portions multiplied by the sum of the width of the second pull-down fin portions and twice the height of the second pull-down fin portions. The fourth channel width is the sum of the number of the first transmission fin portions multiplied by the width of the first transmission fin portions and twice the height of the first transmission fin portions.

In other embodiments, the substrate is a planar substrate, the first channel width is a width of the first pull-down source region along an extending direction of the first pull-down gate structure, the second channel width is a width of the first transmission source region along the extending direction of the first transmission gate structure, the third channel width is a width of the second pull-down source region along the extending direction of the second pull-down gate structure, and the fourth channel width is a width of the second transmission source region along the extending direction of the second transmission gate structure.

In this embodiment, the substrate 200 further includes a first connection region 214 and a second connection region 224. In other embodiments, the substrate may also not include the first and second connection regions.

In this embodiment, the first connection region 214, the first pull-down region 212 and the first transmission region 211 are in contact with each other, and the second connection region 224, the second pull-down region 222 and the second transmission region 221 are in contact with each other.

In this embodiment, the first connection region 214 substrate further includes a first connection fin portion, the first connection fin portion and the first pull-down fin portion extend in the same direction, and the first connection fin portion is connected to the first pull-down fin portion.

In this embodiment, the substrate 200 of the second connection region 224 includes a second connection fin portion, the extending direction of the second connection fin portion is the same as that of the second pull-down fin portion, and the second connection fin portion is connected to the second pull-down fin portion.

In this embodiment, the widths of the fins 201 are the same. In other embodiments, the widths of the fins may also be different.

In this embodiment, the heights of the fins 201 are the same. In other embodiments, the heights of the fins may also be different.

In this embodiment, the number of the first transmission fin portions is smaller than the number of the first pull-down fin portions, and the number of the second transmission fin portions is smaller than the number of the second pull-down fin portions. In other embodiments, the number of the first transmission fins is less than the number of the first pull-down fins, or the number of the second transmission fins is less than the number of the second pull-down fins. As can be seen, in the present embodiment, the first channel width is greater than the second channel width, and the third channel width is greater than the fourth channel width.

Specifically, in this embodiment, the number of the first transmission fin portions is 1, the number of the first pull-down fin portions is 2, and the number of the first pull-up fin portions is 1; the number of the second transmission fin parts is 1, the number of the second pull-down fin parts is 2, and the number of the second pull-up fin parts is 1. In other embodiments, the numbers of the first transmission fin portion, the first pull-down fin portion, the first pull-up fin portion, the second transmission fin portion, the second pull-down fin portion, and the second pull-up fin portion may also be other values.

In this embodiment, the number of the first connection fin portions and the second connection fin portions is 1. In other embodiments, the number of the first connection fin portion and the second connection fin portion may also be other values.

In this embodiment, the step of forming the substrate includes: providing an initial substrate; patterning the initial substrate to form a base 200, a first transmission fin portion located on the base 200 of the first transmission region 211, a first pull-down fin portion located on the base 200 of the first pull-down region 212, a second transmission fin portion located on the base 200 of the second transmission region 221, and a second pull-down fin portion located on the base 200 of the second pull-down region 222.

In this embodiment, the substrate 200 and the fin 201 are made of the same material. Specifically, the material of the substrate 200 and the fin 201 is silicon. In other embodiments, the material of the substrate and the fin portion may also be germanium or silicon germanium.

In other embodiments, the substrate may also be a planar substrate. The substrate can be a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, etc.

In this embodiment, after the substrate is formed, the forming method further includes: isolation structures (not shown) are formed on the substrate 200 between the fins 201, and the isolation structures cover part of the sidewalls and the top surface of the fins 201.

The isolation structure is used to achieve electrical isolation between different fins 201.

In this embodiment, the isolation structure is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon oxynitride.

Subsequently forming a first pull-down transistor in the substrate first pull-down region 212, the first pull-down transistor having a first channel width, the step of forming the first pull-down transistor comprising: forming a first pull-down gate structure on the first pull-down region 212 substrate; respectively forming a first pull-down source region and a first pull-down drain region in the substrates at two sides of the first pull-down gate structure, wherein the first pull-down source region is used for applying a first potential;

forming a first transfer transistor on the first transfer region 211 substrate, the first transfer transistor having a second channel width, the forming the first transfer transistor comprising: forming a first transmission gate structure on the substrate; forming a first transmission source region and a first transmission drain region in the substrate on two sides of the first transmission gate structure, wherein the first transmission source region is electrically connected with the first pull-down drain region;

forming a second pull-down transistor in the substrate second pull-down region 222, the second pull-down transistor having a third channel width, the step of forming the second pull-down transistor comprising: forming a second pull-down gate structure on the second pull-down region 222 substrate; respectively forming a second pull-down source region and a second pull-down drain region in the substrate on two sides of the second pull-down gate structure, wherein the second pull-down gate structure is electrically connected with the first pull-down drain region, the second pull-down drain region is electrically connected with the first pull-down gate structure, and the second pull-down source region is used for applying a first potential;

Forming a second transfer transistor on the second transfer region 221 substrate, the forming of the second transfer transistor including: forming a second transmission gate structure on the substrate; forming a second transmission source region and a second transmission drain region in the substrate on two sides of the second transmission gate structure respectively, wherein the second transmission source region is electrically connected with the second pull-down drain region, and the second transmission transistor has a fourth channel width;

the fourth channel width is less than the third channel width; or the second channel width is less than the first channel width; or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width.

In this embodiment, the substrate further includes a first pull-up region 213 and a second pull-up region 223. The first pull-up load is a first pull-up transistor, and the second pull-up load is a second pull-up transistor. In other embodiments, the first pull-up load may further include a resistor, and the second pull-up load may further include a resistor.

In this embodiment, the forming method further includes: forming a first pull-up transistor at a first pull-up region 213 of the substrate, the first pull-up transistor comprising: the first pull-up gate structure is positioned on the substrate of the first pull-up region 213, and the first pull-up drain region and the first pull-up source region are respectively positioned in the substrate at two sides of the first pull-up gate structure; forming a second pull-up transistor at a second pull-up region 223 of the substrate, the second pull-up transistor comprising: and the second pull-up gate structure is positioned on the second pull-up region 223 substrate, and the second pull-up source region and the second pull-up drain region are respectively positioned in the substrates at two sides of the second pull-up gate structure.

In this embodiment, the steps of forming the first pass transistor, the second pass transistor, the first pull-down transistor and the second pull-down transistor are shown in fig. 3 and 4.

Referring to fig. 3, a gate structure 240 is formed across the fin 201, covering a portion of the sidewalls and the top surface of the fin 201.

The step of forming the gate structure 240 across the fin 201 includes: forming a first pull-down gate structure crossing the first pull-down fin portion, the first pull-down gate structure covering a portion of a sidewall and a top surface of the first pull-down fin portion; forming a first transmission grid electrode structure crossing the first transmission fin part, wherein the first transmission grid electrode structure covers partial side wall and the top surface of the first transmission fin part; forming a second pull-down gate structure crossing the second pull-down fin portion, wherein the second pull-down gate structure covers part of the side wall and the top surface of the second pull-down fin portion; and forming a second transmission gate structure crossing the second transmission fin part, wherein the second transmission gate structure covers partial side wall and the top surface of the second transmission fin part.

In this embodiment, the substrate 200 further includes: a first pull-up region 213 and a second pull-up region 223. The gate structure 240 further includes: a first pull-up gate structure spanning the first pull-up fin portion, the first pull-up gate structure being located on a portion of a sidewall and a top surface of the first pull-up fin portion; and the second pull-up gate structure crosses over the second pull-up fin part and is positioned on the partial side wall and the top surface of the second pull-up fin part.

In this embodiment, the step of forming the gate structure 240 further includes: forming a first pull-up gate structure crossing the first pull-up fin portion, the first pull-up gate structure covering a portion of a sidewall and a top surface of the first pull-up fin portion; and forming a second pull-up gate structure crossing the second pull-up fin portion, wherein the second pull-up gate structure covers part of the side wall and the top surface of the second pull-up fin portion.

In this embodiment, the substrate 200 further includes: first attachment region 214 and second attachment region 224. The gate structure 240 further includes: a first connection gate structure crossing the first connection fin, the first connection gate structure covering a portion of a sidewall and a top surface of the first connection fin; and the second connection grid structure crosses the second connection fin part and covers partial side wall and the top surface of the second connection fin part. In other embodiments, the substrate does not include the first and second connection regions, the fin does not include the first and second connection fins, and the gate structure may also not include the first and second connection gate structures.

In this embodiment, the step of forming the gate structure 240 further includes: forming a first connection gate structure crossing the first connection fin portion, wherein the first connection gate structure is located on partial side wall and top surface of the first connection fin portion; and forming a second connection gate structure crossing the second connection fin part, wherein the second connection gate structure is positioned on the partial side wall and the top surface of the second connection fin part.

In this embodiment, the first pull-up gate structure, the second pull-up gate structure, the first pull-down gate junction, the second pull-down gate structure, the first transmission gate structure, the second transmission gate structure, the first connection gate structure, and the second connection gate structure extend in the same direction. In other embodiments, the extending directions of the first pull-up gate structure, the second pull-up gate structure, the first pull-down gate junction, the second pull-down gate structure, the first transfer gate structure, and the second transfer gate structure may be different.

In this embodiment, the first pull-down gate structure is in contact with the first pull-up gate structure, so as to realize the electrical connection between the first pull-down gate structure and the first pull-up gate structure; the second pull-down gate structure is in contact with the second pull-up gate structure, so that the second pull-down gate structure is electrically connected with the second pull-up gate structure. In other embodiments, the first pull-down gate structure and the first pull-up gate structure may also be not in contact, and the first pull-down gate structure and the first pull-up gate structure are electrically connected through a conductive structure; the second pull-down gate structure and the second pull-up gate structure may also be non-contact, and the second pull-down gate structure and the second pull-up gate structure are electrically connected through a conductive structure.

In this embodiment, the first connection gate structure and the first pull-down gate structure extend in the same direction, and the first connection gate structure is in contact with the first pull-down gate structure.

In this embodiment, the second connection gate structure and the second connection gate structure extend in the same direction, and the second connection gate structure is in contact with the second connection gate structure.

Referring to fig. 4, doped regions 202 are formed in the fin 201 at two sides of the gate structure 240.

The doped regions 202 are used to form the source and drain regions of the transistor.

In this embodiment, the doped region 202 is formed in the fin 201 on both sides of the gate structure 240 by ion implantation. In other embodiments, the doped region may also be formed by an epitaxial growth process.

In this embodiment, the first transmission region 211 is used to form an NMOS transistor, that is, the first transmission transistor is an NMOS transistor; the first pull-down region 212 is used to form an NMOS transistor, i.e., the first pull-down transistor is an NMOS transistor; the first pull-up region 213 is used to form a PMOS transistor, and the first pull-up transistor is a PMOS transistor; the second transmission region 221 is used for forming an NMOS transistor, that is, the second transmission transistor is an NMOS transistor; the second pull-down region 222 is used to form an NMOS transistor, i.e., the second pull-down transistor is an NMOS transistor; the second pull-up region 223 is used to form a PMOS transistor, and the second pull-up transistor is a PMOS transistor. In other embodiments, the first and second pull-up regions may also be used to form a resistor.

In this embodiment, the doped region 202 includes: the first transmission source region and the first transmission drain region are respectively positioned in the first transmission fin parts at two sides of the first transmission gate structure; a first pull-down source region and a first pull-down drain region in the first pull-down fin part at two sides of the first pull-down gate structure; the first pull-up drain region and the first pull-up source region are positioned in the first pull-up fin parts on two sides of the first pull-up gate structure; a second transfer source region and a second transfer drain region respectively located in the second transfer fin portions at both sides of the second transfer gate structure; the second pull-down source region and the second pull-down drain region are positioned in the second pull-down fin parts on two sides of the second pull-down gate structure; and the second pull-up source region and the first pull-up source region are positioned in the second pull-up fin parts on two sides of the second pull-up gate structure.

In this embodiment, the doped region 202 further includes: and the first connecting source region and the first connecting drain region are positioned in the first connecting fin parts at two sides of the first connecting grid structure, the first connecting drain region is connected with the first pull-down drain region, and the first connecting source region is not connected with a first bit line formed subsequently.

In this embodiment, the doped region 202 further includes: and a second connection source region and a second connection drain region in second connection fin parts positioned at two sides of the second connection gate structure, wherein the second connection drain region is connected with a second pull-down drain region in the second connection fin parts, and the second connection source region is not connected with a subsequently formed second bit line.

In this embodiment, the step of forming the doped region 202 includes: forming a first photoresist covering the first pull-up fin portion, the top of the second pull-up fin portion and the surface of the side wall; performing first ion implantation on the first pull-down fin portion, the first transmission fin portion, the second pull-down fin portion and the second transmission fin portion by taking the first photoresist as a mask to form a first transmission source region, a first transmission drain region, a first pull-down source region, a second transmission drain region, a second pull-down drain region and a second pull-down source region; after the first ion implantation, forming second photoresist covering the top and the side wall surfaces of the first transmission fin part, the first pull-down fin part, the second transmission fin part and the second pull-down fin part; and performing second ion implantation on the first pull-up fin portion and the second pull-up fin portion by taking the second photoresist as a mask to form a first pull-up drain region, a first pull-up source region, a second pull-up source region and a second pull-up drain region.

In this embodiment, the first ion implantation implants first doped ions in the first transmission source region, the first transmission drain region, the first pull-down source region, the second transmission drain region, the second pull-down drain region, and the second pull-down source region. The first dopant ions are N-type ions, such as phosphorous ions or arsenic ions.

In this embodiment, the second ion implantation implants second doped ions in the first pull-up drain region, the first pull-up source region, the second pull-up source region and the second pull-up drain region, and the second doped ions are P-type ions, such as boron ions or BF ions^2-Ions.

In this embodiment, the step of forming the doped region 202 further includes: forming a first connection source region and a first connection drain region in the first connection fin portion at both sides of the first connection gate structure by the first ion implantation, the first connection drain region being connected to the first pull-down drain region; and forming a second connection source region and a second connection drain region in the second connection fin parts at two sides of the second connection gate structure through the second ion implantation, wherein the second connection drain region is connected with the second pull-down drain region. In other embodiments, the first connection drain region, the first connection source region, the second connection drain region, and the second connection source region may not be formed.

In this embodiment, the first transmission source region and the first pull-down drain region are in contact with each other to form a first common doped region, and the second transmission source region and the second pull-down drain region are in contact with each other to form a second common doped region.

Referring to fig. 5, a word line 230 connecting the first transfer gate structure and the second transfer gate structure is formed; forming a first bit line 251 connecting the first transfer drain region; a second bit line 252 connecting the second transfer drain region is formed.

In this embodiment, the first connection source region is not connected to the first bit line, and the second connection source region is not connected to the second bit line.

The word line 230 is used for controlling the on and off of the first and second pass transistors; the first bit line 251 and the second bit line 252 are used to read data in the formed memory and write data into the memory.

In this embodiment, the forming method further includes: forming a first connection line 271 connecting the first common doped region, the first pull-down drain region, and the first pull-up source region; a second connection line 272 connecting the second common doped region, the second pull-down drain region, and the second pull-up source region is formed.

The first connection line 271 is used for electrically connecting a first pull-down drain region, a first transmission source region and the first pull-up source region; the second connection line 272 is used to electrically connect the second pull-down drain region, the second transfer source region, and the second pull-up source region.

In this embodiment, the forming method further includes: forming a first pull down source line 231 connecting the first pull down source region, the first pull down source line 231 being used for applying a first potential to the first pull down source region; a second pull-down source line 232 connected to the second pull-down source region, the second pull-down source line 232 being configured to apply the first potential to the second pull-down source region.

In this embodiment, the first potential is zero potential, and the first pull-down source line 231 and the second pull-down source line 232 are used for grounding.

In this embodiment, the forming method further includes: forming a first pull-up drain line 281 connecting the first pull-up drain region, the first pull-up drain line 281 being configured to apply a second potential to the first pull-up drain region, the second potential being greater than the first potential; a second pull-up drain line 282 is formed connecting the second pull-up source region, the second pull-up drain line 282 being for applying the second potential to the second pull-up source region.

In this embodiment, the forming method further includes: forming a first gate line 261 connecting the first connection line 271 and the second pull-up gate structure, wherein the first gate line 261 is used for electrically connecting the second pull-up gate structure and the first pull-down drain region; forming a second gate line 262 connecting the second connection line 272 and the first pull-up gate structure, wherein the second gate line 262 is used for electrically connecting the first pull-up gate structure and the second pull-down drain region.

In this embodiment, the first bit line 251 is used to connect to the first transfer drain region. The transistor connected to the first bit line 251 is a first transfer transistor. The fin 201 of the first transfer transistor is formed as a first transfer fin, and the region where the first transfer fin is located is a first transfer region 211. Therefore, the sum of the width and the height of the first transfer fin multiplied by the number of the first transfer fins determines the second channel width of the formed first transfer transistor.

In this embodiment, the fin 201 forming the first pull-down transistor is a first pull-down fin, and the region where the first pull-down fin is located is a first pull-down region 212. Therefore, the sum of the width and the height of the first pull-down fin portions multiplied by the number of the first pull-down fin portions determines the first channel width of the formed first transfer transistor.

In this embodiment, the first pull-down fin portion and the first transmission fin portion have the same width, and the first pull-down fin portion and the first transmission fin portion have the same height. The number of the first pull-down fin portions is more than that of the first transmission fin portions. Therefore, the second channel width is smaller than the first channel width.

In this embodiment, the second bit line 252 is used to connect to the second transfer drain region. The transistor connected to the second bit line 252 is a second pass transistor. The fin 201 forming the second transfer transistor is a second transfer fin, and a region where the second transfer fin is located is a second transfer region 221. The sum of the width and the height of the second transfer fins multiplied by the number of the second transfer fins determines a fourth channel width of the formed second transfer transistor.

In this embodiment, the fin 201 where the second pull-down transistor is formed is a second pull-down fin, and the region where the second pull-down fin is located is a second pull-down region 222. The sum of the width and the height of the second pull-down fin portions multiplied by the number of the second pull-down fin portions determines a third channel width of the formed second pull-down transistor.

In this embodiment, the second pull-down fin portion and the second transmission fin portion have the same width, and the second pull-down fin portion and the second transmission fin portion have the same height. The number of the second pull-down fin portions is more than that of the second transmission fin portions. Therefore, the fourth channel width is smaller than the third channel width.

In this embodiment, the first pull-down transistor and the second pull-down transistor are pull-down transistors, and the first transmission transistor and the second transmission transistor are transmission transistors.

In this embodiment, the memory is a static memory.

Since the static noise capacity of the static memory is related to the beta ratio of the static memory, the static noise capacity of the static memory is larger when the beta ratio is larger, and the static noise capacity of the static memory is smaller when the beta ratio is smaller. The beta ratio is the ratio between the pull-down transistor and the pass transistor saturation current.

The saturation current of the pull-down transistor is related to the size of the pull-down transistor and the saturation current of the pass transistor is related to the size of the pass transistor. Specifically, the transistor saturation current has the following relationship with the transistor size.

Where k is the scaling factor, W is the width of the transistor, L is the length of the transistor, V_GSIs a gate-source potential, V_thIs the threshold potential of the transistor.

It can be seen that the saturation current of a transistor has a direct relationship to the aspect ratio of the transistor. The larger the width-to-length ratio of the transistor, the larger the saturation current of the transistor.

In this embodiment, the second channel width of the first pass transistor is smaller than the first channel width of the first pull-down transistor, so as to increase the ratio of the saturation currents of the first pull-down transistor and the first pass transistor, thereby increasing the static noise capacity of the memory.

Meanwhile, in this embodiment, the ratio of the saturation current of the second pull-down transistor to the saturation current of the second pass transistor is increased by making the fourth channel width of the second pass transistor smaller than the third channel width of the second pull-down transistor, so as to further increase the static noise capacity of the memory.

In summary, in the method for forming a memory according to the embodiment of the present invention, the width of the fourth channel is smaller than the width of the third channel; or the second channel width is less than the first channel width; or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width.

When the second channel width is less than the first channel width and the fourth channel width is less than the third channel width, the width-to-length ratio of the first pass transistor can be made smaller than the width-to-length ratio of the first pull-down transistor, the width-to-length ratio of the second pass transistor is made smaller than the width-to-length ratio of the second pull-down transistor, such that the saturation current of the first pass transistor is less than the saturation current of the first pull-down transistor, the saturation current of the second pass transistor is less than the saturation current of the second pull-down transistor, thereby increasing the ratio of the first pull-down transistor saturation current to the first pass transistor saturation current, the ratio of the second pull-down transistor saturation current to the second pass transistor saturation current, therefore, the static noise capacity of the memory can be increased, and the interference of static noise on a memory structure can be reduced.

With continued reference to FIG. 5, the present invention also provides an embodiment of a memory structure comprising:

a substrate, the substrate comprising: a first pull-down region 212, a second pull-down region 222, a first transmission region 211, and a second transmission region 221;

a first pull-down transistor located in the substrate first pull-down region 212, the first pull-down transistor having a first channel width, the first pull-down transistor comprising: a first pull-down gate structure located on the first pull-down region 212 substrate; a first pull-down source region and a first pull-down drain region in the substrate of the first pull-down region 212 respectively located at two sides of the first pull-down gate structure, the first pull-down source region being used for applying a first potential;

a second pull-down transistor located in the substrate second pull-down region 222, the second pull-down transistor having a third channel width, the second pull-down transistor comprising: a second pull-down gate structure on the second pull-down region 222 substrate; a second pull-down source region and a second pull-down drain region in the substrate respectively located at two sides of the second pull-down gate structure, the second pull-down gate structure being electrically connected to the first pull-down drain region, the second pull-down drain region being electrically connected to the first pull-down gate structure, the second pull-down source region being configured to apply a first potential;

A first transfer transistor on the first transfer region 211 substrate, the first transfer transistor having a second channel width, the first transfer transistor comprising: a first transfer gate structure on the substrate of the first transfer region 211; a first transmission source region and a first transmission drain region in the first transmission region 211 substrate respectively located at two sides of the first transmission gate structure, the first transmission source region being electrically connected to the first pull-down drain region;

a second pass transistor on the second pass region 221 substrate, the second pass transistor comprising: a second transfer gate structure on the second transfer region 221 substrate; a second transfer source region and a second transfer drain region in the substrate of the second transfer region 221 located at two sides of the second transfer gate structure, the second transfer source region being electrically connected to the second pull-down drain region, the second transfer transistor having a fourth channel width;

the fourth channel width is less than the third channel width;

or the second channel width is smaller than the first channel width, and the fourth channel width is smaller than the third channel width;

A word line 230 connecting the first transfer gate structure and the second transfer structure;

a first bit line 251 connecting the first transfer drain regions;

a second bit line 252 connecting the second transfer drain region.

The first pull-down region 212 is a region for forming a first pull-down transistor, the second pull-down region 222 is a region for forming a second pull-down transistor, the first transfer region 211 is a region for forming a first transfer transistor, and the second transfer region 221 is a region for forming a second transfer transistor.

In this embodiment, the substrate further includes: a first pull-up region 213 and a second pull-up region 223. The first pull-up region 213 is used to form a first pull-up load and the second pull-up region 223 is subsequently used to form a second pull-up load. In other embodiments, the substrate may also not include the first and second pull-up regions.

In this embodiment, the first transmission region 211 is in contact with the first pull-down region 212, and the first transmission fin portion is connected to a portion of the first pull-down fin portion; the second transmission region 221 is in contact with the second pull-down region 222, and the second transmission fin portion is connected to a portion of the second pull-down fin portion.

In this embodiment, the extending directions of the fins 201 are the same.

In this embodiment, the memory further includes: isolation structures (not shown) on the substrate 200 between the fins 201, the isolation structures covering portions of the sidewalls and top surfaces of the fins 201.

In this embodiment, the first transmission gate structure crosses over the first transmission fin, and the first transmission gate structure covers a part of the sidewall and the top surface of the first transmission fin; the first transmission source region and the first transmission drain region are respectively located in the first transmission fin parts on two sides of the first transmission gate structure.

In this embodiment, the first pull-down gate structure crosses over the first pull-down fin portion, and the first pull-down gate structure covers a part of a sidewall and a top surface of the first pull-down fin portion; the first pull-down source region and the first pull-down drain region are respectively located in the first pull-down fin portions on two sides of the first pull-down gate structure.

In this embodiment, the second transmission gate structure crosses over the second transmission fin portion, and the second transmission gate structure covers a part of a sidewall and a top surface of the second transmission fin portion; the second transfer source region and the second transfer drain region are respectively located in the second transfer fin portions on two sides of the second transfer gate structure.

In this embodiment, the second pull-down gate structure crosses over the second pull-down fin portion, and the second pull-down gate structure covers a part of a sidewall and a top surface of the second pull-down fin portion; the second pull-down source region and the second pull-down drain region are respectively located in second pull-down fin portions on two sides of the second pull-down gate structure.

In this embodiment, the substrate further includes a first pull-up region 213 and a second pull-up region 223. The memory further includes a first pull-up load located at the substrate first pull-up region 213 and a second pull-up load located at the substrate second pull-up region 223. In other implementations, the memory may also not include the first pull-up load and the second pull-up load.

In this embodiment, the first pull-up load includes a first pull-up transistor, and the second pull-up load includes a second pull-up transistor. In other implementations, the first pull-up load and the second pull-up load may further include resistors.

In this embodiment, the first pull-up transistor includes: the first pull-up gate structure is positioned on the substrate of the first pull-up region 213, and the first pull-up drain region and the first pull-up source region are respectively positioned in the substrate at two sides of the first pull-up gate structure; the second pull-up transistor includes: and the second pull-up gate structure is positioned on the second pull-up region 223 substrate, and the second pull-up source region and the second pull-up drain region are respectively positioned in the substrates at two sides of the second pull-up gate structure.

In this embodiment, the first pull-up gate structure crosses over the first pull-up fin portion, and the first pull-up gate structure covers a part of a sidewall and a top surface of the first pull-up fin portion; the second pull-up source region and the second pull-up drain region are respectively located in the second pull-up fin portions on two sides of the second pull-up gate structure.

In this embodiment, the second pull-up gate structure crosses over the second pull-up fin portion, and the second pull-up gate structure covers a part of a sidewall and a top surface of the second pull-up fin portion; the first pull-up drain region and the first pull-up source region are respectively located in the first pull-up fin portions on two sides of the first pull-up gate structure.

In this embodiment, the first pull-up gate structure, the second pull-up gate structure, the first pull-down gate junction, the second pull-down gate structure, the first transmission gate structure, and the second transmission gate structure extend in the same direction. In other embodiments, the extending directions of the first pull-up gate structure, the second pull-up gate structure, the first pull-down gate junction, the second pull-down gate structure, the first transfer gate structure, and the second transfer gate structure may be different.

In this embodiment, the first pull-down gate structure is connected to the first pull-up gate structure, so as to realize the electrical connection between the first pull-down gate structure and the first pull-up gate structure; the second pull-down gate structure is connected with the second pull-up gate structure, so that the second pull-down gate structure is electrically connected with the second pull-up gate structure. In other embodiments, the first pull-down gate structure and the first pull-up gate structure may also be unconnected, and the first pull-down gate structure and the first pull-up gate structure are connected through a conductive structure; the second pull-down gate structure and the second pull-up gate structure may also be unconnected, and the second pull-down gate structure and the second pull-up gate structure are connected by a conductive structure.

In this embodiment, the gate structure 240 includes: the first upper-pull gate structure, the second upper-pull gate structure, the first lower-pull gate structure, the second lower-pull gate structure, the first transmission gate structure, the second transmission gate structure, the first connection gate structure and the second connection gate structure.

In this embodiment, the first transmission source region, the first transmission drain region, the first pull-down source region, the second transmission drain region, the second pull-down drain region, and the second pull-down source region are doped with the first dopant ions. The first dopant ions are N-type ions, such as phosphorous ions or arsenic ions.

In this embodiment, the first pull-up drain region, the first pull-up source region, the second pull-up source region and the second pull-up drain region have second doped ions therein, and the second doped ions are P-type ions, such as boron ions or BF^2-Ions.

In this embodiment, the doped region 202 further includes: and the first connecting source region and the first connecting drain region are positioned in the first connecting fin parts at two sides of the first connecting grid structure, the first connecting drain region is connected with the first pull-down drain region, and the first connecting source region is not connected with a first bit line formed subsequently. The first connecting source region and the first connecting drain region have the first doping ions therein.

In this embodiment, the doped region 202 further includes: and a second connection source region and a second connection drain region in second connection fin parts positioned at two sides of the second connection gate structure, wherein the second connection drain region is connected with a second pull-down drain region in the second connection fin parts, and the second connection source region is not connected with a subsequently formed second bit line. The second connecting source region and the second connecting drain region are provided with the first doping ions.

In this embodiment, a portion of the first pull-down drain region and the first transmission source region are connected to form a first common doped region, and a portion of the second pull-down drain region and the second transmission source region are connected to form a second common doped region.

In this embodiment, the doped region 202 includes: the first pull-up drain region, the first pull-up source region, the second pull-up drain region, the first connection source region, the first connection drain region, the second connection source region, and the second connection drain region.

In this embodiment, the memory further includes: a first connection line 271 connecting the first common doped region, the first pull-down drain region, and the first pull-up source region; a second connection line 272 connecting the second common doped region, the second pull-down drain region, and the second pull-up drain region.

In this embodiment, the memory further includes: a first pull down source line 231 connected to the first pull down source region, the first pull down source line 231 for applying a first potential to the first pull down source region; a second pull-down source line 232 connected to the second pull-down source region, the second pull-down source line 232 being configured to apply the first potential to the second pull-down source region.

In this embodiment, the first potential is zero potential, that is, the first pull-down source line 231 and the second pull-down source line 232 are used for grounding.

In this embodiment, the memory further includes: a first pull-up drain line 281 connecting the first pull-up drain region, the first pull-up drain line 281 being configured to apply a second potential to the first pull-up drain region, the second potential being greater than the first potential; a second pull-up drain line 282 coupled to the second pull-up drain region, the second pull-up drain line 282 for applying the second potential to the second pull-up drain region.

In this embodiment, the memory further includes: a first gate line 261 connecting the first connection line 271 and the second pull-up gate structure, wherein the first gate line 261 is used for electrically connecting the second pull-up gate structure and the first pull-down drain region; and a second gate line 262 connecting the second connection line 272 and the first pull-up gate structure, wherein the second gate line 262 is used for electrically connecting the first pull-up gate structure and the second pull-down drain region.

In this embodiment, the first bit line 251 is used to connect to the first transfer drain region. The transistor connected to the first bit line 251 is a first transfer transistor. The fin 201 of the first transfer transistor is formed as a first transfer fin, and the region where the first transfer fin is located is a first transfer region 211. The sum of the width and the height of the first transfer fins multiplied by the number of the first transfer fins determines a second channel width of the formed first transfer transistor.

In this embodiment, the second bit line 252 is used to connect to the second transfer drain region. The transistor connected to the second bit line 252 is a second pass transistor. The fin 201 forming the second transfer transistor is a second transfer fin, and a region where the second transfer fin is located is a second transfer region 221.

The sum of the width and the height of the second transfer fins multiplied by the number of the second transfer fins determines a fourth channel width of the formed second transfer transistor.

In this embodiment, the formed memory is a static memory.

It can be seen that the saturation current of a transistor has a direct relationship to the aspect ratio of the transistor. The larger the aspect ratio of the transistor, the larger the saturation current of the transistor.

In summary, in the memory structure provided in the embodiment of the present invention, the second channel width is smaller than the first channel width; or the fourth channel width is less than the third channel width; or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width.

When the second channel width is smaller than the first channel width, the width-to-length ratio of the first transmission transistor is smaller than the width-to-length ratio of the first pull-down transistor, so that the saturation current of the first transmission transistor is smaller than that of the first pull-down transistor, the ratio of the saturation current of the first pull-down transistor to that of the first transmission transistor can be increased, and the interference of static noise on a first bit line on the memory structure is reduced;

When the fourth channel width is smaller than the third channel width, the width-to-length ratio of the second transmission transistor is smaller than the width-to-length ratio of the second pull-down transistor, so that the saturation current of the second transmission transistor is smaller than the saturation current of the second pull-down transistor, the ratio of the saturation current of the second pull-down transistor to the saturation current of the second transmission transistor can be increased, and the interference of static noise on a second bit line on the memory structure can be reduced;

when the second channel width is smaller than the first channel width and the fourth channel width is smaller than the third channel width, the width-to-length ratio of the first pass transistor is smaller than the width-to-length ratio of the first pull-down transistor, the width-to-length ratio of the second pass transistor is smaller than the width-to-length ratio of the second pull-down transistor, so that the saturation current of the first pass transistor is smaller than the saturation current of the first pull-down transistor, the saturation current of the second pass transistor is smaller than the saturation current of the second pull-down transistor, the ratio between the saturation current of the first pull-down transistor and the saturation current of the first pass transistor is increased, the ratio between the saturation current of the second pull-down transistor and the saturation current of the second pass transistor is increased, and therefore, the static noise capacity of the memory is increased, the interference of static noise to the memory structure is reduced.

In order to improve the static noise capacity of the memory, an embodiment of the present invention further provides a memory circuit, including: a storage unit, the storage unit comprising: the first connecting end, the second connecting end and the grounding end, wherein the grounding end is used for applying a first electric potential; a first transfer transistor, the first transfer transistor comprising: the first transmission grid, the first transmission source electrode and the first transmission drain electrode, wherein the first transmission source electrode is connected with the first connecting end; a first bit line connected to the first transmission drain; a second pass transistor, the second pass transistor comprising: the second transmission source electrode is connected with the second connecting end; a first word line connecting the first and second transfer gates; a second bit line connected to the second transfer drain; the flow dividing unit at least comprises a first flow dividing unit or a second flow dividing unit; the first shunting unit includes: the first shunt output end is connected with the grounding end, and the first shunt input end is used for inputting a preset potential; the second flow dividing unit comprises: the second shunt output end is connected with the grounding end, and the second shunt input end is used for inputting the preset potential.

Wherein the memory circuit comprises at least a first shunting unit or a second shunting unit. In the using process of the memory, the shunt unit can form a path between an interference signal and the grounding terminal, so that the influence of the interference signal on data stored in the memory unit is reduced. Therefore, the shunt unit can reduce the interference of static noise to the memory and increase the static noise capacity of the memory.

Fig. 6 to 9 are schematic structural diagrams of steps of another embodiment of a memory forming method according to the present invention.

Referring to fig. 6, a substrate is provided, the substrate includes a storage region, a first transfer region 311, a second transfer region 321, and a shunting region, and the shunting region includes at least a first shunting region 314 or a second shunting region 324.

The storage area is used for forming a storage unit subsequently; the first transfer region 311 is a region for forming a first transfer transistor later, and the second transfer region 322 is a region for forming a second transfer transistor later; the flow splitting region is a region subsequently used for forming a first flow splitting structure and a second flow splitting structure.

In this embodiment, the storage area includes: a first pull-down region 312 and a second pull-down region 322.

The first pull-down region 312 is a region subsequently used to form a first pull-down transistor, the second pull-down region 322 is a region subsequently used to form a second pull-down transistor,

in this embodiment, the storage area further includes: a first pull-up region 313 and a second pull-up region 323. The first pull-up region 313 is used to form a first pull-up load and the second pull-up region 323 is subsequently used to form a second pull-up load. In other embodiments, the substrate may also not include the first and second pull-up regions.

In this embodiment, the shunting region includes: a first splitter section 314 and a second splitter section 324. The first splitter zone is subsequently used to form a first splitter structure and the second splitter zone is subsequently used to form a second splitter structure.

In this embodiment, the substrate includes: a substrate 300 and a fin 301 on the substrate 300.

In this embodiment, the fin 301 includes: a first transmission fin portion on the substrate 300 of the first transmission region 311; a second transmission fin portion on the base of the second transmission region 321; a first pull-down fin portion on the substrate 300 in the first pull-down region 312; a second pull-down fin portion located on the base 200 of the second pull-down region 322; a first pull-up fin portion on the substrate 300 in the first pull-up region 313; a second pull-up fin portion on the second pull-up region 323 substrate 300; a first shunting fin portion located on the substrate 200 of the first shunting region 314; and a second shunting fin portion located on the substrate 200 of the second shunting region 324.

In this embodiment, the widths of the fins 201 are the same, and the heights of the fins 201 are the same. In other embodiments, the widths of the fins may be different, and the heights of the fins may be different.

In this embodiment, the number of the first transmission fin portions is equal to the number of the first pull-down fin portions, and the number of the second transmission fin portions is equal to the number of the second pull-down fin portions. In other embodiments, the number of the first transmission fins may be smaller or larger than the number of the first pull-down fins, and the number of the second transmission fins may be smaller or larger than the number of the second pull-down fins.

Specifically, in this embodiment, the number of the first transmission fin portions is 1, the number of the first pull-down fin portions is 1, and the number of the first pull-up fin portions is 1; the number of the second transmission fin parts is 1, the number of the second pull-down fin parts is 1, and the number of the second pull-up fin parts is 1. In other embodiments, the numbers of the first transmission fin portion, the first pull-down fin portion, the first pull-up fin portion, the second transmission fin portion, the second pull-down fin portion, and the second pull-up fin portion may also be other values.

In this embodiment, the step of forming the substrate includes: providing an initial substrate; patterning the initial substrate to form a substrate 300, a first transmission fin portion located on the substrate 300 of the first transmission region 311, a first pull-down fin portion located on the substrate of the first pull-down region 312, a first shunting fin portion located on the substrate 300 of the first shunting region 314, a second transmission fin portion located on the substrate 300 of the second transmission region 321, a second pull-down fin portion located on the substrate 300 of the second pull-down region 322, and a second shunting fin portion located on the substrate 300 of the second shunting region 324.

In this embodiment, the substrate 300 and the fin 301 are made of the same material. Specifically, the material of the substrate 300 and the fin 301 is silicon. In other embodiments, the material of the substrate and the fin portion may also be germanium or silicon germanium.

In this embodiment, the first transmission region 311 is in contact with the first pull-down region 312, and the first transmission fin portion is connected to the first pull-down fin portion; the second transmission region 321 is in contact with the second pull-down region 322, and the second transmission fin portion is connected to the second pull-down fin portion.

In this embodiment, the extending directions of the fins 301 are the same. In other embodiments, the extending directions of the fins may be different.

In this embodiment, after the substrate is formed, the forming method further includes: isolation structures (not shown) are formed on the substrate 300 between the fins 201, and the isolation structures cover part of the sidewalls and the top surface of the fins 301.

The isolation structure is used to achieve electrical isolation between different fins 301.

Subsequently forming a storage structure in the storage area; forming a first transfer transistor in a first transfer region 311 of the substrate, the step of forming the first transfer transistor comprising: forming a first transmission gate structure on the first transmission region 311 substrate, and forming a first transmission source region and a first transmission drain region in the first transmission region 311 substrate on both sides of the first transmission gate structure, respectively, wherein the first transmission source region is electrically connected to the first connection portion;

forming a second transfer transistor in the substrate second transfer region 321, the step of forming the second transfer transistor including: forming a second transfer gate structure on the second transfer region 321 substrate, and forming a second transfer drain region and a second transfer source region in the second transfer region 321 substrate on both sides of the second transfer gate structure, respectively, wherein the second transfer source region is electrically connected to the second connection portion;

Forming a first shunting structure at the substrate first shunting region 314;

or forming a second shunt structure at substrate first shunt region 314;

or forming a first shunt structure at the substrate first shunt region 314 and forming a second shunt structure at the substrate first shunt region 314;

the first shunting structure comprises: the first shunt input part is used for inputting a preset potential, and the first shunt output part is used for connecting a first potential; the second shunting structure comprises: a second shunt input portion for inputting the preset potential, and a second shunt output portion for applying the first potential.

Specifically, in this embodiment, the steps of forming the storage structure and the shunting structure are shown in fig. 7 and 8.

Referring to fig. 7, a gate structure 340 is formed across the fin 301, wherein the gate structure 340 covers a portion of the sidewalls and the top surface of the fin.

Specifically, the step of forming the gate structure 340 includes: forming a first pull-down gate structure crossing the first pull-down fin portion, the first pull-down gate structure covering a portion of a sidewall and a top surface of the first pull-down fin portion; forming a first transmission grid electrode structure crossing the first transmission fin part, wherein the first transmission grid electrode structure covers partial side wall and the top surface of the first transmission fin part; forming a second pull-down gate structure crossing the second pull-down fin portion, wherein the second pull-down gate structure covers part of the side wall and the top surface of the second pull-down fin portion; forming a second transmission gate structure crossing the second transmission fin part, wherein the second transmission gate structure covers partial side wall and the top surface of the second transmission fin part; forming a first shunt gate group crossing the first shunt fin part, wherein the first shunt gate group is positioned on the top of the first shunt fin part and the surface of the side wall; and forming a second shunt gate group crossing the second shunt fin part, wherein the second shunt gate group is positioned on the partial top and the side wall surface of the second shunt fin part.

The forming method comprises the following steps: forming a first pull-up gate structure crossing the first pull-up fin portion, the first pull-up gate structure covering a portion of a sidewall and a top surface of the first pull-up fin portion; and forming a second pull-up gate structure crossing the second pull-up fin portion, wherein the second pull-up gate structure covers part of the side wall and the top surface of the second pull-up fin portion.

In this embodiment, the first pull-down gate structure is in contact with the first pull-up gate structure, so as to realize the electrical connection between the first pull-down gate structure and the first pull-up gate structure; the second pull-down gate structure is in contact with the second pull-up gate structure, so that the second pull-down gate structure is electrically connected with the second pull-up gate structure. In other embodiments, the first pull-down gate structure and the first pull-up gate structure may also be not in contact, and the first pull-down gate structure and the first pull-up gate structure are connected through a conductive structure; the second pull-down gate structure and the second pull-up gate structure may also be non-contact, and the second pull-down gate structure and the second pull-up gate structure are connected by a conductive structure.

In this embodiment, the first shunt gate set includes: a first shunt gate structure connected to the first pull-down gate structure; a second shunt gate structure connected to the first transfer gate structure.

In this embodiment, the first shunt gate structure is in contact with the first pull-down gate structure, so as to electrically connect the first shunt gate structure and the first pull-down gate structure; the second shunt gate structure is in contact with the first transfer gate structure, thereby enabling electrical connection of the first shunt gate structure and the first transfer gate structure. In other embodiments, the first shunt gate structure and the first pull-down gate structure may also be not in contact, and the first shunt gate structure and the first pull-down gate structure are electrically connected through a conductive structure; the second shunt gate structure and the first transmission gate structure can also be in non-contact, and the electrical connection is realized through a conductive structure.

In this embodiment, the second shunt gate group includes: a third shunt gate structure electrically connected to the first pull-down gate structure; a fourth shunt gate structure electrically connected to the second transfer gate structure.

In this embodiment, the third shunt gate structure is in contact with the second pull-down gate structure, so as to electrically connect the third shunt gate structure and the second pull-down gate structure; the fourth shunt gate structure is in contact with the first transfer gate structure, thereby achieving electrical connection of the fourth shunt gate structure and the second transfer gate structure. In other embodiments, the third shunt gate structure and the second pull-down gate structure may also be not in contact, and are electrically connected through a conductive structure; the fourth shunt gate structure and the second transfer gate structure can also be in non-contact and electrically connected through a conductive structure.

In this embodiment, the gate structure 340 includes: the first upper-pull gate structure, the second upper-pull gate structure, the first lower-pull gate structure, the second lower-pull gate structure, the first transmission gate structure, the second transmission gate structure, the first shunt gate group and the second shunt gate group.

Referring to fig. 8, doped regions 302 are formed in the fin 301 on both sides of the gate structure 340.

The doped regions 302 are used to form source and drain regions of a transistor.

In this embodiment, the doped regions 302 are formed in the fin 301 on both sides of the gate structure 340 by ion implantation. In other embodiments, the doped region may also be formed by an epitaxial growth process.

In this embodiment, the first transmission region 311 is used to form an NMOS transistor, that is, the first transmission transistor is an NMOS transistor; the first pull-down region 312 is used to form an NMOS transistor, i.e., the first pull-down transistor is an NMOS transistor; the first pull-up region 313 is used to form a PMOS transistor, and the first pull-up transistor is a PMOS transistor; the second transmission region 321 is used to form an NMOS transistor, that is, the second transmission transistor is an NMOS transistor; the second pull-down region 322 is used to form an NMOS transistor, i.e., the second pull-down transistor is an NMOS transistor; the second pull-up region 323 is used to form a PMOS transistor, and the second pull-up transistor is a PMOS transistor. In other embodiments, the first and second pull-up regions may also be used to form a resistor.

In this embodiment, the first shunt transistor, the second shunt transistor, the third shunt transistor, and the fourth shunt transistor are NMOS transistors.

In this embodiment, the doped region 302 includes: the first transmission source region and the first transmission drain region are respectively positioned in the first transmission fin parts at two sides of the first transmission gate structure; a first pull-down source region and a first pull-down drain region in the first pull-down fin part at two sides of the first pull-down gate structure; the first pull-up drain region and the first pull-up source region are positioned in the first pull-up fin parts on two sides of the first pull-up gate structure; a second transfer source region and a second transfer drain region respectively located in the second transfer fin portions at both sides of the second transfer gate structure; the second pull-down source region and the second pull-down drain region are positioned in the second pull-down fin parts on two sides of the second pull-down gate structure; the second pull-up source region and the second pull-up source region are positioned in the second pull-up fin parts on two sides of the second pull-up gate structure; the first shunt drain region and the first shunt source region are positioned in the first shunt fin parts on two sides of the first shunt gate structure; the second shunt drain region and the second shunt source region are positioned in the first shunt fin parts on two sides of the second shunt gate structure; a third shunt drain region and a third shunt source region which are positioned in the second shunt fin parts on two sides of the third shunt gate structure; and the fourth shunt drain region and the fourth shunt source region are positioned in the second shunt fin parts on two sides of the fourth shunt gate structure.

In this embodiment, the step of forming the doped region 302 includes: forming a first photoresist covering the top and the side wall surfaces of the first pull-up fin part and the second pull-up fin part; performing first ion implantation on the first pull-down fin part, the first transmission fin part, the second pull-down fin part, the second transmission fin part, the first shunt fin part and the second shunt fin part by taking the first photoresist as a mask to form a first transmission source region, a first transmission drain region, a first pull-down source region, a second transmission drain region, a second pull-down source region, a first shunt drain region, a second shunt source region, a second shunt drain region, a third shunt source region, a third shunt drain region, a fourth shunt source region and a fourth shunt drain region; after the first ion implantation, forming a second photoresist covering the top and the side wall surfaces of the first transmission fin part, the first pull-down fin part, the second transmission fin part, the second pull-down fin part, the first shunting fin part and the second shunting fin part; and performing second ion implantation on the first pull-up fin portion and the second pull-up fin portion by taking the second photoresist as a mask to form a first pull-up drain region, a first pull-up source region, a second pull-up source region and a second pull-up drain region.

In this embodiment, the first transmission source region, the first transmission drain region, the first pull-down source region, the second transmission drain region, the second pull-down source region, the first shunt drain region, the second shunt source region, the second shunt drain region, the third shunt source region, the third shunt drain region, the fourth shunt source region, and the fourth shunt drain region have first doping ions therein. The first dopant ions are N-type ions, such as phosphorous ions or arsenic ions.

In this embodiment, the first pull-down drain region and the first transmission source region are connected to form a first common doped region, and the second pull-down drain region and the second transmission source region are connected to form a second common doped region.

In this embodiment, the first shunt drain region is in contact with the second shunt source region to form a first shunt co-doped region, so that the first shunt drain region and the second shunt source region are electrically connected; and the third shunt drain region is in contact with the fourth shunt source region to form a second shunt co-doped region, so that the third shunt drain region is electrically connected with the fourth shunt source region.

In this embodiment, the storage structure includes: a first pull-down transistor located in the first pull-down region 312.

The substrate first pull-down region 312 has a first pull-down transistor comprising: a first pull-down gate structure located on the first pull-down region 312 substrate; the first pull-down source region and the first pull-down drain region are respectively positioned on the substrate at two sides of the first pull-down gate structure, and the first pull-down source region is used for being connected with a first potential;

the substrate second pull-down region 322 has a second pull-down transistor comprising: a second pull-down gate structure on the substrate; a second pull-down source region and a second pull-down drain region in the substrate respectively located at two sides of the second pull-down gate structure, the second pull-down gate structure being electrically connected to the first pull-down drain region, the second pull-down drain region being electrically connected to the first pull-down gate structure, the second pull-down source region being configured to apply a first potential;

a first transfer transistor on the first transfer region 311 substrate, the first transfer transistor comprising: a first transmission gate structure on the substrate; the first transmission source region and the first transmission drain region are respectively positioned in the substrates at two sides of the first transmission grid structure, and the first transmission source region is electrically connected with the first pull-down drain region;

A second pass transistor on the second pass region 321 substrate, the second pass transistor comprising: forming a second transfer gate structure on the second transfer region 321 substrate; and forming a second transmission source region and a second transmission drain region in the second transmission region 321 substrate on two sides of the second transmission gate structure, wherein the second transmission source region is electrically connected with the second pull-down drain region.

In this embodiment, the substrate further includes a first pull-up region 313 and a second pull-up region 323. The substrate first pull-up region 313 has a first pull-up load, the substrate second pull-up region 323 has a second pull-up load,

the first pull-up load comprises a first pull-up transistor and the second pull-up load comprises a second pull-up transistor. In other embodiments, the first pull-up load and the second pull-up load may further include a resistor.

In this embodiment, the storage structure further includes: a first pull-up transistor located in a first pull-up region 313 of the substrate, the first pull-up transistor comprising: the first pull-up gate structure is positioned on the first pull-up region 313 substrate, and the first pull-up drain region and the first pull-up source region are respectively positioned in the substrate at two sides of the first pull-up gate structure; a second pull-up transistor located in a second pull-up region 323 of the substrate, the second pull-up transistor comprising: and the second pull-up gate structure is positioned on the second pull-up region 323 substrate, and the second pull-up source region and the second pull-up drain region are respectively positioned in the substrates at two sides of the second pull-up gate structure.

In this embodiment, the substrate first shunt region 314 has a first shunt structure; the second shunt section 324 has a second shunt structure.

The first shunting structure comprises: a first shunt transistor, the first shunt transistor comprising: a first shunt gate structure on the first shunt region 314 substrate, the first shunt gate structure electrically connected to the first pull-down gate structure; and a first shunt source region and a first shunt drain region in the substrate of the first shunt region 314 at two sides of the first shunt gate structure, and the first shunt output part comprises the first shunt source region.

The first shunting structure further comprises a second shunting transistor, the second shunting transistor comprising: a second shunt gate structure on the substrate of the first shunt region 314, the second shunt gate structure electrically connected to the second pull-down gate structure; and the second shunt source region and the second shunt drain region are respectively positioned in the first shunt region 314 substrate at two sides of the second shunt gate structure, the first shunt input part comprises the second shunt drain region, and the second shunt source region is electrically connected with the first shunt drain region.

In this embodiment, the second shunting structure includes: a third shunt transistor and a fourth shunt transistor.

In this embodiment, the third shunt transistor includes: a third shunt gate structure on the substrate of the second shunt region 324, the third shunt gate structure being electrically connected to the second pull-down gate structure; and a third shunt source region and a third shunt drain region which are positioned in the substrate of the second shunt region 324 on two sides of the third shunt gate structure, and the second shunt output part comprises the third shunt source region.

In this embodiment, the fourth shunt transistor includes: a fourth shunt gate structure on the substrate of the second shunt region 324, the fourth shunt gate structure being electrically connected to the second transfer gate structure; and the fourth shunt source region and the fourth shunt drain region are positioned in the substrates at two sides of the second shunt gate structure at two sides of the fourth shunt gate structure, the second shunt input part comprises the fourth shunt source region, and the fourth shunt drain region is electrically connected with the third shunt source region.

In other embodiments, the first shunt structure may further include only a first shunt transistor, the first shunt output includes the first shunt source region, the first shunt gate structure is electrically connected to the first pull-down gate structure, and the first shunt input includes the first shunt drain region.

In other embodiments, the second shunt structure may further include only a third shunt transistor, the second shunt output includes the third shunt source region, the third shunt gate structure is electrically connected to the second pull-down gate structure, and the second shunt input includes the third shunt drain region.

Referring to fig. 9, a word line 330 connecting the first transfer gate structure and the second transfer structure is formed; forming a first bit line 351 connecting the first transfer drain region; a second bit line 352 connecting the second transfer drain region is formed.

The word line 330 is used for controlling the on and off of the first transmission transistor and the second transmission transistor; the first bit line 351 and the second bit line 352 are used to read data in the formed memory structure and write data into the memory structure.

In this embodiment, the first bit line 351 is further connected to the first shunting input portion; the second bit line 352 is also connected to the second shunt input.

In other embodiments, the first bit line may also not connect the first split input; the second bit line may also be unconnected to the second shunt input. The memory structure further comprises: a third bit line electrically connected to the first shunt input; a fourth bit line electrically connected to the second shunt input.

It should be noted that, during a read operation of the memory structure, a preset potential is applied to the first bit line 351 and the second bit line 352, and the preset potential is a high level "1"; a high level "1" is applied to the word line 330, and the second shunt transistor is turned on; meanwhile, if the potential of a node where the first pull-down drain region is connected to the first transmission source region is low level "0", the first shunt transistor is turned on, thereby turning on the first shunt structure. The first shunt structure is conducted, so that the preset potential can be connected with a grounding end through the first shunt structure, the grounding end can pull down the preset potential, the influence of the preset potential on the node potential connected with the first pull-down drain region and the first transmission source region can be reduced, the interference of static noise on a formed memory can be reduced, and the static noise capacity of the memory can be improved.

In this embodiment, the forming method further includes: forming a first connection line 371 connecting the first common doped region and the first pull-up source region; forming a second connection line 372 connecting the second common doped region and the second pull-up drain region.

The first connection line 371 is used to realize electrical connection between a first pull-down drain region, a first transmission source region, and the first pull-up source region; the second connection line 372 is used for electrically connecting the second pull-down drain region, the second transfer source region and the second pull-up drain region.

In this embodiment, the forming method further includes: forming a first pull-down source line 331 connected to the first pull-down source region, the first pull-down source line 331 being used for applying a first potential to the first pull-down source region; forming a second pull-down source line 332 connected to the second pull-down source region, the second pull-down source line 332 being used for applying the first potential to the second pull-down source region.

In this embodiment, the first potential is zero potential, and the first pull-down source line 331 and the second pull-down source line 332 are used for grounding.

In this embodiment, the forming method further includes: forming a first pull-up drain line 381 connected to the first pull-up drain region, wherein the first pull-up drain line 381 is used for applying a second potential to the first pull-up drain region, and the second potential is greater than the first potential; a second pull-up drain line 382 is formed connecting the second pull-up source region, the second pull-up drain line 382 being for applying the second potential to the second pull-up drain region.

In this embodiment, the forming method further includes: forming a first gate line 361 for connecting the first connection line 371 and the second pull-up gate structure, wherein the first gate line 361 is used for realizing the electrical connection between the second pull-up gate structure and the first pull-down drain region; forming a second gate line 362 connecting the second connection line 372 and the first pull-up gate structure, wherein the second gate line 362 is used for realizing the electrical connection between the first pull-up gate structure and the second pull-down drain region.

In summary, in the method for forming a memory structure according to the embodiment of the present invention, a shunting structure is formed in the substrate shunting region. In the using process of the memory, the shunt structure can form a path between an interference signal and the first transmission source region, so that the influence of the interference signal on data stored in the storage structure is reduced.

The present invention also provides an embodiment of a memory structure, with continued reference to FIG. 9, the memory structure comprising:

a substrate including a storage region, a first transfer region 311, and a second transfer region 321;

The storage structure is positioned in the substrate storage area and comprises a first connecting part, a second connecting part and a grounding part, and the grounding part is used for applying a first potential;

a first transfer transistor located in the substrate first transfer region 311, the first transfer transistor comprising: the first transmission gate structure is positioned on the substrate of the first transmission region 311, and the first transmission drain region and the first transmission source region are respectively positioned in the substrates at two sides of the first transmission gate structure, and the first transmission source region is connected with the first connecting part;

a first bit line electrically connected to the first transfer drain region;

a second transmission transistor located in the second transmission region 321 of the substrate, a second transmission gate structure located on the second transmission region 321 of the substrate, and a second transmission drain region and a second transmission source region located in the second transmission region 321 of the substrate on two sides of the second transmission gate structure, respectively, wherein the second transmission source region is electrically connected to the second connection portion;

a word line electrically connected to the first and second transfer gate structures;

a second bit line electrically connected to the second transfer drain region;

The substrate further comprises at least a first shunt region 314 or a second shunt region 324, the substrate first shunt region 314 having a first shunt structure comprising: a first shunt input part and a first shunt output part, wherein the first shunt input part is used for applying a preset potential, and the first shunt output part is used for connecting the grounding part; the substrate second shunt region 324 has a second shunt structure comprising: the second shunt input part is used for applying the preset potential, and the second shunt output part is used for connecting the grounding part.

The storage area is used for forming a storage structure subsequently; the first transfer region 311 is a region for forming a first transfer transistor later, and the second transfer region 321 is a region for forming a second transfer transistor later; the flow splitting region is a region subsequently used for forming a first flow splitting structure and a second flow splitting structure.

In this embodiment, the fin 301 includes: a first transmission fin portion on the substrate 300 of the first transmission region 311; a second transmission fin portion on the base of the second transmission region 321; a first pull-down fin portion on the substrate 300 in the first pull-down region 312; a second pull-down fin portion located on the base 300 of the second pull-down region 322; a first pull-up fin portion on the substrate 300 in the first pull-up region 313; a second pull-up fin portion on the second pull-up region 323 substrate 300; a first shunting fin portion on the substrate 300 of the first shunting region 314; and a second shunting fin portion on the substrate 300 of the second shunting region 324.

In this embodiment, the widths of the fins 301 are the same, and the heights of the fins 301 are the same. In other embodiments, the widths of the fins may be different, and the heights of the fins may be different.

In this embodiment, the first transmission region 311 is connected to the first pull-down region 312, and the first transmission fin portion is connected to the first pull-down fin portion; the second transmission region 321 is connected to the second pull-down region 322, and the second transmission fin portion is connected to the second pull-down fin portion.

In this embodiment, the memory structure further comprises an isolation structure (not shown) on the substrate

In this embodiment, the storage structure includes: a first pull-down transistor located in the first pull-down region 312, a first pass transistor located in the first pass region 311, a second pull-down transistor located in the second pull-down region 322, and a second pass transistor located in the second pass region 321.

In this embodiment, the ground is used to apply a first potential, specifically, the ground is grounded to apply the first potential to the ground.

The first pull-down transistor includes: a first pull-down gate structure located on the first pull-down region 312 substrate; and a first pull-down source region and a first pull-down drain region in the substrate of the first pull-down region 312 located at two sides of the first pull-down gate structure, wherein the first pull-down source region is used for applying a first potential.

In this embodiment, the first pull-down gate structure crosses over the first pull-down fin portion, and the second pull-down gate structure covers a part of a sidewall and a top surface of the first pull-down fin portion; the first pull-down source region and the first pull-down drain region are respectively located in the first pull-down fin portions on two sides of the first pull-down gate structure.

In this embodiment, the second pull-down transistor includes: a second pull-down gate structure on the second pull-down region 322 substrate; and a second pull-down source region and a second pull-down drain region which are positioned in the substrate of the second pull-down region 322 at two sides of the second pull-down gate structure, wherein the second pull-down gate structure is electrically connected with the first pull-down drain region, the second pull-down drain region is electrically connected with the first pull-down gate structure, and the second pull-down source region is used for applying a first potential.

The first transfer transistor includes: a first transmission gate structure on the substrate of the first transmission region 311; and the first transmission source region and the first transmission drain region are positioned in the substrate of the first transmission region 311 at two sides of the first transmission gate structure, and the first transmission source region is electrically connected with the first pull-down drain region.

In this embodiment, a first transmission gate structure crosses over the first transmission fin, and the first transmission gate structure covers a portion of a sidewall and a top surface of the first transmission fin.

In this embodiment, the first transfer source region and the first transfer drain region are respectively located in the first transfer fin portions on two sides of the first transfer gate structure.

In this embodiment, the second pass transistor includes: a second transfer gate structure on the substrate of the second transfer region 321; and a second transfer source region and a second transfer drain region in the second transfer region 321 substrate at two sides of the second transfer gate structure, wherein the second transfer source region is electrically connected with the second pull-down drain region.

In this embodiment, the second transfer gate structure crosses over the second transfer fin, and the second transfer gate structure covers a portion of a sidewall and a top surface of the second transfer fin.

In this embodiment, the second transfer source region and the second transfer drain region are respectively located in the second transfer fin portions on two sides of the second transfer gate structure.

In this embodiment, the first shunting structure includes: a first shunt gate set spanning the first shunt fin, the first shunt gate set located at a portion of a top and a sidewall surface of the first shunt fin.

In this embodiment, the second shunting structure includes: a second shunt gate group spanning the second shunt fin, the second shunt gate group located at a portion of a top and a sidewall surface of the second shunt fin.

In this embodiment, the substrate further includes a first pull-up region 313 and a second pull-up region 323. The storage structure further comprises: a first pull-up load located at the first pull-up region 313; a second load located in the second pull-up 323 region. In other embodiments, the memory region may further not include the first pull-up region and the second pull-up region, and the memory structure may further not include the first pull-up load and the second pull-up load.

The first pull-up load comprises a first pull-up transistor and the second pull-up load comprises a second pull-up transistor. In other embodiments, the first and second pull-up transistors may further include a resistor.

In this embodiment, the first pull-up transistor includes: the first pull-up gate structure is positioned on the substrate of the first pull-up region 313, and the first pull-up drain region and the first pull-up source region are respectively positioned in the substrate at two sides of the first pull-up gate structure.

In this embodiment, a first pull-up gate structure crosses over the first pull-up fin portion, and the first pull-up gate structure covers a portion of a sidewall and a top surface of the first pull-up fin portion.

In this embodiment, the first pull-up drain region and the first transfer drain region are respectively located in the first pull-up fin portions on two sides of the first pull-up gate structure.

In this embodiment, the second pull-up transistor includes: and the second pull-up gate structure is positioned on the second pull-up region 323 substrate, and the second pull-up source region and the second pull-up drain region are respectively positioned in the substrates at two sides of the second pull-up gate structure.

In this embodiment, a second pull-up gate structure crosses over the second pull-up fin portion, and the second pull-up gate structure covers a portion of a sidewall and a top surface of the second pull-up fin portion.

In this embodiment, the second pull-up source region and the first pull-up drain region are respectively located in the second pull-up fin portions on two sides of the second pull-up gate structure.

In this embodiment, the first pull-down gate structure is in contact with the first pull-up gate structure, so as to realize the electrical connection between the first pull-down gate structure and the first pull-up gate structure; the second pull-down gate structure is in contact with the second pull-up gate structure, so that the second pull-down gate structure is electrically connected with the second pull-up gate structure.

In other embodiments, the first pull-down gate structure and the first pull-up gate structure may also be not in contact, and the first pull-down gate structure and the first pull-up gate structure are connected through a conductive structure; the second pull-down gate structure and the second pull-up gate structure may also be non-contact, and the second pull-down gate structure and the second pull-up gate structure are connected by a conductive structure.

In this embodiment, the substrate shunt area includes a first shunt area 314 and a second shunt area 324, the substrate first shunt area 314 has a first shunt structure, and the first shunt structure includes: a first shunt input part and a first shunt output part, wherein the first shunt input part is used for applying a preset potential, and the first shunt output part is used for connecting the grounding part; the substrate second shunt region 324 has a second shunt structure comprising: the second shunt input part is used for applying the preset potential, and the second shunt output part is used for connecting the grounding part. In other embodiments, the substrate may further include only the first current splitting region or the second current splitting region.

The first shunting structure comprises: a first shunt transistor, the first shunt transistor comprising: a first shunt gate structure on the first shunt region 314 substrate, the first shunt gate structure electrically connected to the first pull-down gate structure; and the first shunt output part comprises the first shunt source region.

The first shunting structure further comprises a second shunting transistor, the second shunting transistor comprising: a second shunt gate structure on the first shunt area substrate, the second shunt gate structure electrically connected to the first transmission gate structure; and the first shunt input part comprises a first shunt drain region, and the first shunt source region is connected with the first shunt drain region.

In this embodiment, the first shunt gate structure and the second shunt gate structure form a first shunt gate group.

In this embodiment, the fourth shunt transistor includes: a fourth shunt gate structure on the substrate of the second shunt region 324, the fourth shunt gate structure being electrically connected to the second transfer gate structure; and the fourth shunt source region and the fourth shunt drain region are positioned in the substrates at two sides of the fourth shunt gate structure, the second shunt input part comprises the fourth shunt drain region, and the fourth shunt source region is electrically connected with the third shunt drain region.

In this embodiment, the third shunt gate structure and the fourth shunt gate structure form a second shunt gate group.

In other embodiments, the first shunt structure may further include only a first shunt transistor, the first shunt output includes the first shunt source region, and the first shunt output includes the first shunt drain region.

In other embodiments, the second shunt structure may further include only a second shunt transistor, the second shunt output portion includes the third shunt source region, and the second shunt output portion includes the fourth shunt drain region.

In this embodiment, the first shunt gate structure is in contact with the first pull-down gate structure, so as to electrically connect the second shunt gate structure with the first pull-down gate structure; the second shunt gate structure is in contact with the first transfer gate structure, thereby achieving electrical connection of the first shunt gate structure and the first transfer gate structure. In other embodiments, the first shunt gate structure and the first pull-down gate structure may not be in contact, and the first shunt gate structure and the first pull-down gate structure are electrically connected through a conductive structure; the second shunt gate structure and the first transmission gate structure can also be in non-contact, and the electrical connection is realized through a conductive structure.

In this embodiment, the third shunt gate structure is in contact with the second pull-down gate structure, so as to realize the electrical connection between the third shunt gate structure and the second pull-down gate structure; the fourth shunt gate structure is in contact with the second transfer gate structure, thereby achieving an electrical connection between the fourth shunt gate structure and the first transfer gate structure. In other embodiments, the third shunt gate structure and the second pull-down gate structure may not be in contact, and the third shunt gate structure and the second pull-down gate structure are electrically connected through a conductive structure; the fourth shunt gate structure and the second transfer gate structure can also be in non-contact and electrically connected through a conductive structure.

In this embodiment, the first pull-up gate structure, the second pull-up gate structure, the first pull-down gate junction, the second pull-down gate structure, the first transmission gate structure, the second transmission gate structure, the first shunt gate group and the second shunt gate group form a gate structure 340.

In this embodiment, the doped region 304 is formed by the first transmission source region, the first transmission drain region, the first pull-down source region, the second transmission drain region, the second pull-down source region, the first shunt drain region, the second shunt source region, the second shunt drain region, the third shunt source region, the third shunt drain region, the fourth shunt source region, the fourth shunt drain region, the first pull-up source region, the second pull-up source region, and the second pull-up drain region.

In this embodiment, the first pull-up drain region, the first pull-up source region, the second pull-up source region, and the second pull-up drain region have second doped ions therein, and the second doped ions are P-type ions, such as boronIons or BF^2-Ions.

The word line 330 is used for controlling the on and off of the first transmission transistor and the second transmission transistor; the first bit line 351 and the second bit line 352 are used to read data in the formed memory and write data into the memory.

In this embodiment, the first bit line 351 is further connected to the first shunting input portion; the second bit line 352 is also connected to the second shunt input. In other embodiments, the first bit line may also not connect the first split input; the second bit line may also be unconnected to the second shunt input.

It should be noted that, during a read operation of the memory structure, a preset potential is applied to the first bit line 351 and the second bit line 352 during the read operation of the memory structure, and the preset potential is a high level "1"; a high level "1" is applied to the word line 330, and the second shunt transistor is turned on; meanwhile, if the potential of a node where the first pull-down drain region is connected to the first transmission source region is low level "0", the first shunt transistor is turned on, thereby turning on the first shunt structure. The first shunt structure is conducted, so that the preset potential can be connected with a grounding end through the first shunt structure, the grounding end can pull down the preset potential, the influence of the preset potential on the node potential connected with the first pull-down drain region and the first transmission source region can be reduced, the interference of static noise on a formed memory can be reduced, and the static noise capacity of the memory can be improved.

In this embodiment, the memory further includes: a first connection line 371 connecting the first common doped region and the first pull-up source region; a second connection line 372 connecting the second common doped region and the second pull-up drain region.

In this embodiment, the memory further includes: a first pull-down source line 331 connected to the first pull-down source region, the first pull-down source line 331 being configured to apply a first potential to the first pull-down source region; a second pull-down source line 332 connected to the second pull-down source region, the second pull-down source line 332 being configured to apply the first potential to the second pull-down source region.

In this embodiment, the first potential is zero, i.e., the first pull-down source line 331 and the second pull-down source line 332 are used for grounding.

In this embodiment, the memory further includes: a first pull-up drain line 381 connected to the first pull-up drain region, wherein the first pull-up drain line 381 is configured to apply a second potential to the first pull-up drain region, and the second potential is greater than the first potential; a second pull-up drain line 382 connected to the second pull-up drain region, the second pull-up drain line 382 being configured to apply the second potential to the second pull-up drain region.

In this embodiment, the memory further includes: a first gate line 361 for connecting the first connection line 371 and the second pull-up gate structure, wherein the first gate line 361 is used for realizing the electrical connection between the second pull-up gate structure and the first pull-down drain region; and a second gate line 362 connecting the second connection line 372 and the first pull-up gate structure, wherein the second gate line 362 is used for electrically connecting the first pull-up gate structure and the second pull-down drain region.

In summary, in the memory structure provided by the embodiments of the present invention, the memory structure includes at least a first shunting structure and a second shunting structure, and the memory circuit includes at least a first shunting unit and a second shunting unit. The first shunt unit can reduce the interference of static noise on the first shunt input end to the memory circuit; the second shunt unit can reduce the interference of static noise on the second shunt input end to the memory circuit, so that the forming method can reduce the interference of the static noise to the memory structure and increase the static noise capacity of the memory structure.

FIG. 10 is a schematic diagram of a memory structure according to yet another embodiment of the present invention.

Referring to fig. 10, the same parts of the memory structure of the present embodiment as those of the previous embodiment are not repeated herein, and the differences include:

in this embodiment, the first shunt input is not electrically connected to the first bit line; the second shunt input is not electrically connected to the second bit line.

The memory structure further comprises: a third bit line 411 connected to the first shunt input; a fourth bit line 421 connected to the fourth input.

In this embodiment, during the process of reading the data stored in the memory structure, a high level "1" is applied to the word line 330, so that the first pass transistor and the second pass transistor are turned on, and the first shunt transistor and the second shunt transistor are turned on at the same time.

In this embodiment, in the process of reading the data stored in the memory structure, reading is performed through the third bit line 411 and the fourth bit line 421.

Specifically, a preset potential is applied to the third bit line 411 and the fourth bit line 421, and the preset potential is at a high level "1".

The junction of the first pull-down drain region and the first transmission drain region is a first storage node of the memory; and the joint of the second pull-down drain region and the second transmission drain region is a second storage node of the memory.

If the potential of the first storage node is at a high level "1", the potential of the second pull-down gate structure is opposite to the potential of the second storage node, the potential of the second storage node is at a low level "0", and thus the potential of the first pull-down gate structure is at a low level "0".

Since the potential of the second pull-down gate structure is high level "1", and the second pull-up transistor gate structure is electrically connected to the second pull-down gate structure, the second pull-up transistor is turned off, the second pull-down transistor and the third shunt transistor are turned on, so that a path is formed between the fourth bit line 421 and the ground, the first potential can pull down the potential of the fourth bit line 421, so that the fourth bit line 421 outputs low level "0", which is the same as the second storage node potential, and thus the storage data of the second storage node can be read through the fourth bit line 421.

Since the potential of the first pull-down gate structure is a low level "0", and the first pull-up gate structure is electrically connected to the first pull-down gate structure, the first pull-up transistor is turned on, and the first pull-down transistor and the first shunt transistor are turned off, so that the third bit line 411 is disconnected from the first potential, and further, a preset potential applied to the third bit line 411 is not pulled down, so that the third bit line 411 outputs a high level "1", and thus data stored in the first storage node can be read through the third bit line 411.

If the potential of the second storage node is at a high level "1", the potential of the first pull-down gate structure is opposite to the potential of the first storage node, the potential of the first storage node is at a low level "0", and thus the potential of the second pull-down gate structure is at a low level "0".

Since the potential of the first pull-down gate structure is a high level "1", the first pull-up transistor is turned off, and the first pull-down transistor and the first shunt transistor are turned on, so that a path is formed between the third bit line 411 and the first potential, and the first potential can pull down the potential of the third bit line 411, so that the third bit line 411 outputs a low level "0", which is the same as the potential of the first storage node, so that the stored data of the first storage node can be read through the third bit line 411.

Since the potential of the second pull-down gate structure is a low level "0", the second pull-up transistor is turned on, and the second pull-down transistor and the third shunt transistor are turned off, so that the fourth bit line 421 is disconnected from the first potential, and the preset potential applied to the fourth bit line 421 is not pulled down, so that the fourth bit line 421 outputs a high level "1", and thus the data stored in the second storage node can be read through the fourth bit line 421.

As can be seen from the above analysis, in this embodiment, the data in the storage structure is read through the third bit line 411 and the fourth bit line 421, and the preset potential is not applied to the first storage node and the second storage node during the reading process, so that the data stored in the storage structure is not easily affected, and thus a reading error is not easily generated, and therefore, the noise immunity of the memory is improved, and the static noise capacity is increased.

In summary, the memory structure provided by the embodiment of the present invention at least includes a first shunting structure and a second shunting structure. The memory applies a preset potential, which is a high level "1", to the first shunt input portion in a read operation.

FIG. 11 is a circuit diagram of an embodiment of a memory circuit of the present invention.

Specifically, this embodiment is a circuit diagram of the memory structure of fig. 10.

Referring to fig. 11, the memory circuit includes: a storage unit 20, the storage unit 20 comprising: a first connection terminal 31, a second connection terminal 32, and a ground terminal for applying a first potential;

a first transfer transistor PG1, the first transfer transistor PG1 including: the first transmission grid, the first transmission source electrode and the first transmission drain electrode, wherein the first transmission source electrode is connected with the first connection end 31;

a first bit line BL1 connected to the first transfer drain;

a second pass transistor PG2, the second pass transistor PG2 including: a second transfer gate electrode, a second transfer source electrode and a second transfer drain electrode, the second transfer source electrode being connected to the second connection terminal 32;

a first word line WL connecting the first and second transfer gates;

a second bit line BL2 connected to the second transfer drain;

the flow dividing unit at least comprises a first flow dividing unit 12 or a second flow dividing unit 22; the first flow dividing unit 12 includes: the first shunt input end is used for inputting a preset potential, and the first shunt output end is used for being connected with the grounding end; the second flow dividing unit 22 includes: the second shunt output end is connected with the grounding end, and the second shunt input end is used for inputting the preset potential.

In this embodiment, the first shunt input terminal inputs the preset potential through a first bit line, and the second shunt input terminal inputs the preset potential through a second bit line.

In this embodiment, the memory is a six-tube memory. In other embodiments, the memory may also be a four-transistor memory or a four-transistor plus two-resistor memory.

In this embodiment, the storage unit 20 includes: a first pull-down transistor PD1, the first pull-down transistor PD1 including: a first pull-down gate; the first pull-down drain electrode is connected with the first transmission source electrode;

a second pull-down transistor PD2, the second pull-down transistor PD2 including: a second pull-down gate connected to the first pull-down drain; a second pull-down source connected to the second transfer source; a second pull-down drain connected to the first pull-down gate.

In this embodiment, the first potential is low, and the first potential is applied to the ground terminal by grounding the ground terminal.

In this embodiment, the memory circuit further includes: a first pull-up load, the first pull-up load comprising: a first load input terminal for inputting a second potential Vdd which is greater than a first potential Vss; the first load output end is connected with the drain electrode of the first pull-down transistor; a second pull-up load, the second pull-up load comprising: a second load input terminal for inputting the second potential Vdd; and the second load output end is connected with the drain electrode of the second pull-down transistor. In other embodiments, the memory cell may also not include the first pull-up load and the second pull-up load.

In this embodiment, the first pull-up load includes a first pull-up transistor PU1, and the first pull-up transistor PU1 includes: the first pull-up grid is connected with the first pull-down grid; the first pull-up drain is connected with the first load input end, and the first pull-up source is connected with the first load output end;

in this embodiment, the second pull-up load includes a second pull-up transistor PU2, and the second pull-up transistor PU2 includes: the second pull-up grid is connected with the second pull-down grid; the second pull-up drain is connected with the second load input end; a second pull-up source connected to the second load output terminal.

In this embodiment, the first pull-down transistor PD1, the second pull-down transistor PD2, the first pass transistor PG1, and the second pass transistor PG2 are NMOS transistors; the first pull-up transistor PU1 and the second pull-up transistor PU2 are PMOS transistors.

In this embodiment, the first pull-down transistor PD1 and the first pull-up transistor PU1 form a first inverter; the second pull-down transistor PD2 and the second pull-up transistor PU2 constitute a second inverter. The first inverter and the second inverter form a memory cell. The storage unit realizes the storage of data through the latching function.

In this embodiment, a first storage node a of the memory is formed at a connection point of the first pull-up source and the first pull-down drain; a second storage node B of the memory is formed at the connection point of the second pull-up drain and the second pull-down drain; the connection point of the first pull-up grid and the first pull-down grid is a first connection point 1, and the connection point of the second pull-up grid and the second pull-down grid is a second connection point 2.

Since the first pull-down transistor PD1 and the first pull-up transistor PU1 form a first inverter, the first storage node a has a potential opposite to that of the first connection point 1, and the first connection point 1 has a potential identical to that of the second storage node B, the second storage node B has a potential opposite to that of the first storage node a, and the second storage node B has a potential opposite to that of the second connection point 2, thereby implementing a latch function.

Specifically, if the potential of the storage node a is at the high level "1" and the potential of the first connection point 1 is opposite to the potential of the first storage node a, the potential of the first connection point 1 is at the low level "0", and thus the potential of the second storage node B is at the low level "0", and since the potential of the second storage node B is opposite to the potential of the second connection point 2, the potential of the second connection point 2 is at the high level "1" and the storage node a is at the high level "1". Therefore, the memory cell can realize the latching function.

In this embodiment, the first potential is zero potential. Specifically, the first shunt output terminal, the first pull-down transistor source, the second shunt output terminal, and the second pull-down transistor source are grounded.

In this embodiment, the word line WL is used to control the on and off of the first pass transistor PG1 and the second pass transistor PG 2. Thereby realizing the selection of the memory cell and reading, writing and storing the data in the selected memory cell 30.

In this embodiment, applying a high level "1" to the word line WL may turn on the first pass transistor PG1 and the second pass transistor PG2, thereby connecting the first bit line BL1 to the memory cell 30 and connecting the second bit line BL2 to the memory cell 30.

In the process of reading the data stored in the memory cell 30, a preset potential is required to be applied to the first bit line BL1 and the second bit line BL2, and the preset potential is high level "1". Since the potentials of the first storage node a and the second storage node B are opposite, the potential of one of the first storage node a and the second storage node B is necessarily low level "0", and the preset potential easily inverts the potential of the storage node that is low level "0", thereby causing a read error. The first shunting unit 11 and the second shunting unit 12 can be turned on in the reading process, so that the first potential Vss pulls down a preset potential connected with a storage node with a low level "0" through the shunting unit, thereby reducing reading errors, further increasing the anti-interference capability of the memory, and increasing the static noise capacity of the memory.

In this embodiment, in order to reduce the interference of the static noise to the memory, the memory circuit includes: a first flow splitting unit 12, the first flow splitting unit 12 comprising: a first shunt input terminal and a first shunt output terminal, the first shunt input terminal is connected to the first bit line BL1, and the first shunt output terminal is used for being connected to a ground terminal; a second flow splitting unit 22, the second flow splitting unit 22 comprising: and the second shunt input end is connected with the second bit line BL2, and the second shunt output end is connected with the ground terminal.

In this embodiment, the first shunting unit 12 includes: a first shunt transistor FD1, the first shunt transistor FD1 including: a first shunt gate connected to the first pull-down gate; the first shunt source electrode is connected with the grounding end.

In this embodiment, the first shunting unit 12 further includes a second shunting transistor FG1, and the second shunting transistor FG1 includes: a second shunt gate connected to the first transfer gate; a second shunt source connected to the first shunt drain; a second shunt drain connected to the first shunt input.

In this embodiment, if the first storage node a is at a low level "0", the first connection point 1 is at a high level "1", and the preset potential applied to the first bit line BL1 is a first preset potential; in the reading process, the word line WL is connected to the high node "1", the first pass transistor PG1 and the second shunt transistor FG1 are turned on, and the first connection node 1 is at the high level "1", so that the first pull-down transistor PD1 and the first shunt transistor FD1 are turned on, and therefore, the first preset potential and the ground end can form a path through the first shunt unit 12, so that the first potential Vss can be pulled down by the first shunt unit 12 by the preset potential, and thus the preset potential can be prevented from inverting the potential of the first storage node a, and the first bit line BL1 can output a correct reading result. Therefore, the first shunting unit 12 can reduce static noise interference to the memory, and thus can increase the static noise capacity of the memory.

The second flow dividing unit 22 includes: a third shunt transistor FD2, the third shunt transistor FD2 including: a third shunt gate connected to the second pull-down gate; the third shunt source electrode is connected with the second shunt output end;

A fourth shunt transistor FG2, the fourth shunt transistor FG2 comprising: a fourth shunt gate connected with the second transfer gate; the fourth shunt source electrode is connected with the third shunt drain electrode; a fourth shunt drain connected to the second shunt input.

In this embodiment, if the second storage node B is at a low level "0", the second connection point 2 is at a high level "1", and the preset potential applied to the second bit line BL2 is a preset potential; in the reading process, the word line WL is connected to the high node "1", the second pass transistor PG2 and the fourth shunt transistor FG2 are turned on, and the second connection point is at the high level "1", so that the second pull-down transistor PD2 and the third shunt transistor FD2 are turned on, and therefore, the preset potential and the ground terminal can form a path through the second shunt unit 22, so that the ground terminal can pull down the second preset potential through the second shunt unit 22, and the second bit line BL2 can output a correct reading result. Therefore, the second shunting unit 22 can reduce the interference of static noise to the memory, and thus can increase the static noise capacity of the memory.

In other embodiments, the first shunting unit may further include only the first shunting transistor, the first shunting source region is connected to the ground terminal, and the first shunting drain region is connected to the first bit line; the second shunt unit may further include only the third shunt transistor, the third shunt source region is connected to the ground terminal, and the third shunt drain region is connected to the second bit line.

In other embodiments, the first shunt unit and the second shunt unit may further include a resistor.

In the memory circuit provided by the embodiment of the invention, the memory circuit at least comprises a first shunt unit and a second shunt unit. The first shunt unit can reduce the interference of static noise on the first shunt input end to the memory circuit; the second shunt unit can reduce the interference of static noise on the second shunt input end to the memory circuit. It follows that static noise is less disturbing to the memory circuitry, and the static noise capacity of the memory is greater.

FIG. 12 is a schematic diagram of another embodiment of a memory circuit according to the present invention.

In this embodiment, the same parts of the memory circuit as those of the previous embodiment are not repeated herein, and the differences are shown in fig. 12.

Referring to fig. 12, the memory circuit further includes: a third bit line BL1a, the third bit line BL1a connected to the first shunt input; a fourth bit line BL2a, the fourth bit line BL2a being connected to the second shunt input.

In this embodiment, the preset potential is applied to the first shunt input end through the third bit line BL1a, and the preset potential is applied to the second shunt input end through the fourth bit line BL2 a.

In the present embodiment, in the process of reading the data stored in the memory cell 30, a high level "1" is applied to the word line WL, so that the first transfer transistor PG1 and the second transfer transistor PG2 are turned on, while the first shunt transistor FD1 and the fourth shunt transistor FG2 are turned on.

In this embodiment, in the process of reading the data stored in the memory cell 30, reading is performed through the third bit line BL1a and the fourth bit line BL2 a.

Specifically, a preset potential is applied to the third bit line BL1a and the fourth bit line BL2a, and the preset potential is at a high level "1".

If the potential of the first storage node a is at the high level "1", the potential of the second connection point 2 is at the high level "1", the second connection point 2 is opposite to the second storage node potential, and the potential of the second storage node B is at the low level "0", so that the potential of the first connection point 1 is at the low level "0".

Since the potential of the second connection point 2 is at the high level "1", the second pull-up transistor PU2 is turned off, and the second pull-down transistor PD2 and the third shunt transistor FD2 are turned on, so that a path is formed between the fourth bit line BL2a and the ground terminal, which can pull down the potential on the fourth bit line BL2a, so that the fourth bit line BL2a outputs a low level "0", so that the potential of the fourth bit line BL2a is the same as the potential of the second storage node B, and the stored data of the second storage node B can be read through the fourth bit line BL2 a.

Since the potential of the first connection point 1 is low level "0", the first pull-up transistor PU1 is turned on, the first pull-down transistor PD1 and the first shunt transistor FD1 are turned off, so that the third bit line BL1a is disconnected from the ground, and further, the preset potential applied to the third bit line BL1a is not pulled down, so that the third bit line BL1a outputs high level "1", and thus the data stored in the first storage node a can be read through the third bit line BL1 a.

If the potential of the second storage node B is at the high level "1", the potential of the first connection point 1 is at the high level "1", the first connection point 1 is opposite to the potential of the first storage node a, the potential of the first storage node a is at the low level "0", and thus the potential of the second connection point 2 is at the low level "0".

Since the potential of the first connection point 1 is at the high level "1", the first pull-up transistor PU1 is turned off, and the first pull-down transistor PD1 and the first shunt transistor FD1 are turned on, so that a path is formed between the third bit line BL1a and the ground terminal, which can pull down the potential on the third bit line BL1a, so that the third bit line BL1a outputs a low level "0", which is the same as the potential of the first storage node a, so that the storage data of the first storage node a can be read through the third bit line BL1 a.

Since the potential of the second connection point 2 is at a low level "0", the second pull-up transistor PU2 is turned on, the second pull-down transistor PD2 and the third shunt transistor FD2 are turned off, and the fourth bit line BL2a is disconnected from the ground, so that the preset potential applied to the fourth bit line BL2a is not pulled down, and the fourth bit line BL2a outputs a high level "1", so that the data stored in the second storage node B can be read through the fourth bit line BL2 a.

As can be seen from the above analysis, in this embodiment, the data in the memory cell 30 can be read through the third bit line BL1a and the fourth bit line BL2a, and the preset potential is not applied to the first storage node a and the second storage node B during the reading process, so that the data stored in the memory cell 30 is not easily affected, and thus, a reading error does not easily occur, and therefore, the noise immunity of the memory is improved, and the static noise capacity is increased.

In this embodiment, the first shunting unit 12 includes: a first shunt transistor FD1 and a second shunt transistor FG 1; the second flow dividing unit 22 includes: a third shunt transistor FD2 and a fourth shunt transistor FG 2.

In other embodiments, the first shunting unit may further include only the first shunting transistor, and the first shunting drain is connected to the third bit line, and the first shunting source is connected to the ground terminal; the second shunt unit may further include only the third shunt transistor, the third shunt drain is connected to the fourth bit line, and the third shunt source region is connected to the ground terminal.

In summary, in the memory circuit provided in the embodiment of the present invention, the memory circuit at least includes a first shunting unit and a second shunting unit. The first shunt unit can reduce the interference of static noise on the first shunt input end to the memory circuit; the second shunt unit can reduce the interference of static noise on the second shunt input end to the memory circuit. It follows that static noise is less disturbing to the memory circuitry, and the static noise capacity of the memory is greater.

The invention also provides an embodiment of a working method of the memory.

Memory circuitry is provided with continued reference to fig. 11.

In this embodiment, the memory circuit is the same as the memory circuit described in the first embodiment of the memory circuit, and details thereof are not repeated here.

In this embodiment, the first shunting input terminal is connected to the first bit line BL 1; the second shunt input terminal is connected to the second bit line BL 2.

With continued reference to fig. 11, a first potential is applied to the ground.

In this embodiment, the first potential is a low level "0".

In this embodiment, a first potential is applied to the first pull-down transistor source region and the second pull-down transistor source region by grounding the first pull-down source region and the second pull-down source region.

In this embodiment, the storage unit 30 further includes: a first pull-up load, the first pull-up load comprising: the first load input end is used for applying a second potential, and the second potential is larger than the first potential; a second pull-up load, the second pull-up load comprising: and the second load output end is connected with the drain region of the second pull-down transistor, and the second load input end is used for applying the second potential Vdd.

The working method further comprises the following steps: applying a second potential Vdd to the first load input and the second load input, the second potential Vdd being greater than the first potential Vss.

In this embodiment, the second potential Vdd is a high level "1".

In other embodiments, the memory circuit does not include the first pull-up load and the second pull-up load. The working method does not comprise the following steps: a step of applying a second potential to the first load input terminal and the second load input terminal.

With continued reference to fig. 11, a word line potential is connected on the word line WL, the second word line potential being greater than the first potential Vss.

In this embodiment, the word line potential is high level "1".

In this embodiment, since the first pass transistor PG1 and the second pass transistor PG2 are NMOS transistors and the word line potential is high level "1", the first pass transistor PG1 and the second pass transistor PG2 are turned on.

In this embodiment, the second shunt transistor FG1 and the fourth shunt transistor FG2 are NMOS transistors, and the second shunt transistor FG1 and the fourth shunt transistor FG2 are turned on.

With continued reference to FIG. 11, an operating potential is applied across the first bit line BL1 and the second bit line BL 2.

In this embodiment, the working method includes: a write operation and a read operation.

In the write operation, the working potential is a storage potential.

The step of applying a storage potential on the first bit line BL1 and the second bit line BL2 comprises: a storage potential is applied to the first bit line BL1 and the second bit line BL2, forming a storage signal in the memory cell 30.

Specifically, if the signal to be stored is at a high level "1", the storage potential applied to the first bit line BL1 is at a high level "1"; the storage potential applied to the second bit line BL2 is low level "0".

Since the potential on the first bit line BL1 is high level "1", the potential of the first storage node a is high level "1"; since the potential on the second bit line BL2 is at low level "0", the potential on the second storage node B is at low level "0".

When the potential of the first storage node a is at the high level "1", the potential of the second connection point 2 is at the high level "1", so that the second pull-down transistor PD2 is turned on, the second storage node B applies the first potential Vss, the first potential is at the low level "0", and therefore, the potential of the second storage node B is at the low level "0", the first pull-down transistor is turned off, the first pull-up transistor PU1 is turned on, so that the first storage node a applies the second potential Vdd, and the second potential Vdd is at the high level "1", so that the first storage node a stores the high level "1".

If the signal to be stored is low level "0", the storage potential applied on the first bit line BL1 is high level "0"; the storage potential applied to the second bit line BL2 is high level "1".

Since the potential on the first bit line BL1 is at a low level "0", the potential of the first storage node a is at a low level "0"; since the potential on the second bit line BL2 is at the high level "1", the potential on the second storage node B is at the high level "1".

The potential of the first storage node a is at a low level "0", and the potential of the second connection point 2 is at a low level "0", so that the second pull-down transistor PD2 is turned off, and the second pull-up transistor PU2 is turned on, so that the second storage node B applies the second potential Vdd, and the second potential is at a high level "1", and thus, the second storage node potential is at a high level "1"; when the potential of the second storage node B is at the high level "1", the potential of the first connection point 1 is at the high level "1", the first pull-down transistor PD1 is turned on, the first pull-up transistor PU1 is turned off, and the first storage node a is applied with the first potential Vss, which is at the high level "0", so that the first storage node a stores the low level "0".

As can be seen from the above analysis, the operating method of the memory is capable of writing a storage signal in the memory.

In the reading operation, the working potential is a preset potential. The step of applying an operating potential on the first bit line BL1 and the second bit line BL2 comprises: a preset potential is applied to the first bit line BL1 and the second bit line BL2, and the preset potential is greater than the first potential Vss.

In this embodiment, the preset potential is a high level "1".

In this embodiment, if the potential of the storage node a is at the high level "1", and the potential of the second node 2 is at the high level "1", the second pull-up transistor PU2 is turned off, and the second pull-down transistor PD2 is turned on, and the first potential Vss is applied to the second bit line BL 2. Since the first potential Vss is at a low level "1", the preset potential of the second bit line BL2 is pulled down to a low level "0", forming a read potential negation. Meanwhile, the second storage node B is at a low level "0", the potential of the first connection point 1 is at a low level "0", the first pull-down transistor PD1 is turned off, the first pull-up transistor PU1 is turned on, so that the first bit line BL1 applies the second potential Vdd, the second potential Vdd is at a high level "1", and thus, the preset potential of the first bit line BL1 is at a high level "1", forming a read potential. The read signal includes the read potential and the read potential.

It should be noted that, from the above analysis, when the potential of the first storage node a is at the high level "1" during the process of applying the preset potential to the first bit line BL1 and the second bit line BL2, the potential of the second storage node B is at the low level "0", the potential of the second connection point 2 is at the high level "1", the third shunt transistor FD2 is turned on because the third shunt gate is connected to the second connection point 2, and the second shunt unit 22 is turned on because the fourth shunt transistor FG2 is turned on, so that the second bit line BL2 applies the first potential Vss through the second shunt unit 22, and therefore the first potential Vss can also pull down the preset potential on the second bit line BL2 through the second shunt unit 22, so that the preset potential can be prevented from raising the potential of the second storage node B, the potential inversion is avoided, so that the interference of static noise on the memory can be reduced, and the static storage capacity of the memory is increased.

In addition, in the process of applying the preset potential to the first bit line BL1 and the second bit line BL2, when the potential of the second storage node B is at a high level "1" and the potential of the first storage node a is at a low level "0", the potential of the first connection point is at a high level "1", the first shunt transistor FD1 is turned on because the first shunt gate is connected to the first connection point 1, and the first shunt unit 12 is turned on because the second shunt transistor FG1 is turned on, so that the first bit line BL1 applies the first potential Vss through the first shunt unit 12, and thus Vss can also pull down the preset potential on the first bit line BL1 through the first shunt unit 12, thereby preventing the preset potential from raising the potential of the first storage node a, the potential inversion is avoided, so that the interference of static noise on the memory can be reduced, and the static storage capacity of the memory is increased.

In this embodiment, the first channel width of the first pull-down transistor PD1 is greater than the second channel width of the first pass transistor PG1, thereby enabling the saturation current of the first pull-down transistor PD1 to be greater than the running sum current of the first pass transistor PG 1. Meanwhile, the third channel width of the second pull-down transistor PD2 is greater than the fourth channel width of the second pass transistor PG2, thereby enabling the saturation current of the second pull-down transistor PD2 to be greater than the saturation current of the second pass transistor PG 2. The beta ratio of the memory can be increased, and the static noise capacity of the memory can be increased.

In other embodiments, the first channel width of the first pull-down transistor may also be equal to the second channel width of the first pass transistor; the third channel width of the second pull-down transistor may also be equal to the fourth channel width of the second pass transistor.

In the operating method of the memory provided in the embodiment of the present invention, the memory circuit includes at least a first shunting unit and a second shunting unit. The first shunt unit can reduce the interference of static noise on the first shunt input end to the memory circuit; the second shunt unit can reduce the interference of static noise on the second shunt input end to the memory circuit. Therefore, the static noise has less interference with the memory circuit, and the static noise capacity of the memory circuit is large.

The working method of the memory of the invention also provides another embodiment, and the working method of the memory is shown in FIG. 12.

Referring to fig. 12, the same parts of this embodiment as those of the previous embodiment are not repeated herein, and the differences include:

in this embodiment, the memory further includes: a third bit line BL1a connected to the first shunt input; a fourth bit line BL2a connected to the second shunt input.

In this embodiment, the first shunt input terminal is not connected to the first bit line BL1, and the second shunt input terminal is not connected to the second bit line BL 2.

In this embodiment, the write operation of the memory is implemented by the first bit line BL1 and the second bit line BL2, and the read operation of the memory is implemented by the third bit line BL1a and the fourth bit line BL2 a.

In a write operation, the step of applying an operating potential on the first bit line BL1 and the second bit line BL2 comprises: a storage potential is applied to the first bit line BL1 and the second bit line BL2, forming a storage signal in the memory cell.

Specifically, in the write operation, the operating potential is a storage potential.

When the potential of the first storage node a is at the high level "1", the potential of the second connection point 2 is at the high level "1", so that the second pull-down transistor PD2 is turned on, the second storage node B applies the first potential Vss, which is at the low level "0", and thus, the potential of the second storage node B is at the low level "0", the potential of the first connection point 1 is at the low level "0", the first pull-down transistor PD1 is turned off, the first pull-up transistor PU1 is turned on, so that the first storage node a applies the second potential Vdd, which is at the high level "1", and thus the first storage node a stores the high level "1".

When the potential of the first storage node a is at the low level "0", the potential of the second connection point 2 is at the low level "0", so that the second pull-down transistor PD2 is turned off, the second pull-up transistor PU2 is turned on, the second storage node B applies the second potential Vdd, and the second potential is at the high level "1", so that the potential of the second storage node B is at the high level "1", the first pull-down transistor PD1 is turned on, the first pull-up transistor PU1 is turned off, so that the first storage node a applies the first potential Vss, and the first potential Vss is at the low level "0", so that the first storage node a stores the low level "0".

In the reading operation, the working method further includes: applying preset potentials to the third bit line BL1a and the fourth bit line BL2a, wherein the preset potentials act with the memory cell to form a read signal; the read signals are taken on the third bit line BL1a and fourth bit line BL2 a.

Specifically, in a read operation, a word line signal is applied to the word line WL, the word line signal is at a high level "1", the first pass transistor PG1 and the second shunt transistor FG1 are turned on, and the second pass transistor PG2 and the fourth shunt transistor FG2 are turned on.

A preset potential is applied to the third bit line BL1a and the fourth bit line BL2 a.

In this embodiment, the preset potential is a high level "1".

If the potential of the first storage node a is at the high level "1" and the potential of the second storage node B is at the low level "0", the potential of the second connection point 2 is at the high level "1", so that the second pull-down transistor PD2 and the third shunt transistor FD2 are turned on, the second shunt unit 22 is turned on, so that the fourth bit line BL2a applies the first potential Vss, which pulls down the preset potential on the fourth bit line BL2a due to the first potential Vss being at the low level "0", to form a read potential not, so that the fourth bit line BL2a outputs a low level "0", so that the read potential is not the same as the potential of the second storage node B. Meanwhile, since the potential of the first connection point 1 is at the low level "0", the first pull-down transistor PD1 and the first shunt transistor FD1 are turned off, and the preset potential on the third bit line BL1a is not pulled down by the first potential Vss, so that the third bit line BL1a outputs a read potential, which is at the high level "1", the read potential being the same as the potential of the first storage node a.

If the potential of the first storage node a is at a low level "0" and the potential of the second storage node B is at a high level "1", the potential of the first connection point 1 is at a high level "1", so that the first pull-down transistor PD1 and the first shunt transistor FD1 are turned on, the first shunt unit 12 is turned on, so that the first potential Vss is applied to the third bit line BL1a, and since the first potential Vss is at a low level "0", the first potential Vss pulls down a preset potential on the third bit line BL1a to form a read potential, even if the third bit line BL1a outputs a low level "0", so that the read potential is the same as the potential of the first storage node a. Meanwhile, since the potential of the second connection point 2 is at the low level "0", the second pull-down transistor PD2 and the third shunting unit FD2 are turned off, and the preset potential on the fourth bit line BL2a is not pulled down by the first potential Vss, so that the fourth bit line BL2a outputs a high level "1", forming a read potential. Therefore, the read potential is the same as the potential of the second storage node B.

As can be seen from the above analysis, in the present embodiment, the storage data in the memory cell 30 can be read through the third bit line BL1a and the fourth bit line BL2 a.

It should be noted that, in the read operation, the preset potential is applied to the third bit line BL1a and the fourth bit line BL2a, when the first storage node a is at a low level "0", the first shunting unit 12 is turned on, and the preset potential is connected to the first potential Vss through the first shunting unit 12, so that the preset potential is not applied to the first storage node a, and therefore the potential of the first storage node a is not raised, and therefore the potential of the first storage node a is not easily inverted, and further a read error is not easily generated, and therefore, the working method can reduce the interference of static noise on the memory, and further can increase the static noise capacity of the memory;

when the second storage node B is at a low level "0", the second shunting unit 22 is turned on, and the preset potential is connected to the second potential Vdd through the second shunting unit 22, so that the preset potential is not applied to the second storage node B, and thus the potential of the second storage node B is not raised, and the potential of the second storage node B is not easily inverted, and thus a reading error is not easily generated.

In summary, in the operating method of the memory provided in the embodiments of the present invention, the memory circuit at least includes a first shunting unit and a second shunting unit. The first shunt unit can reduce the interference of static noise on the first shunt input end to the memory circuit; the second shunt unit can reduce the interference of static noise on the second shunt input end to the memory circuit. It can be seen that static noise has less interference with the memory circuit, and the static noise capacity of the memory circuit is greater.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A memory structure, comprising:

a substrate, the substrate comprising: a first pull-down area, a second pull-down area, a first transmission area and a second transmission area, and a first division area or a second division area;

a first pull-down transistor located in a first pull-down region of a substrate, the first pull-down transistor having a first channel width, the first pull-down transistor comprising: the first pull-down gate structure is positioned on the substrate, and the first pull-down source region and the first pull-down drain region are respectively positioned in the substrate on two sides of the first pull-down gate structure and are used for applying a first potential;

A second pull-down transistor located in a second pull-down region of the substrate, the second pull-down transistor having a third channel width, the second pull-down transistor comprising: the second pull-down gate structure is positioned on the substrate, and the second pull-down source region and the second pull-down drain region are respectively positioned in the substrate at two sides of the second pull-down gate structure;

a first transfer transistor on the first transfer region substrate, the first transfer transistor having a second channel width, the first transfer transistor comprising: the first transmission grid structure is positioned on the substrate, and the first transmission source region and the first transmission drain region are positioned in the substrate on two sides of the first transmission grid structure, and the first transmission source region is electrically connected with the first pull-down drain region;

a second pass transistor on a second pass region substrate, the second pass transistor having a fourth channel width, the second pass transistor comprising: a second transfer gate structure on the substrate; the second transmission source region and the second transmission drain region are positioned in the substrate on two sides of the second transmission gate structure, and the second transmission source region is electrically connected with the second pull-down drain region;

The fourth channel width is less than the third channel width;

or the second channel width is less than the first channel width;

or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width;

a word line connecting the first transfer gate structure and the second transfer gate structure;

a first bit line connected to the first transfer drain region;

a second bit line connected to the second transfer drain region;

a first shunting structure located over a first shunting region of a substrate, the first shunting structure comprising a first connection and a second connection, the first connection for applying the first potential; the second connecting part is electrically connected with the first bit line, or the memory further comprises a third bit line, and the second connecting part is connected with the third bit line;

a second shunt structure located on a second shunt area of the substrate, the second shunt structure comprising a third connection and a fourth connection, the third connection for applying the first potential; the fourth connection portion is electrically connected to the second bit line, or the memory further includes a fourth bit line, and the fourth connection portion is connected to the fourth bit line.

2. The memory structure of claim 1, wherein the first transmission region substrate has a first transmission fin portion thereon, the first transmission gate structure crosses over the first transmission fin portion, and the first transmission source region and the first transmission drain region are respectively located in the first transmission fin portion at two sides of the first transmission gate structure;

the second transmission region substrate is provided with a second transmission fin part, the second transmission grid electrode structure stretches across the second transmission fin part, and the second transmission source region and the second transmission drain region are respectively positioned in the second transmission fin parts on two sides of the second transmission grid electrode structure;

the first pull-down region substrate comprises a first pull-down fin portion, the first pull-down gate structure stretches across the first pull-down fin portion and is located on partial side wall and top surface of the first pull-down fin portion, and the first pull-down source region and the first pull-down drain region are respectively located in the first pull-down fin portions on two sides of the first pull-down gate structure;

the second pull-down region substrate comprises a second pull-down fin portion, the second pull-down gate structure stretches across the second pull-down fin portion and is located on the partial side wall and the top surface of the second pull-down fin portion, and the second pull-down source region and the second pull-down drain region are located in the second pull-down fin portions on two sides of the second pull-down gate structure respectively.

3. The memory structure of claim 2, wherein the substrate further comprises a first connection region and a second connection region;

the first connecting region, the first pull-down region and the first transmission region are in contact with each other, and the second connecting region, the second pull-down region and the second transmission region are in contact;

the first connection region substrate includes a first connection fin portion connected with the first pull-down fin portion; the first transmission fin part is connected with the first pull-down fin part;

the memory structure further comprises: a first connection gate structure crossing the first connection fin portion, the first connection gate structure being connected to the first transmission gate structure; a first connection source region and a first connection drain region in the first connection fin portion at both sides of the first connection gate structure, the first connection drain region being connected to the first pull-down drain region, the first connection source region not being in contact with the first bit line;

the second connection region substrate comprises a second connection fin portion, and the second connection fin portion is connected with the second pull-down fin portion; the second transmission fin part is connected with the second pull-down fin part;

the memory structure further comprises: a second connection gate structure crossing the second connection fin portion, the second connection gate structure being connected to the second transmission gate structure; and a second connection source region and a second connection drain region in the second connection fin part at two sides of the second connection gate structure, wherein the second connection drain region is connected with the second pull-down drain region, and the second connection source region is not in contact with the second bit line.

4. The memory structure of claim 2, wherein the first pull-down fin, the second pull-down fin, the first transmission fin, and the second transmission fin have the same width, and wherein the first pull-down fin, the second pull-down fin, the first transmission fin, and the second transmission fin have the same height; the number of the first pull-down fin portions is more than that of the first transmission fin portions, and the number of the second pull-down fin portions is more than that of the second transmission fin portions.

5. The memory structure of claim 1, wherein the substrate further comprises: a first pull-up region and a second pull-up region;

the memory structure further comprises: a first pull-up transistor located in a first pull-up region of a substrate; the first pull-up transistor includes: a first pull-up gate structure on the substrate, the first pull-up gate structure being electrically connected to the first pull-down gate structure; the first pull-up drain region and the first pull-up source region are respectively positioned in the substrate on two sides of the first pull-up gate structure, the first pull-up source region is electrically connected with the first pull-down drain region, the first pull-up drain region is used for applying a second potential, and the second potential is greater than the first potential;

A second pull-up transistor located in a second pull-up region of the substrate, the second pull-up transistor comprising: the second upper pull-up gate structure is positioned on the substrate and is electrically connected with the second lower pull-down gate structure; and the second pull-up source region and the second pull-up drain region are respectively positioned in the substrates at two sides of the second pull-up gate structure, the second pull-up drain region is electrically connected with the second pull-down drain region, and the second pull-up source region is used for applying the second potential.

6. The memory structure of claim 1, wherein the first shunting structure comprises: a first shunt transistor comprising a first shunt region substrate

A first shunt gate structure electrically connected to the first pull-down gate structure; the first shunt source region and the first shunt drain region are respectively positioned in the first shunt area substrates on two sides of the first shunt gate structure, and the first connecting part comprises the first shunt source region;

a second shunt transistor, the second shunt transistor comprising: a second shunt gate structure on the second shunt area substrate, the second shunt gate structure electrically connected to the second transfer gate structure; a second shunt source region and a second shunt drain region in the substrate of the second shunt region on two sides of the second shunt gate structure, wherein the second connection portion comprises the second shunt drain region;

A first source-drain connection line connecting the second shunt source region and the first shunt drain region;

the second shunting structure comprises: a third shunt transistor, the third shunt transistor comprising: a third shunt gate structure located on the second shunt area substrate, the third shunt gate structure being electrically connected to the second pull-down gate structure; a third shunt source region and a third shunt drain region which are respectively positioned in the substrate of the second shunt region at two sides of the third shunt gate structure, wherein the third connecting part comprises the third shunt source region;

a fourth shunt transistor, the fourth shunt transistor comprising: a fourth shunt gate structure located on the second shunt area substrate, the fourth shunt gate structure being electrically connected to the second pull-down gate structure; a fourth shunt source region and a fourth shunt drain region which are respectively positioned in the substrate of the second shunt region at two sides of the fourth shunt gate structure, wherein the fourth connecting part comprises the fourth shunt drain region;

and the second source-drain connecting line is connected with the fourth shunt source region and the third shunt drain region.

7. A method of forming the memory structure of any one of claims 1 to 6, comprising:

Providing a substrate, the substrate comprising: a first pull-down area, a second pull-down area, a first transmission area and a second transmission area, and a first division area or a second division area;

forming a first pull-down transistor at the substrate first pull-down region, the first pull-down transistor having a first channel width, the step of forming the first pull-down transistor comprising: forming a first pull-down gate structure on the substrate; respectively forming a first pull-down source region and a first pull-down drain region in the substrate at two sides of the first pull-down gate structure, wherein the first pull-down source region is used for applying a first potential;

forming a first transfer transistor on the first transfer region substrate, the first transfer transistor having a second channel width, the forming the first transfer transistor comprising: forming a first transmission grid structure on the substrate, and respectively forming a first transmission source region and a first transmission drain region in the substrate at two sides of the first transmission grid structure, wherein the first transmission source region is electrically connected with the first pull-down drain region;

forming a second pull-down transistor in a second pull-down region of the substrate, the second pull-down transistor having a third channel width, the step of forming the second pull-down transistor comprising: forming a second pull-down gate structure on the substrate, and respectively forming a second pull-down source region and a second pull-down drain region in the substrate at two sides of the second pull-down gate structure, wherein the second pull-down gate structure is electrically connected with the first pull-down drain region, the second pull-down drain region is electrically connected with the first pull-down gate structure, and the second pull-down source region is used for applying the first potential;

Forming a second pass transistor on the second pass region substrate, the second pass transistor having a fourth channel width, the forming the second pass transistor comprising: forming a second transmission grid structure on the substrate, and respectively forming a second transmission source region and a second transmission drain region in the substrate at two sides of the second transmission grid structure, wherein the second transmission source region is electrically connected with the second pull-down drain region;

the fourth channel width is less than the third channel width;

or the second channel width is less than the first channel width;

forming a word line connecting the first transfer gate structure and the second transfer gate structure after forming the first transfer transistor and the second transfer transistor;

forming a first bit line connected to the first transfer drain region;

forming a second bit line connecting the second transfer drain regions;

forming a first shunting structure on a first shunting region of a substrate, the first shunting structure comprising a first connection and a second connection, the first connection for applying the first potential; the second connecting part is electrically connected with the first bit line, or the memory further comprises a third bit line, and the second connecting part is connected with the third bit line;

Forming a second shunt structure on the substrate second shunt area, the second shunt structure comprising a third connection and a fourth connection, the third connection for applying the first potential; the fourth connection portion is electrically connected to the second bit line, or the memory further includes a fourth bit line, and the fourth connection portion is connected to the fourth bit line.

8. A memory structure, comprising:

a substrate including a storage region, a first transfer region, a second transfer region, and a diversion region;

a first pass transistor located in the first pass region of the substrate, the first pass transistor comprising: the first transmission grid structure is positioned on the first transmission area substrate, and the first transmission drain area and the first transmission source area are respectively positioned in the substrates at two sides of the first transmission grid structure;

a first bit line electrically connected to the first transfer drain region;

the second transmission transistor is positioned in a second transmission region of the substrate, the second transmission transistor is positioned on a second transmission grid structure on the substrate of the second transmission region, and a second transmission drain region and a second transmission source region are respectively positioned in the substrate at two sides of the second transmission grid structure, and the second transmission source region is electrically connected with the second connecting part;

a second bit line electrically connected to the second transfer drain region;

the shunt area at least comprises a first shunt area or a second shunt area, the substrate first shunt area is provided with a first shunt structure, and the first shunt structure comprises: the first shunt input part is used for applying a preset potential, and the first shunt output part is electrically connected with the grounding part; the substrate second shunt region has a second shunt structure comprising: a second shunt input portion for applying the preset potential, and a second shunt output portion electrically connected to the ground portion.

9. The memory structure of claim 8, wherein the first shunt input is electrically connected to the first bit line; the second shunt input is electrically connected to the second bit line.

10. The memory structure of claim 8, further comprising: a third bit line connected to the first shunt input; a fourth bit line connected to the second shunt input.

11. The memory structure of claim 8, wherein the storage area comprises: a first pull-down region and a second pull-down region, the memory structure comprising: a first pull-down transistor located in a first pull-down region of the substrate, the first pull-down transistor comprising: a first pull-down gate structure located on the first pull-down region substrate; a first pull-down source region and a first pull-down drain region respectively located in the substrate at two sides of the first pull-down gate structure, the first connection portion including the first pull-down drain region, the ground portion including: the first pull-down source region;

a second pull-down transistor located in a second pull-down region of the substrate, the second pull-down transistor comprising: a second pull-down gate structure on the second pull-down region substrate, the second pull-down gate structure being electrically connected to the first pull-down drain region; and the second pull-down source region and the second pull-down drain region are respectively positioned in the substrates at two sides of the second pull-down gate structure, the second pull-down drain region is electrically connected with the first pull-down gate structure, the second connecting part comprises the second pull-down drain region, and the grounding part comprises the second pull-down source region.

12. The memory structure of claim 11, in which the first pull-down transistor has a first channel width, the first pass transistor has a second channel width, the second pull-down transistor has a third channel width, the second pass transistor has a fourth channel width; the fourth channel width is less than the third channel width; or the second channel width is less than the first channel width; or the second channel width is less than the first channel width, and the fourth channel width is less than the third channel width.

13. The memory structure of claim 11, wherein the first transmission region substrate comprises a first transmission fin, the first transmission gate structure crosses over the first transmission fin, the first transmission gate structure is located on partial side wall and top surface of the first transmission fin, and the first transmission source region and the first transmission drain region are respectively located in the first transmission fin at two sides of the first transmission gate structure;

the second transmission region substrate comprises a second transmission fin part, the second transmission gate structure crosses the second transmission fin part, the second transmission gate structure is located on the partial side wall and the top surface of the second transmission fin part, and the second transmission source region and the second transmission drain region are respectively located in the second transmission fin parts on two sides of the second transmission gate structure;

The first pull-down region substrate comprises a first pull-down fin portion, the first pull-down gate structure stretches across the first pull-down fin portion, the first pull-down gate structure is located on partial side wall and top surface of the first pull-down fin portion, and the first pull-down source region and the first pull-down drain region are respectively located in the first pull-down fin portions on two sides of the first pull-down gate structure;

the second pull-down region substrate comprises a second pull-down fin portion, the second pull-down gate structure crosses over the second pull-down fin portion, the second pull-down gate structure is located on the partial side wall and the top surface of the second pull-down fin portion, and the second pull-down source region and the second pull-down drain region are respectively located in the second pull-down fin portions on two sides of the second pull-down gate structure;

the widths of the first pull-down fin portion, the second pull-down fin portion, the first transmission fin portion and the second transmission fin portion are the same, and the heights of the first pull-down fin portion, the second pull-down fin portion, the first transmission fin portion and the second transmission fin portion are the same; the number of the first pull-down fin portions is more than that of the first transmission fin portions, and the number of the second pull-down fin portions is more than that of the second transmission fin portions.

14. The memory structure of claim 11, wherein the memory region further comprises a first pull-up region and a second pull-up region; the memory structure further comprises: a first pull-up load located at a first pull-up region of the substrate, the first pull-up load comprising: a first load input portion for inputting a second potential, the second potential being greater than the first potential; a first load output portion electrically connected to the first pull-down transistor drain region;

a second pull-up load located at a second pull-up region of the substrate, the second pull-up load comprising: a second load input section for inputting the second potential; a second load output portion electrically connected with the second pull-down transistor drain region.

15. The memory structure of claim 14, wherein the first pull-up load comprises a first pull-up transistor, the first pull-up transistor comprising: a first pull-up gate structure on the substrate, the first pull-up gate structure being electrically connected to the first pull-down gate structure; the first pull-up drain region and the first pull-up source region are positioned in the substrate on two sides of the first pull-up gate structure, the first load output part comprises the first pull-up source region, and the first load input part comprises the first pull-up drain region;

The second load comprises a second pull-up transistor comprising: a second pull-up gate structure on the substrate, the second pull-up gate structure being electrically connected to the second pull-down gate structure; a second pull-up source region and a second pull-up drain region respectively located in the substrate at two sides of the second pull-up gate structure, the second load input portion includes the second pull-up drain region, and the second load output portion includes the second pull-up source region;

or, the first pull-up load includes a first pull-up resistor, and the first pull-up resistor includes: a first pull-up doped region and a second pull-up doped region in the substrate, the first load input including the first pull-up doped region, the first load output including the second pull-up doped region;

the second pull-up load includes a second pull-up resistor, and the second pull-up resistor includes: and the second load input part comprises the third pull-up doped region, and the second load output part comprises the fourth pull-up doped region.

16. The memory structure of claim 11, wherein the first shunting structure comprises: a first shunt transistor located in a first shunt region of a substrate, the first shunt transistor comprising: a first shunt gate structure located on the first shunt area substrate, the first shunt gate structure being electrically connected to the first pull-down gate structure; the first shunt output part comprises a first shunt source region and a first shunt drain region which are respectively positioned in the first shunt area substrates at two sides of the first shunt gate structure;

The first shunting structure further comprises a second shunting transistor located in the first shunting region, the second shunting transistor comprising: a second shunt gate structure located on the first shunt area substrate, the second shunt gate structure electrically connected to the second transfer gate structure; the second shunt source region and the second shunt drain region are respectively positioned in the first shunt region substrate on two sides of the second shunt gate structure, the second shunt source region is electrically connected with the first shunt drain region, and the first shunt input part comprises the second shunt drain region;

the second shunting structure comprises: the third shunt transistor is positioned in the substrate second shunt area, and the fourth shunt transistor is positioned in the substrate second shunt area;

the third shunt transistor includes: a third shunt gate structure located on the second shunt area substrate, the third shunt gate structure being electrically connected to the second pull-down gate structure; a third shunt source region and a third shunt drain region which are respectively positioned in the substrate of the second shunt region at two sides of the third shunt gate structure, wherein the second shunt output part comprises the third shunt source region;

the fourth shunt transistor includes: a fourth shunt gate structure located on the second shunt area substrate, the fourth shunt gate structure being electrically connected to the second transfer gate structure; and the fourth shunt source region and the fourth shunt drain region are respectively positioned in the substrates at two sides of the fourth shunt gate structure, the second shunt input part comprises the fourth shunt drain region, and the fourth shunt source region is electrically connected with the third shunt drain region.

17. The memory structure of claim 16, further comprising: a first source line connecting the first shunt source region and the first pull-down source region; and a second source line connecting the third shunt source region and the second pull-down source region.

18. A method of forming the memory structure of any one of claims 8 to 17, comprising:

providing a substrate, wherein the substrate comprises a storage area, a first transmission area, a second transmission area and a diversion area, and the diversion area at least comprises a first diversion area or a second diversion area;

forming a storage structure on the substrate storage area, wherein the storage structure comprises a first connecting part and a second connecting part;

forming a first transfer transistor in a first transfer region of the substrate, the step of forming the first transfer transistor comprising: forming a first transmission gate structure on the substrate, and forming a first transmission source region and a first transmission drain region in the substrate on two sides of the first transmission gate structure respectively, wherein the first transmission source region is electrically connected with the first connecting part;

forming a second pass transistor in the substrate second pass region, the step of forming the second pass transistor comprising: forming a second transmission gate structure on the substrate, and forming a second transmission drain region and a second transmission source region in the substrate on two sides of the second transmission gate structure respectively, wherein the second transmission source region is electrically connected with the second connecting portion;

Forming a first shunting structure at the substrate first shunting region;

or forming a second shunt structure in the substrate first shunt area;

or forming a first shunt structure in the substrate first shunt area and forming a second shunt structure in the substrate first shunt area; the first shunting structure comprises: a first shunt input for inputting a preset potential and a first shunt output for applying a first potential; the second shunting structure comprises: a second shunt input portion for inputting the preset potential and a second shunt output portion for applying the first potential;

forming a word line connecting the first transfer gate structure and the second transfer gate structure;

forming a first bit line connected to the first transfer drain region;

and forming a second bit line connected with the second transmission drain region.

19. A memory circuit, comprising:

a storage unit, the storage unit comprising: the first connecting end, the second connecting end and the grounding end, wherein the grounding end is used for applying a first electric potential;

a first transfer transistor, the first transfer transistor comprising: the first transmission grid, the first transmission source electrode and the first transmission drain electrode, wherein the first transmission source electrode is connected with the first connecting end;

A first bit line connected to the first transmission drain;

a second pass transistor, the second pass transistor comprising: the second transmission source electrode is connected with the second connecting end;

a word line connecting the first and second transfer gates;

a second bit line connected to the second transfer drain;

the flow dividing unit at least comprises a first flow dividing unit or a second flow dividing unit; the first shunting unit includes: the first shunt output end is connected with the grounding end, and the first shunt input end is used for inputting a preset potential; the second flow dividing unit comprises: the second shunt output end is connected with the grounding end, and the second shunt input end is used for inputting the preset potential.

20. The memory circuit of claim 19, wherein the first shunt input is connected to the first bit line and the second shunt input is connected to the second bit line.

21. The memory circuit of claim 19, wherein the storage unit comprises: a first pull-down transistor, the first pull-down transistor comprising: a first pull-down gate; a first pull-down drain connected to the first transmission source; a first pull-down source connected to the first potential;

A second pull-down transistor, the second pull-down transistor comprising: a second pull-down gate connected to the first pull-down drain; a second pull-down source connected to the first shunt output; a second pull-down drain connected to the first pull-down gate.

22. The memory circuit of claim 21, wherein the first shunting unit comprises: a first shunt transistor, the first shunt transistor comprising: a first shunt gate connected to the first pull-down gate; the first shunt source electrode is connected with the first shunt output end;

the first shunting unit further includes a second shunting transistor, the second shunting transistor including: a second shunt gate connected to the first transfer gate; a second shunt source connected to the first shunt drain; a second shunt drain connected to the first shunt input terminal;

the second flow dividing unit comprises: a third shunt transistor, the third shunt transistor comprising: a third shunt gate connected to the second pull-down gate; the third shunt source electrode is connected with the second shunt output end;

A fourth shunt transistor, the fourth shunt transistor comprising: a fourth shunt gate connected with the second transfer gate; a fourth shunt source connected to the third shunt drain; a fourth shunt drain connected to the second shunt input.

23. The memory circuit of claim 19, further comprising: a third bit line connected to the first shunt input; a fourth bit line connected to the second shunt input.

24. The memory circuit of claim 21, wherein the first shunting unit comprises: a first shunt transistor, the first shunt transistor comprising: a first shunt gate connected to the first pull-down gate; the first shunt source electrode is connected with the first shunt output end; the first shunt drain electrode is connected with the first shunt input end;

the second flow dividing unit comprises: a third shunt transistor, the third shunt transistor comprising: a third shunt gate electrically connected to the second pull-down gate; a third shunt source connected to the second shunt output terminal; and the third shunt drain electrode is connected with the second shunt input end.

25. The memory circuit of claim 21, wherein the memory cell further comprises:

a first pull-up load, the first pull-up load comprising: a first load input terminal for inputting a second potential, the second potential being greater than the first potential; the first load output end is connected with the drain electrode of the first pull-down transistor;

a second pull-up load, the second pull-up load comprising: a second load input terminal for inputting the second potential; and the second load output end is connected with the drain electrode of the second pull-down transistor.

26. The memory circuit of claim 25, wherein the first pull-up load comprises a first pull-up transistor, the first pull-up transistor comprising: the first pull-up grid is connected with the first pull-down grid; the first pull-up drain is connected with the first load input end, and the first pull-up source is connected with the first load output end;

the second pull-up load comprises a second pull-up transistor comprising: the second pull-up grid is connected with the second pull-down grid; the second pull-up drain is connected with the second load input end; the second pull-up drain is connected with the second load output end;

Alternatively, the first pull-up load includes a first resistor, and the first resistor includes: the first resistor input end is connected with the first load input end, and the first resistor output end is connected with the first load output end;

the second pull-up load is a second resistor, and the second resistor includes: the second resistor input end is connected with the second load input end, and the second resistor output end is connected with the second load output end.

27. A method of operating a memory circuit, comprising:

providing a memory circuit as recited in claim 21;

applying a first potential to the ground terminal;

applying a word line potential on the word line, the word line potential being greater than the first potential;

applying an operating potential on the first bit line and the second bit line.

28. The method of operating a memory circuit of claim 27 wherein said first shunt input is connected to said first bit line; the second shunt input is connected to the second bit line; the step of applying an operating potential on the first bit line and the second bit line comprises: applying preset potentials on the first bit line and the second bit line, wherein the preset potentials interact with a storage unit to form a reading signal;

The working method further comprises the following steps: acquiring the read signal through the first bit line and the second bit line; the step of acquiring the read signal through the first bit line and the second bit line includes: applying a preset potential to the first bit line and the second bit line, wherein the preset potential is greater than the first potential, and the preset potential acts with the memory cell to form a read signal; the read signal is acquired on the first bit line and the second bit line.

29. The method of operating a memory circuit of claim 27, wherein the memory circuit comprises: a first shunting unit and a second shunting unit;

the memory circuit further comprises: a third bit line connected to the first shunt input terminal; a fourth bit line connected to the second shunt input terminal;

the step of applying an operating potential on the first bit line and the second bit line comprises: applying a storage potential on the first bit line and the second bit line to form a storage signal in the memory cell; after forming a storage signal in the memory cell, the operating method further includes: applying a preset potential to the third bit line and the fourth bit line, wherein the preset potential is greater than the first potential, and the preset potential acts with the memory cell to form a read signal; the read signal is acquired on the third bit line and the fourth bit line.

30. The method of operating a memory circuit of claim 27, wherein said memory cell further comprises: a first pull-up load, the first pull-up load comprising: the first load output end is connected with the drain region of the first pull-down transistor;

a second pull-up load, the second pull-up load comprising: the second load output end is connected with the drain region of the second pull-down transistor;

before applying an operating potential on the first bit line and the second bit line, the operating method further comprises: applying a second potential to the first load input and the second load input, the second potential being greater than the first potential.