CN108074930A

CN108074930A - Memory construction and forming method thereof, memory circuitry and its method of work

Info

Publication number: CN108074930A
Application number: CN201611011878.0A
Authority: CN
Inventors: 王楠
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2016-11-17
Filing date: 2016-11-17
Publication date: 2018-05-25
Anticipated expiration: 2036-11-17
Also published as: CN108074930B

Abstract

The present invention provides a kind of memory construction and forming method thereof, memory circuitry and its method of work, wherein, memory construction includes：First pull-down transistor, first pull-down transistor have the first channel width；Second pull-down transistor, second pull-down transistor have triple channel width；First transmission transistor, first transmission transistor have the second channel width；Second transmission transistor, second transmission transistor have the 4th channel width；4th channel width is less than the triple channel width；Or second channel width is less than first channel width；Or second channel width is less than first channel width, and the 4th channel width is less than the triple channel width.The memory construction can increase the static noise capacity of the memory.

Description

Memory construction and forming method thereof, memory circuitry and its method of work

Technical field

The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of memory construction and forming method thereof, storages Device circuit and its method of work.

Background technology

With the development of information technology, information memory capacity sharply increases.The increase of information memory capacity promotes memory Rapid development, while higher requirement also is proposed to the stability of memory.

Basic static memory (Static Random Access Memory, SRAM) depends on six transistors, this Six transistors form two cross-linked phase inverters.Each phase inverter includes：One pull up transistor, a lower crystal pulling Pipe and an access transistor.

In order to obtain enough antijamming capability and read stability, the transistor for forming memory is mostly fin field Effect transistor (Fin Field-Effect Transistor, FinFET).In FinFET transistors, grid is covering fin The 3D frameworks on three, portion surface, can greatly improve circuit control.The applications of FinFET in memory can improve memory Data storage stability and integrated level.

The static noise capacity of static memory is the outstanding feature for weighing the anti-static noise interference performance of static memory. The static noise capacity of static memory is related with the beta rates of static memory, and beta rates refer to the drop-down of static memory The ratio of the saturation current of transistor and the saturation current to pull up transistor.And the saturation current of transistor and the width of transistor are long Than related, the ratio of the breadth length ratio of transistor between the width and channel length of the raceway groove of transistor, the breadth length ratio of transistor Bigger, the saturation current of transistor is bigger.It can be seen that pull-down transistor and the ratio of transmission transistor breadth length ratio can influence it is quiet The static noise capacity of state memory.

However, the memory that the prior art is formed, which still has, reads the shortcomings that capacity of Noise is small, and read stability is poor.

The content of the invention

The present invention solves the problems, such as to be to provide a kind of memory construction and forming method thereof, memory circuitry and its work side Method, to improve static noise capacity.

To solve the above problems, the present invention provides a kind of memory construction, including：Substrate, the substrate include：Under first Draw area, the second drop-down area, the first transmission range and the second transmission range；First pull-down transistor in area, institute are pulled down positioned at substrate first The first pull-down transistor is stated with the first channel width, first pull-down transistor includes：First on the substrate Pulldown gate structure, respectively the first drop-down source region and first time bleedout in the substrate of the first pulldown gate structure both sides Area, the first drop-down source region is for the first current potential of application；Pull down second pull-down transistor in area positioned at substrate second, described the Two pull-down transistors have triple channel width, and second pull-down transistor includes：The second drop-down on the substrate Gate structure, respectively in the substrate of the second pulldown gate structure both sides second drop-down source region and second drop-down drain region, The second pulldown gate structure is electrically connected with the described first drop-down drain region, the second drop-down drain region and the described first drop-down grid Pole structure electrical connection, the second drop-down source region are used to apply first current potential；First on the first transmission range substrate Transmission transistor, first transmission transistor have the second channel width, and first transmission transistor includes：Positioned at described The first transmission gate structure on substrate, the first transmission source region in the described first transmission gate structure both sides substrate and the One transmission drain region, the first transmission source region are electrically connected with the described first drop-down drain region；On the second transmission range substrate Two transmission transistors, second transmission transistor have the 4th channel width, and second transmission transistor includes：Positioned at institute State the second transmission gate structure on substrate；The second transmission source region in the described second transmission gate structure both sides substrate and Second transmission drain region, the second transmission source region are electrically connected with the described second drop-down drain region；4th channel width is less than institute State triple channel width；Or second channel width is less than first channel width；Or second channel width Less than first channel width, and the 4th channel width is less than the triple channel width；Connect first transmission The wordline of gate structure and the second transmission gate structure；Connect first bit line in the first transmission drain region；Described in connection Second bit line in the second transmission drain region.

Optionally, on the first transmission range substrate have first transmission fin, it is described first transmission gate structure across The first transmission fin, the first transmission source region and the first transmission drain region are located at the described first transmission gate structure two respectively In first transmission fin of side；The second transmission range substrate has the second transmission fin, and the second transmission gate structure is horizontal Fin is transmitted across described second, the second transmission source region and the second transmission drain region are located at the described second transmission gate structure respectively In second transmission fin of both sides；First drop-down area's substrate includes the first drop-down fin, the first pulldown gate structure Across the described first drop-down fin, and positioned at the described first drop-down fin partial sidewall and top surface, the first drop-down source Area and the first drop-down drain region are pulled down positioned at the first of the first pulldown gate structure both sides in fin respectively；Described second Pulling down area's substrate includes the second drop-down fin, and the second pulldown gate structure is located at institute across the described second drop-down fin The second drop-down fin partial sidewall and top surface are stated, the second drop-down source region and the second drop-down drain region are located at institute respectively In the second drop-down fin for stating the second pulldown gate structure both sides.

Optionally, the substrate further includes the first bonding pad and the second bonding pad；First bonding pad, the first drop-down area It contacts with each other with first transmission range, second bonding pad, the second drop-down area and second transmission range contact；Described One bonding pad substrate includes the first connection fin, and the first connection fin is connected with the described first drop-down fin；Described first Transmission fin is connected with the described first drop-down fin；The memory construction further includes：Across the of the described first connection fin One connection gate structure, the first connection gate structure are connected with the described first transmission gate structure；Connect positioned at described first It connects the first connection source region that gate structure both sides first are connected in fin and is connected drain region, the first connection drain region and institute with first The connection of the first drop-down drain region is stated, the first connection source region is not contacted with first bit line；The second bonding pad substrate bag The second connection fin is included, the second connection fin is connected with the described second drop-down fin；It is described second transmission fin with it is described Second drop-down fin connection；The memory construction further includes：Second across the described second connection fin connects gate structure, The second connection gate structure is connected with the described second transmission gate structure；Positioned at the described second connection gate structure both sides the The second connection source region in two connection fins is connected drain region with second, and the second connection drain region connects with the described second drop-down drain region It connects, the second connection source region is not contacted with second bit line.

Optionally, the width of the first drop-down fin, the second drop-down fin, the first transmission fin and the second transmission fin Identical, the height that the first drop-down fin, the second drop-down fin, the first transmission fin and second transmit fin is identical；It is described First drop-down fin number is more than the number of the described first transmission fin, and the number of the second drop-down fin is more than described second Transmit the number of fin.

Optionally, the substrate further includes：First pull-up area and the second pull-up area；The memory construction further includes：Position Pull up area in substrate first first pulls up transistor；Described first pull up transistor including：First on the substrate Gate structure is pulled up, the first pull-up gate structure is electrically connected with the first pulldown gate structure；It is located at described the respectively The first pull-up drain region and the first pull-up source region in one pull-up gate structure both sides substrate, the first pull-up source region and described the Once bleedout area is electrically connected, and for applying the second current potential, second current potential is more than the first current potential in the first pull-up drain region；Position In second pulling up transistor for the substrate second pull-up area, described second pull up transistor including：Second on substrate Gate structure is pulled up, the second pull-up gate structure is electrically connected with the second pulldown gate structure；It is located at described the respectively The second pull-up source region and the second pull-up drain region in two pull-up gate structure both sides substrates, the second pull-up drain region and described the Two drop-down drain region electrical connections, the second pull-up source region are used to apply second current potential.

Optionally, the substrate includes at least：First shunting zone or the second shunting zone；Have on the substrate of first shunting zone There is the first flow dividing structure, first flow dividing structure includes first connecting portion and second connecting portion, and the first connecting portion is used for Apply first current potential；The second connecting portion is electrically connected with first bit line or the memory further includes the 3rd Bit line, the second connecting portion connect the 3rd bit line；There is the second flow dividing structure on the substrate of second shunting zone, it is described Second flow dividing structure includes the 3rd connecting portion and the 4th connecting portion, and the 3rd connecting portion is used to apply first current potential；Institute State that the 4th connecting portion is electrically connected with second bit line or the memory further includes the 4th bit line, the 4th connecting portion Connect the 4th bit line.

Optionally, first flow dividing structure includes：First shunting transistor, first shunting transistor include being located at The first shunting gate structure on the substrate of first shunting zone, the first shunting gate structure and first pulldown gate Structure is electrically connected；The the first shunting source region and the being located at respectively in described first shunting the first shunting zone of gate structure both sides substrate One shunting drain region, the first connecting portion include the described first shunting source region；Second shunting transistor, the second shunting crystal Pipe includes：On the substrate of second shunting zone second shunting gate structure, it is described second shunting gate structure with it is described Second transmission gate structure electrical connection；The second shunting in described second shunting the second shunting zone of gate structure both sides substrate Source region and the second shunting drain region, the second connecting portion include the described second shunting drain region；Connect it is described second shunting source region with The first source and drain connecting line in the first shunting drain region；Second flow dividing structure includes：3rd shunting transistor, the described 3rd Shunting transistor includes：The 3rd shunting gate structure on the 3rd shunting zone substrate, the 3rd shunting grid knot Structure is electrically connected with the second pulldown gate structure；It is located at the described 3rd shunting the second shunting zone of gate structure both sides substrate respectively In the 3rd shunting source region and the 3rd shunting drain region, the 3rd connecting portion include the described 3rd shunting source region；4th shunting is brilliant Body pipe, the 4th shunting transistor include：The 4th shunting gate structure on the substrate of second shunting zone, described the Four shunting gate structures are electrically connected with the second pulldown gate structure；It is located at the described 4th shunting gate structure both sides the respectively The 4th shunting source region and the 4th shunting drain region in two shunting zone substrates, the 4th connecting portion include the described 4th shunting and leak Area；Connect the second source and drain connecting line of the 4th shunting source region and the 3rd point of drain source area.

Correspondingly, the present invention also provides it is a kind of formed memory construction method, including：Substrate, the substrate bag are provided It includes：First drop-down area, the second drop-down area, the first transmission range and the second transmission range；First is formed in the substrate first drop-down area The step of pull-down transistor, first pull-down transistor has the first channel width, forms first pull-down transistor, wraps It includes：The first pulldown gate structure is formed over the substrate；Shape is distinguished in the substrate of the first pulldown gate structure both sides Into the first drop-down source region and the first drop-down drain region, the first drop-down source region is for the first current potential of application；In the described first transmission The first transmission transistor is formed on area's substrate, first transmission transistor has the second channel width, forms described first and passes The step of defeated transistor, includes：The first transmission gate structure is formed over the substrate, and gate structure two is transmitted described first The first transmission source region and the first transmission drain region, the first transmission source region and first time bleedout are respectively formed in the substrate of side Area is electrically connected；The second pull-down transistor is formed in the substrate second drop-down area, second pull-down transistor has the 3rd ditch The step of road width, formation second pull-down transistor, includes：The second pulldown gate structure is formed over the substrate, in institute It states and the second drop-down source region and the second drop-down drain region is respectively formed in the substrate of the second pulldown gate structure both sides, second drop-down Gate structure is electrically connected with the described first drop-down drain region, and the second drop-down drain region is electrically connected with the first pulldown gate structure It connects, the second drop-down source region is used to apply first current potential；It is brilliant that the second transmission is formed on the second transmission range substrate Body pipe, second transmission transistor have the 4th channel width, and forming second transmission transistor includes：In the substrate It is upper to form the second transmission gate structure, be respectively formed in the described second transmission gate structure both sides substrate the second transmission source region and Second transmission drain region, the second transmission source region are electrically connected with the described second drop-down drain region；4th channel width is less than institute State triple channel width；Or second channel width is less than first channel width；Or second channel width Less than first channel width, and the 4th channel width is less than the triple channel width；Form first transmission After transistor and the second transmission transistor, the connection first transmission gate structure and the second transmission gate structure are formed Wordline；Form first bit line in connection the first transmission drain region；Form second bit line in connection the second transmission drain region.

The present invention also provides a kind of memory construction, including：Substrate, the substrate include memory block, the first transmission range, the Two transmission ranges and shunting zone；Storage organization positioned at the substrate storage region, the storage organization include first connecting portion, second Connecting portion and grounding parts, the grounding parts are for the first current potential of application；The first transmission positioned at first transmission range of substrate is brilliant Body pipe, first transmission transistor include：The first transmission gate structure on the first transmission range substrate, difference position The first transmission drain region and the first transmission source region in the described first transmission gate structure both sides substrate, the first transmission source region It is electrically connected with the first connecting portion；The first bit line being electrically connected with the described first transmission drain region；It is passed positioned at the substrate second Second transmission transistor in defeated area, second transmission transistor are located at the second transmission grid on the second transmission range substrate Structure, the second transmission drain region in the described second transmission gate structure both sides substrate and the second transmission source region, described respectively Second transmission source region is electrically connected with the second connecting portion；With the described first transmission gate structure and the second transmission grid knot The wordline of structure electrical connection；The second bit line being electrically connected with the described second transmission drain region；The shunting zone includes at least the first shunting Area or the second shunting zone, first shunting zone of substrate have the first flow dividing structure, and first flow dividing structure includes：First point Input unit and the first shunting output section are flowed, for the first shunting input unit for applying preset potential, described first shunts output Portion is electrically connected with the grounding parts；Second shunting zone of substrate has the second flow dividing structure, and second flow dividing structure includes： Second shunting input unit and the second shunting output section, the second shunting input unit is for applying the preset potential, and described the Two shunting output sections are electrically connected with the grounding parts.

Optionally, the first shunting input unit is electrically connected with first bit line；The second shunting input unit and institute State the electrical connection of the second bit line.

Optionally, further include：Connect the 3rd bit line of the first shunting input unit；Connect the of the 4th input unit Four bit lines.

Optionally, the memory block includes：First drop-down area and the second drop-down area, the storage organization include：Positioned at institute The first pull-down transistor that substrate first pulls down area is stated, first pull-down transistor includes：Positioned at the described first drop-down area lining The first pulldown gate structure on bottom；Respectively be located at the first pulldown gate structure both sides substrate in first drop-down source region and First drop-down drain region, the first connecting portion include the described first drop-down drain region, and the grounding parts include：The first drop-down source Area；The second pull-down transistor positioned at the substrate second drop-down area, second pull-down transistor include：Positioned at described second The second pulldown gate structure on area's substrate is pulled down, the second pulldown gate structure is electrically connected with the described first drop-down drain region； It is located at the second drop-down source region in the substrate of the second pulldown gate structure both sides and the second drop-down drain region respectively, under described second Bleedout area is electrically connected with the first pulldown gate structure, and the second connecting portion includes the described second drop-down drain region, described Grounding parts include the described second drop-down source region.

Optionally, first pull-down transistor has the first channel width, and first transmission transistor has second Channel width, second pull-down transistor have triple channel width, and second transmission transistor has the 4th ditch road width Degree；4th channel width is less than the triple channel width；Or second channel width is less than first raceway groove Width；Or second channel width is less than first channel width, and the 4th channel width is less than the described 3rd Channel width.

Optionally, the first transmission range substrate includes the first transmission fin, and the first transmission gate structure is across institute The first transmission fin is stated, and the first transmission gate structure is located at the described first transmission fin partial sidewall and top surface, The first transmission source region and the first transmission drain region are located at the first transmission fin of the described first transmission gate structure both sides respectively In；The second transmission range substrate includes the second transmission fin, and the second transmission gate structure is across the described second transmission fin Portion, and the second transmission gate structure is located at the described second transmission fin partial sidewall and top surface, second transmission Source region and the second transmission drain region are located at respectively in the second transmission fin of the described second transmission gate structure both sides；Under described first Area's substrate is drawn to include the first drop-down fin, the first pulldown gate structure pulls down fin, and described first across described first Pulldown gate structure is located at the described first drop-down fin partial sidewall and top surface, the first drop-down source region and described first Drain region is pulled down to pull down in fin positioned at the first of the first pulldown gate structure both sides respectively；Second drop-down area's substrate bag The second drop-down fin is included, the second pulldown gate structure pulls down fin, and the second pulldown gate knot across described second Structure is located at the described second drop-down fin partial sidewall and top surface, the second drop-down source region and the second drop-down drain region point Not Wei Yu the second pulldown gate structure both sides second drop-down fin in；It is described first drop-down fin, second drop-down fin, First transmission fin and second transmits being of same size for fin, the first drop-down fin, the second drop-down fin, the first transmission fin Portion is identical with the height of the second transmission fin；The first drop-down fin number is more than the number of the described first transmission fin, institute State number of the number more than the described second transmission fin of the second drop-down fin.

Optionally, the memory block further includes the first pull-up area and the second pull-up area；The memory construction further includes：Position The first pull-up load in the substrate first pull-up area, the first pull-up load include：First load input unit, described the For one load input unit for inputting the second current potential, second current potential is more than the first current potential；First load output section, described first Load output section is electrically connected with the first pull-down transistor drain region；The second pull-up positioned at the substrate second pull-up area is negative It carries, the second pull-up load includes：Second load input unit, the second load input unit are electric for inputting described second Position；Second load output section, the second load output section are electrically connected with the second pull-down transistor drain region.

Optionally, the first pull-up load includes first and pulls up transistor, described first pull up transistor including：It is located at The first pull-up gate structure on the substrate, the first pull-up gate structure are electrically connected with the first pulldown gate structure It connects；The first pull-up drain region and the first pull-up source region in the described first pull-up gate structure both sides substrate, described first is negative Carrying output section includes the described first pull-up source region, and the first load input unit includes the described first pull-up drain region；Described second Load includes second and pulls up transistor, described second pull up transistor including：The second pull-up grid knot on the substrate Structure, the second pull-up gate structure are electrically connected with the second pulldown gate structure；It is located at the described second pull-up grid respectively The second pull-up source region and the second pull-up drain region in the substrate of structure both sides, the second load input unit include the described second pull-up Drain region, the second load output section include the described second pull-up source region；Alternatively, the first pull-up load includes the first pull-up Resistance, first pull-up resistor include：The first pull-up doped region and the second pull-up doped region in the substrate, it is described First load input unit includes the described first pull-up doped region, and the first load output section includes the described second pull-up and adulterates Area；The second pull-up load includes the second pull-up resistor, and second pull-up resistor includes：Positioned at the described second pull-up area lining The 3rd pull-up doped region and the 4th pull-up doped region in bottom, the second load input unit include the described 3rd pull-up and adulterate Area, the second load output section include the described 4th pull-up doped region.

Optionally, first flow dividing structure includes：The first shunting transistor positioned at the first shunting zone of substrate, described One shunting transistor includes：The first shunting gate structure on the substrate of first shunting zone, the first shunting grid Structure is electrically connected with the first pulldown gate structure；It is located at described first shunting the first shunting zone of gate structure both sides lining respectively The first shunting source region and the first shunting drain region in bottom, the first shunting output section includes the described first shunting source region；It is described First flow dividing structure further includes the second shunting transistor positioned at the first shunting zone, and second shunting transistor includes：It is located at The second shunting gate structure on the substrate of first shunting zone, the second shunting gate structure and the described second transmission grid Structure is electrically connected；The the second shunting source region and the being located at respectively in described second shunting the first shunting zone of gate structure both sides substrate Two shunting drain regions, the second shunting source region are electrically connected with the described first shunting drain region, and the first shunting input unit includes institute State the second shunting drain region；Second flow dividing structure includes：Positioned at second shunting zone of substrate the 3rd shunting transistor and The 4th shunting transistor positioned at second shunting zone of substrate；3rd shunting transistor includes：Positioned at the second shunting zone The 3rd shunting gate structure on substrate, the 3rd shunting gate structure are electrically connected with the second pulldown gate structure；Point Not Wei Yu it is described 3rd shunting the second shunting zone of gate structure both sides substrate in the 3rd shunting source region and the 3rd shunting drain region, institute Stating the second shunting output section includes the described 3rd shunting source region；4th shunting transistor includes：Positioned at the described second shunting The 4th shunting gate structure on area's substrate, the 4th shunting gate structure are electrically connected with the described second transmission gate structure； The 4th shunting source region in the described 4th shunting gate structure both sides substrate and the 4th shunting drain region respectively, described second point Flowing input unit includes the described 4th shunting drain region, and the 4th shunting source region is electrically connected with the described 3rd shunting drain region.

Optionally, further include：Connect the first source line of the second shunting source region and the described first drop-down source region；Connection institute State the second source line of the 4th shunting source region and the described second drop-down source region.

Correspondingly, the present invention also provides a kind of forming method of memory construction, including：Substrate, the substrate bag are provided Memory block, the first transmission range, the second transmission range and shunting zone are included, the shunting zone includes at least the first shunting zone or the second shunting Area；Storage organization is formed in the substrate storage region, the storage organization includes first connecting portion and second connecting portion；Described The step of the first transmission range the first transmission transistor of formation of substrate, formation first transmission transistor, includes：In the lining The first transmission gate structure is formed on bottom, forms the first transmission sources in the substrate of the described first transmission gate structure both sides respectively Area and the first transmission drain region, the first transmission source region are electrically connected with the first connecting portion；In second transmission range of substrate The step of forming the second transmission transistor, forming second transmission transistor includes：The second transmission is formed over the substrate Gate structure forms the second transmission drain region and the second transmission sources in the substrate of the described second transmission gate structure both sides respectively Area, the second transmission source region are electrically connected with the second connecting portion；The first shunting knot is formed in first shunting zone of substrate Structure；Or form the second flow dividing structure in the first shunting zone of substrate；Or the first shunting is formed in first shunting zone of substrate Structure, and form the second flow dividing structure in the first shunting zone of substrate；First flow dividing structure includes：First shunting input unit and First shunting output section, the first shunting input unit is for inputting preset potential, and first output section is for application first Current potential；Second flow dividing structure includes：Second shunting input unit and the second shunting output section, the second shunting input unit are used In inputting the preset potential, the second shunting output section is used to apply first current potential；Connection described first is formed to pass The wordline of defeated gate structure and the second transmission gate structure；Form first bit line in connection the first transmission drain region；Shape Into the second bit line for connecting the second transmission drain region.

In addition, the present invention also provides a kind of memory circuitry, including：Storage unit, the storage unit include：First connects End, second connection end and ground terminal are connect, the ground terminal is for the first current potential of application；First transmission transistor, described first passes Defeated transistor includes：First transmission grid, the first transmission source electrode and the first transmission drain electrode, the first transmission source electrode and described the One connecting pin connects；Connect the first bit line of the first transmission drain electrode；Second transmission transistor, second transmission transistor Including：Second transmission grid, the second transmission source electrode and the second transmission drain electrode, the second transmission source electrode and the second connection end Connection；Connect the wordline of the first transmission grid and the second transmission grid；Connect the second bit line of the second transmission drain electrode； Dividing cell, the dividing cell include at least the first dividing cell or the second dividing cell；First dividing cell includes： First shunting input terminal and the first shunting output terminal, the first shunting output terminal are connected with the ground terminal, described first point Stream input terminal is used to input preset potential；Second dividing cell includes：Second shunting input terminal and the second shunting output terminal, The second shunting output terminal is connected with the ground terminal, and the second shunting input terminal is used to input the preset potential.

Optionally, it is described first shunting input terminal be connected with first bit line, it is described second shunt input terminal with it is described Second bit line connects.

Optionally, first dividing cell includes：First shunting transistor, first shunting transistor include：The One shunting grid, the first shunting grid are connected with first pulldown gate；First shunting source electrode and the first shunting drain electrode, The first shunting source electrode is connected with the described first shunting output terminal；First dividing cell further includes the second shunting crystal Pipe, second shunting transistor include：Second shunting grid, the second shunting grid connect with the described first transmission grid It connects；Second shunting source electrode, the second shunting source electrode and the described first shunting drain electrode connection；Second shunting drain electrode, described second Shunting drain electrode is connected with the described first shunting input terminal；Second dividing cell includes：3rd shunting transistor, the described 3rd Shunting transistor includes：3rd shunting grid, the 3rd shunting grid are connected with second pulldown gate；3rd shunting source Pole and the 3rd shunting drain electrode, the 3rd shunting source electrode are connected with the described second shunting output terminal；4th shunting transistor, it is described 4th shunting transistor includes：4th shunting grid, the 4th shunting grid are connected with the described second transmission grid；4th point Flow source electrode, the 4th shunting source electrode and the described 3rd shunting drain electrode connection；4th shunting drain electrode, it is described 4th shunting drain electrode with The second shunting input terminal connection.

Optionally, further include：3rd bit line, the 3rd bit line connection the first shunting input terminal；4th bit line, institute State the 4th bit line connection the second shunting input terminal.

Optionally, first dividing cell includes：First shunting transistor, first shunting transistor include：The One shunting grid, the first shunting grid are connected with first pulldown gate；First shunting source electrode, the first shunting source Pole connection the first shunting output terminal；First shunting drain electrode, the first shunting drain electrode connection the first shunting input terminal； Second dividing cell includes：3rd shunting transistor, the 3rd shunting transistor include：3rd shunting grid, it is described 3rd shunting grid is electrically connected with second pulldown gate；3rd shunting source electrode, the 3rd shunting source electrode and described second Shunt output terminal connection；3rd shunting drain electrode, the 3rd shunting drain electrode connection the second shunting input terminal.

Optionally, the storage unit includes：First pull-down transistor, first pull-down transistor include：Under first Draw grid；First drop-down drain electrode, the first drop-down drain electrode are connected with the described first transmission source electrode；First drop-down source electrode, it is described First drop-down source electrode is connected with first current potential；Second pull-down transistor, second pull-down transistor include：Second drop-down Grid, second pulldown gate and the described first drop-down drain electrode connection；Second drop-down source electrode, the second drop-down drain electrode and institute State the connection of the first shunting output terminal；Second drop-down drain electrode, the second drop-down drain electrode are connected with first pulldown gate.

Optionally, the storage unit further includes：First pull-up load, the first pull-up load include：First load Input terminal, for first load input terminal for inputting the second current potential, second current potential is more than the first current potential；First load is defeated Outlet, first load outputs connect the first pull-down transistor drain electrode；Second pull-up load, second pull-up are negative Load includes：Second load input terminal, second load input terminal are used to input second current potential；Second load outputs, Second load outputs connect the second pull-down transistor drain electrode.

Optionally, the first pull-up load includes first and pulls up transistor, described first pull up transistor including：First Grid is pulled up, the first pull-up grid is connected with first pulldown gate；First pull-up drain electrode, the first pull-up drain electrode First load input terminal, the first pull-up source electrode are connected, the first pull-up source electrode connects first load outputs；Institute Stating the load of the second pull-up includes second and pulls up transistor, described second pull up transistor including：Second pull-up grid, the pull-up Grid connects second pulldown gate；Second pull-up source electrode, the second pull-up drain electrode connect second load input terminal；Second Source electrode is pulled up, the second pull-up drain electrode connects second load outputs；Alternatively, the first pull-up load includes first Resistance, the first resistor include：First resistor input terminal and first resistor output terminal, the first resistor input terminal connect institute The first load input terminal is stated, the first resistor output terminal connects first load outputs；Second pull-up, which loads, is Second resistance, the second resistance include：Second resistance input terminal and second resistance output terminal, the second resistance input terminal connect Second load input terminal is connect, the second resistance output terminal connects second load outputs.

The present invention also provides a kind of method of work of memory circuitry, including：Memory circuitry is provided；In the ground terminal The first current potential of upper application；Apply word line potential in the wordline, the word line potential is more than first current potential；Described Apply operating potential on one bit line and second bit line.

Optionally, the first shunting input terminal is connected with first bit line；It is described second shunting input terminal with it is described Second bit line connects；Include in the step of application operating potential on first bit line and second bit line：Described first Apply preset potential on bit line and the second bit line, the preset potential interacts to form reading signal with storage unit；It is described Method of work further includes：The reading signal is obtained by first wordline and the second bit line；By first wordline and Second bit line obtain it is described reading signal the step of include：Apply default electricity on first bit line and second bit line Position, the preset potential are more than first current potential, and the preset potential acts on forming reading signal with the storage unit； The reading signal is obtained on 3rd bit line and the 4th bit line.

Optionally, the memory circuitry includes：First dividing cell and the second dividing cell；The memory circuitry is also Including：Connect the 3rd bit line of the first shunting input terminal；Connect the 4th bit line of the second shunting input terminal；Described The step of applying operating potential on first bit line and second bit line includes：On first bit line and second bit line Apply storage current potential, storage signal is formed in the storage unit；It is formed in the storage unit after storage signal, institute Method of work is stated to further include：Apply preset potential on the 3rd bit line and the 4th bit line, the preset potential is more than described First current potential, the preset potential act on forming reading signal with the storage unit；In the 3rd bit line and the 4th bit line It is upper to obtain the reading signal.

Optionally, the storage unit further includes：First pull-up load, the first pull-up load include：First load Input terminal and the first load outputs, first load outputs connect the first pull-down transistor drain region；Second pull-up Load, the second pull-up load include：Second load input terminal and the second load outputs, second load outputs connect Connect the second pull-down transistor drain region；It is described before applying operating potential on first bit line and second bit line Method of work further includes：Apply the second current potential to first load input terminal and second load input terminal, described second Current potential is more than first current potential.

Compared with prior art, technical scheme has the following advantages：

In the static storage structure that technical solution of the present invention provides, second channel width is less than the first ditch road width Degree；Or the 4th channel width is less than the triple channel width；Or second channel width is less than described first Channel width, and the 4th channel width is less than the triple channel width.

When second channel width is less than first channel width, then the breadth length ratio of first transmission transistor Less than the breadth length ratio of first pull-down transistor, so that the saturation current of first transmission transistor is less than described first The saturation current of pull-down transistor, and then the saturation current and the described first transmission crystalline substance of first pull-down transistor can be increased Ratio between body pipe saturation current reduces the interference that the static noise on the first bit line generates the memory construction.

When the 4th channel width is less than the triple channel width, then the breadth length ratio of second transmission transistor Less than the breadth length ratio of second pull-down transistor, so that the saturation current of second transmission transistor is less than described second The saturation current of pull-down transistor, and then the saturation current and the described second transmission crystalline substance of second pull-down transistor can be increased Ratio between body pipe saturation current, the static noise that can be reduced on the second bit line do the memory construction generation It disturbs.

When second channel width is less than the described 3rd less than first channel width and the 4th channel width Channel width, so as to which the breadth length ratio of first transmission transistor is made to be less than the breadth length ratio of first pull-down transistor, The breadth length ratio of second transmission transistor is less than the breadth length ratio of second pull-down transistor, and then described first can be made to pass The saturation current of defeated transistor is less than the saturation current of first pull-down transistor, the saturation electricity of second transmission transistor Stream is less than the saturation current of second pull-down transistor, and then can increase the first pull-down transistor saturation current and institute State the ratio between the first transmission transistor saturation current, the second pull-down transistor saturation current and second transmission transistor Ratio between saturation current therefore, it is possible to increase the static noise capacity of the memory, reduces static noise to memory The interference that structure generates.

Further, the memory construction includes the first flow dividing structure and the second flow dividing structure.In answering for the memory It is described if the current potential in the first drop-down drain region and the described first transmission drain region junction is low level " 0 " in the process First flow dividing structure turns on, and so as to which first bit line is made to be connected with first current potential, and then can make described first Current potential drags down the current potential on first bit line by first flow dividing structure, prevents the current potential on first bit line from making institute The current potential for stating the first drop-down drain region and the described first transmission drain region junction is raised, and then can be avoided on first bit line Current potential inverts the current potential in the first drop-down drain region and the described first transmission drain region junction, therefore, it is possible to few static noise Interference to the memory construction increases the static noise capacity of the memory construction.

If the current potential in the second drop-down drain region and the described second transmission drain region junction is low level " 0 ", described Second flow dividing structure turns on, and so as to which second bit line is made to be connected with second current potential, and then can make described second Current potential drags down the current potential on second bit line by second flow dividing structure, prevents the current potential on second bit line from making institute The current potential for stating the second drop-down drain region and the described second transmission drain region junction is raised, and then can be avoided on second bit line Current potential inverts the current potential in the second drop-down drain region and the described second transmission drain region junction.Therefore, the flow dividing structure energy Interference of the static noise to the memory construction is enough reduced, increases the static noise capacity of the memory construction.

In the forming method for the memory that technical scheme provides, the 4th channel width is made to be less than described the Triple channel width；Or second channel width is less than first channel width；Or second channel width is less than First channel width, and the 4th channel width is less than the triple channel width, can increase formed storage The static noise capacity of device structure reduces the interference that static noise generates memory construction.

In the memory construction that technical scheme provides, the memory construction includes at least the first flow dividing structure With the second flow dividing structure.The memory applies preset potential in read operation, in the described first shunting input unit, described pre- If current potential is high level " 1 ".

When the memory construction includes the first flow dividing structure, if the current potential of the first connecting portion is low level When " 0 ", the first flow dividing structure conducting makes the first connecting portion be connected with the grounding parts.The grounding parts can lead to It crosses first flow dividing structure and drags down the preset potential, so as to reduce current potential of the predeterminated voltage to the first connecting portion Influence, the current potential of the first connecting portion is avoided to invert, therefore, first flow dividing structure can reduce described first Shunt interference of the static noise in input unit to the memory construction.

When the memory construction includes the second flow dividing structure, if the current potential of the second connecting portion is low level When " 0 ", the second flow dividing structure conducting makes the second connecting portion be connected with the grounding parts.The grounding parts can lead to It crosses second flow dividing structure and drags down the preset potential, so as to reduce current potential of the predeterminated voltage to the second connecting portion Influence, the current potential of the second connecting portion is avoided to invert, so as to reduce it is described second shunting input unit on it is quiet Interference of the state noise to the memory construction.

When the memory construction includes the first shunting and the second flow dividing structure, if the current potential of the first connecting portion For low level " 0 ", when the current potential of the second connecting portion is high level " 1 ", first flow dividing structure turns on, described first point Flow structure can reduce interference of the static noise to the memory construction in the first shunting input unit；If described The current potential of two connecting portions is low level " 0 ", when the current potential of the first connecting portion is high level " 1 ", second flow dividing structure Conducting, second flow dividing structure can reduce it is described second shunting input unit on static noise to the memory construction Interference.Therefore, the flow dividing structure can reduce interference of the static noise to memory, increase the static noise of the memory Capacity.

Further, the first shunting input unit connects first bit line, and described second shunts described in input unit connection Second bit line.Apply in the reading process of the memory, it is necessary on first bit line and second bit line default Current potential, the preset potential are high level " 1 ".If the current potential of the first connecting portion is low level " 0 ", second connection The current potential in portion is high level " 1 ", then first flow dividing structure conducting, first bit line by first flow dividing structure with The grounding parts connection, the current potential so as to make the grounding parts drag down first bit line by first flow dividing structure On preset potential, and then prevent the preset potential from raising the current potential of the first connecting portion, prevent the first connecting portion Current potential invert, therefore, the flow dividing structure can reduce interference of the static noise to memory.Similarly, it is if described The current potential of second connecting portion is low level " 0 ", and the current potential of the first connecting portion is high level " 1 ", then the second shunting knot Structure turns on, and second bit line is connected by second flow dividing structure with second current potential, so as to make the ground connection The current potential in portion drags down the preset potential on second bit line by second flow dividing structure, and then prevents the preset potential The current potential of the second connecting portion is raised, prevents the current potential of the second connecting portion from inverting, therefore, the flow dividing structure energy Enough reduce interference of the static noise to memory.

Further, the memory construction further includes：3rd bit line, the 3rd bit line connection the first shunting input Portion；4th bit line, the 4th bit line connection the second shunting input unit.During the read operation of the memory, Apply preset potential on three bit line and the 4th bit line.If the current potential of the first connecting portion is low level " 0 ", described The current potential of second connecting portion is high level " 1 ", then the first flow dividing structure conducting, the 3rd bit line pass through described first point Flow structure is connected with the grounding parts, and therefore, the preset potential will not be applied in the first connecting portion, so as to lift The current potential of the high first connecting portion so as to prevent first connecting portion current potential from inverting, reduces static noise to described The interference of static storage structure；If the current potential of the second connecting portion is low level " 0 ", the current potential of the first connecting portion is High level " 1 ", then the second flow dividing structure conducting, the 4th bit line pass through second flow dividing structure and the grounding parts It is connected, therefore, the preset potential will not be applied in the second connecting portion, so as to raise the second connecting portion Current potential can prevent second connecting portion current potential from inverting.Connect it can be seen that the preset potential will not be applied to described first Socket part and second connecting portion, so as to which the preset potential is avoided to disturb the electricity of the first connecting portion and second connecting portion Position, and then it is not easy read error occur, therefore, it is possible to increase the static noise capacity of the memory construction.

In the forming method for the memory construction that technical scheme provides, include at least the memory construction First flow dividing structure and the second flow dividing structure, and the memory circuitry includes at least the first dividing cell and the second shunting is single Member.The static noise that first dividing cell can be reduced on the first shunting input terminal does the memory circuitry It disturbs；The static noise that second dividing cell can be reduced on the second shunting input terminal does the memory circuitry It disturbs, it can be seen that, the forming method can reduce interference of the static noise to memory construction, increase the memory construction Static noise capacity.

In the memory circuitry that technical scheme provides, the memory circuitry includes at least the first dividing cell With the second dividing cell.The static noise that first dividing cell can be reduced on the first shunting input terminal is deposited to described The interference of memory circuit；The static noise that second dividing cell can be reduced on the second shunting input terminal is deposited to described The interference of memory circuit.It can be seen that static noise is smaller to the interference of memory circuitry, the static noise of the memory holds It measures larger.

In the method for work for the memory circuitry that technical scheme provides, the memory circuitry includes at least the One dividing cell and the second dividing cell.The static state that first dividing cell can be reduced on the first shunting input terminal is made an uproar Interference of the sound to the memory circuitry；The static state that second dividing cell can be reduced on the second shunting input terminal is made an uproar Interference of the sound to the memory circuitry.It can be seen that static noise is smaller to the interference of the memory circuitry, the storage The static noise capacity of device circuit is larger.

Description of the drawings

Fig. 1 is a kind of structure diagram of static memory structure；

Fig. 2 to Fig. 5 is the structure diagram of each step of one embodiment of forming method of the memory construction of the present invention；

Fig. 6 to Figure 10 is the structure diagram of each step of another embodiment of forming method of memory construction of the present invention；

Figure 11 is the circuit diagram of one embodiment of memory circuitry of the present invention；

Figure 12 is the circuit diagram of another embodiment of memory circuitry of the present invention.

Specific embodiment

The memory construction of the prior art is smaller with problems, such as the static noise capacity of static memory, resists Interference performance is poor.

In conjunction with the memory of the prior art, analysis causes memory static noise capacity small, the original of poor anti jamming capability Cause：

Fig. 1 is a kind of structure diagram of static memory structure.

It please refers to Fig.1, the static memory includes：Two are mirrored into symmetrical reverser；The phase inverter includes：Lining Bottom 100, the substrate 100 include：Transmission range 1, drop-down area 2 and pull-up area 3；Positioned at the transmission range 1, drop-down area 2 and pull-up Fin 101 on 3 substrate of area, the fin 101 of the transmission range 1, drop-down area 2 and pull-up area 3 is mutually identical, and the transmission range 1 is connected with each other with the fin 101 for pulling down area 2；Across the gate structure 110 of the fin 101, the gate structure 110 Cover 101 partial sidewall of fin and top surface；The source region being located at respectively in the 110 both sides fin 101 of gate structure And drain region；The source line being connected with the source region；The thread cast-off being connected with the drain region, the source line of the transmission range 1 pull down area 2 Thread cast-off and the source line in pull-up area 3 are interconnected to constitute memory node 10, the bit line 11 being connected with 1 thread cast-off of transmission range；With institute State the gate line 130 of the connection of gate structure 110.

It is described, it is necessary to apply preset potential on the bit line 11 during the read operation of the static memory Preset potential is high level " 1 ", and since static memory tool is there are two the reverser of mirror symmetry, the static state is deposited Reservoir includes two memory nodes 10, and the current potential of the two memory nodes 10 is opposite, that is to say, that in two memory nodes 10 Must be low level " 0 " there are one the current potential of node, then current potential is that the memory node 10 of low level " 0 " is low level node.With When applying preset potential on the bit line 11 for the transmission range 1 that the low level node is connected, the preset potential is easily raised described The potential value of low level node so as to invert easily the current potential of the low level node, and then easily makes reading result There is mistake.Therefore, the capacity of Noise of the static memory is relatively low.

To solve the technical problem, the present invention provides a kind of memory construction, including：Substrate, the substrate include： First drop-down area, the second drop-down area, the first transmission range and the second transmission range；First time crystal pulling in area is pulled down positioned at substrate first Pipe, first pull-down transistor have the first channel width, and first pull-down transistor includes：On the substrate First pulldown gate structure, respectively under the first drop-down source region and first in the substrate of the first pulldown gate structure both sides Bleedout area, the first drop-down source region are used to connect the first current potential；Second pull-down transistor in area is pulled down positioned at substrate second, it is described Second pull-down transistor has triple channel width, and second pull-down transistor includes：On the substrate second under Gate structure is drawn, respectively the second drop-down source region and second time bleedout in the substrate of the second pulldown gate structure both sides Area, the second pulldown gate structure are electrically connected with the described first drop-down drain region, under the second drop-down drain region and described first Gate structure electrical connection is drawn, the second drop-down source region is used to apply first current potential；On the first transmission range substrate First transmission transistor, first transmission transistor have the second channel width, and first transmission transistor includes：It is located at The first transmission gate structure on the substrate, the first transmission sources in the substrate of the described first transmission gate structure both sides Area and the first transmission drain region, the first transmission source region are electrically connected with the described first drop-down drain region；Positioned at the second transmission range substrate On the second transmission transistor, second transmission transistor has the 4th channel width, and second transmission transistor includes： The second transmission gate structure on the substrate；The second transmission in the described second transmission gate structure both sides substrate Source region and the second transmission drain region, the second transmission source region are electrically connected with the described second drop-down drain region；4th channel width Less than the triple channel width；Or second channel width is less than first channel width；Or second ditch Road width is less than first channel width, and the 4th channel width is less than the triple channel width；Connect described The wordline of one transmission gate structure and the second transmission gate structure；Connect first bit line in the first transmission drain region；Even Connect second bit line in the second transmission drain region.

Wherein, the static noise capacity of the memory increases, the interference that static noise generates the memory construction It is smaller.

It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention Specific embodiment be described in detail.

Fig. 2 to Fig. 5 is the structure diagram of each step of one embodiment of forming method of the memory of the present invention.

It please refers to Fig.2, substrate is provided, the substrate includes：First drop-down area 212, second pulls down area 222, first and transmits 211 and second transmission range 221 of area.

First transmission range 211 is the region for being subsequently used for being formed the first transmission transistor；The first drop-down area 212 The region of the first pull-down transistor is formed to be subsequently used for；Second transmission range 221 is brilliant to be subsequently used for being formed the second transmission The region of body pipe；The second drop-down area 222 is the region for being subsequently used for being formed the second pull-down transistor.

In the present embodiment, the memory is static memory, and the substrate is used to form static memory.

In the present embodiment, the substrate further includes：First pull-up area 213 and second pulls up area 223.In other embodiment In, the substrate can not also include the first pull-up area and the second pull-up area.

The first pull-up area 213 is subsequently used for forming the load of the first pull-up, and the second pull-up area 223 is subsequently used for shape Into the second pull-up load.In other embodiments, the substrate can not also include the described first pull-up area and the second pull-up area.

In the present embodiment, the substrate includes：Substrate 200 and positioned at first transmission range 211, first drop-down area 212, First pull-up area 213, second transmission range 221, second pull down the fin in pull-up 213 substrate 200 of area of area 222, first 201。

In the present embodiment, the fin 201 includes：The first transmission fin in 211 substrate 200 of the first transmission range Portion；The second transmission fin in 221 substrate of the second transmission range；In the described first drop-down 212 substrate 200 of area First drop-down fin；The second drop-down fin on the described second drop-down 222 base 200 of area；Positioned at the described first pull-up area The first pull-up fin in 213 substrates 200；The second pull-up fin in the described second pull-up 223 substrate 200 of area.

In the present embodiment, the first transmission fin is identical with the described first drop-down fin extending direction, and described first passes Defeated fin is connected with the described first drop-down fin.In other embodiments, the first transmission fin and the described first drop-down fin Portion can not also be connected with each other.

In the present embodiment, the second transmission fin is identical with the described second drop-down fin extending direction, and described second passes Defeated fin is connected with the described second drop-down fin.In other embodiments, the second transmission fin and the described second drop-down fin Portion can not also be connected with each other.

It should be noted that in the present embodiment, first channel width is multiplied by for the number of the described first drop-down fin The sum of first drop-down fin width and the first of twice the drop-down fin height；Second channel width is the described second transmission fin Portion's number is multiplied by the sum of the second transmission fin width and the second of twice the transmission fin height；The triple channel width is The number of the second drop-down fin is multiplied by the sum of the second drop-down fin width and the second of twice the drop-down fin height.Described Four channel widths are multiplied by the first transmission fin width and the first of twice the transmission fin for the described first transmission fin number The sum of height.

In other embodiments, the substrate is planar substrate, and first channel width is the first drop-down source region along the The width of one drop-down gate structure extending direction, second channel width transmit gate structure for the first transmission source region along first The width of extending direction, the triple channel width are width of the second drop-down source region along the second pulldown gate structure extending direction Degree, the 4th channel width are width of the second transmission source region along the second transmission gate structure extending direction.

In the present embodiment, the substrate 200 further includes the first bonding pad 214 and the second bonding pad 224.In other embodiment In, the substrate can not also include the first bonding pad and the second bonding pad.

In the present embodiment, first bonding pad 214, first pulls down 211 phase mutual connection of area 212 and first transmission range It touches, second bonding pad 224, second pulls down area 222 and second transmission range 221 contacts with each other.

In the present embodiment, 214 substrate of the first bonding pad further includes the first connection fin, the first connection fin with The extending direction of the first drop-down fin is identical, and the first connection fin is connected with the described first drop-down fin.

In the present embodiment, 224 substrate 200 of the second bonding pad includes the second connection fin, the second connection fin Identical with the extending direction of the described second drop-down fin, the second connection fin is connected with the described second drop-down fin.

In the present embodiment, the fin 201 is of same size.In other embodiments, the width of the fin can be with It differs.

In the present embodiment, the height of the fin 201 is identical.In other embodiments, the height of the fin can be with It differs.

In the present embodiment, the first transmission fin number is less than the described first drop-down fin number, and described second passes Defeated fin number is less than the described second drop-down fin number.In other embodiments, the first transmission fin number is less than institute It states the first drop-down fin number or the second transmission fin number is less than the described second drop-down fin number.It can be seen that In the present embodiment, first channel width is more than second channel width, and the triple channel width is more than the described 4th Channel width.

Specifically, in the present embodiment, the number of the first transmission fin is 1, the number of the first drop-down fin For 2, the number of the first pull-up fin is 1；The number of the second transmission fin is 1, the second drop-down fin The number in portion is 2, and the number of the second pull-up fin is 1.In other embodiments, the first transmission fin, the One drop-down fin, the first pull-up fin, the second transmission fin, the second drop-down fin and the second pull-up fin The number in portion can also be other values.

In the present embodiment, the number that the first connection fin is connected fin with described second is 1.In other embodiment In, the number that the first connection fin is connected fin with described second can also be other values.

In the present embodiment, the step of forming the substrate, includes：Initial substrate is provided；Figure is carried out to the initial substrate Change, form substrate 200, the first transmission fin in 211 substrate 200 of the first transmission range, positioned at the described first drop-down The first drop-down fin in 212 substrate 200 of area, the second transmission fin in 221 substrate 200 of the second transmission range, position In the second drop-down fin in the described second drop-down 222 substrate 200 of area.

In the present embodiment, the material identical of the substrate 200 and fin 201.Specifically, the substrate 200 and fin 201 Material be silicon.In other embodiments, the material of substrate and fin can also be germanium or SiGe.

In other embodiments, the substrate can also be planar substrate.The substrate can be silicon substrate, germanium substrate, The Semiconductor substrates such as silicon-Germanium substrate, silicon-on-insulator substrate, germanium substrate on insulator.

It in the present embodiment, is formed after the substrate, the forming method further includes：Base between the fin 201 Isolation structure (not shown) is formed on bottom 200, the isolation structure covers 201 partial sidewall of fin and top table Face.

The isolation structure is used to implement the electric isolution between different fins 201.

In the present embodiment, the material of the isolation structure is silica.In other embodiments, the material of the isolation structure Material can also be silicon oxynitride.

The first pull-down transistor subsequently is formed in the substrate first drop-down area 212, first pull-down transistor has The step of first channel width, formation first pull-down transistor, includes：The is formed on the described first drop-down 212 substrate of area One drop-down gate structure；The first drop-down source region and the first drop-down are respectively formed in the substrate of the first pulldown gate structure both sides Drain region, the first drop-down source region is for the first current potential of application；

Form the first transmission transistor on 211 substrate of the first transmission range, first transmission transistor has the The step of two channel widths, formation first transmission transistor, includes：The first transmission gate structure is formed over the substrate； The first transmission source region and the first transmission drain region, first transmission are formed in the substrate of the described first transmission gate structure both sides Source region is electrically connected with the described first drop-down drain region；

The second pull-down transistor is formed in the substrate second drop-down area 222, second pull-down transistor has the 3rd The step of channel width, formation second pull-down transistor, includes：It is formed on the described second drop-down 222 substrate of area under second Draw gate structure；The second drop-down source region and second time bleedout are respectively formed in the substrate of the second pulldown gate structure both sides Area, the second pulldown gate structure are electrically connected with the described first drop-down drain region, under the second drop-down drain region and described first Gate structure electrical connection is drawn, the second drop-down source region is for the first current potential of application；

The second transmission transistor is formed on 221 substrate of the second transmission range, forms second transmission transistor Step includes：The second transmission gate structure is formed on substrate；In the substrate of the described second transmission gate structure both sides respectively The second transmission source region and the second transmission drain region are formed, the second transmission source region is electrically connected with the described second drop-down drain region, described Second transmission transistor has the 4th channel width；

4th channel width is less than the triple channel width；Or second channel width is less than described first Channel width；Or second channel width is less than first channel width, and the 4th channel width is less than described Triple channel width.

In the present embodiment, the substrate further includes the first pull-up area 213 and the second pull-up area 223.First pull-up is negative It carries and pulls up transistor for first, the second pull-up load pulls up transistor for second.In other embodiments, on described first Draw load that can also include resistance, the second pull-up load can also include resistance.

In the present embodiment, the forming method further includes：Crystal pulling on first is formed in the first pull-up area 213 of the substrate Body pipe, described first pull up transistor including：The first pull-up gate structure on the described first pull-up 213 substrate of area, point The first pull-up drain region that Wei Yu be in the first pull-up gate structure both sides substrate and the first pull-up source region；In the substrate Second pull-up area 223, which is formed, second to pull up transistor, described second pull up transistor including：Positioned at the described second pull-up area 223 The second pull-up gate structure on substrate pulls up the second pull-up source region in the substrate of gate structure both sides positioned at described second respectively With the second pull-up drain region.

In the present embodiment, first transmission transistor, the second transmission transistor, the first pull-down transistor and second are formed The step of pull-down transistor, is as shown in Figure 3 and Figure 4.

It please refers to Fig.3, is developed across the gate structure 240 of the fin 201, the gate structure covers the fin 201 partial sidewalls and top surface.

The step of being developed across gate structure 240 of the fin 201 includes：It is developed across the first drop-down fin First pulldown gate structure, the first pulldown gate structure covering described first pull down fin partial sidewall and top surface； The first transmission gate structure of the first transmission fin is developed across, the first transmission gate structure covering described first passes Defeated fin partial sidewall and top surface；Be developed across it is described second drop-down fin the second pulldown gate structure, described second The pulldown gate structure covering second drop-down fin partial sidewall and top surface；It is developed across the second transmission fin Fin partial sidewall and top surface are transmitted in second transmission gate structure, the second transmission gate structure covering described second.

In the present embodiment, the substrate 200 further includes：First pull-up area 213 and second pulls up area 223.The grid knot Structure 240 further includes：Across the first pull-up gate structure of the described first pull-up fin, the first pull-up gate structure is located at institute State the first pull-up fin partial sidewall and top surface；It is described across the second pull-up gate structure of the described second pull-up fin Second pull-up gate structure is located at the described second pull-up fin partial sidewall and top surface.

In the present embodiment, the step of forming gate structure 240, further includes：It is developed across the first pull-up fin First pull-up gate structure, the first pull-up gate structure covering described first pull up fin partial sidewall and top surface； The second pull-up gate structure of the second pull-up fin is developed across, the second pull-up gate structure is covered on described second Draw fin partial sidewall and top surface.

In the present embodiment, the substrate 200 further includes：First bonding pad 214 and the second bonding pad 224.The grid knot Structure 240 further includes：Across the first connection gate structure of the described first connection fin, the first connection gate structure covering institute State the first connection fin partial sidewall and top surface；It is described across the second connection gate structure of the described second connection fin Second connection gate structure covering, the second connection fin partial sidewall and top surface.In other embodiments, the lining Bottom does not include first bonding pad and the second bonding pad, then the fin does not include the first connection fin and the second connection fin Portion, the gate structure can not also include the first connection gate structure and the second connection gate structure.

In the present embodiment, the step of forming gate structure 240, further includes：It is developed across the first connection fin First connection gate structure, the first connection gate structure are located at the described first connection fin partial sidewall and top surface； The second connection gate structure of the second connection fin is developed across, the second connection gate structure is located at described second and connects Connect fin partial sidewall and top surface.

In the present embodiment, the first pull-up gate structure, the second pull-up gate structure, first pulldown gate Knot, the second pulldown gate structure, the first transmission gate structure, the second transmission gate structure, the first connection gate structure and second The extending direction for connecting gate structure is identical.In other embodiments, the first pull-up gate structure, the second pull-up grid Pole structure, the first pulldown gate knot, the second pulldown gate structure, the first transmission gate structure and the second transmission gate structure Extending direction can also differ.

In the present embodiment, the first pulldown gate structure is contacted with the described first pull-up gate structure, so as to fulfill institute State being electrically connected between the first pulldown gate structure and the described first pull-up gate structure；The second pulldown gate structure and institute The contact of the second pull-up gate structure is stated, so as to fulfill between the second pulldown gate structure and the second pull-up gate structure Electrical connection.In other embodiments, the first pulldown gate structure can not also connect with the described first pull-up gate structure It touches, the first pulldown gate structure is electrically connected with the described first pull-up gate structure by conductive structure realization；Described second Pulldown gate structure can not also be contacted with the described second pull-up gate structure, the second pulldown gate structure and described second It pulls up gate structure and electrical connection is realized by conductive structure.

In the present embodiment, the first connection gate structure is identical with the extending direction of the first pulldown gate structure, And described first connects gate structure and the first pulldown gate form touch.

In the present embodiment, the second connection gate structure is identical with the extending direction of the described second connection gate structure, And the second connection gate structure is contacted with the described second connection gate structure.

It please refers to Fig.4, doped region 202 is formed in the fin 201 of 240 both sides of gate structure.

The doped region 202 is used to be formed source region and the drain region of transistor.

In the present embodiment, doped region 202 is formed in the fin 201 of 240 both sides of gate structure by ion implanting. In other embodiments, the doped region can also be formed by epitaxial growth technology.

In the present embodiment, for forming NMOS transistor, i.e., described first transmission transistor is first transmission range 211 NMOS transistor；For forming NMOS transistor, i.e., described first pull-down transistor is NMOS crystal in the first drop-down area 212 Pipe；For forming PMOS transistor, described first pulls up transistor as PMOS transistor in the first pull-up area 213；Described For two transmission ranges 221 for forming NMOS transistor, i.e., described second transmission transistor is NMOS transistor；The second drop-down area 222 for forming NMOS transistor, i.e., described second pull-down transistor is NMOS transistor；The second pull-up area 223 is used for PMOS transistor is formed, described second pulls up transistor as PMOS transistor.In other embodiments, it is described first pull-up area and Second pull-up area can be also used for forming resistance.

In the present embodiment, the doped region 202 includes：It is located at the described first transmission gate structure both sides first respectively to transmit The first transmission source region and the first transmission drain region in fin；It is pulled down positioned at the first pulldown gate structure both sides first in fin First drop-down source region and first drop-down drain region；First in fin is pulled up positioned at the described first pull-up gate structure both sides first Pull up drain region and the first pull-up source region；Second be located at respectively in described second the second transmission of transmission gate structure both sides fin passes Defeated source region and the second transmission drain region；The second drop-down source region in fin is pulled down positioned at the second pulldown gate structure both sides second With the second drop-down drain region；The second pull-up source region and first in fin is pulled up positioned at the described second pull-up gate structure both sides second Pull up source region.

In the present embodiment, the doped region 202 further includes：Fin is connected positioned at the described first connection gate structure both sides first The first connection source region in portion is connected drain region with first, and the first connection drain region is connected with the first drop-down drain region, and described first Connection source region is not connected to the first bit line being subsequently formed.

In the present embodiment, the doped region 202 further includes：Fin is connected positioned at the described second connection gate structure both sides second The second connection source region in portion is connected drain region with second, and the second connection drain region is connected the second drop-down in fin with described two Drain region connects, and the second connection source region is not connected to the second bit line being subsequently formed.

In the present embodiment, the step of forming doped region 202, includes：Form covering the first pull-up fin, second Pull up the first photoresist with sidewall surfaces at the top of fin；Using first photoresist as mask to described first drop-down fin, First transmission fin, the second drop-down fin and the second transmission fin, carry out the first ion implanting, form first transmission sources Area, the first transmission drain region, the first drop-down drain region, the first drop-down source region, the second transmission source region, the second transmission drain region, the second drop-down Drain region and the second drop-down source region；After first ion implanting, covering the first transmission fin, the first drop-down fin are formed Portion, the second transmission fin and the second photoresist of the second drop-down fin top and sidewall surfaces；Using second photoresist to cover Film carries out the second ion implanting to the described first pull-up fin and the second pull-up fin, forms the first pull-up drain region, the first pull-up Source region, the second pull-up source region and the second pull-up drain region.

In the present embodiment, first ion implanting transmits source region, the first transmission drain region, first time bleedout described first The is injected in area, the first drop-down source region, the second transmission source region, the second transmission drain region, the second drop-down drain region and the second drop-down source region One Doped ions.First Doped ions are N-type ion, for example, phosphonium ion or arsenic ion.

In the present embodiment, second ion implanting pulls up drain region, the first pull-up source region, the second pull-up source described first The second Doped ions are injected in area and the second pull-up drain region, and second Doped ions are p-type ion, such as boron ion or BF^2- Ion.

In the present embodiment, the step of forming doped region 202, further includes：By first ion implanting described The first connection source region and the first connection drain region, first connection are formed in first connection fin of one connection gate structure both sides Drain region is connected with the described first drop-down drain region；By second ion implanting the of the described second connection gate structure both sides The second connection source region and the second connection drain region, the second connection drain region and the described second drop-down drain region are formed in two connection fins Connection.In other embodiments, can not also be formed it is described first connection drain region, first connection source region, second connection drain region and Second connection source region.

In the present embodiment, the first transmission source region contacts with each other with the described first drop-down drain region, and formation first is public to mix Miscellaneous area, the second transmission source region contact with each other with the described second drop-down drain region, form the second public doped region.

Fig. 5 is refer to, forms the wordline of the connection first transmission gate structure and the second transmission gate structure 230；Form first bit line 251 in connection the first transmission drain region；Form second bit line in connection the second transmission drain region 252。

In the present embodiment, the first connection source region is not connected to first bit line, the second connection source region and institute The second bit line is stated to be not connected to.

The wordline 230 is used to control being switched on and off for first transmission transistor and the second transmission transistor；Institute The first bit line 251 and the second bit line 252 are stated for reading the data in formed memory, and is write into the memory Data.

In the present embodiment, the forming method further includes：It is formed and connects the first public doped region, the first drop-down drain region And the first connecting line 271 of the first pull-up source region；Formed connect the second public doped region, the second drop-down drain region with And the second connecting line 272 of the second pull-up source region.

First connecting line 271 is used to implement the first drop-down drain region, the first transmission source region and the first pull-up source Electrical connection between area；Second connecting line 272 is used to implement the second drop-down drain region, the second transmission source region and described second Pull up the electrical connection between source region.

In the present embodiment, the forming method further includes：Form the first drop-down source line of connection the first drop-down source region 231, the first drop-down source line 231 is used to apply the first current potential to the described first drop-down source region；Connect the second drop-down source The second drop-down source line 232 in area, the second drop-down source line 232 are used to apply first electricity to the described second drop-down source region Position.

In the present embodiment, first current potential is zero potential, and the first drop-down source line 231 and second pulls down source line 232 For being grounded.

In the present embodiment, the forming method further includes：Form the first pull-up thread cast-off in connection the first pull-up drain region 281, the first pull-up thread cast-off 281 is used to apply the second current potential to the described first pull-up drain region, and second current potential is more than institute State the first current potential；The second pull-up thread cast-off 282 of connection the second pull-up source region is formed, the second pull-up thread cast-off 282 is used for Second current potential is applied to the described second pull-up source region.

In the present embodiment, the forming method further includes：It is formed and connects first connecting line 271 and the described second pull-up The first grid polar curve 261 of gate structure, the first grid polar curve 261 are used to implement the second pull-up gate structure and described the The electrical connection between bleedout area once；It is formed and connects second connecting line 271 and the second of the described first pull-up gate structure Gate line 262, the second gate line 262 are used to implement between the first pull-up gate structure and the second drop-down drain region Electrical connection.

It should be noted that in the present embodiment, first bit line 251 transmits drain region for connecting first.With described The connected transistor of one bit line 251 is the first transmission transistor.The fin 201 of first transmission transistor is formed to pass for first Defeated fin, the region where the first transmission fin is the first transmission range 211.Therefore, the width of the first transmission fin With height the sum of be multiplied by it is described first transmission fin number determine to form the second channel width of the first transmission transistor.

In the present embodiment, the fin 201 of first pull-down transistor is formed as the first drop-down fin, first drop-down Region where fin is the first drop-down area 212.Therefore, the sum of the width of the first drop-down fin and height are multiplied by under first Fin number is drawn to determine to form the first channel width of the first transmission transistor.

In the present embodiment, the first drop-down fin is equal with the width of the described first transmission fin, first drop-down Fin is equal with the height of the described first transmission fin.The number of the first drop-down fin is more than the described first transmission fin Number.Therefore, second channel width is less than first channel width.

In the present embodiment, second bit line 252 transmits drain region for connecting second.It is connected with second bit line 252 Transistor be the second transmission transistor.The fin 201 of second transmission transistor is formed as the second transmission fin, described the Region where two transmission fins is the second transmission range 221.The sum of the width of the second transmission fin and height are multiplied by described The number of second transmission fin determines to form the 4th channel width of the second transmission transistor.

In the present embodiment, form the fin 201 of second pull-down transistor institute and pull down fin for second, under described second Region where drawing fin is the second drop-down area 222.The sum of the width of the second drop-down fin and height are multiplied by the second drop-down Fin number determines to form the triple channel width of the second pull-down transistor.

In the present embodiment, the second drop-down fin is equal with the width of the described second transmission fin, second drop-down Fin is equal with the height of the described second transmission fin.The number of the second drop-down fin is more than the described second transmission fin Number.Therefore, the 4th channel width is less than the triple channel width.

In the present embodiment, first pull-down transistor and the second pull-down transistor are pull-down transistor, and described first passes Defeated transistor and the second transmission transistor are transmission transistor.

In the present embodiment, the memory is static memory.

Since the static noise capacity of static memory and the beta rates of static memory are related, the bigger static state of beta rates is deposited The static noise capacity of reservoir is bigger, and the static noise capacity of the smaller static memory of beta rates is smaller.Under the beta rates are Ratio between pull transistor and transmission transistor saturation current.

The saturation current of pull-down transistor is related with the size of pull-down transistor, the saturation current of transmission transistor and transmission The size of transistor is related.Specifically, transistor saturation current has following relation with transistor size.

Wherein, k is proportionality coefficient, and W is the width of transistor, and L is the length of transistor, V_GSFor grid source electric potential, V_thFor crystalline substance The threshold potential of body pipe.

It can be seen that the saturation current of transistor and the breadth length ratio of transistor have direct relation.The breadth length ratio of transistor is got over Greatly, then the saturation current of transistor is bigger.

In the present embodiment, first pull-down transistor is less than by the second channel width for making the first transmission transistor First channel width so as to increase the ratio of the saturation current of the first pull-down transistor and the first transmission transistor, and then increases The static noise capacity of the memory.

Meanwhile in the present embodiment, second time crystal pulling is less than by the 4th channel width for making the second transmission transistor The triple channel width of body pipe, so as to increase the ratio of the saturation current of the second pull-down transistor and the second transmission transistor, into One step increases the static noise capacity of the memory.

To sum up, in the forming method of memory provided in an embodiment of the present invention, it is less than the 4th channel width described Triple channel width；Or second channel width is less than first channel width；Or second channel width is small In first channel width, and the 4th channel width is less than the triple channel width.

When second channel width is less than first channel width, the breadth length ratio of first transmission transistor is small In the breadth length ratio of first pull-down transistor, so that the saturation current of first transmission transistor is less than under described first The saturation current of pull transistor, and then the saturation current and the described first transmission crystal of first pull-down transistor can be increased Ratio between pipe saturation current reduces the interference that the static noise on the first bit line generates the memory construction.

When the 4th channel width is less than the triple channel width, the breadth length ratio of second transmission transistor is small In the breadth length ratio of second pull-down transistor, so that the saturation current of second transmission transistor is less than under described second The saturation current of pull transistor, and then the saturation current and the described second transmission crystal of second pull-down transistor can be increased Ratio between pipe saturation current can reduce the interference that the static noise on the second bit line generates the memory construction.

When second channel width is less than the described 3rd less than first channel width and the 4th channel width During channel width, the breadth length ratio of first transmission transistor can be made to be less than the breadth length ratio of first pull-down transistor, institute The breadth length ratio for stating the second transmission transistor is less than the breadth length ratio of second pull-down transistor, so that the first transmission crystal The saturation current of pipe is less than the saturation current of first pull-down transistor, and the saturation current of second transmission transistor is less than The saturation current of second pull-down transistor, and then the first pull-down transistor saturation current and described first can be increased Ratio between transmission transistor saturation current, the second pull-down transistor saturation current and the second transmission transistor saturation electricity Ratio between stream therefore, it is possible to increase the static noise capacity of the memory, reduces static noise and memory construction is produced Raw interference.

With continued reference to Fig. 5, the present invention also provides a kind of embodiment of memory construction, including：

Substrate, the substrate include：First drop-down area 212, second pulls down area 222, the first transmission range 211 and the second transmission Area 221；

First pull-down transistor in area 212 is pulled down positioned at substrate first, first pull-down transistor has the first raceway groove Width, first pull-down transistor include：The first pulldown gate structure on the described first drop-down 212 substrate of area；Point The first drop-down source region and first time bleedout that Wei Yu be in the first drop-down 212 substrate of area of the first pulldown gate structure both sides Area, the first drop-down source region is for the first current potential of application；

Second pull-down transistor in area 222 is pulled down positioned at substrate second, second pull-down transistor has triple channel Width, second pull-down transistor include：The second pulldown gate structure on the described second drop-down 222 substrate of area；Point The second drop-down source region that Wei Yu be in the substrate of the second pulldown gate structure both sides and the second drop-down drain region, under described second Gate structure is drawn to be electrically connected with the described first drop-down drain region, the second drop-down drain region is electrically connected with the first pulldown gate structure It connects, the second drop-down source region is for the first current potential of application；

The first transmission transistor on 211 substrate of the first transmission range, first transmission transistor have the second ditch Road width, first transmission transistor include：The first transmission gate structure on 211 substrate of the first transmission range； It is located at the first transmission source region in 211 substrate of the first transmission range of the described first transmission gate structure both sides and the first transmission respectively Drain region, the first transmission source region are electrically connected with the described first drop-down drain region；

The second transmission transistor on 221 substrate of the second transmission range, second transmission transistor include：Positioned at institute State the second transmission gate structure on 221 substrate of the second transmission range；Second positioned at the described second transmission gate structure both sides passes The second transmission source region and the second transmission drain region in defeated 221 substrate of area, the second transmission source region and the described second drop-down drain region Electrical connection, second transmission transistor have the 4th channel width；

4th channel width is less than the triple channel width；

Either second channel width is less than first channel width or second channel width less than described First channel width, and the 4th channel width is less than the triple channel width；

Connect the wordline 230 of the first transmission gate structure and second transmission structure；

Connect first bit line 251 in the first transmission drain region；

Connect second bit line 252 in the second transmission drain region.

The first drop-down area 212 is the region for being subsequently used for being formed the first pull-down transistor, the second drop-down area 222 To be subsequently used for being formed the region of the second pull-down transistor, first transmission range 211 is brilliant to be subsequently used for being formed the first transmission The region of body pipe, second transmission range 221 are the region for being subsequently used for being formed the second transmission transistor.

In the present embodiment, the substrate further includes：First pull-up area 213 and second pulls up area 223.The first pull-up area 213 for forming the first pull-up load, and the second pull-up area 223 is subsequently used for forming the load of the second pull-up.In other implementations In example, the substrate can not also include the described first pull-up area and the second pull-up area.

In the present embodiment, first transmission range 211 is contacted with the described first drop-down area 212, the first transmission fin The first drop-down fin described with part is connected；Second transmission range 221 is contacted with the described second drop-down area 222, and described second Transmission fin the second drop-down fin described with part is connected.

In the present embodiment, the extending direction of the fin 201 is mutually identical.

In the present embodiment, the memory further includes：The isolation structure in substrate 200 between the fin 201 (not shown), the isolation structure cover 201 partial sidewall of fin and top surface.

In the present embodiment, the first transmission gate structure is across the described first transmission fin, the first transmission grid The structure covering first transmission fin partial sidewall and top surface；The first transmission source region and the first transmission drain region difference In the first transmission fin of the described first transmission gate structure both sides.

In the present embodiment, the first pulldown gate structure is across the described first drop-down fin, first pulldown gate The structure covering first drop-down fin partial sidewall and top surface；The first drop-down source region and the first drop-down drain region difference In the first drop-down fin of the first pulldown gate structure both sides.

In the present embodiment, the second transmission gate structure is across the described second transmission fin, the second transmission grid The structure covering second transmission fin partial sidewall and top surface；The second transmission source region and the second transmission drain region difference In the second transmission fin of the described second transmission gate structure both sides.

In the present embodiment, the second pulldown gate structure is across the described second drop-down fin, second pulldown gate The structure covering second drop-down fin partial sidewall and top surface；The second drop-down source region and the second drop-down drain region difference In the second drop-down fin of the second pulldown gate structure both sides.

In the present embodiment, the substrate further includes the first pull-up area 213 and the second pull-up area 223.The memory also wraps Include the first pull-up load positioned at the substrate first pull-up area 213, the second pull-up positioned at the substrate second pull-up area 223 Load.During other are implemented, the memory can not also include the described first pull-up load and the described second pull-up loads.

In the present embodiment, the first pull-up load includes first and pulls up transistor, and second pull-up, which loads, includes the Two pull up transistor.During other are implemented, the first pull-up load and the described second pull-up load can also include resistance.

In the present embodiment, described first pull up transistor including：Positioned at described first pull-up 213 substrate of area on first on Gate structure is drawn, respectively the first pull-up drain region and the first pull-up source in the described first pull-up gate structure both sides substrate Area；Described second pull up transistor including：The second pull-up gate structure on the described second pull-up 223 substrate of area, respectively The second pull-up source region and the second pull-up drain region in the described second pull-up gate structure both sides substrate.

In the present embodiment, the first pull-up gate structure is across the described first pull-up fin, the first pull-up grid The structure covering first pull-up fin partial sidewall and top surface；The second pull-up source region and the second pull-up drain region difference In the second pull-up fin of the described second pull-up gate structure both sides.

In the present embodiment, the second pull-up gate structure is across the described second pull-up fin, the second pull-up grid The structure covering second pull-up fin partial sidewall and top surface；The first pull-up drain region and the first pull-up source region difference In the first pull-up fin of the described first pull-up gate structure both sides.

In the present embodiment, the first pull-up gate structure, the second pull-up gate structure, first pulldown gate The extending direction that knot, the second pulldown gate structure, the first transmission gate structure and second transmit gate structure is identical.In other realities It applies in example, the first pull-up gate structure, the second pull-up gate structure, the first pulldown gate knot, the second drop-down The extending direction of gate structure, the first transmission gate structure and the second transmission gate structure can also differ.

In the present embodiment, the first pulldown gate structure is connected with the described first pull-up gate structure, so as to fulfill institute State being electrically connected between the first pulldown gate structure and the described first pull-up gate structure；The second pulldown gate structure and institute The connection of the second pull-up gate structure is stated, so as to fulfill between the second pulldown gate structure and the second pull-up gate structure Electrical connection.In other embodiments, the first pulldown gate structure can not also connect with the described first pull-up gate structure It connects, the first pulldown gate structure is connected with the described first pull-up gate structure by conductive structure；The second drop-down grid Pole structure can also be not connected to the described second pull-up gate structure, the second pulldown gate structure and the described second pull-up grid Pole structure is connected by conductive structure.

In the present embodiment, the gate structure 240 includes：The first pull-up gate structure, the second pull-up grid Structure, the first pulldown gate knot, the second pulldown gate structure, the first transmission gate structure, the second transmission gate structure, the One connection gate structure and the second connection gate structure.

In the present embodiment, the first transmission source region, the first transmission drain region, the first drop-down drain region, the first drop-down source region, the First Doped ions in two transmission source regions, the second transmission drain region, the second drop-down drain region and the second drop-down source region.First doping Ion is N-type ion, for example, phosphonium ion or arsenic ion.

In the present embodiment, in the first pull-up drain region, the first pull-up source region, the second pull-up source region and the second pull-up drain region With the second Doped ions, second Doped ions are p-type ion, such as boron ion or BF^2-Ion.

In the present embodiment, the doped region 202 further includes：Fin is connected positioned at the described first connection gate structure both sides first The first connection source region in portion is connected drain region with first, and the first connection drain region is connected with the first drop-down drain region, and described first Connection source region is not connected to the first bit line being subsequently formed.The first connection source region is connected in drain region with first with described the One Doped ions.

In the present embodiment, the doped region 202 further includes：Fin is connected positioned at the described second connection gate structure both sides second The second connection source region in portion is connected drain region with second, and the second connection drain region is connected the second drop-down in fin with described two Drain region connects, and the second connection source region is not connected to the second bit line being subsequently formed.The second connection source region connects with second Connecing has first Doped ions in drain region.

In the present embodiment, the part first pulls down drain region and is connected with each other with the described first transmission source region, and it is public to form first Codope area, the part second pull down drain region and are connected with each other with the described second transmission source region, form the second public doped region.

In the present embodiment, doped region 202 includes：It is described first pull-up drain region, first pull-up source region, second pull-up source region and Second pull-up drain region, the first pull-up drain region, the first pull-up source region, the second pull-up source region, the second pull-up drain region, the first connection Source region, the first connection drain region, the second connection source region and the second connection drain region.

In the present embodiment, the memory further includes：Connect the described first public doped region, the first drop-down drain region and institute State the first connecting line 271 of the first pull-up source region；Connect the described second public doped region, the second drop-down drain region and described second Pull up second connecting line 272 in drain region.

In the present embodiment, the memory further includes：Connect the first drop-down source line 231 of the first drop-down source region, institute The first drop-down source line 231 is stated for applying the first current potential to the described first drop-down source region；Connect the of the second drop-down source region Two drop-down source lines 232, the second drop-down source line 232 are used to apply first current potential to the described second drop-down source region.

In the present embodiment, first current potential is zero potential, i.e., described first drop-down source line 231 and second pulls down source line 232 are used to be grounded.

In the present embodiment, the memory further includes：Connect the first pull-up thread cast-off 281 in the first pull-up drain region, institute The first pull-up thread cast-off 281 is stated for applying the second current potential to the described first pull-up drain region, second current potential is more than described first Current potential；The second pull-up thread cast-off 282 in the second pull-up drain region is connected, the second pull-up thread cast-off 282 is used for described second It pulls up drain region and applies second current potential.

In the present embodiment, the memory further includes：Connect first connecting line 271 and the described second pull-up grid knot The first grid polar curve 261 of structure, the first grid polar curve 261 are used to implement the second pull-up gate structure and the described first drop-down Electrical connection between drain region；The second gate line 262 of second connecting line 271 and the described first pull-up gate structure is connected, The second gate line 262 is used to implement being electrically connected between the first pull-up gate structure and the described second drop-down drain region.

It should be noted that in the present embodiment, first bit line 251 transmits drain region for connecting first.With described The connected transistor of one bit line 251 is the first transmission transistor.The fin 201 of first transmission transistor is formed to pass for first Defeated fin, the region where the first transmission fin is the first transmission range 211.The width and height of the first transmission fin The sum of be multiplied by it is described first transmission fin number determine to form the second channel width of the first transmission transistor.

In the present embodiment, second bit line 252 transmits drain region for connecting second.It is connected with second bit line 252 Transistor be the second transmission transistor.The fin 201 of second transmission transistor is formed as the second transmission fin, described the Region where two transmission fins is the second transmission range 221.

The number that the sum of the width of the second transmission fin and height are multiplied by the second transmission fin determines institute's shape Into the 4th channel width of the second transmission transistor.

In the present embodiment, the second drop-down fin is equal with the width of the described second transmission fin, second drop-down Fin is equal with the height of the described second transmission fin..The number of the second drop-down fin is more than the described second transmission fin Number.Therefore, the 4th channel width is less than the triple channel width.

In the present embodiment, the memory formed is static memory.

It can be seen that the saturation current of transistor and the breadth length ratio of transistor have direct relation.The wide ratio of transistor is bigger, Then the saturation current of transistor is bigger.

To sum up, in memory construction provided in an embodiment of the present invention, second channel width is less than first raceway groove Width；Or the 4th channel width is less than the triple channel width；Or second channel width is less than described the One channel width, and the 4th channel width is less than the triple channel width.

When second channel width is less than first channel width, then the breadth length ratio of first transmission transistor Less than the breadth length ratio of first pull-down transistor, so that the saturation current of first transmission transistor is less than described first The saturation current of pull-down transistor, and then the saturation current and the described first transmission crystalline substance of first pull-down transistor can be increased Ratio between body pipe saturation current reduces the interference that the static noise on the first bit line generates the memory construction；

When the 4th channel width is less than the triple channel width, then the breadth length ratio of second transmission transistor Less than the breadth length ratio of second pull-down transistor, so that the saturation current of second transmission transistor is less than described second The saturation current of pull-down transistor, and then the saturation current and the described second transmission crystalline substance of second pull-down transistor can be increased Ratio between body pipe saturation current, the static noise that can be reduced on the second bit line do the memory construction generation It disturbs；

When second channel width is less than the described 3rd less than first channel width and the 4th channel width During channel width, so as to make the width that the breadth length ratio of first transmission transistor is less than first pull-down transistor long Than the breadth length ratio of second transmission transistor is less than the breadth length ratio of second pull-down transistor, so that described first passes The saturation current of defeated transistor is less than the saturation current of first pull-down transistor, the saturation electricity of second transmission transistor Stream is less than the saturation current of second pull-down transistor, and then can increase the first pull-down transistor saturation current and institute State the ratio between the first transmission transistor saturation current, the second pull-down transistor saturation current and second transmission transistor Ratio between saturation current therefore, it is possible to increase the static noise capacity of the memory, reduces static noise to memory The interference that structure generates.

In order to improve the static noise capacity of memory, the embodiment of the present invention also provides a kind of memory circuitry, including： Storage unit, the storage unit include：First connecting pin, second connection end and ground terminal, the ground terminal is for applying the One current potential；First transmission transistor, first transmission transistor include：First transmission grid, the first transmission source electrode and first Transmission drain electrode, the first transmission source electrode are connected with first connecting pin；Connect the first bit line of the first transmission drain electrode； Second transmission transistor, second transmission transistor include：Second transmission grid, the second transmission source electrode and the second transmission leakage Pole, the second transmission source electrode are connected with the second connection end；It connects the first transmission grid and second and transmits grid First wordline；Connect the second bit line of the second transmission drain electrode；Dividing cell, the dividing cell include at least the first shunting Unit or the second dividing cell；First dividing cell includes：First shunting input terminal and the first shunting output terminal, described the One shunting output terminal is connected with the ground terminal, and the first shunting input terminal is used to input preset potential；Second shunting Unit includes：Second shunting input terminal and the second shunting output terminal, the second shunting output terminal are connected with the ground terminal, institute The second shunting input terminal is stated for inputting the preset potential.

Wherein, the memory circuitry includes at least the first dividing cell or second unit.The memory is using In the process, the dividing cell can form access between interference signal and the ground terminal, so as to reduce the interference letter Number to memory cell storage data influence.Therefore, the dividing cell can reduce static noise and memory is done It disturbs, increases the static noise capacity of the memory.

Fig. 6 to Fig. 9 is the structure diagram of each step of another embodiment of forming method of the memory of the present invention.

Fig. 6 is refer to, substrate is provided, the substrate includes memory block, the first transmission range 311, the second transmission range 321 and divides Area is flowed, the shunting zone includes at least the first shunting zone 314 or the second shunting zone 324.

The memory block is used to be subsequently formed storage unit；First transmission range 311 is to be subsequently used for forming the first biography The region of defeated transistor, second transmission range 322 are the region for being subsequently used for being formed the second transmission transistor；The shunting zone The region of the first flow dividing structure and the second flow dividing structure is formed to be subsequently used for.

In the present embodiment, the memory block includes：First drop-down area 312 and second pulls down area 322.

The first drop-down area 312 is the region for being subsequently used for being formed the first pull-down transistor, the second drop-down area 322 The region of the second pull-down transistor is formed to be subsequently used for,

In the present embodiment, the memory block further includes：First pull-up area 313 and second pulls up area 323.First pull-up For forming the first pull-up load, the second pull-up area 323 is subsequently used for forming the load of the second pull-up in area 313.In other realities It applies in example, the substrate can not also include the described first pull-up area and the second pull-up area.

In the present embodiment, the shunting zone includes：First shunting zone 314 and the second shunting zone 324.First shunting zone It is subsequently used for forming the first flow dividing structure, second shunting zone is subsequently used for forming the second flow dividing structure.

In the present embodiment, the substrate includes：Substrate 300 and the fin 301 in the substrate 300.

In the present embodiment, the fin 301 includes：The first transmission fin in 311 substrate 300 of the first transmission range Portion；The second transmission fin in 321 substrate of the second transmission range；In the described first drop-down 312 substrate 300 of area First drop-down fin；The second drop-down fin on the described second drop-down 322 base 200 of area；Positioned at the described first pull-up area The first pull-up fin in 313 substrates 300；The second pull-up fin in the described second pull-up 323 substrate 300 of area；It is located at The first shunting fin in first shunting zone, 314 substrate 200；Second in 324 substrate 200 of the second shunting zone Shunt fin.

In the present embodiment, the fin 201 is of same size, and the height of the fin 201 is identical.In other embodiment In, the width of the fin can also differ, and the height of the fin can also differ.

In the present embodiment, the first transmission fin number is equal to the described first drop-down fin number, and described second passes Defeated fin number is equal to the described second drop-down fin number.In other embodiments, the first transmission fin number can be with Less than or greater than described first drop-down fin number, it is described second transmission fin number be also less than or more than described second under Draw fin number.

Specifically, in the present embodiment, the number of the first transmission fin is 1, the number of the first drop-down fin For 1, the number of the first pull-up fin is 1；The number of the second transmission fin is 1, the second drop-down fin The number in portion is 1, and the number of the second pull-up fin is 1.In other embodiments, the first transmission fin, the One drop-down fin, the first pull-up fin, the second transmission fin, the second drop-down fin and the second pull-up fin The number in portion can also be other values.

In the present embodiment, the step of forming the substrate, includes：Initial substrate is provided；Figure is carried out to the initial substrate Change, form substrate 300, the first transmission fin in 311 substrate 300 of the first transmission range, positioned at the described first drop-down The first drop-down fin in 312 substrate of area, the first shunting fin in 314 substrate 300 of the first shunting zone, positioned at institute The second transmission fin in 321 substrate 300 of the second transmission range is stated, under second in the described second drop-down 322 substrate 300 of area Fin is drawn, the second shunting fin in 324 substrate 300 of the second shunting zone.

In the present embodiment, the material identical of the substrate 300 and fin 301.Specifically, the substrate 300 and fin 301 Material be silicon.In other embodiments, the material of substrate and fin can also be germanium or SiGe.

In the present embodiment, first transmission range 311 is contacted with the described first drop-down area 312, the first transmission fin It is connected with the described first drop-down fin；Second transmission range 321 is contacted with the described second drop-down area 322, second transmission Fin is connected with the described second drop-down fin.

In the present embodiment, the extending direction of the fin 301 is identical.In other embodiments, the extension side of the fin To can also differ.

It in the present embodiment, is formed after the substrate, the forming method further includes：Base between the fin 201 Isolation structure (not shown) is formed on bottom 300, the isolation structure covers 301 partial sidewall of fin and top table Face.

The isolation structure is used to implement the electric isolution between different fins 301.

Subsequently storage organization is formed in the memory block；It is brilliant that the first transmission is formed in the first transmission range 311 of the substrate The step of body pipe, formation first transmission transistor, includes：The first transmission grid are formed on 311 substrate of the first transmission range Pole structure, formed respectively in 311 substrate of the first transmission range of the described first transmission gate structure both sides the first transmission source region and First transmission drain region, the first transmission source region are electrically connected with the first connecting portion；

The second transmission transistor is formed in second transmission range of substrate 321, forms the step of second transmission transistor Suddenly include：The second transmission gate structure is formed on 321 substrate of the second transmission range, transmits grid knot described second respectively In 321 substrate of the second transmission range of structure both sides formed second transmission drain region and second transmission source region, it is described second transmission source region with The second connecting portion electrical connection；

The first flow dividing structure is formed in first shunting zone of substrate 314；

Or form the second flow dividing structure in the first shunting zone of substrate 314；

Or the first flow dividing structure is formed in first shunting zone of substrate 314, and formed in the first shunting zone of substrate 314 Second flow dividing structure；

First flow dividing structure includes：First shunting input unit and the first shunting output section, the first shunting input For inputting preset potential, the first shunting output section is used to connect the first current potential in portion；Second flow dividing structure includes：Second Input unit and the second shunting output section are shunted, the second shunting input unit is for inputting the preset potential, described second point Stream output section is used to apply first current potential.

Specifically, in the present embodiment, the step of forming the storage organization and the flow dividing structure, is as shown in Figure 7 and Figure 8.

Fig. 7 is refer to, is developed across the gate structure 340 of the fin 301, the gate structure 340 covers the fin Portion's partial sidewall and top surface.

Specifically, the step of forming gate structure 340 includes：It is developed across under the first of the first drop-down fin Gate structure is drawn, the first pulldown gate structure covering described first pulls down fin partial sidewall and top surface；It is formed horizontal Across the first transmission gate structure of the described first transmission fin, the first transmission gate structure covering the first transmission fin Partial sidewall and top surface；It is developed across the second pulldown gate structure of the second drop-down fin, the second drop-down grid The pole structure covering second drop-down fin partial sidewall and top surface；Be developed across the second transmission fin second passes Fin partial sidewall and top surface are transmitted in defeated gate structure, the second transmission gate structure covering described second；It is formed horizontal Across the first shunting grid group of the described first shunting fin, the first shunting grid group is located at the described first shunting fin part Top and sidewall surfaces；It is developed across the second shunting grid group of the second shunting fin, the second shunting grid group position In the described second shunting fin atop part and sidewall surfaces.

The forming method includes：Be developed across it is described first pull-up fin first pull-up gate structure, described first Pull up the gate structure covering first pull-up fin partial sidewall and top surface；It is developed across the second pull-up fin Second pull-up gate structure, the second pull-up gate structure covering described second pull up fin partial sidewall and top surface.

In the present embodiment, the first pulldown gate structure is contacted with the described first pull-up gate structure, so as to fulfill institute State being electrically connected between the first pulldown gate structure and the described first pull-up gate structure；The second pulldown gate structure and institute The contact of the second pull-up gate structure is stated, so as to fulfill between the second pulldown gate structure and the second pull-up gate structure Electrical connection.In other embodiments, the first pulldown gate structure can not also connect with the described first pull-up gate structure It touches, the first pulldown gate structure is connected with the described first pull-up gate structure by conductive structure；The second drop-down grid Pole structure can not also be contacted with the described second pull-up gate structure, the second pulldown gate structure and the described second pull-up grid Pole structure is connected by conductive structure.

In the present embodiment, the first shunting grid group includes：First point be connected with the first pulldown gate structure Flow gate structure；The second shunting gate structure being connected with the described first transmission gate structure.

In the present embodiment, the first shunting gate structure and the first pulldown gate form touch, so as to fulfill first point Stream gate structure is electrically connected with the first pulldown gate structure；The second shunting gate structure and the described first transmission grid Pole form touch transmits being electrically connected for gate structure so as to fulfill the described first shunting gate structure with described first.At other In embodiment, the first shunting gate structure can not also be contacted with the first pulldown gate structure, pass through conductive structure Realize electrical connection；The second shunting gate structure can not also be contacted with the described first transmission gate structure, be tied by conduction Structure realizes electrical connection.

In the present embodiment, the second shunting grid group includes：The 3rd be electrically connected with the first pulldown gate structure Shunt gate structure；The 4th shunting gate structure being electrically connected with the described second transmission gate structure.

In the present embodiment, the 3rd shunting gate structure and the second pulldown gate form touch, so as to fulfill the Three shunting gate structures are electrically connected with the second pulldown gate structure；The 4th shunting gate structure is passed with described first The contact of defeated gate structure, so as to fulfill the 4th shunting gate structure transmit being electrically connected for gate structure with described second.At it In his embodiment, the 3rd shunting gate structure can not also be contacted with the second pulldown gate structure, be tied by conduction Structure realizes electrical connection；The 4th shunting gate structure can not also be contacted with the described second transmission gate structure, pass through conduction Structure realizes electrical connection.

In the present embodiment, the gate structure 340 includes：The first pull-up gate structure, the second pull-up grid Structure, the first pulldown gate structure, the second pulldown gate structure, first transmission gate structure, second transmission gate structure, First shunting grid group and the second shunting grid group.

Fig. 8 is refer to, doped region 302 is formed in the fin 301 of 340 both sides of gate structure.

The doped region 302 is used to be formed source region and the drain region of transistor.

In the present embodiment, doped region 302 is formed in the fin 301 of 340 both sides of gate structure by ion implanting. In other embodiments, the doped region can also be formed by epitaxial growth technology.

In the present embodiment, for forming NMOS transistor, i.e., described first transmission transistor is first transmission range 311 NMOS transistor；For forming NMOS transistor, i.e., described first pull-down transistor is NMOS crystal in the first drop-down area 312 Pipe；For forming PMOS transistor, described first pulls up transistor as PMOS transistor in the first pull-up area 313；Described For two transmission ranges 321 for forming NMOS transistor, i.e., described second transmission transistor is NMOS transistor；The second drop-down area 322 for forming NMOS transistor, i.e., described second pull-down transistor is NMOS transistor；The second pull-up area 323 is used for PMOS transistor is formed, described second pulls up transistor as PMOS transistor.In other embodiments, it is described first pull-up area and Second pull-up area can be also used for forming resistance.

In the present embodiment, first shunting transistor, the second shunting transistor, the 3rd shunting transistor and the 4th shunting Transistor is NMOS transistor.

In the present embodiment, the doped region 302 includes：It is located at the described first transmission gate structure both sides first respectively to transmit The first transmission source region and the first transmission drain region in fin；It is pulled down positioned at the first pulldown gate structure both sides first in fin First drop-down source region and first drop-down drain region；First in fin is pulled up positioned at the described first pull-up gate structure both sides first Pull up drain region and the first pull-up source region；Second be located at respectively in described second the second transmission of transmission gate structure both sides fin passes Defeated source region and the second transmission drain region；The second drop-down source region in fin is pulled down positioned at the second pulldown gate structure both sides second With the second drop-down drain region；The second pull-up source region and second in fin is pulled up positioned at the described second pull-up gate structure both sides second Pull up source region；The the first shunting drain region and the first shunting source in fin are shunted positioned at the described first shunting gate structure both sides first Area；The second shunting drain region and the second shunting source region in fin are shunted positioned at the described second shunting gate structure both sides first；Position The 3rd shunting drain region and the 3rd shunting source region in fin are shunted in the described 3rd shunting gate structure both sides second；Positioned at described 4th shunting gate structure both sides second shunt the 4th shunting drain region and the 4th shunting source region in fin.

In the present embodiment, the step of forming doped region 302, includes：Form covering the first pull-up fin and second Pull up the first photoresist with sidewall surfaces at the top of fin；Using first photoresist as mask to described first drop-down fin, First transmission fin, the second drop-down fin, the second transmission fin, the first shunting fin and the second shunting fin carry out the first ion Injection forms the first transmission source region, the first transmission drain region, the first drop-down drain region, the first drop-down source region, the second transmission source region, the Two transmission drain regions, second drop-down drain region, second drop-down source region, first shunting source region, first shunting drain region, second shunting source region, Second shunting drain region, the 3rd shunting source region, the 3rd shunting drain region, the 4th shunting source region and the 4th shunting drain region；Described first from After son injection, covering the first transmission fin, the first drop-down fin, the second transmission fin, the second drop-down fin, the are formed The second photoresist at the top of one shunting fin and the second shunting fin with sidewall surfaces；It is mask to institute using second photoresist It states the first pull-up fin and the second pull-up fin carries out the second ion implanting, form the first pull-up drain region, the first pull-up source region, the Two pull-up source regions and the second pull-up drain region.

In the present embodiment, the first transmission source region, the first transmission drain region, the first drop-down drain region, the first drop-down source region, the Two transmission source regions, the second transmission drain region, the second drop-down drain region, the second drop-down source region first shunt source region, the first shunting drain region, the Two shunting source regions, the second shunting drain region, the 3rd shunting source region, the 3rd shunting drain region, the 4th shunting source region and the 4th shunting drain region In have the first Doped ions.First Doped ions are N-type ion, for example, phosphonium ion or arsenic ion.

In the present embodiment, the first drop-down drain region is connected with each other with the described first transmission source region, and formation first is public to mix Miscellaneous area, the second drop-down drain region are connected with each other with the described second transmission source region, form the second public doped region.

In the present embodiment, the first shunting drain region and the described second shunting source contact form the first shunting codope Area, so as to fulfill being electrically connected between the first shunting drain region and the described second shunting source region；It is described 3rd shunting drain region with it is described 4th shunting source contact forms the second shunting codope area, so as to fulfill the 3rd shunting drain region and the described 4th shunting source region Between electrical connection.

In the present embodiment, the storage organization includes：The first pull-down transistor positioned at the first drop-down area 312.

The substrate first, which pulls down area 312, has the first pull-down transistor, and first pull-down transistor includes：Positioned at institute State the first pulldown gate structure on 312 substrate of the first drop-down area；It is located at the first pulldown gate structure both sides substrate respectively The first drop-down source region and the first drop-down drain region, the first drop-down source region is for connecing the first current potential；

The substrate second, which pulls down area 322, has the second pull-down transistor, and second pull-down transistor includes：Positioned at institute State the second pulldown gate structure on substrate；The second drop-down in the substrate of the second pulldown gate structure both sides respectively Source region and the second drop-down drain region, the second pulldown gate structure are electrically connected with the described first drop-down drain region, second drop-down Drain region is electrically connected with the first pulldown gate structure, and the second drop-down source region is for the first current potential of application；

The first transmission transistor on 311 substrate of the first transmission range, first transmission transistor include：Position In the first transmission gate structure on the substrate；First be located at respectively in the described first transmission gate structure both sides substrate passes Defeated source region and the first transmission drain region, the first transmission source region are electrically connected with the described first drop-down drain region；

The second transmission transistor on 321 substrate of the second transmission range, second transmission transistor include： The second transmission gate structure is formed on second transmission range, 321 substrate；It is passed in the described second transmission gate structure both sides second The second transmission source region and the second transmission drain region, the second transmission source region and second time bleedout are formed in defeated 321 substrate of area Area is electrically connected.

In the present embodiment, the substrate further includes the first pull-up area 313 and the second pull-up area 323.On the substrate first Draw area 313 that there is the first pull-up to load, the substrate second pulls up area 323, and there is the second pull-up to load,

The first pull-up load includes first and pulls up transistor, and the second pull-up load includes crystal pulling on second Pipe.In other embodiments, the first pull-up load and the described second pull-up load can also include resistance.

In the present embodiment, the storage organization further includes：The crystal pulling on the first of the first pull-up area 313 of the substrate Body pipe, described first pull up transistor including：The first pull-up gate structure on the described first pull-up 313 substrate of area, point The first pull-up drain region that Wei Yu be in the first pull-up gate structure both sides substrate and the first pull-up source region；Positioned at the substrate The second pull-up area 323 second pull up transistor, described second pull up transistor including：Positioned at the described second pull-up area 323 The second pull-up gate structure on substrate pulls up the second pull-up source region in the substrate of gate structure both sides positioned at described second respectively With the second pull-up drain region.

In the present embodiment, first shunting zone of substrate 314 has the first flow dividing structure；Second shunting zone 324 has There is the second flow dividing structure.

First flow dividing structure includes：First shunting transistor, first shunting transistor include：Positioned at described The first shunting gate structure on one shunting zone, 314 substrate, the first shunting gate structure and the first pulldown gate knot Structure is electrically connected；The first shunting source region and first in the described first shunting 314 substrate of the first shunting zone of gate structure both sides Drain region is shunted, the first shunting output section includes the described first shunting source region.

First flow dividing structure further includes the second shunting transistor, and second shunting transistor includes：Positioned at described The second shunting gate structure on first shunting zone, 314 substrate, the second shunting gate structure and second pulldown gate Structure is electrically connected；The second shunting source region being located at respectively in the described second shunting 314 substrate of the first shunting zone of gate structure both sides With second shunting drain region, it is described first shunting input unit include described second shunting drain region, it is described second shunting source region with it is described First shunting drain region electrical connection.

In the present embodiment, second flow dividing structure includes：3rd shunting transistor and the 4th shunting transistor.

In the present embodiment, the 3rd shunting transistor includes：The 3rd shunting grid on 324 substrate of the second shunting zone Pole structure, the 3rd shunting gate structure are electrically connected with the second pulldown gate structure；Positioned at the described 3rd shunting grid The 3rd shunting source region and the 3rd shunting drain region in 324 substrate of the second shunting zone of structure both sides, the second shunting output section bag Include the 3rd shunting source region.

In the present embodiment, the 4th shunting transistor includes：The 4th point on 324 substrate of the second shunting zone Gate structure is flowed, the 4th shunting gate structure is electrically connected with the described second transmission gate structure；Positioned at the described 4th shunting The 4th shunting source region and the 4th shunting drain region in the substrate of the shunting gate structure both sides of gate structure both sides second, described second point Flowing input unit includes the described 4th shunting source region, and the 4th shunting drain region is electrically connected with the described 3rd shunting source region.

In other embodiments, first flow dividing structure can also only include the first shunting transistor, described first point Flowing output section includes the described first shunting source region, and the first shunting gate structure is electrically connected with the first pulldown gate structure It connects, the first shunting input unit includes the described first shunting drain region.

In other embodiments, second flow dividing structure can also only include the 3rd shunting transistor, described second point Flowing output section includes the described 3rd shunting source region, and the 3rd shunting gate structure is electrically connected with the second pulldown gate structure It connects, the second shunting input unit includes the described 3rd shunting drain region.

Fig. 9 is refer to, forms the wordline 330 of the connection first transmission gate structure and second transmission structure；Shape Into the first bit line 351 for connecting the first transmission drain region；Form second bit line 352 in connection the second transmission drain region.

The wordline 330 is used to control being switched on and off for first transmission transistor and the second transmission transistor；Institute The first bit line 351 and the second bit line 352 are stated for reading the data in formed memory construction, and to the memory knot Data are write in structure.

In the present embodiment, first bit line 351 is also connected with the first shunting input unit；Second bit line 352 is also Connect the second shunting input unit.

In other embodiments, first bit line can also be not connected to the first shunting input unit；The second Line can also be not connected to the second shunting input unit.The memory construction further includes：With the described first shunting input unit electricity 3rd bit line of connection；The 4th bit line being electrically connected with the described second shunting input unit.

It should be noted that during the read operation of the memory construction, in first bit line 351 and second Apply preset potential on bit line 352, the preset potential is high level " 1 "；Apply high level " 1 " in the wordline 330, then The second shunting transistor conducting；Meanwhile the if node that the first drop-down drain region is connected with the described first transmission source region Current potential for low level " 0 ", then the first shunting transistor turns on, so that first flow dividing structure turns on.Described first point Flow structure conducting can be such that the preset potential is connected by first flow dividing structure with ground terminal, and the ground terminal can be drawn The low preset potential transmits what source region was connected to the described first drop-down drain region so as to reduce preset potential with described first The influence of node potential so as to reduce interference of the static noise to formed memory, and then can improve memory Static noise capacity.

In the present embodiment, the forming method further includes：It is formed and connects the first public doped region and described first Pull up the first connecting line 371 of source region；It is formed and connects the second of the second public doped region and the second pull-up drain region Connecting line 372.

First connecting line 371 is used to implement the first drop-down drain region, the first transmission source region and the first pull-up source Electrical connection between area；Second connecting line 372 is used to implement the second drop-down drain region, the second transmission source region and described second Pull up the electrical connection between drain region.

In the present embodiment, the forming method further includes：Form the first drop-down source line of connection the first drop-down source region 331, the first drop-down source line 331 is used to apply the first current potential to the described first drop-down source region；It is formed under connection described second The second drop-down source line 332 of source region is drawn, the second drop-down source line 332 is used to apply described first to the described second drop-down source region Current potential.

In the present embodiment, first current potential is zero potential, and the first drop-down source line 331 and second pulls down source line 332 For being grounded.

In the present embodiment, the forming method further includes：Form the first pull-up thread cast-off in connection the first pull-up drain region 381, the first pull-up thread cast-off 381 is used to apply the second current potential to the described first pull-up drain region, and second current potential is more than institute State the first current potential；The second pull-up thread cast-off 382 of connection the second pull-up source region is formed, the second pull-up thread cast-off 382 is used for Second current potential is applied to the described second pull-up drain region.

In the present embodiment, the forming method further includes：It is formed and connects first connecting line 371 and the described second pull-up The first grid polar curve 361 of gate structure, the first grid polar curve 361 are used to implement the second pull-up gate structure and described the The electrical connection between bleedout area once；It is formed and connects second connecting line 371 and the second of the described first pull-up gate structure Gate line 362, the second gate line 362 are used to implement between the first pull-up gate structure and the second drop-down drain region Electrical connection.

To sum up, in the forming method of memory construction provided in an embodiment of the present invention, formed in the substrate shunt area There is flow dividing structure.In use, the flow dividing structure can be in interference signal and first transmission sources for the memory Access is formed between area, so as to reduce influence of the interference signal to the data of storage organization memory storage therefore, the shunting Structure can reduce interference of the static noise to memory, increase the static noise capacity of the memory.

The present invention also provides a kind of embodiments of memory construction, and with continued reference to Fig. 9, the memory construction includes：

Substrate, the substrate include memory block, the first transmission range 311 and the second transmission range 321；

Storage organization positioned at the substrate storage region, the storage organization include first connecting portion, second connecting portion and Grounding parts, the grounding parts are for the first current potential of application；

Positioned at the first transmission transistor of first transmission range of substrate 311, first transmission transistor includes：It is located at The first transmission gate structure on first transmission range, 311 substrate, respectively positioned at the described first transmission gate structure both sides lining The first transmission drain region and the first transmission source region in bottom, the first transmission source region are connected with the first connecting portion；

The first bit line being electrically connected with the described first transmission drain region；

Positioned at the second transmission transistor of second transmission range of substrate 321, second transmission transistor is located at described The second transmission gate structure on second transmission range, 321 substrate, passes respectively positioned at the described second transmission gate structure both sides second The second transmission drain region and the second transmission source region in defeated 321 substrate of area, the second transmission source region and second connecting portion electricity Connection；

The wordline being electrically connected with the described first transmission gate structure and the second transmission gate structure；

The second bit line being electrically connected with the described second transmission drain region；

The substrate at least further includes the first shunting zone 314 or the second shunting zone 324, first shunting zone of substrate 314 With the first flow dividing structure, first flow dividing structure includes：First shunting input unit and the first shunting output section, described first For applying preset potential, the first shunting output section is used to connect the grounding parts shunting input unit；The substrate second Shunting zone 324 has the second flow dividing structure, and second flow dividing structure includes：Second shunting input terminal and the second shunting output End, the second shunting input unit and the second shunting output section, the second shunting input unit are described for applying the preset potential Second shunting output section is used to connect the grounding parts.

The memory block is used to be subsequently formed storage organization；First transmission range 311 is to be subsequently used for forming the first biography The region of defeated transistor, second transmission range 321 are the region for being subsequently used for being formed the second transmission transistor；The shunting zone The region of the first flow dividing structure and the second flow dividing structure is formed to be subsequently used for.

In the present embodiment, the fin 301 includes：The first transmission fin in 311 substrate 300 of the first transmission range Portion；The second transmission fin in 321 substrate of the second transmission range；In the described first drop-down 312 substrate 300 of area First drop-down fin；The second drop-down fin on the described second drop-down 322 base 300 of area；Positioned at the described first pull-up area The first pull-up fin in 313 substrates 300；The second pull-up fin in the described second pull-up 323 substrate 300 of area；It is located at The first shunting fin in first shunting zone, 314 substrate 300；Second in 324 substrate 300 of the second shunting zone Shunt fin.

In the present embodiment, the fin 301 is of same size, and the height of the fin 301 is identical,.In other embodiment In, the width of the fin can also differ, and the height of the fin can also differ.

In the present embodiment, first transmission range 311 is connected with the described first drop-down area 312, the first transmission fin It is connected with the described first drop-down fin；Second transmission range 321 is connected with the described second drop-down area 322, second transmission Fin is connected with the described second drop-down fin.

In the present embodiment, the memory construction further includes the isolation structure (not shown) in substrate

In the present embodiment, the storage organization includes：The first pull-down transistor positioned at the first drop-down area 312, positioned at the First transmission transistor of one transmission range 311 pulls down second pull-down transistor in area 322 positioned at second, positioned at the second transmission range 321 the second transmission transistor.

In the present embodiment, the grounding parts are for applying the first current potential, specifically, the grounding parts are grounded, thus The grounding parts apply the first current potential.

First pull-down transistor includes：The first pulldown gate structure on the described first drop-down 312 substrate of area； The first drop-down source region and first time bleedout in the first drop-down 312 substrate of area of the first pulldown gate structure both sides Area, the first drop-down source region is for the first current potential of application.

In the present embodiment, the first pulldown gate structure is across the described first drop-down fin, second pulldown gate The structure covering first drop-down fin partial sidewall and top surface；The first drop-down source region and the described first drop-down drain region Respectively in the first drop-down fin of the first pulldown gate structure both sides.

In the present embodiment, second pull-down transistor includes：Positioned at described second drop-down 322 substrate of area on second under Draw gate structure；The second drop-down source region and the in 322 substrate of area is pulled down positioned at the second pulldown gate structure both sides second Two drop-down drain regions, the second pulldown gate structure are electrically connected with the described first drop-down drain region, the second drop-down drain region and institute The electrical connection of the first pulldown gate structure is stated, the second drop-down source region is for the first current potential of application.

In the present embodiment, the second pulldown gate structure is across the described second drop-down fin, second pulldown gate The structure covering second drop-down fin partial sidewall and top surface；The second drop-down source region and the described second drop-down drain region Respectively in the second drop-down fin of the second pulldown gate structure both sides.

First transmission transistor includes：The first transmission gate structure on 311 substrate of the first transmission range； The first transmission source region and the first transmission leakage in 311 substrate of the first transmission range of the described first transmission gate structure both sides Area, the first transmission source region are electrically connected with the described first drop-down drain region.

In the present embodiment, the first transmission gate structure is across the described first transmission fin, the first transmission gate structure Cover the first transmission fin partial sidewall and top surface.

In the present embodiment, the first transmission source region is located at the described first transmission grid respectively with the described first transmission drain region In first transmission fin of structure both sides.

In the present embodiment, second transmission transistor includes：Second on 321 substrate of the second transmission range passes Defeated gate structure；The second transmission source region in 321 substrate of the second transmission range of the described second transmission gate structure both sides and Second transmission drain region, the second transmission source region are electrically connected with the described second drop-down drain region.

In the present embodiment, the second transmission gate structure is across the described second transmission fin, the second transmission grid The structure covering second transmission fin partial sidewall and top surface.

In the present embodiment, the second transmission source region is located at the described second transmission grid respectively with the described second transmission drain region In second transmission fin of structure both sides.

In the present embodiment, first flow dividing structure includes：First across the described first shunting fin shunts grid group, The first shunting grid group is located at the described first shunting fin atop part and sidewall surfaces.

In the present embodiment, second flow dividing structure includes：Second across the described second shunting fin shunts grid group, The second shunting grid group is located at the described second shunting fin atop part and sidewall surfaces.

In the present embodiment, the substrate further includes the first pull-up area 313 and the second pull-up area 323.The storage organization is also Including：The first pull-up load positioned at the first pull-up area 313；The second load positioned at the second 323rd area of pull-up.In other embodiment In, the memory block can not also include the described first pull-up area and the second pull-up area, and the storage organization can not also include The first pull-up load and the second pull-up load.

The first pull-up load includes first and pulls up transistor, and the second pull-up load includes crystal pulling on second Pipe.In other embodiments, described first pull up transistor to pull up transistor with second and can also include resistance.

In the present embodiment, described first pull up transistor including：Positioned at described first pull-up 313 substrate of area on first on Gate structure is drawn, respectively the first pull-up drain region and the first pull-up source in the described first pull-up gate structure both sides substrate Area.

In the present embodiment, the first pull-up gate structure is across the described first pull-up fin, the first pull-up gate structure Cover the first pull-up fin partial sidewall and top surface.

In the present embodiment, the first pull-up drain region is located at the described first pull-up grid respectively with the described first transmission drain region In first pull-up fin of structure both sides.

In the present embodiment, described second pull up transistor including：Positioned at described second pull-up 323 substrate of area on second on Gate structure is drawn, respectively the bleedout in the second pull-up source region and second in the described second pull-up gate structure both sides substrate Area.

In the present embodiment, the second pull-up gate structure is across the described second pull-up fin, the second pull-up gate structure Cover the second pull-up fin partial sidewall and top surface.

In the present embodiment, the second pull-up source region is located at the described second pull-up grid respectively with the described first pull-up drain region In second pull-up fin of structure both sides.

In the present embodiment, the first pulldown gate structure is contacted with the described first pull-up gate structure, so as to fulfill institute State being electrically connected between the first pulldown gate structure and the described first pull-up gate structure；The second pulldown gate structure and institute The contact of the second pull-up gate structure is stated, so as to fulfill between the second pulldown gate structure and the second pull-up gate structure Electrical connection.

In other embodiments, the first pulldown gate structure can not also connect with the described first pull-up gate structure It touches, the first pulldown gate structure is connected with the described first pull-up gate structure by conductive structure；The second drop-down grid Pole structure can not also be contacted with the described second pull-up gate structure, the second pulldown gate structure and the described second pull-up grid Pole structure is connected by conductive structure.

In the present embodiment, the substrate shunt area includes the first shunting zone 314 and the second shunting zone 324, the substrate the One shunting zone 314 has the first flow dividing structure, and first flow dividing structure includes：First shunting input unit and the first shunting output Portion, for applying preset potential, the first shunting output section is used to connect the grounding parts the first shunting input unit；Institute The second shunting zone of substrate 324 is stated with the second flow dividing structure, second flow dividing structure includes：Second shunting input unit and second Output section is shunted, for applying the preset potential, the second shunting output section is used to meet institute the second shunting input unit State grounding parts.In other embodiments, the substrate can also only include the first shunting zone or the second shunting zone.

First flow dividing structure includes：First shunting transistor, first shunting transistor include：Positioned at described The first shunting gate structure on one shunting zone, 314 substrate, the first shunting gate structure and the first pulldown gate knot Structure is electrically connected；The first shunting source region and the first shunting in described first shunting the first shunting zone of gate structure both sides substrate Drain region, the first shunting output section include the described first shunting source region.

First flow dividing structure further includes the second shunting transistor, and second shunting transistor includes：Positioned at described The second shunting gate structure on first shunting zone substrate, the second shunting gate structure and the described first transmission gate structure Electrical connection；It is located at the second shunting source region in described second shunting the first shunting zone of gate structure both sides substrate and second point respectively Drain region is flowed, the first shunting input unit includes the described second shunting drain region, the second shunting source region and the described first shunting Drain region connects.

In the present embodiment, the first shunting gate structure forms the first shunting grid with the described second shunting gate structure Group.

In the present embodiment, the 4th shunting transistor includes：The 4th point on 324 substrate of the second shunting zone Gate structure is flowed, the 4th shunting gate structure is electrically connected with the described second transmission gate structure；Positioned at the described 4th shunting The 4th shunting source region and the 4th shunting drain region in the substrate of gate structure both sides, the second shunting input unit include the described 4th shunting Drain region, the 4th shunting source region are electrically connected with the described 3rd shunting drain region.

In the present embodiment, the 3rd shunting gate structure forms the second shunting grid with the described 4th shunting gate structure Group.

In other embodiments, first flow dividing structure can also only include the first shunting transistor, described first point Flowing output section includes the described first shunting source region, and the first shunting output section includes the described first shunting drain region.

In other embodiments, second flow dividing structure can also only include the second shunting transistor, described second point Flowing output section includes the described 3rd shunting source region, and the second shunting output section includes the described 4th shunting drain region.

In the present embodiment, the first shunting gate structure and the first pulldown gate form touch, so as to fulfill second point Stream gate structure is electrically connected with the first pulldown gate structure；Second shunting gate structure and the described first transmission grid knot Structure contacts, so as to fulfill the first shunting gate structure transmit gate structure with described first and be electrically connected.In other embodiment In, the first shunting gate structure can not also be contacted with the first pulldown gate structure, realized and be electrically connected by conductive structure； The second shunting gate structure can not also be contacted with the described first transmission gate structure, be electrically connected by conductive structure realization It connects.

In the present embodiment, the 3rd shunting gate structure and the second pulldown gate form touch, so as to fulfill the Being electrically connected between three shunting gate structures and the second pulldown gate structure；The 4th shunting gate structure and described the Two transmission gate structure contacts, so as to fulfill the electricity between the described 4th shunting gate structure and the first transmission gate structure Connection.In other embodiments, the 3rd shunting gate structure can not also be contacted with the second pulldown gate structure, by leading Electric structure realizes electrical connection；The 4th shunting gate structure can not also be contacted with the described second transmission gate structure, be passed through Conductive structure realizes electrical connection.

In the present embodiment, the first pull-up gate structure, the second pull-up gate structure, first pulldown gate Knot, the second pulldown gate structure, the first transmission gate structure, the second transmission gate structure, the first shunting grid group and second point It flows grid group and forms gate structure 340.

In the present embodiment, the first transmission source region, the first transmission drain region, the first drop-down drain region, the first drop-down source region, the Two transmission source regions, the second transmission drain region, the second drop-down drain region, the second drop-down source region first shunt source region, the first shunting drain region, the Two shunting source regions, second shunting drain region, the 3rd shunting source region, the 3rd shunting drain region, the 4th shunting source region, the 4th shunting drain region, The first pull-up drain region, the first pull-up source region, the second pull-up source region and the second pull-up drain region form doped region 304.

The wordline 330 is used to control being switched on and off for first transmission transistor and the second transmission transistor；Institute The first bit line 351 and the second bit line 352 are stated for reading the data in formed memory, and is write into the memory Data.

In the present embodiment, first bit line 351 is also connected with the first shunting input unit；Second bit line 352 is also Connect the second shunting input unit.In other embodiments, it is defeated can also to be not connected to first shunting for first bit line Enter portion；Second bit line can also be not connected to the second shunting input unit.

It should be noted that during the read operation of the memory construction, in the reading of the memory construction In operating process, apply preset potential on 351 and second bit line 352 of the first bit line, the preset potential is high level “1”；Apply high level " 1 " in the wordline 330, then the second shunting transistor conducting；Meanwhile if under described first Bleedout area is low level " 0 " with the current potential for the node that the described first transmission source region is connected, then the first shunting transistor turns on, so as to Turn on first flow dividing structure.The first flow dividing structure conducting can be such that the preset potential is shunted by described first Structure is connected with ground terminal, and the ground terminal can drag down the preset potential, so as to reduce preset potential to described The influence for the node potential that bleedout area is connected with the described first transmission source region once, so as to reduce static noise to being formed The interference of memory, and then the static noise capacity of memory can be improved.

In the present embodiment, the memory further includes：Connect the described first public doped region and the first pull-up source First connecting line 371 in area；Connect the described second public doped region and second connecting line 372 in the second pull-up drain region.

In the present embodiment, the memory further includes：Connect the first drop-down source line 331 of the first drop-down source region, institute The first drop-down source line 331 is stated for applying the first current potential to the described first drop-down source region；Connect the of the second drop-down source region Two drop-down source lines 332, the second drop-down source line 332 are used to apply first current potential to the described second drop-down source region.

In the present embodiment, first current potential is zero potential, i.e., described first drop-down source line 331 and second pulls down source line 332 are used to be grounded.

In the present embodiment, the memory further includes：Connect the first pull-up thread cast-off 381 in the first pull-up drain region, institute The first pull-up thread cast-off 381 is stated for applying the second current potential to the described first pull-up drain region, second current potential is more than described first Current potential；The second pull-up thread cast-off 382 in the second pull-up drain region is connected, the second pull-up thread cast-off 382 is used for described second It pulls up drain region and applies second current potential.

In the present embodiment, the memory further includes：Connect first connecting line 371 and the described second pull-up grid knot The first grid polar curve 361 of structure, the first grid polar curve 361 are used to implement the second pull-up gate structure and the described first drop-down Electrical connection between drain region；The second gate line 362 of second connecting line 371 and the described first pull-up gate structure is connected, The second gate line 362 is used to implement being electrically connected between the first pull-up gate structure and the described second drop-down drain region.

To sum up, in the memory construction that the embodiment of the present invention provides, the memory construction includes at least the first shunting Structure and the second flow dividing structure, and the memory circuitry includes at least the first dividing cell and the second dividing cell.Described One dividing cell can reduce interference of the static noise to the memory circuitry on the first shunting input terminal；Described Two dividing cells can reduce interference of the static noise to the memory circuitry on the second shunting input terminal, thus may be used See, the forming method can reduce interference of the static noise to memory construction, and the static state for increasing the memory construction is made an uproar Acoustical volume.

Figure 10 is the structure diagram of the another embodiment of memory construction of the present invention.

0 is please referred to Fig.1, the memory construction of the present embodiment and the something in common of a upper embodiment do not repeat herein, Difference includes：

In the present embodiment, the first shunting input unit is not electrically connected with first bit line；The second shunting input Portion is not electrically connected with second bit line.

The memory construction further includes：Connect the 3rd bit line 411 of the first shunting input unit；Connect the described 4th 4th bit line 421 of input unit.

In the present embodiment, during the data stored in reading the storage organization, apply in the wordline 330 High level " 1 " turns on first transmission transistor and second transmission transistor, while first shunting transistor It is turned on second shunting transistor.

In the present embodiment, during the data stored in reading the storage organization, pass through the 3rd bit line 411 It is read out with the 4th bit line 421.

Specifically, apply preset potential, the preset potential on the 3rd bit line 411 and the 4th bit line 421 For high level " 1 ".

The first drop-down drain region and the first memory node that the described first transmission drain region junction is the memory；Institute State second memory node of the second drop-down drain region with the described second transmission drain region junction for the memory.

If the current potential of first memory node is high level " 1 ", the current potential in the second pulldown gate structure is High level " 1 ", the current potential in the second pulldown gate structure is with the second memory node current potential on the contrary, second memory node Current potential for low level " 0 ", so as to which the current potential of the first pulldown gate structure is low level " 0 ".

Since the current potential of the second pulldown gate structure is high level " 1 ", second pulls up transistor gate structure and institute The electrical connection of the second pulldown gate structure is stated, then second is pulled up transistor cut-off, the second pull-down transistor and the 3rd shunting transistor Conducting, so that forming access between the 4th bit line 421 and grounding parts, first current potential can drag down described 4th The current potential of line 421, so that the 4th bit line 421 output low level " 0 ", identical with the second memory node current potential, from And the storage data of the second memory node can be read by the 4th bit line 421.

Since the current potential of the first pulldown gate structure is low level " 0 ", the first pull-up gate structure and the first drop-down Gate structure is electrically connected, then first is pulled up transistor conducting, and the first pull-down transistor and the first shunting transistor end, so that 3rd bit line 411 is disconnected with first current potential, and then the preset potential applied on the 3rd bit line 411 will not be drawn It is low, so that the 3rd bit line 411 output high level " 1 ", so as to read first storage by the 3rd bit line 411 The data of node storage.

If the current potential of second memory node is high level " 1 ", the current potential in the first pulldown gate structure is High level " 1 ", the first pulldown gate structure is with the first memory node current potential on the contrary, the current potential of first memory node is Low level " 0 ", so as to which the current potential of the second pulldown gate structure is low level " 0 ".

Since the current potential of the first pulldown gate structure is high level " 1 ", first pulls up transistor cut-off, and first pulls down Transistor and the conducting of the first shunting transistor, so that form access between the 3rd bit line 411 and the first current potential, described the One current potential can drag down the current potential of the 3rd bit line 411, so that the 3rd bit line 411 output low level " 0 ", and described First memory node current potential is identical, so as to read the storage data of the first memory node by the 3rd bit line 411.

Since the current potential of the second pulldown gate structure is low level " 0 ", second pulls up transistor conducting, and second pulls down Transistor and the cut-off of the 3rd shunting transistor, so that the 4th bit line 421 and first current potential disconnect, and then described the The preset potential applied on four bit lines 421 will not be pulled low, so that the 4th bit line 421 output high level " 1 ", so as to The data of the second memory node storage are enough read by the 4th bit line 421.

It can be drawn by analyzing above, in the present embodiment, institute is read by the 3rd bit line 411 and the 4th bit line 421 State the data in storage organization, in the reading process, the preset potential will not be applied to first memory node and On second memory node, so as to be not easy to influence the data stored in the storage organization, so as to which read error be less likely to occur, Therefore, the anti-noise jamming ability of the memory is improved, and static noise capacity is increased.

To sum up, in memory construction provided in an embodiment of the present invention, the memory construction is made to include at least the first shunting Structure and the second flow dividing structure.The memory applies preset potential, institute in read operation, in the described first shunting input unit Preset potential is stated as high level " 1 ".

Figure 11 is the circuit diagram of one embodiment of memory circuitry of the present invention.

Specifically, the present embodiment is the circuit diagram of the memory construction of Figure 10.

1 is please referred to Fig.1, the memory circuitry includes：Storage unit 20, the storage unit 20 include：First connection End 31, second connection end 32 and ground terminal, the ground terminal is for the first current potential of application；

First transmission transistor PG1, the first transmission transistor PG1 include：First transmission grid, the first transmission source electrode With the first transmission drain electrode, the first transmission source electrode is connected with first connecting pin 31；

Connect the first bit line BL1 of the first transmission drain electrode；

Second transmission transistor PG2, the second transmission transistor PG2 include：Second transmission grid, the second transmission source electrode With the second transmission drain electrode, the second transmission source electrode is connected with the second connection end 32；

Connect the first wordline WL of the first transmission grid and the second transmission grid；

Connect the second bit line BL2 of the second transmission drain electrode；

Dividing cell, the dividing cell include at least the first dividing cell 12 or the second dividing cell 22；Described first Dividing cell 12 includes：First shunting input terminal and the first shunting output terminal, the first shunting input terminal are default for inputting Current potential, the first shunting output terminal are used to be connected with the ground terminal；Second dividing cell 22 includes：Second shunting is defeated Enter end and the second shunting output terminal, the second shunting output terminal is connected with the ground terminal, and the second shunting input terminal is used In the input preset potential.

In the present embodiment, the first shunting input terminal inputs the preset potential by the first bit line, described second point It flows input terminal and the preset potential is inputted by the second bit line.

In the present embodiment, the memory is six pipe memories.In other embodiments, the memory can also be four Pipe memory or four pipes plus two Memisters.

In the present embodiment, the storage unit 20 includes：First pull-down transistor PD1, the first pull-down transistor PD1 Including：First pulldown gate；First drop-down source electrode and the first drop-down drain electrode, the first drop-down drain electrode and first transmission sources Pole connects；

Second pull-down transistor PD2, the second pull-down transistor PD2 include：Second pulldown gate, second drop-down Grid and the described first drop-down drain electrode connection；Second drop-down source electrode, the second drop-down drain electrode connect with the described second transmission source electrode It connects；Second drop-down drain electrode, the second drop-down drain electrode are connected with first pulldown gate.

In the present embodiment, first current potential is low level, by the way that the ground terminal ground connection is made to apply in the ground terminal First current potential.

In the present embodiment, the memory circuitry further includes：First pull-up load, the first pull-up load include：The One load input terminal, first load input terminal are more than the first electricity for inputting the second current potential Vdd, the second current potential Vdd Position Vss；First load outputs, first load outputs connect the first pull-down transistor drain electrode；Second pull-up is negative It carries, the second pull-up load includes：Second load input terminal, second load input terminal are used to input second current potential Vdd；Second load outputs, second load outputs connect the second pull-down transistor drain electrode.In other embodiment In, the storage unit can not also include the first pull-up load and the second pull-up loads.

In the present embodiment, the first pull-up load includes first and pulls up transistor PU1, and described first pulls up transistor PU1 includes：First pull-up grid, the first pull-up grid are connected with first pulldown gate；First pull-up drain electrode, it is described First pull-up drain electrode connects first load input terminal, the first pull-up source electrode, the first pull-up source electrode connection described first Load outputs；

In the present embodiment, the second pull-up load includes second and pulls up transistor PU2, and described second pulls up transistor PU2 includes：Second pull-up grid, the pull-up grid connect second pulldown gate；Second pull-up drains, bleedout on second Pole connects second load input terminal；Second pull-up source electrode, the second pull-up source electrode connect second load outputs.

In the present embodiment, the first pull-down transistor PD1, the second pull-down transistor PD2, the first transmission transistor PG1, Second transmission transistor PG2 is NMOS transistor；Described first PU1 and second that pulls up transistor pulls up transistor PU2 as PMOS Transistor.

In the present embodiment, the first pull-down transistor PD1 and first pull up transistor PU1 form the first phase inverter；Institute State the second pull-down transistor PD2 and second pull up transistor PU2 form the second reverser.Then first reverser and described the Two reversers form storage unit.The storage unit realizes the storage to data by the effect of latch.

In the present embodiment, the first pull-up source electrode at the tie point of the described first drop-down drain electrode with forming the memory The first memory node A；The second pull-up drain electrode at the tie point of the described second drop-down drain electrode with forming the memory Second memory node B；It is the first tie point 1 at the first pull-up grid and the tie point of the first pulldown gate connection, it is described It is the second tie point 2 at second pull-up grid and the tie point of the second pulldown gate connection.

Due to the first pull-down transistor PD1 and first pull up transistor PD2 form the first reverser, it is described first storage section The current potential of point A and first tie point 1 on the contrary, first tie point 1 is identical with the current potential of the second memory node B, Therefore, the current potential of the second memory node B and the first memory node A are on the contrary, again due to the current potential of the second memory node B and The current potentials of two tie points 2 is on the contrary, function so as to fulfill latch.

If specifically, the current potential of memory node A be high level " 1 ", the current potential and the first memory node of the first tie point 1 The current potential of A is on the contrary, then the current potential of the first tie point 1 is low level " 0 ", so as to which the current potential of the second memory node B is low level " 0 ", and due to the current potential of the second memory node B and the second tie point 2 on the contrary, the current potential of second tie point 2 is high level " 1 ", memory node A are high level " 1 ".It can be seen that the storage unit can realize the function of latch.

In the present embodiment, first current potential is zero potential.Specifically, under the first shunting output terminal, described first Pull transistor source electrode, the second shunting output terminal and the second pull-down transistor source electrode ground connection.

In the present embodiment, the wordline WL opens for control the first transmission transistor PG1's and the second transmission transistor PG2 It opens and turns off.So as to fulfill the selection to storage unit, and the data in selected storage unit 30 are read out, are write With storage.

In the present embodiment, the biographies of the first transmission transistor PG1 and second can be made by applying high level " 1 " on the wordline WL Defeated transistor PG2 conducting so that the first bit line BL1 is connected with the storage unit 30, make the second bit line BL2 with it is described Storage unit 30 is connected.

, it is necessary in the first bit line BL1 and second during the data stored in reading the storage unit 30 Apply preset potential on bit line BL2, the preset potential is high level " 1 ".Since the first memory node A and second is stored The current potential of node B on the contrary, must be low level " 0 " there are one the current potential of node in the first memory node A and the second memory node B, The preset potential easily inverts the current potential of the memory node for low level " 0 ", so as to which read error occur.Described One dividing cell 11 and the second dividing cell 12 can turn in reading process, so that the first current potential Vss passes through described point Stream unit drags down the preset potential being connected with for the memory node of low level " 0 ", so as to reduce read error, and then can Increase the antijamming capability of the memory, increase the static noise capacity of the memory.

In the present embodiment, in order to reduce interference of the static noise to the memory, the memory circuitry includes：First Dividing cell 12, first dividing cell 12 include：First shunting input terminal and the first shunting output terminal, first shunting Input terminal is connected with the first bit line BL1, and the first shunting output terminal is used to be connected with ground terminal；Second dividing cell 22, second dividing cell 22 includes：Second shunting input terminal and second shunting output terminal, it is described second shunting input terminal with The second bit line BL2 connections, the second shunting output terminal are connected with affiliated ground terminal.

In the present embodiment, first dividing cell 12 includes：First shunting transistor PG1, the first shunting crystal Pipe PG1 includes：First shunting grid, the first shunting grid are connected with first pulldown gate；First shunting source electrode and First shunting drain electrode, the first shunting source electrode connect the ground terminal.

In the present embodiment, first dividing cell 12 further includes the second shunting transistor FG1, the second shunting crystal Pipe FG1 includes：Second shunting grid, the second shunting grid are connected with the described first transmission grid；Second shunting source electrode, institute State the second shunting source electrode and the described first shunting drain electrode connection；Second shunting drain electrode, the second shunting drain electrode and described first Shunt input terminal connection.

In the present embodiment, if the first memory node A be low level " 0 ", the first tie point 1 be high level " 1 ", institute It is the first preset potential to state the preset potential applied on the first bit line BL1；In reading process, the wordline WL connects high point position " 1 ", the first transmission transistor PG1 and the second shunting transistor FG1 conductings, the first tie point 1 is high level " 1 ", then under first Pull transistor PD1 and the first shunting transistor FD1 conductings, therefore, first preset potential and the ground terminal can be with Access is formed by first dividing cell 12, so that the first current potential Vss can pass through first dividing cell 12 drag down the preset potential, and the current potential for making the first memory node A so as to prevent the preset potential inverts, And then the first bit line BL1 can be enable to export and correctly read result.Therefore, first dividing cell 12 can drop Interference of the low static noise to the memory, so as to increase the static noise capacity of the memory.

Second dividing cell 22 includes：3rd shunting transistor FD2, the 3rd shunting transistor FD2 include：The Three shunting grids, the 3rd shunting grid are connected with second pulldown gate；3rd shunting source electrode and the 3rd shunting drain electrode, The 3rd shunting source electrode is connected with the second shunting output terminal；

4th shunting transistor FG2, the 4th shunting transistor FG2 include：4th shunting grid, the 4th shunting Grid is connected with the described second transmission grid；4th shunting source electrode, the 3rd shunting drain electrode of the 4th shunting source electrode connection；4th Shunting drain electrode, the 4th shunting drain electrode are connected with the described second shunting input terminal.

In the present embodiment, if the second memory node B be low level " 0 ", the second tie point 2 be high level " 1 ", institute It is preset potential to state the preset potential applied on the second bit line BL1；In reading process, the wordline WL connects high point position " 1 ", the Two transmission transistor PG1 and the 4th shunting transistor FG2 conductings, the second tie point are high level " 1 ", then the second pull-down transistor PD1 and the 4th shunting transistor FD1 conductings, therefore, the preset potential can pass through described second with the ground terminal Dividing cell 22 forms access, is preset so that the ground terminal can drag down described second by second dividing cell 22 Current potential, so that the second bit line BL1, which can be exported, correctly reads result.Therefore, second dividing cell 22 can Interference of the static noise to the memory is reduced, so as to increase the static noise capacity of the memory.

In other embodiments, first dividing cell can also only include first shunting transistor, and described One shunting source region is connected with the ground terminal, and the first shunting drain region is connected with first bit line；Second shunting is single Member can also only include the 3rd shunting transistor, and the 3rd shunting source region is connected with the ground terminal, described 3rd point Stream drain region is connected with second bit line.

In other embodiments, first dividing cell and the second dividing cell can also include resistance.

In memory circuitry provided in an embodiment of the present invention, the memory circuitry includes at least the first dividing cell and the Two dividing cells.First dividing cell can reduce it is described first shunting input terminal on static noise to the memory The interference of circuit；Second dividing cell can reduce it is described second shunting input terminal on static noise to the memory The interference of circuit.It can be seen that static noise is smaller to the interference of memory circuitry, the static noise capacity of the memory compared with Greatly.

Figure 12 is the structure diagram of another embodiment of memory circuitry of the present invention.

In the present embodiment, the memory circuitry and the something in common of a upper embodiment do not repeat herein, difference Place is as shown in figure 12.

2 are please referred to Fig.1, the memory circuitry further includes：3rd bit line BL1a, described in the 3rd bit line BL1a connections First shunting input terminal；4th bit line BL2a, the 4th bit line BL2a connections the second shunting input terminal.

In the present embodiment, the preset potential is applied to the described first shunting input terminal by the 3rd bit line BL1a, The preset potential is applied to the described second shunting input terminal by the 4th bit line BL2a.

In the present embodiment, during the data stored in reading the storage unit 30, applied on the wordline WL Increase level " 1 ", turn on the first transmission transistor PG1 and the second transmission transistor PG2, while described first point Flow transistor FG1 and the 4th shunting transistor FG2 conductings.

In the present embodiment, during the data stored in reading the storage unit 30, pass through the 3rd bit line BL1a and the 4th bit line BL2a are read out.

Specifically, apply preset potential on the 3rd bit line BL1a and the 4th bit line BL2a, the default electricity Position is high level " 1 ".

If the current potential of the first memory node A is high level " 1 ", the current potential of second tie point 2 is high level " 1 ", the second tie point 2 with the second memory node current potential on the contrary, the current potential of the second memory node B is low level " 0 ", So as to which the current potential of first tie point 1 is low level " 0 ".

Since the current potential of second tie point 2 is high level " 1 ", second pulls up transistor PU2 cut-offs, second time crystal pulling Body pipe PD2 and the 3rd shunting transistor FD2 conductings, so that access is formed between the 4th bit line BL2a and ground terminal, institute Current potential on the 4th bit line BL2a can be dragged down by stating ground terminal, so that the 4th bit line BL2a output low levels " 0 ", So that the current potential of the 4th bit line BL2a is identical in the second memory node B current potentials, so as to pass through the 4th bit line BL2a reads the storage data of the second memory node B.

Since the current potential of first tie point 1 is low level " 0 ", first pulls up transistor PU1 conductings, first time crystal pulling Body pipe PD1 and the first shunting transistor FD1 cut-offs, so that the 3rd bit line BL1a is disconnected with the ground terminal, Jin Ersuo Stating the preset potential applied on the 3rd bit line BL1a will not be pulled low, so that the 3rd bit line BL1a output high level " 1 ", So as to read the data of the first memory node A storages by the 3rd bit line BL1a.

If the current potential of the second memory node B is high level " 1 ", the current potential of first tie point 1 is high level " 1 ", the first tie point 1 is with the first memory node A current potentials on the contrary, the current potential of the first memory node A is low level " 0 ", so as to which the current potential of second tie point 2 is low level " 0 ".

Since the current potential of first tie point 1 is high level " 1 ", first pulls up transistor PU1 cut-offs, first time crystal pulling Body pipe PD1 and the first shunting transistor FD1 conductings, so that access is formed between the 3rd bit line BL1a and ground terminal, institute Current potential on the 3rd bit line BL1a can be dragged down by stating ground terminal, so that the 3rd bit line BL1a output low levels " 0 ", It is identical with the first memory node A current potentials, so as to read depositing for the first memory node A by the 3rd bit line BL1a Store up data.

Since the current potential of second tie point 2 is low level " 0 ", second pulls up transistor PU2 conductings, second time crystal pulling Body pipe PD2 and the 3rd shunting transistor FD2 cut-offs, so that the 4th bit line BL2a is disconnected with the ground terminal, therefore institute Stating the preset potential applied on the 4th bit line BL2a will not be pulled low, so that the 4th bit line BL2a output high level " 1 ", So as to read the data of the second memory node B storages by the 4th bit line BL2a.

It can be drawn by analyzing above, in the present embodiment, the 3rd bit line BL1a and the 4th bit line BL2a can be passed through The data in the storage unit 30 are read, in the reading process, the preset potential will not be applied to described first and deposit It stores up on node A and the second memory node B, so as to be not easy to influence the data stored in the storage unit 30, so as to be not easy Generation read error, therefore, the anti-noise jamming ability of the memory are improved, and static noise capacity is increased.

In the present embodiment, first dividing cell 12 includes：First shunting transistor FD1 and the second shunting transistor FG1；Second dividing cell 22 includes：3rd shunting transistor FD2 and the 4th shunting transistor FG2.

In other embodiments, first dividing cell can also only include first shunting transistor, and described First shunting drain electrode is connected with the 3rd bit line, and the first shunting source region is connected with the ground terminal；Second shunting Unit can also only include the 3rd shunting transistor, and the 3rd shunting drain electrode is connected with the 4th bit line, and described the Three shunting source regions are connected with the ground terminal.

To sum up, in memory circuitry provided in an embodiment of the present invention, it is single that the memory circuitry includes at least the first shunting Member and the second dividing cell.First dividing cell can reduce it is described first shunting input terminal on static noise to described The interference of memory circuitry；Second dividing cell can reduce it is described second shunting input terminal on static noise to described The interference of memory circuitry.It can be seen that static noise is smaller to the interference of memory circuitry, the static noise of the memory Capacity is larger.

The present invention also provides a kind of embodiments of the method for work of memory.

Memory circuitry is provided with continued reference to Figure 11.

In the present embodiment, memory circuitry phase of the memory circuitry described in one embodiment of memory circuitry Together, do not repeat herein.

In the present embodiment, the first shunting input terminal is connected with the first bit line BL1；The second shunting input terminal Connect the second bit line BL2.

With continued reference to Figure 11, the first current potential is applied to the grounding parts.

In the present embodiment, first current potential is low level " 0 ".

In the present embodiment, by being grounded the first drop-down source region and the second drop-down source region, so as to described the Apply the first current potential in one pull-down transistor source region and the second pull-down transistor source region.

In the present embodiment, the storage unit 30 further includes：First pull-up load, the first pull-up load include：The One load input terminal and the first load outputs, first load outputs connect the first pull-down transistor drain region, institute State the first load input terminal for apply the second current potential, second current potential is more than first current potential；Second pull-up load, institute Stating the load of the second pull-up includes：Second load input terminal and the second load outputs, described in second load outputs connection Second pull-down transistor drain region, second load input terminal are used to apply the second current potential Vdd.

The method of work further includes：Second electricity is applied to first load input terminal and second load input terminal Position Vdd, the second current potential Vdd are more than the first current potential Vss.

In the present embodiment, the second current potential Vdd is high level " 1 ".

In other embodiments, the memory circuitry does not include the described first pull-up load and the described second pull-up is negative It carries.The method of work does not include：Second current potential is applied to first load input terminal and second load input terminal Step.

With continued reference to Figure 11, word line potential is connected on the wordline WL, the word line potential is more than the described first electricity Position Vss.

In the present embodiment, the word line potential is high level " 1 ".

In the present embodiment, since the first transmission transistor PG1 and the second transmission transistor PG2 is NMOS crystal Pipe, the word line potential are high level " 1 ", then the first transmission transistor PG1 and the second transmission transistor PG2 conductings.

In the present embodiment, the second shunting transistor FG1 and the 4th shunting transistor FG2 are NMOS transistor, then institute State the second shunting transistor FG1 and the 4th shunting transistor FG2 conductings.

With continued reference to Figure 11, apply operating potential on the first bit line BL1 and the second bit line BL2.

In the present embodiment, the method for work includes：Write operation and read operation.

In said write operation, the operating potential is storage current potential.

Include applying the step of storing current potential on the first bit line BL1 and the second bit line BL2：Described first Apply storage current potential on bit line BL1 and the second bit line BL2, storage signal is formed in the storage unit 30.

If specifically, the signal to be stored be high level " 1 ", the storage applied on the first bit line BL1 Current potential is high level " 1 "；The storage current potential applied on the second bit line BL2 is low level " 0 ".

Since the current potential on the first wordline BL1 is high level " 1 ", the current potential of the first memory node A is high electricity Flat " 1 "；Since the current potential on the second wordline BL2 is low level " 0 ", then the current potential on the second memory node B is low Level " 0 ".

The current potential of the first memory node A is high level " 1 ", then the current potential of second tie point 2 is high level " 1 ", so as to which the second pull-down transistor PD2 is turned on, the second memory node B applies the first current potential Vss, and described the One current potential is low level " 0 ", and therefore, the second memory node B current potentials are the electricity of low level " 0 ", then first tie point 1 Low level " 0 " is in position, then the first pull-down transistor cut-off, and first pulls up transistor PU1 conductings, so that described first deposits It stores up node A and applies the second current potential Vdd, the second current potential Vdd is high level " 1 ", so that the first memory node A Store high level " 1 ".

If the signal to be stored is low level " 0 ", the storage current potential applied on the first bit line BL1 is height Level " 0 "；The storage current potential applied on the second bit line BL2 is high level " 1 ".

Since the current potential on the first wordline BL1 is low level " 0 ", the current potential of the first memory node A is low electricity Flat " 0 "；Since the current potential on the second wordline BL2 is high level " 1 ", then the current potential on the second memory node B is height Level " 1 ".

The current potential of the first memory node A is low level " 0 ", then the current potential of second tie point 2 is low level " 0 ", so as to the second pull-down transistor PD2 end, described second pull up transistor PU2 conducting so that described second deposits It stores up node B and applies the second current potential Vdd, second current potential is high level " 1 ", therefore, the second memory node current potential For high level " 1 "；The current potential of the second memory node B is high level " 1 ", then the current potential of first tie point 1 is high electricity Flat " 1 ", then the first pull-down transistor PD1 conductings, first pulls up transistor PU1 cut-offs, so that the first storage section Point A applies the first current potential Vss, and the first current potential Vss is high level " 0 ", so that the first memory node A is stored Low level " 0 ".

It can be obtained by analyzing above, the method for work of the memory can write storage signal in the memory.

In the read operation, the operating potential is preset potential.In the first bit line BL1 and the second The step of applying operating potential on line BL2 includes：Apply default electricity on the first bit line BL1 and the second bit line BL2 Position, the preset potential are more than the first current potential Vss.

In the present embodiment, the preset potential is high level " 1 ".

In the present embodiment, if the current potential of the memory node A is high level " 1 ", the current potential of second tie point 2 For high level " 1 ", then described second pull up transistor PU2 cut-offs, the second pull-down transistor PD2 conductings, then described the Apply the first current potential Vss on two bit line BL2.Since the first current potential Vss is low level " 1 ", then second bit line The preset potential of BL2 is pulled low as low level " 0 ", and it is non-to form reading potential.Meanwhile the second memory node B is low level " 0 ", the current potential of first tie point 1 is low level " 0 ", then the first pull-down transistor PD1 cut-offs, first pull-up Transistor PU1 is turned on, so that the first bit line BL1 applies the second current potential Vdd, the second current potential Vdd is high electricity Flat " 1 ", therefore, the preset potential of the first bit line WL1 is high level " 1 ", forms reading potential.The reading signal includes The reading potential is non-with the reading potential.

It needs to illustrate bright, by analyzing above, applies on the first bit line BL1 and the second bit line BL2 described pre- If during current potential, when the current potential of the first memory node A is high level " 1 ", the current potential of the second memory node B For low level " 0 ", the current potential of second tie point 2 is high level " 1 ", due to the described 3rd shunting grid and the described second company Contact 2 connects, therefore, the 3rd shunting transistor FD2 conductings, and since the 4th shunting transistor FG2 is turned on, because This, second dividing cell 22 turns on so that the second bit line BL2 applied by second dividing cell 22 it is described First current potential Vss, therefore, the first current potential Vss can also drag down second bit line by second dividing cell 22 Preset potential on BL2 so as to which the preset potential is avoided to raise the current potential of the second memory node B, avoids the occurrence of The reversion of current potential, and then interference of the static noise to the memory can be reduced, the static storage for increasing the memory is held Amount.

In addition, during applying the preset potential on the first bit line BL1 and the second bit line BL2, when described The current potential of second memory node B is high level " 1 ", when the current potential of the first memory node A is low level " 0 ", described first The current potential of tie point is high level " 1 ", since the described first shunting grid is connected with first tie point 1, described the One shunting transistor FD1 is turned on, and since the second shunting transistor FG1 is turned on, first dividing cell 12 is led It is logical, so that the first bit line BL1 applies the first current potential Vss by first dividing cell 12, therefore, described the One current potential Vss can also drag down the preset potential on the first bit line BL1 by first dividing cell 12, so as to It prevents the preset potential from raising the current potential of the first memory node A, avoids the occurrence of the reversion of current potential, and then can reduce quiet Interference of the state noise to the memory increases the static storage capacity of the memory.

In the present embodiment, the first channel width of the first pull-down transistor PD1 is more than first transmission transistor The second channel width of PG1, it is brilliant so as to which the saturation current of the first pull-down transistor PD1 is made to be more than the described first transmission The race of body pipe PG1 and electric current.Meanwhile the triple channel width of the second pull-down transistor PD1 is more than the described second transmission crystalline substance The 4th channel width of body pipe PG1 passes so as to which the saturation current of the second pull-down transistor PD1 is made to be more than described second The saturation current of defeated transistor PG1.So as to increase the beta rates of the memory, and then the memory can be increased Static noise capacity.

In other embodiments, the first channel width of first pull-down transistor can also be equal to the described first transmission Second channel width of transistor；It is brilliant that the triple channel width of second pull-down transistor can also be equal to the described second transmission 4th channel width of body pipe.

In the method for work of memory provided in an embodiment of the present invention, it is single that the memory circuitry includes at least the first shunting Member and the second dividing cell.First dividing cell can reduce it is described first shunting input terminal on static noise to described The interference of memory circuitry；Second dividing cell can reduce it is described second shunting input terminal on static noise to described The interference of memory circuitry.Therefore, static noise is smaller to the interference of memory circuitry, the static noise of the memory circuitry Capacity is larger.

The method of work of the memory of the present invention additionally provides another embodiment, method of work such as Figure 12 of the memory It is shown.

2 are please referred to Fig.1, the present embodiment and the something in common of a upper embodiment do not repeat herein, and difference includes：

In the present embodiment, the memory further includes：Connect the 3rd bit line BL3 of the first shunting input terminal；Connection 4th bit line BL4 of the second shunting input terminal.

In the present embodiment, the first shunting input end is not connected with the first bit line BL1, and second shunting is defeated Enter end not to be connected with the second bit line BL2.

In the present embodiment, the write operation of the memory is realized by the first bit line BL1 and the second bit line BL2, The read operation of the memory is realized by the 3rd bit line BL2 and the 4th bit line BL4.

In write operation, wrapped in the step of application operating potential on the first bit line BL1 and the second bit line BL2 It includes：Apply storage current potential on the first bit line BL1 and the second bit line BL2, storage is formed in the storage unit Signal.

Specifically, in said write operation, the operating potential is storage current potential.

The current potential of the first memory node A is high level " 1 ", then the current potential of second tie point 2 is high level " 1 ", so as to which the second pull-down transistor FD2 is turned on, the second memory node B applies the first current potential Vss, and described the One current potential Vss is low level " 0 ", and therefore, the second memory node B current potentials are low level " 0 ", then first tie point 1 Current potential for low level " 0 ", then the first pull-down transistor PD1 cut-offs, first pulls up transistor PU1 conductings, so that institute It states the first memory node A and applies the second current potential Vdd, the second current potential Vdd is high level " 1 ", so that described first Memory node A storage high level " 1 ".

The current potential of the first memory node A is low level " 0 ", then the current potential of second tie point 2 is low level " 0 ", so as to the second pull-down transistor FD2 end, described second pull up transistor PU2 conducting, the second memory node B Apply the second current potential Vdd, second current potential is high level " 1 ", and therefore, the second memory node B current potentials are high electricity Flat " 1 ", then the current potential of first tie point 1 is high level " 1 ", then the first pull-down transistor PD1 conductings, the first pull-up Transistor PU1 ends, so that the first memory node A applies the first current potential Vss, the first current potential Vss is low Level " 0 ", so that the first memory node A storage low levels " 0 ".

In read operation, the method for work further includes：Apply on the 3rd bit line BL3 and the 4th bit line BL4 Preset potential, the preset potential are acted on the storage unit, are formed and are read signal；In the 3rd bit line BL3 and the 4th The reading signal is obtained on bit line BL4.

Specifically, in read operation, apply word-line signal on the wordline WL, the word-line signal is high level " 1 ", then the first transmission transistor PG1 and the second shunting transistor FG1 conductings, and second transmission transistor PG2 and the 4th shunting transistor FG2 conductings.

Apply preset potential on the 3rd bit line BL1a and the 4th bit line BL2a.

In the present embodiment, the preset potential is high level " 1 ".

If the current potential of the first memory node A is high level " 1 ", the current potential of the second memory node B is low electricity Flat " 0 ", then the current potential of second tie point 2 is high level " 1 ", so that the second pull-down transistor PD2 and described the Three shunting transistor FD2 are turned on, then second dividing cell 22 turns on, so that the 4th bit line BL2a applies described the One current potential Vss, since the first current potential Vss is low level " 0 ", the first current potential Vss can drag down the 4th bit line Preset potential on BL2a, formation reading potential is non-, so that the 4th bit line BL2a output low levels " 0 ", so that institute It is non-identical with the current potential of the second memory node B to state reading potential.Simultaneously as the current potential of first tie point 1 is low Level " 0 ", the first pull-down transistor PD1 and the first shunting transistor FD1 end, on the 3rd bit line BL1a Preset potential will not be dragged down by the first current potential Vss, so that the 3rd bit line BL1a exports reading potential, the reading Current potential is high level " 1 ", and the reading potential is identical with the current potential of the first memory node A.

If the current potential of the first memory node A is low level " 0 ", the current potential of the second memory node B is high electricity Flat " 1 ", then the current potential of first tie point 1 is high level " 1 ", so that the first pull-down transistor PD1 and described the One shunting transistor FD1 is turned on, then first dividing cell 12 turns on, described in applying on the 3rd bit line BL1a First current potential Vss, since the first current potential Vss is low level " 0 ", the first current potential Vss can drag down the 3rd bit line Preset potential on BL1a forms reading potential, even if the 3rd bit line BL1a output low levels " 0 ", so as to the reading Current potential is identical with the current potential of the first memory node A.Simultaneously as the current potential of second tie point 2 is low level " 0 ", The second pull-down transistor PD2 and the 3rd dividing cell FD2 ends, and the preset potential on the 4th bit line BL2a is not It can be dragged down by the first current potential Vss, so that the 4th bit line BL2a output high level " 1 ", forms reading potential.Cause This, the reading potential is identical with the current potential of the second memory node B.

It can be obtained by analyzing above, in the present embodiment, the 3rd bit line BL1a and the 4th bit line BL2a can be passed through Read the storage data in the storage unit 30.

It should be noted that in the read operation, the preset potential is applied to the 3rd bit line BL1a and institute It states on the 4th bit line BL2a, when the first memory node A is low level " 0 ", first dividing cell 12 turns on, described Preset potential is connected by the first dividing cell 12 with the first current potential Vss, and therefore, the preset potential will not be applied to institute It states on the first memory node A, so as to which the current potential of the first memory node A will not be raised, is also just not easy to cause the first storage The reversion of node A current potentials, and then it is not easy read error occur, therefore, the method for work can reduce static noise to institute The interference of memory is stated, and then the static noise capacity of the memory can be increased；

When the second memory node B is low level " 0 ", second dividing cell 22 turns on, the preset potential It is connected by the second dividing cell 22 with the second current potential Vss, therefore, the preset potential will not be applied to described second and deposit It stores up on node B, so as to which the current potential of the second memory node B will not be raised, is also just not easy to cause the second memory node B current potentials Reversion, and then be not easy read error occur, therefore, the method for work can reduce static noise to the memory Interference, and then the static noise capacity of the memory can be increased.

To sum up, in the method for work for the memory that the embodiment of the present invention provides, the memory circuitry includes at least the One dividing cell and the second dividing cell.The static state that first dividing cell can be reduced on the first shunting input terminal is made an uproar Interference of the sound to the memory circuitry；The static state that second dividing cell can be reduced on the second shunting input terminal is made an uproar Interference of the sound to the memory circuitry.It can be seen that static noise is smaller to the interference of the memory circuitry, the storage The static noise capacity of device circuit is larger.

Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute Subject to the scope of restriction.

Claims

1. a kind of memory construction, which is characterized in that including：

Substrate, the substrate include：First drop-down area, the second drop-down area, the first transmission range and the second transmission range；

First pull-down transistor in area is pulled down positioned at substrate first, first pull-down transistor has the first channel width, institute Stating the first pull-down transistor includes：The first pulldown gate structure on the substrate, respectively positioned at the described first drop-down grid The first drop-down source region and the first drop-down drain region in the substrate of pole structure both sides, the first drop-down source region is for the first electricity of application Position；

Second pull-down transistor in area is pulled down positioned at substrate second, second pull-down transistor has triple channel width, institute Stating the second pull-down transistor includes：The second pulldown gate structure on the substrate, respectively positioned at the described second drop-down grid The second drop-down source region and the second drop-down drain region in the substrate of pole structure both sides, under the second pulldown gate structure and described first Bleedout area is electrically connected, and the second drop-down drain region is electrically connected with the first pulldown gate structure, and the second drop-down source region is used In application first current potential；

The first transmission transistor on the first transmission range substrate, first transmission transistor have the second channel width, First transmission transistor includes：The first transmission gate structure on the substrate, positioned at the described first transmission grid The first transmission source region and the first transmission drain region in the substrate of structure both sides, the first transmission source region and the described first drop-down drain region Electrical connection；

The second transmission transistor on the second transmission range substrate, second transmission transistor have the 4th channel width, Second transmission transistor includes：The second transmission gate structure on the substrate；Positioned at the described second transmission grid The second transmission source region and the second transmission drain region in the substrate of structure both sides, the second transmission source region and the described second drop-down drain region Electrical connection；

4th channel width is less than the triple channel width；

Or second channel width is less than first channel width；

Or second channel width is less than first channel width, and the 4th channel width is less than the 3rd ditch Road width；

Connect the wordline of the first transmission gate structure and the second transmission gate structure；

Connect first bit line in the first transmission drain region；

Connect second bit line in the second transmission drain region.

2. memory construction as described in claim 1, which is characterized in that there is the first transmission on the first transmission range substrate Fin, the first transmission gate structure is across the described first transmission fin, the first transmission source region and the first transmission drain region It is located at respectively in the first transmission fin of the described first transmission gate structure both sides；

The second transmission range substrate has the second transmission fin, and the second transmission gate structure is across the described second transmission fin Portion, the second transmission source region and the second transmission drain region are located at the second transmission fin of the described second transmission gate structure both sides respectively In portion；

First drop-down area's substrate includes the first drop-down fin, and the first pulldown gate structure is across the described first drop-down fin Portion, and pull down source region and first time bleedout positioned at the described first drop-down fin partial sidewall and top surface, described first Area is respectively in the first drop-down fin of the first pulldown gate structure both sides；

Second drop-down area's substrate includes the second drop-down fin, and the second pulldown gate structure is across the described second drop-down fin Portion, and pull down source region and second time bleedout positioned at the described second drop-down fin partial sidewall and top surface, described second Area is respectively in the second drop-down fin of the second pulldown gate structure both sides.

3. memory construction as claimed in claim 2, which is characterized in that the substrate further includes the first bonding pad and second and connects Meet area；

First bonding pad, the first drop-down area and first transmission range contact with each other, second bonding pad, the second drop-down Area and second transmission range contact；

First bonding pad substrate includes the first connection fin, and the first connection fin connects with the described first drop-down fin It connects；The first transmission fin is connected with the described first drop-down fin；

The memory construction further includes：Across the first connection gate structure of the described first connection fin, first connection Gate structure is connected with the described first transmission gate structure；It is connected positioned at the described first connection gate structure both sides first in fin The first connection source region be connected drain region with first, described first, which connects drain region, pulls down drain region with described first and is connected, described first Connection source region is not contacted with first bit line；

Second bonding pad substrate includes the second connection fin, and the second connection fin connects with the described second drop-down fin It connects；The second transmission fin is connected with the described second drop-down fin；

The memory construction further includes：Across the second connection gate structure of the described second connection fin, second connection Gate structure is connected with the described second transmission gate structure；It is connected positioned at the described second connection gate structure both sides second in fin The second connection source region be connected drain region with second, described second, which connects drain region, pulls down drain region with described second and is connected, described second Connection source region is not contacted with second bit line.

4. memory construction as claimed in claim 2, which is characterized in that the first drop-down fin, the second drop-down fin, the One transmission fin and second transmits being of same size for fin, the first drop-down fin, the second drop-down fin, the first transmission fin It is identical with the height of the second transmission fin；The first drop-down fin number transmits the number of fin more than described first, described The number of second drop-down fin is more than the number of the described second transmission fin.

5. memory construction as described in claim 1, which is characterized in that the substrate further includes：First pull-up area and second Pull up area；

The memory construction further includes：Pull up area positioned at substrate first first pulls up transistor；Crystal pulling on described first Pipe includes：The first pull-up gate structure on the substrate, the first pull-up gate structure and the described first drop-down grid Pole structure electrical connection；The the first pull-up drain region and the first pull-up source being located at respectively in the described first pull-up gate structure both sides substrate Area, the first pull-up source region are electrically connected with the described first drop-down drain region, and the first pull-up drain region is used to apply the second current potential, Second current potential is more than the first current potential；

Positioned at second pulling up transistor for the substrate second pull-up area, described second pull up transistor including：On substrate Second pull-up gate structure, it is described second pull-up gate structure is electrically connected with the second pulldown gate structure；It is located at respectively The second pull-up source region and the second pull-up drain region in the second pull-up gate structure both sides substrate, the second pull-up drain region with The second drop-down drain region electrical connection, the second pull-up source region are used to apply second current potential.

6. memory construction as described in claim 1, which is characterized in that the substrate includes at least：First shunting zone or Two shunting zones；

There is the first flow dividing structure, first flow dividing structure includes first connecting portion and second on the substrate of first shunting zone Connecting portion, the first connecting portion are used to apply first current potential；The second connecting portion is electrically connected with first bit line, Or the memory further includes the 3rd bit line, the second connecting portion connects the 3rd bit line；

There is the second flow dividing structure, second flow dividing structure includes the 3rd connecting portion and the 4th on the substrate of second shunting zone Connecting portion, the 3rd connecting portion are used to apply first current potential；4th connecting portion is electrically connected with second bit line, Or the memory further includes the 4th bit line, the 4th connecting portion connects the 4th bit line.

7. memory construction as claimed in claim 6, which is characterized in that first flow dividing structure includes：

First shunting transistor, first shunting transistor include the be located on the substrate of first shunting zone first shunting grid Pole structure, the first shunting gate structure are electrically connected with the first pulldown gate structure；It is located at the described first shunting respectively The first shunting source region and the first shunting drain region, the first connecting portion in the substrate of the first shunting zone of gate structure both sides include institute State the first shunting source region；

Second shunting transistor, second shunting transistor include：The second shunting on the substrate of second shunting zone Gate structure, the second shunting gate structure are electrically connected with the described second transmission gate structure；Positioned at the described second shunting grid The second shunting source region and the second shunting drain region in the substrate of the second shunting zone of pole structure both sides, the second connecting portion includes described Second shunting drain region；

Connect the second shunting source region and the first source and drain connecting line in the described first shunting drain region；

Second flow dividing structure includes：3rd shunting transistor, the 3rd shunting transistor include：Positioned at described 3rd point The 3rd shunting gate structure on area's substrate is flowed, the 3rd shunting gate structure is electrically connected with the second pulldown gate structure It connects；It is located at the 3rd shunting source region in the described 3rd shunting the second shunting zone of gate structure both sides substrate and the 3rd shunting leakage respectively Area, the 3rd connecting portion include the described 3rd shunting source region；

4th shunting transistor, the 4th shunting transistor include：The 4th shunting on the substrate of second shunting zone Gate structure, the 4th shunting gate structure are electrically connected with the second pulldown gate structure；It is located at described 4th point respectively Flowing the 4th shunting source region in the substrate of the second shunting zone of gate structure both sides and the 4th shunting drain region, the 4th connecting portion includes The 4th shunting drain region；

Connect the second source and drain connecting line of the 4th shunting source region and the 3rd point of drain source area.

8. a kind of method for forming the memory construction as described in claim 1 to claim 7 any one claim, It is characterized in that, including：

Substrate is provided, the substrate includes：First drop-down area, the second drop-down area, the first transmission range and the second transmission range；

The first pull-down transistor is formed in the substrate first drop-down area, first pull-down transistor has the first ditch road width The step of degree, formation first pull-down transistor, includes：The first pulldown gate structure is formed over the substrate；Described The first drop-down source region and the first drop-down drain region, the first drop-down source region are respectively formed in the substrate of one drop-down gate structure both sides For applying the first current potential；

The first transmission transistor is formed on the first transmission range substrate, first transmission transistor has the second ditch road width The step of degree, formation first transmission transistor, includes：The first transmission gate structure is formed over the substrate, described the The first transmission source region and the first transmission drain region, the first transmission source region are respectively formed in the substrate of one transmission gate structure both sides It is electrically connected with the described first drop-down drain region；

The second pull-down transistor is formed in the substrate second drop-down area, second pull-down transistor is wide with triple channel The step of degree, formation second pull-down transistor, includes：The second pulldown gate structure is formed over the substrate, described The second drop-down source region and the second drop-down drain region, second pulldown gate are respectively formed in the substrate of two pulldown gate structure both sides Structure is electrically connected with the described first drop-down drain region, and the second drop-down drain region is electrically connected with the first pulldown gate structure, institute The second drop-down source region is stated for applying first current potential；

The second transmission transistor is formed on the second transmission range substrate, second transmission transistor has the 4th ditch road width Degree, forming second transmission transistor includes：The second transmission gate structure is formed over the substrate, in the described second transmission The second transmission source region and the second transmission drain region, the second transmission source region and described the are respectively formed in the substrate of gate structure both sides Two drop-down drain region electrical connections；

4th channel width is less than the triple channel width；

Or second channel width is less than first channel width；

Formed after first transmission transistor and the second transmission transistor, formed connection it is described first transmission gate structure and The wordline of the second transmission gate structure；

Form first bit line in connection the first transmission drain region；

Form second bit line in connection the second transmission drain region.

9. a kind of memory construction, which is characterized in that including：

Substrate, the substrate include memory block, the first transmission range, the second transmission range and shunting zone；

Storage organization positioned at the substrate storage region, the storage organization include first connecting portion, second connecting portion and ground connection Portion, the grounding parts are for the first current potential of application；

Positioned at the first transmission transistor of first transmission range of substrate, first transmission transistor includes：Positioned at described The first transmission gate structure on one transmission range substrate transmits first in the substrate of gate structure both sides positioned at described first respectively Drain region and the first transmission source region are transmitted, the first transmission source region is electrically connected with the first connecting portion；

Positioned at the second transmission transistor of second transmission range of substrate, second transmission transistor is located at the described second transmission The second transmission gate structure on area's substrate, respectively the second transmission leakage in the described second transmission gate structure both sides substrate Area and the second transmission source region, the second transmission source region are electrically connected with the second connecting portion；

The shunting zone includes at least the first shunting zone or the second shunting zone, and there is the first shunting to tie for first shunting zone of substrate Structure, first flow dividing structure include：First shunting input unit and the first shunting output section, the first shunting input unit are used for Apply preset potential, the first shunting output section is electrically connected with the grounding parts；Second shunting zone of substrate has second Flow dividing structure, second flow dividing structure include：Second shunting input unit and the second shunting output section, the second shunting input For applying the preset potential, the second shunting output section is electrically connected with the grounding parts in portion.

10. memory construction as claimed in claim 9, which is characterized in that the first shunting input unit and described first Line is electrically connected；The second shunting input unit is electrically connected with second bit line.

11. memory construction as claimed in claim 9, which is characterized in that further include：Connect the first shunting input unit 3rd bit line；Connect the 4th bit line of the 4th input unit.

12. memory construction as claimed in claim 9, which is characterized in that the memory block includes：First drop-down area and second Area is pulled down, the storage organization includes：The first pull-down transistor positioned at the substrate first drop-down area, first time crystal pulling Body pipe includes：The first pulldown gate structure on described first drop-down area's substrate；It is located at first pulldown gate respectively The first drop-down source region and the first drop-down drain region, the first connecting portion in the substrate of structure both sides include first time bleedout Area, the grounding parts include：The first drop-down source region；

The second pull-down transistor positioned at the substrate second drop-down area, second pull-down transistor include：Positioned at described The second pulldown gate structure on two drop-down area's substrates, the second pulldown gate structure are electrically connected with the described first drop-down drain region It connects；It is located at the second drop-down source region in the substrate of the second pulldown gate structure both sides and the second drop-down drain region respectively, described the Two drop-down drain regions are electrically connected with the first pulldown gate structure, and the second connecting portion includes the described second drop-down drain region, The grounding parts include the described second drop-down source region.

13. memory construction as claimed in claim 12, which is characterized in that first pull-down transistor has the first raceway groove Width, first transmission transistor have the second channel width, and second pull-down transistor has triple channel width, institute The second transmission transistor is stated with the 4th channel width；4th channel width is less than the triple channel width；Or institute The second channel width is stated less than first channel width；Or second channel width is less than first channel width, And the 4th channel width is less than the triple channel width.

14. memory construction as claimed in claim 12, which is characterized in that the first transmission range substrate includes the first transmission Fin, the first transmission gate structure is across the described first transmission fin, and the first transmission gate structure is positioned at described First transmission fin partial sidewall and top surface, the first transmission source region and the first transmission drain region are located at described first respectively In the first transmission fin for transmitting gate structure both sides；

The second transmission range substrate includes the second transmission fin, and the second transmission gate structure is across the described second transmission fin Portion, and the second transmission gate structure is located at the described second transmission fin partial sidewall and top surface, second transmission Source region and the second transmission drain region are located at respectively in the second transmission fin of the described second transmission gate structure both sides；

First drop-down area's substrate includes the first drop-down fin, and the first pulldown gate structure is across the described first drop-down fin Portion, and the first pulldown gate structure is located at the described first drop-down fin partial sidewall and top surface, first drop-down Source region and the first drop-down drain region are pulled down positioned at the first of the first pulldown gate structure both sides in fin respectively；

Second drop-down area's substrate includes the second drop-down fin, and the second pulldown gate structure is across the described second drop-down fin Portion, and the second pulldown gate structure is located at the described second drop-down fin partial sidewall and top surface, second drop-down Source region and the second drop-down drain region are pulled down positioned at the second of the second pulldown gate structure both sides in fin respectively；

The first drop-down fin, the second drop-down fin, the first transmission fin and the second transmission fin are of same size, and described the The height that one drop-down fin, the second drop-down fin, the first transmission fin and second transmit fin is identical；The first drop-down fin For number more than the number of the described first transmission fin, described second pulls down of the number more than the described second transmission fin of fin Number.

15. memory construction as claimed in claim 12, which is characterized in that the memory block further includes the first pull-up Qu He Two pull-up areas；The memory construction further includes：The first pull-up positioned at the substrate first pull-up area loads, on described first Load is drawn to include：First load input unit, for inputting the second current potential, second current potential is more than the first load input unit First current potential；First load output section, the first load output section are electrically connected with the first pull-down transistor drain region；

The second pull-up load positioned at the substrate second pull-up area, the second pull-up load include：Second load input unit, The second load input unit is used to input second current potential；Second load output section, the second load output section and institute State the electrical connection of the second pull-down transistor drain region.

16. memory construction as claimed in claim 15, which is characterized in that the first pull-up load includes crystal pulling on first Body pipe, described first pull up transistor including：The first pull-up gate structure on the substrate, the first pull-up grid Structure is electrically connected with the first pulldown gate structure；The first pull-up in the described first pull-up gate structure both sides substrate Drain region and the first pull-up source region, the first load output section include the described first pull-up source region, the first load input unit Including the described first pull-up drain region；

Second load includes second and pulls up transistor, described second pull up transistor including：On the substrate Two pull-up gate structures, the second pull-up gate structure are electrically connected with the second pulldown gate structure；It is located at respectively described The second pull-up source region and the second pull-up drain region in second pull-up gate structure both sides substrate, the second load input unit include The second pull-up drain region, the second load output section include the described second pull-up source region；

Alternatively, the first pull-up load includes the first pull-up resistor, first pull-up resistor includes：In the substrate First pull-up doped region and second pull-up doped region, it is described first load input unit include described first pull-up doped region, institute Stating the first load output section includes the described second pull-up doped region；

The second pull-up load includes the second pull-up resistor, and second pull-up resistor includes：Positioned at the described second pull-up area The 3rd pull-up doped region and the 4th pull-up doped region in substrate, the second load input unit include the described 3rd pull-up and adulterate Area, the second load output section include the described 4th pull-up doped region.

17. memory construction as claimed in claim 9, which is characterized in that first flow dividing structure includes：Positioned at substrate First shunting transistor of one shunting zone, first shunting transistor include：On the substrate of first shunting zone One shunting gate structure, the first shunting gate structure are electrically connected with the first pulldown gate structure；It is located at respectively described The first shunting source region and the first shunting drain region in first shunting the first shunting zone of gate structure both sides substrate, first shunting Output section includes the described first shunting source region；

First flow dividing structure further includes the second shunting transistor positioned at the first shunting zone, the second shunting transistor bag It includes：The second shunting gate structure on the substrate of first shunting zone, the second shunting gate structure and described second Transmit gate structure electrical connection；The second shunting being located at respectively in described second shunting the first shunting zone of gate structure both sides substrate Source region and the second shunting drain region, the second shunting source region are electrically connected with the described first shunting drain region, the first shunting input Portion includes the described second shunting drain region；

Second flow dividing structure includes：Positioned at the 3rd shunting transistor of second shunting zone of substrate and positioned at the substrate 4th shunting transistor of the second shunting zone；

3rd shunting transistor includes：The 3rd shunting gate structure on the second shunting zone substrate, described 3rd point Stream gate structure is electrically connected with the second pulldown gate structure；It is located at the described 3rd shunting gate structure both sides second respectively to divide The 3rd shunting source region in area's substrate and the 3rd shunting drain region are flowed, the second shunting output section includes the described 3rd shunting source Area；

4th shunting transistor includes：The 4th shunting gate structure on the substrate of second shunting zone, described the Four shunting gate structures are electrically connected with the described second transmission gate structure；It is located at the described 4th shunting gate structure both sides lining respectively The 4th shunting source region and the 4th shunting drain region in bottom, the second shunting input unit includes the described 4th shunting drain region, described 4th shunting source region is electrically connected with the described 3rd shunting drain region.

18. memory construction as claimed in claim 17, which is characterized in that further include：Connect it is described first shunting source region with First source line of the first drop-down source region；Connect the second source line of the 3rd shunting source region and the described second drop-down source region.

19. a kind of method for forming the memory construction as described in claim 9 to claim 18 any one claim, It is characterised in that it includes：

Substrate is provided, the substrate includes memory block, the first transmission range, the second transmission range and shunting zone, and the shunting zone is at least Including the first shunting zone or the second shunting zone；

Storage organization is formed in the substrate storage region, the storage organization includes first connecting portion and second connecting portion；

It is wrapped the step of the first transmission range of the substrate forms the first transmission transistor, forms first transmission transistor It includes：The first transmission gate structure is formed over the substrate, respectively the shape in the substrate of the described first transmission gate structure both sides Into the first transmission source region and the first transmission drain region, the first transmission source region is electrically connected with the first connecting portion；

The step of forming the second transmission transistor in second transmission range of substrate, form second transmission transistor includes： The second transmission gate structure is formed over the substrate, forms the in the substrate of the described second transmission gate structure both sides respectively Two transmission drain regions and the second transmission source region, the second transmission source region are electrically connected with the second connecting portion；

The first flow dividing structure is formed in first shunting zone of substrate；

Or form the second flow dividing structure in the first shunting zone of substrate；

Or the first flow dividing structure is formed in first shunting zone of substrate, and the second shunting knot is formed in the first shunting zone of substrate Structure；First flow dividing structure includes：First shunting input unit and the first shunting output section, the first shunting input unit are used for Preset potential is inputted, first output section is for the first current potential of application；Second flow dividing structure includes：Second shunting input Portion and the second shunting output section, for the second shunting input unit for inputting the preset potential, described second shunts output section For applying first current potential；

Form the wordline of the connection first transmission gate structure and the second transmission gate structure；

Form first bit line in connection the first transmission drain region；

Form second bit line in connection the second transmission drain region.

20. a kind of memory circuitry, which is characterized in that including：

Storage unit, the storage unit include：First connecting pin, second connection end and ground terminal, the ground terminal are used to apply Add the first current potential；

First transmission transistor, first transmission transistor include：First transmission grid, the first transmission source electrode and the first transmission Drain electrode, the first transmission source electrode are connected with first connecting pin；

Connect the first bit line of the first transmission drain electrode；

Second transmission transistor, second transmission transistor include：Second transmission grid, the second transmission source electrode and the second transmission Drain electrode, the second transmission source electrode are connected with the second connection end；

Connect the wordline of the first transmission grid and the second transmission grid；

Connect the second bit line of the second transmission drain electrode；

Dividing cell, the dividing cell include at least the first dividing cell or the second dividing cell；First dividing cell Including：First shunting input terminal and the first shunting output terminal, the first shunting output terminal are connected with the ground terminal, and described the One shunting input terminal is used to input preset potential；Second dividing cell includes：Second shunting input terminal and the second shunting are defeated Outlet, the second shunting output terminal are connected with the ground terminal, and the second shunting input terminal is used to input the default electricity Position.

21. memory circuitry as claimed in claim 20, which is characterized in that the first shunting input terminal and described first Line connects, and the second shunting input terminal is connected with second bit line.

22. memory circuitry as claimed in claim 20, which is characterized in that first dividing cell includes：First shunting Transistor, first shunting transistor include：First shunting grid, the first shunting grid and first pulldown gate Connection；First shunting source electrode and the first shunting drain electrode, the first shunting source electrode are connected with the described first shunting output terminal；

First dividing cell further includes the second shunting transistor, and second shunting transistor includes：Second shunting grid, The second shunting grid is connected with the described first transmission grid；Second shunting source electrode, the second shunting source electrode and described the One shunting drain electrode connection；Second shunting drain electrode, the second shunting drain electrode are connected with the described first shunting input terminal；

Second dividing cell includes：3rd shunting transistor, the 3rd shunting transistor include：3rd shunting grid, The 3rd shunting grid is connected with second pulldown gate；3rd shunting source electrode and the 3rd shunting drain electrode, described 3rd point Stream source electrode is connected with the described second shunting output terminal；

4th shunting transistor, the 4th shunting transistor include：4th shunting grid, it is described 4th shunting grid with it is described Second transmission grid connection；4th shunting source electrode, the 4th shunting source electrode and the described 3rd shunting drain electrode connection；4th shunting Drain electrode, the 4th shunting drain electrode are connected with the described second shunting input terminal.

23. memory circuitry as claimed in claim 20, which is characterized in that further include：3rd bit line, the 3rd bit line connect Connect the first shunting input terminal；4th bit line, the 4th bit line connection the second shunting input terminal.

24. memory circuitry as claimed in claim 20, which is characterized in that first dividing cell includes：First shunting Transistor, first shunting transistor include：First shunting grid, the first shunting grid and first pulldown gate Connection；First shunting source electrode, the first shunting source electrode connection the first shunting output terminal；First shunting drain electrode, described the One shunting drain electrode connection the first shunting input terminal；

Second dividing cell includes：3rd shunting transistor, the 3rd shunting transistor include：3rd shunting grid, The 3rd shunting grid is electrically connected with second pulldown gate；3rd shunting source electrode, it is described 3rd shunting source electrode with it is described Second shunting output terminal connection；3rd shunting drain electrode, the 3rd shunting drain electrode connection the second shunting input terminal.

25. memory circuitry as claimed in claim 20, which is characterized in that the storage unit includes：First time crystal pulling Pipe, first pull-down transistor include：First pulldown gate；First drop-down drain electrode, the first drop-down drain electrode and described the One transmission source electrode connection；First drop-down source electrode, the first drop-down source electrode are connected with first current potential；

Second pull-down transistor, second pull-down transistor include：Second pulldown gate, second pulldown gate with it is described First drop-down drain electrode connection；Second drop-down source electrode, the second drop-down drain electrode are connected with the described first shunting output terminal；Under second Bleedout pole, the second drop-down drain electrode are connected with first pulldown gate.

26. memory circuitry as claimed in claim 25, which is characterized in that the storage unit further includes：

First pull-up load, the first pull-up load include：First load input terminal, first load input terminal is for defeated Enter the second current potential, second current potential is more than the first current potential；First load outputs, described in first load outputs connection First pull-down transistor drains；

Second pull-up load, the second pull-up load include：Second load input terminal, second load input terminal is for defeated Enter second current potential；Second load outputs, second load outputs connect the second pull-down transistor drain electrode.

27. memory circuitry as claimed in claim 26, which is characterized in that the first pull-up load includes crystal pulling on first Body pipe, described first pull up transistor including：First pull-up grid, the first pull-up grid connect with first pulldown gate It connects；First pull-up drain electrode, the first pull-up drain electrode connection first load input terminal, the first pull-up source electrode, described first It pulls up source electrode and connects first load outputs；

The second pull-up load includes second and pulls up transistor, described second pull up transistor including：Second pull-up grid, institute It states pull-up grid and connects second pulldown gate；Second pull-up source electrode, second pull-up drain electrode connection the second load input End；Second pull-up source electrode, the second pull-up drain electrode connect second load outputs；

Alternatively, the first pull-up load includes first resistor, the first resistor includes：First resistor input terminal and the first electricity Hinder output terminal, the first resistor input terminal connects first load input terminal, described in the first resistor output terminal connection First load outputs；

The second pull-up load is second resistance, and the second resistance includes：Second resistance input terminal and second resistance output End, the second resistance input terminal connect second load input terminal, and the second resistance output terminal connection described second is negative Carry output terminal.

28. a kind of method of work of memory circuitry, which is characterized in that including：

Memory circuitry as claimed in claim 20 is provided；

Apply the first current potential on the ground terminal；

Apply word line potential in the wordline, the word line potential is more than first current potential；

Apply operating potential on first bit line and second bit line.

29. the method for work of memory circuitry as claimed in claim 28, which is characterized in that it is described first shunting input terminal with The first bit line connection；The second shunting input terminal is connected with second bit line；In first bit line and described The step of applying operating potential on two bit lines includes：Apply preset potential on first bit line and the second bit line, it is described pre- If current potential interacts to form reading signal with storage unit；

The method of work further includes：The reading signal is obtained by first wordline and the second bit line；Pass through described One wordline and the second bit line, which obtain the step of reading signal, to be included：Apply on first bit line and second bit line Preset potential, the preset potential are more than first current potential, and the preset potential acts on forming reading with the storage unit Signal；The reading signal is obtained on the 3rd bit line and the 4th bit line.

30. the method for work of memory circuitry as claimed in claim 28, which is characterized in that the memory circuitry includes： First dividing cell and the second dividing cell；

The memory circuitry further includes：Connect the 3rd bit line of the first shunting input terminal；It is defeated to connect second shunting Enter the 4th bit line at end；

Include in the step of application operating potential on first bit line and second bit line：In first bit line and described Apply storage current potential on second bit line, storage signal is formed in the storage unit；

It is formed in the storage unit after storage signal, the method for work further includes：In the 3rd bit line and the 4th Apply preset potential on bit line, the preset potential is more than first current potential, and the preset potential is made with the storage unit Signal is read with being formed；The reading signal is obtained on the 3rd bit line and the 4th bit line.

31. the method for work of memory as claimed in claim 28, which is characterized in that the storage unit further includes：First Pull-up load, the first pull-up load include：First load input terminal and the first load outputs, the first load output End connects the first pull-down transistor drain region；

Second pull-up load, the second pull-up load include：Second load input terminal and the second load outputs, described second Load outputs connect the second pull-down transistor drain region；

Before applying operating potential on first bit line and second bit line, the method for work further includes：To described First load input terminal and second load input terminal apply the second current potential, and second current potential is more than first current potential.