CN104751876B - Dual-port SRAM structures - Google Patents
Dual-port SRAM structures Download PDFInfo
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- CN104751876B CN104751876B CN201310745731.4A CN201310745731A CN104751876B CN 104751876 B CN104751876 B CN 104751876B CN 201310745731 A CN201310745731 A CN 201310745731A CN 104751876 B CN104751876 B CN 104751876B
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Abstract
A kind of dual-port SRAM structures.Physically connected by the active area three of the first pull-down NMOS pipe in the phase inverter that is connected the active area of the transmission transistor of first port first with the active area of the transmission transistor of second port second and two transmission transistors, widen the active area width of the first pull-down NMOS pipe, pull-down current of the first pull-down NMOS pipe of increase in read operation；Similarly, the active area three of the second pull-down NMOS pipe physically connects in the phase inverter that the active area of the transmission transistor of first port the 3rd is connected with the active area of the transmission transistor of second port the 4th and two transmission transistors, widen the active area width of the second pull-down NMOS pipe, increase pull-down current of second pull-down NMOS pipe in read operation, whether the transmission transistor for depending merely on certain Single port reads storage node data, or the transmission transistor for opening two-port simultaneously reads data, reading electric current can be increased, improves noise margin.
Description
Technical field
The present invention relates to technical field of integrated circuits, more particularly to a kind of dual-port SRAM structures.
Background technology
Static RAM（SRAM）It is embedded into almost all of large scale integrated circuit（VLSI）In, and
It is required that serve critical effect in high speed, high integration, low-power consumption, low-voltage, low cost, short-period application.It is embedded
Formula SRAM compares dynamic random access memory（DRAM）Faster access can be provided etc. other memory embedded semiconductors
Speed, so in occupation of dominant position in high-end applications.
Static noise margin（SNM）To assess one of parameter of SRAM memory cell, refer to what memory cell can bear
The amplitude of maximum dc noise signal, if exceeding this value, the data of storage node can occur to invert by mistake, and it is to weigh storage list
One important parameter of first antijamming capability.It can be seen that SNM represents the stability for the data being stored in memory cell.With SNM
The increase of value, the data retention operation of memory cell become more stable, however, on the contrary, by opposite data write storage unit
It is more difficult from.SRAM performances need in SNM and write noise margin（WNR）Between make trade-offs.However, with SRAM processes
Diminution, cellar area is reduced significantly, thus supply voltage（VDD）It is less and less, and then cause noise margin（SNM）Made an uproar with writing
Acoustic capacitance limits（WNR）Constantly become grain.In addition, the diminution of above-mentioned process also results in, read current is less and less, and this can cause height
SRAM under speed operation reads failure.Above mentioned problem all proposes new challenge to SRAM cell design.
In view of the above-mentioned problems, prior art also has the proposition of some schemes.For example, single port is replaced using the SRAM of dual-port
SRAM to increase read current, while improve noise margin.
However, with the further diminution of SRAM processes, the SRAM increase read currents of existing dual-port and improvement
Noise margin limited extent, can not meet demand.
The content of the invention
What the present invention solved is the read current and noise margin for improving existing dual-port SRAM.
To solve the above problems, the present invention provides a kind of dual-port SRAM structures, including：
First phase inverter and the second phase inverter, first phase inverter include the first pull-up PMOS and the first pull-down NMOS
Pipe, second phase inverter include the second pull-up PMOS and the second pull-down NMOS pipe, and first phase inverter has first to deposit
Node is stored up, second phase inverter has the second storage node；
The first transmission transistor and the second transmission transistor being connected with first storage node, with the described second storage
Node connected the 3rd transmission transistor and the 4th transmission transistor, first transmission transistor and the 3rd transmission transistor pair
Answer first port, the second transmission transistor second port corresponding with the 4th transmission transistor；
Wherein, the active area of first transmission transistor, the active area of the first pull-down NMOS pipe and the second transmission crystal
The active area of pipe physically connects；Active area, the active area and the 4th of the second pull-down NMOS pipe of 3rd transmission transistor
The active area of transmission transistor physically connects.
Alternatively, the active area of first pull-down NMOS pipe physically connects with the active area of the first transmission transistor,
The active area of first pull-down NMOS pipe extends to physically to connect with the active area of the second transmission transistor.
Alternatively, the active area of second pull-down NMOS pipe physically connects with the active area of the 3rd transmission transistor,
The active area of second pull-down NMOS pipe extends to physically to connect with the active area of the 4th transmission transistor.
Alternatively, first transmission transistor is NMOS tube.
Alternatively, second transmission transistor is NMOS tube.
Alternatively, the 3rd transmission transistor is NMOS tube.
Alternatively, the 4th transmission transistor is NMOS tube.
Alternatively, in the reading process of first storage node and the second storage node, first transmission transistor
Opened with the 3rd transmission transistor.
Alternatively, in the reading process of first storage node and the second storage node, second transmission transistor
Opened with the 4th transmission transistor.
Alternatively, in the reading process of first storage node, first transmission transistor, the 3rd transmission crystal
Pipe, the second transmission transistor and the 4th transmission transistor are opened simultaneously.
Compared with prior art, technical scheme has advantages below：
By by the active area of the active area of the transmission transistor of first port first and the transmission transistor of second port second,
And two transmission transistor connection phase inverter in the active area of the first pull-down NMOS pipe three is physically connected, change speech
It, has widened the active area width of the first pull-down NMOS pipe, increases the saturation current of the first pull-down NMOS pipe, that is, increases
Pull-down current in read operation；Similarly, the active area of the transmission transistor of first port the 3rd and second port the 4th are transmitted
The active area of the second pull-down NMOS pipe makes three in thing in the active area of transistor and the phase inverter of two transmission transistors connection
Connect in reason, in other words, widened the active area width of the second pull-down NMOS pipe, increase the saturation electricity of the second pull-down NMOS pipe
Stream, that is, increase the pull-down current in read operation, and the transmission transistor for whether depending merely on certain Single port reads storage node number
According to, or the transmission transistor reading data of two-port are opened simultaneously, reading electric current can be increased, is improved anti-in read operation
Noise immune, that is, improve noise margin.
In alternative, if the active area of the active area of first pull-down NMOS pipe and the first transmission transistor is physically
Connect, then the active area for extending first pull-down NMOS pipe extremely physically connects with the active area of the second transmission transistor；If
The active area of first pull-down NMOS pipe physically connects with the active area of the second transmission transistor, then extends under described first
The active area of NMOS tube is drawn extremely physically to connect with the active area of the first transmission transistor.Such scheme provides a kind of increase the
The method of one pull-down NMOS pipe active area width so that three connected transistor active areas of the first storage node share.
In alternative, if the active area of the active area of second pull-down NMOS pipe and the 3rd transmission transistor is physically
Connect, then the active area for extending second pull-down NMOS pipe extremely physically connects with the active area of the 4th transmission transistor；If
The active area of second pull-down NMOS pipe physically connects with the active area of the 4th transmission transistor, then extends under described second
The active area of NMOS tube is drawn extremely physically to connect with the active area of the 3rd transmission transistor.Such scheme provides a kind of increase the
The method of two pull-down NMOS pipe active area widths so that three connected transistor active areas of the second storage node share.
Brief description of the drawings
Fig. 1 is dual-port SRAM structural circuit figures provided in an embodiment of the present invention；
Fig. 2 is the Integrated circuit layouts top view of dual-port SRAM structures provided in an embodiment of the present invention；
Fig. 3 is the active area schematic diagram of dual-port SRAM structures provided in an embodiment of the present invention；
Fig. 4 is that the structural representation after grid is made in Fig. 3 structures；
Fig. 5 is that the structural representation after conductive plunger is made in Fig. 4 structures；
Fig. 6 is that the structural representation after the metal level of metal interconnection structure is made in Fig. 5 structures；
Fig. 7 is in the case of first port is opened and carries out read operation, SRAM structures and contrast test in the present embodiment
The butterfly curve of SRAM structures；
In the case of Fig. 8 is first port and second port while opens progress read operation, the SRAM structures in the present embodiment
With the butterfly curve of the SRAM structures of contrast test.
Embodiment
As described in the background art, existing existing dual-port SRAM read current and noise margin are smaller.For above-mentioned
Technical problem, the present invention is by by the active area of the transmission transistor of first port first and the transmission transistor of second port second
The active area three of the first pull-down NMOS pipe physically connects in active area and the phase inverter of two transmission transistors connection,
In other words, the active area width of the first pull-down NMOS pipe has been widened, the saturation current of the first pull-down NMOS pipe has been increased, that is, increases
Pull-down current in read operation；Similarly, by the active area of the transmission transistor of first port the 3rd and second port the 4th
The active area three of the second pull-down NMOS pipe exists in the active area of transmission transistor and the phase inverter of two transmission transistors connection
Physically connect, in other words, widened the active area width of the second pull-down NMOS pipe, increased the saturation of the second pull-down NMOS pipe
Electric current, that is, increase the pull-down current in read operation, and the transmission transistor for whether depending merely on certain Single port reads storage node
Data, or the transmission transistor reading data of two-port are opened simultaneously, reading electric current can be increased, improves noise margin.
In order to facilitate the understanding of the purposes, features and advantages of the present invention, below in conjunction with the accompanying drawings to the present invention
Embodiment be described in detail.
It is dual-port SRAM structural circuit figures provided in an embodiment of the present invention shown in Fig. 1, Fig. 2 is in Fig. 1 corresponding to circuit
The Integrated circuit layouts top view of SRAM structures.Shown in reference picture 1 and Fig. 2, dual-port SRAM structures, including：
First phase inverter and the second phase inverter, first phase inverter include the first pull-up PMOS PU1 and the first drop-down
NMOS tube PD1, second phase inverter include the second pull-up PMOS PU2 and the second pull-down NMOS pipe PD2, and described first is anti-phase
Utensil has the first storage node（Do not indicate）, second phase inverter has the second storage node（Do not indicate）；
The the first transmission transistor PG1 and the second transmission transistor PG2 being connected with first storage node, with described
Two storage nodes connected the 3rd transmission transistor PG3 and the 4th transmission transistor PG4, the first transmission transistor PG1 and
3rd transmission transistor PG3 corresponds to first port Port-A, the second transmission transistor PG2 and the 4th transmission transistor PG4
Corresponding second port Port-B；
Wherein, the active area of the first transmission transistor PG1, the first pull-down NMOS pipe PD1 active area and second pass
Defeated transistor PG2 active area physically connects；Active area, the second pull-down NMOS pipe PD2 of the 3rd transmission transistor PG3
Active area and the 4th transmission transistor PG4 active area physically connect.
In order to clearly show that the connection between each transistor of SRAM structures in Fig. 2, SRAM is present embodiments provided
The preparation method of structure.
Specifically, shown in reference picture 3, substrate is provided first, each well region is made on substrate, corresponds to each transistor respectively
Active area 10.Including two U-shaped active areas 101,102, active area 101 is used to form the first transmission transistor PG1, first
Pull-down NMOS pipe PD1 and the second transmission transistor PG2 source-drain area；Active area 102 is used to form the 3rd transmission transistor
PG3, the second pull-down NMOS pipe PD2 and the 4th transmission transistor PG4 source-drain area.In addition, also include being used to form first
Draw the active area 103 of PMOS PU1 source-drain areas and the active area 104 for forming the second pull-up PMOS PU2 source-drain areas.
It is understood that during read operation, pull-down transistor PD1, PD2 saturation current and having for the transistor
Area width W（The width of transistor gate, Width）It is directly proportional, thus the active area for increasing pull-down transistor PD1, PD2 is wide
Degree, you can increase the read current of the pull-down transistor PD1, PD2 in read operation, improve SNM.It is in addition, two anti-in SRAM structures
The evolution of the probability of mismatch of phase device and pull-down transistor active area width is inversely proportional, thus, increase pull-down transistor active area is wide
Degree, the probability of mismatch of two phase inverters in SRAM structures can be reduced, improve the yield rate of SRAM structures.
In specific implementation process, in order to reduce the area of SRAM structures, if the first pull-down NMOS pipe PD1 active area with
First transmission transistor PG1 active area physically connects, rather than by setting conductive plunger on respective active area
To be connected by metal interconnection structure, for the above situation, then the active area for extending the first pull-down NMOS pipe PD1 passes to second
Defeated transistor PG2 active area physically connects.Similarly, if the active area of the first pull-down NMOS pipe PD1 and second passes
Defeated transistor PG2 active area physically connects, then extends the active area of the first pull-down NMOS pipe PD1 to the
One transmission transistor PG1 active area physically connects.It is active that such scheme provides a kind of the first pull-down NMOS pipe PD1 of increase
The method of sector width so that three connected transistor PG1, PG2, PD1 active areas of the first storage node share.
Similarly, in order to reduce the area of SRAM structures, if the active area of the second pull-down NMOS pipe PD2 and the 3rd passes
Defeated transistor PG3 active area physically connects, then extends the active area of the second pull-down NMOS pipe PD2 to the 4th
Transmission transistor PG4 active area physically connects；If the active area of the second pull-down NMOS pipe PD2 and the 4th transmission crystal
Pipe PG4 active area physically connects, then extend the active area of the second pull-down NMOS pipe PD2 to the 3rd transmission transistor
PG3 active area physically connects.Such scheme provides a kind of side for increasing the second pull-down NMOS pipe PD2 active area widths
Method so that three connected transistor PG3, PG4, PD2 active areas of the second storage node share.
Shown in reference picture 1, the first transmission transistor PG1, the second transmission transistor PG2, the 3rd transmission transistor PG3 and
4th transmission transistor PG4 can be nmos pass transistor, and in other embodiments, above-mentioned transistor can also all be PMOS crystal
Pipe.
Referring next to shown in Fig. 4, deposited oxide layer and polysilicon on substrate, patterning form each transistor after etching
Grid oxic horizon（It is not shown）And grid 20.
Wherein, the first pull-down NMOS pipe PD1 is connected with the first pull-up PMOS PU1 grid 20, the second pull-down NMOS pipe
PD2 is connected with the second pull-up PMOS PU2 grid 20.
Afterwards shown in reference picture 5, the deposited oxide layer on substrate（It is not shown）And after planarizing, formed in oxide layer logical
Hole, and insert metal, remove through hole outside excess metal after, formation be located at each active area 10（Fig. 3）Or grid 20（Fig. 4）Place
Conductive plunger 30.
With reference to shown in Fig. 5 and Fig. 2, wherein, the conductive plunger 30 at the first transmission transistor PG1 grid 20 is used for the
Single port Port-A word-line signal Port-A WL access the grid 20, and the conductive plunger 30 at drain region is used for first port
Port-A bit line signal Port-A BL access the drain region, and source region and the first pull-down NMOS pipe PD1 drain region share.
Conductive plunger 30 at second transmission transistor PG2 grid 20 is used for second port Port-B word-line signal
Port-B WL access the grid 20, and the conductive plunger 30 at drain region is used for second port Port-B bit line signal Port-B
BL accesses the drain region, and the conductive plunger 30 at source region is used for the source region and the conduction at the first pull-up PMOS PU1 source region
The conductive plunger 30 that connector 30, second pulls up at PMOS PU2 grid 20 is respectively connected with；In addition, the second transmission transistor PG2
Source region and the first pull-down NMOS pipe PD1 drain region share.
Conductive plunger 30 at first pull-down NMOS pipe PD1 source regions is used to earthing power supply VSS accessing the source region.
Conductive plunger 30 at first pull-up PMOS PU1 drain region is used to supply voltage VDD accessing the source region.
Conductive plunger 30 at 4th transmission transistor PG4 grid 20 is used for second port Port-B word-line signal
Port-B WL access the grid 20, and the conductive plunger 30 at drain region is used for second port Port-B bit line opposite signal
Port-B BLB access the drain region, and source region and the second pull-down NMOS pipe PD2 drain region share.
Conductive plunger 30 at 3rd transmission transistor PG3 grid 20 is used for first port Port-A word-line signal
Port-A WL access the grid 20, and the conductive plunger 30 at drain region is used for first port Port-A bit line opposite signal
Port-A BLB access the drain region, and the conductive plunger 30 at source region is used for the source region by the source region and the second pull-up PMOS PU2
The conductive plunger 30 that the conductive plunger 30, first at place pulls up at PMOS PU1 grid 20 is respectively connected with；In addition, the 3rd transmission
Transistor PG3 source region and the second pull-down NMOS pipe PD2 drain region share.
Conductive plunger 30 at second pull-down NMOS pipe PD2 source regions is used to earthing power supply VSS accessing the source region.
Conductive plunger 30 at second pull-up PMOS PU2 drain region is used to supply voltage VDD accessing the source region.
With reference to shown in Fig. 6 and Fig. 2, the deposited metal layer on substrate（It is not shown）, metal interconnection is formed after selective removal
The metal level 40 of structure.
Wherein, the conductive plunger 30, first at the second transmission transistor PG2 source regions is pulled up PMOS by metal level 40 at one
The conductive plunger 30 that conductive plunger 30 and second at PU1 source region pulls up at PMOS PU2 grid 20 is connected.At one
Metal level 40 pulls up the conductive plunger 30, second at the 3rd transmission transistor PG3 source regions the conduction at PMOS PU2 source region
The conductive plunger 30 that connector 30, first pulls up at PMOS PU1 grid 20 is respectively connected with.
To verify that dual-port SRAM structures provided by the invention can improve the noise resisting ability during read operation, improve
Noise margin, inventor have carried out comparative simulation experiment.Wherein, the second curve is the butterfly curve of structure shown in Fig. 2, to first
Phase inverter access input voltage vin, the first phase inverter output for the second phase inverter input, measure respectively the first phase inverter with
The output voltage Vout of second phase inverter.The SRAM structures that SRAM structures measured by first curve are surveyed with the second curve are substantially
It is identical, differ only in：On first pull-down NMOS pipe PD1 active area and the first transmission transistor PG1 active area are non-physical
It is connected, but is connected using conductive plunger；Second pull-down NMOS pipe PD2 active area is active with the 4th transmission transistor PG4's
Area is non-physical connected, but is connected using conductive plunger.
If opening first port Port-A word-line signal Port-A WL, turn on the first transmission transistor PG1 and the 3rd and pass
Defeated transistor PG3, second port Port-B word-line signal Port-B WL are closed, close the second transmission transistor PG2 and the 4th
Transmission transistor PG4, in other words, read operation is carried out only with first port Port-A.Butterfly curve such as Fig. 7 of above-mentioned read procedure
It is shown.As can be seen that the noise margin of the first curve is 215mV, the noise margin of the second curve is 190mV, using extension the
After one pull-down NMOS pipe PD1 and the second pull-down NMOS pipe PD2 active area width, noise margin can improve 16%.
If opening first port Port-A word-line signal Port-A WL, turn on the first transmission transistor PG1 and the 3rd and pass
Defeated transistor PG3, while opening second port Port-B word-line signal Port-B WL, open the second transmission transistor PG2
With the 4th transmission transistor PG4, in other words, read operation is carried out using first port Port-A and second port Port-B simultaneously.
The butterfly curve of above-mentioned read procedure is as shown in Figure 8.As can be seen that the noise margin of the first curve is 170mV, the second curve is made an uproar
Acoustic capacitance is limited to 145mV, after the active area width using extension the first pull-down NMOS pipe PD1 and the second pull-down NMOS pipe PD2, noise
Tolerance limit can improve 31%.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, this is not being departed from
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
The scope of restriction is defined.
Claims (10)
1. a kind of dual-port SRAM structures, including：
First phase inverter and the second phase inverter, first phase inverter include the first pull-up PMOS and the first pull-down NMOS pipe,
Second phase inverter includes the second pull-up PMOS and the second pull-down NMOS pipe, and there is first phase inverter the first storage to tie
Point, second phase inverter have the second storage node；
The first transmission transistor and the second transmission transistor being connected with first storage node, with second storage node
The 3rd connected transmission transistor and the 4th transmission transistor, first transmission transistor corresponding with the 3rd transmission transistor
Single port, the second transmission transistor second port corresponding with the 4th transmission transistor；
Characterized in that, the active area of the active area of first transmission transistor, the first pull-down NMOS pipe and the second transmission are brilliant
The active area of body pipe physically connects；The active area of 3rd transmission transistor, the active area of the second pull-down NMOS pipe and
The active area of four transmission transistors physically connects；
Wherein, the conductive plunger of the active area of second transmission transistor, described first are pulled up by PMOS by metal level
Active area conductive plunger and it is described second pull-up PMOS grid at conductive plunger link together；Pass through metal
Layer pulls up the conductive plunger of the active area of the 3rd transmission transistor, described second conductive plunger of the active area of PMOS
And the conductive plunger at the grid of the first pull-up PMOS links together.
2. dual-port SRAM structures according to claim 1, it is characterised in that the active area of first pull-down NMOS pipe
Physically connect with the active area of the first transmission transistor, the active area of first pull-down NMOS pipe extends to and the second transmission
The active area of transistor physically connects.
3. dual-port SRAM structures according to claim 1, it is characterised in that the active area of second pull-down NMOS pipe
Physically connect with the active area of the 3rd transmission transistor, the active area of second pull-down NMOS pipe extends to and the 4th transmission
The active area of transistor physically connects.
4. dual-port SRAM structures according to claim 1, it is characterised in that first transmission transistor is NMOS
Pipe.
5. dual-port SRAM structures according to claim 1, it is characterised in that second transmission transistor is NMOS
Pipe.
6. dual-port SRAM structures according to claim 1, it is characterised in that the 3rd transmission transistor is NMOS
Pipe.
7. dual-port SRAM structures according to claim 1, it is characterised in that the 4th transmission transistor is NMOS
Pipe.
8. dual-port SRAM structures according to claim 1, it is characterised in that first storage node and the second storage
In the reading process of node, first transmission transistor and the 3rd transmission transistor are opened.
9. dual-port SRAM structures according to claim 1, it is characterised in that first storage node and the second storage
In the reading process of node, second transmission transistor and the 4th transmission transistor are opened.
10. dual-port SRAM structures according to claim 1, it is characterised in that the reading of first storage node
Cheng Zhong, first transmission transistor, the 3rd transmission transistor, the second transmission transistor and the 4th transmission transistor are beaten simultaneously
Open.
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| KR102627228B1 (en) * | 2018-09-14 | 2024-01-22 | 에스케이하이닉스 주식회사 | Fuse latch of semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101064188A (en) * | 2006-04-28 | 2007-10-31 | 台湾积体电路制造股份有限公司 | Semiconductor framework and sram storage element |
| CN101246888A (en) * | 2007-02-15 | 2008-08-20 | 台湾积体电路制造股份有限公司 | Integrated circuit, dual port sram cell and semiconductor structure |
| CN101299348A (en) * | 2007-05-04 | 2008-11-05 | 台湾积体电路制造股份有限公司 | Semiconductor device, static state memory unit and semiconductor memory circuit |
| CN102034825A (en) * | 2009-09-30 | 2011-04-27 | 台湾积体电路制造股份有限公司 | Embedded sram structure and chip |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101064188A (en) * | 2006-04-28 | 2007-10-31 | 台湾积体电路制造股份有限公司 | Semiconductor framework and sram storage element |
| CN101246888A (en) * | 2007-02-15 | 2008-08-20 | 台湾积体电路制造股份有限公司 | Integrated circuit, dual port sram cell and semiconductor structure |
| CN101299348A (en) * | 2007-05-04 | 2008-11-05 | 台湾积体电路制造股份有限公司 | Semiconductor device, static state memory unit and semiconductor memory circuit |
| CN102034825A (en) * | 2009-09-30 | 2011-04-27 | 台湾积体电路制造股份有限公司 | Embedded sram structure and chip |
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