CN104751876A - Dual port SRAM (static random access memory) structure - Google Patents
Dual port SRAM (static random access memory) structure Download PDFInfo
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- CN104751876A CN104751876A CN201310745731.4A CN201310745731A CN104751876A CN 104751876 A CN104751876 A CN 104751876A CN 201310745731 A CN201310745731 A CN 201310745731A CN 104751876 A CN104751876 A CN 104751876A
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Abstract
The invention discloses a dual port SRAM (static random access memory) structure. Through physical connection of an active region of a first transmission transistor of a first port, an active region of a second transmission transistor of a second port, and an active region of a first pull-down NMOS (N-Mental-Oxide-Semiconductor) tube in an inverter connected with the first transmission transistor and the second transmission transistor, the width of the active region of the first pull-down NMOS tube is enlarged, pull-down current of the first pull-down NMOS tube in the read operation can be increased; similarly, through physical connection of an active region of a third transmission transistor of the first port, an active region of a fourth transmission transistor of the second port, and an active region of a second pull-down NMOS (N-Mental-Oxide-Semiconductor) tube in an inverter connected with the third transmission transistor and the fourth transmission transistor, the width of the active region of the second pull-down NMOS tube is enlarged, pull-down current of the second pull-down NMOS tube in the read operation can be increased, and the read current can be increased and the noise tolerance can be improved whether by only depending on a transmission transistor of one certain port to read storage node data, or opening simultaneously two transmission transistors of two ports to read the data.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly a kind of dual-port SRAM structure.
Background technology
Static RAM (SRAM) is embedded in nearly all large scale integrated circuit (VLSI), and is requiring to serve critical effect in high speed, high integration, low-power consumption, low-voltage, low cost, short-period application.Embedded SRAM compares other memory embedded semiconductors such as dynamic RAM (DRAM) can provide access speed faster, so in occupation of dominant position in high-end applications.
Static noise margin (SNM) is one of parameter of assessment SRAM memory cell, refer to the amplitude of the maximum DC noise signal that storage unit can bear, if exceed this value, can there is reversion by mistake in the data of storage node, it is the important parameter weighing storage unit antijamming capability.Visible, SNM represents the stability of the data be stored in the memory unit.Along with the increase of SNM value, the data retention operation of storage unit becomes more stable, but, on the contrary, contrary data write storage unit is also become more difficult.SRAM performance need makes trade-offs at SNM and writing between noise margin (WNR).But along with reducing of SRAM process, cellar area significantly reduces, thus supply voltage (VDD) is more and more less, and then causes noise margin (SNM) and write noise margin (WNR) constantly becoming grain.In addition, reducing of above-mentioned process also can cause read current more and more less, and this can cause the SRAM under high-speed cruising to read unsuccessfully.The problems referred to above all propose new challenge to sram cell design.
For the problems referred to above, prior art also has some schemes to propose.Such as, adopt the SRAM of dual-port to replace the SRAM of single port to increase read current, improve noise margin simultaneously.
But along with reducing further of SRAM process, the SRAM of existing dual-port increases read current and improves noise margin limited extent, cannot satisfy the demands.
Summary of the invention
What the present invention solved is read current and the noise margin of improving existing dual-port SRAM.
For solving the problem, the invention provides a kind of dual-port SRAM structure, comprising:
First phase inverter and the second phase inverter, described first phase inverter comprises the first pull-up PMOS and the first pull-down NMOS pipe, described second phase inverter comprises the second pull-up PMOS and the second pull-down NMOS pipe, described first phase inverter has the first storage node, and described second phase inverter has the second storage node;
The first transmission transistor be connected with described first storage node and the second transmission transistor, the 3rd transmission transistor be connected with described second storage node and the 4th transmission transistor, described first transmission transistor and corresponding first port of the 3rd transmission transistor, described second transmission transistor and corresponding second port of the 4th transmission transistor;
Wherein, the active area of the active area of described first transmission transistor, the active area of the first pull-down NMOS pipe and the second transmission transistor physically connects; The active area of the described active area of the 3rd transmission transistor, the active area of the second pull-down NMOS pipe and the 4th transmission transistor physically connects.
Alternatively, the active area of described first pull-down NMOS pipe physically connects with the active area of the first transmission transistor, and the active area of described first pull-down NMOS pipe extends to and physically connects with the active area of the second transmission transistor.
Alternatively, the active area of described second pull-down NMOS pipe physically connects with the active area of the 3rd transmission transistor, and the active area of described second pull-down NMOS pipe extends to and physically connects with the active area of the 4th transmission transistor.
Alternatively, described first transmission transistor is NMOS tube.
Alternatively, described second transmission transistor is NMOS tube.
Alternatively, described 3rd transmission transistor is NMOS tube.
Alternatively, described 4th transmission transistor is NMOS tube.
Alternatively, in the reading process of described first storage node and the second storage node, described first transmission transistor and the 3rd transmission transistor are opened.
Alternatively, in the reading process of described first storage node and the second storage node, described second transmission transistor and the 4th transmission transistor are opened.
Alternatively, in the reading process of described first storage node, described first transmission transistor, the 3rd transmission transistor, the second transmission transistor and the 4th transmission transistor are opened simultaneously.
Compared with prior art, technical scheme of the present invention has the following advantages:
By the active area of the first pull-down NMOS pipe in the phase inverter that is connected with active area and two transmission transistors of the second port second transmission transistor the active area of the first port first transmission transistor, three is connected physically, in other words, widen the active area width of the first pull-down NMOS pipe, increase the saturation current of the first pull-down NMOS pipe, namely increase the pull-down current in read operation, similarly, by the active area of the active area of the first port the 3rd transmission transistor and the second port the 4th transmission transistor, and two the active area of the second pull-down NMOS pipe in the phase inverter that connects of transmission transistor three is connected physically, in other words, widen the active area width of the second pull-down NMOS pipe, increase the saturation current of the second pull-down NMOS pipe, namely the pull-down current in read operation is increased, no matter be that the transmission transistor depending merely on certain Single port reads storage node data, still the transmission transistor simultaneously opening two-port reads data, reading electric current can be strengthened, improve the noise resisting ability in read operation, namely improve noise margin.
In possibility, if the active area of described first pull-down NMOS pipe physically connects with the active area of the first transmission transistor, then extend the active area of described first pull-down NMOS pipe to physically connecting with the active area of the second transmission transistor; If the active area of described first pull-down NMOS pipe physically connects with the active area of the second transmission transistor, then extend the active area of described first pull-down NMOS pipe to physically connecting with the active area of the first transmission transistor.Such scheme provides the method for a kind of increase the first pull-down NMOS pipe active area width, and three transistor active area that the first storage node is connected share.
In possibility, if the active area of described second pull-down NMOS pipe physically connects with the active area of the 3rd transmission transistor, then extend the active area of described second pull-down NMOS pipe to physically connecting with the active area of the 4th transmission transistor; If the active area of described second pull-down NMOS pipe physically connects with the active area of the 4th transmission transistor, then extend the active area of described second pull-down NMOS pipe to physically connecting with the active area of the 3rd transmission transistor.Such scheme provides the method for a kind of increase the second pull-down NMOS pipe active area width, and three transistor active area that the second storage node is connected share.
Accompanying drawing explanation
Fig. 1 is the dual-port SRAM structural circuit figure that the embodiment of the present invention provides;
Fig. 2 is the Integrated circuit layouts vertical view of the dual-port SRAM structure that the embodiment of the present invention provides;
Fig. 3 is the active area schematic diagram of the dual-port SRAM structure that the embodiment of the present invention provides;
Fig. 4 is the structural representation after Fig. 3 structure making grid;
Fig. 5 is the structural representation after Fig. 4 structure making conductive plunger;
Fig. 6 is the structural representation after metal level Fig. 5 structure making metal interconnect structure;
Fig. 7 is under the first port is opened and carried out read operation situation, the butterfly curve of the SRAM structure in the present embodiment and the SRAM structure of contrast test;
Fig. 8 is under the first port and the second port are opened simultaneously and carried out read operation situation, the butterfly curve of the SRAM structure in the present embodiment and the SRAM structure of contrast test.
Embodiment
As described in the background art, the read current of existing existing dual-port SRAM and noise margin less.For above-mentioned technical matters, the active area three that the present invention passes through the first pull-down NMOS pipe in the phase inverter be connected with active area and two transmission transistors of the second port second transmission transistor the active area of the first port first transmission transistor connects physically, in other words, widen the active area width of the first pull-down NMOS pipe, increase the saturation current of the first pull-down NMOS pipe, namely increase the pull-down current in read operation, similarly, by the active area of the active area of the first port the 3rd transmission transistor and the second port the 4th transmission transistor, and two the active area three of the second pull-down NMOS pipe in the phase inverter that connects of transmission transistor connect physically, in other words, widen the active area width of the second pull-down NMOS pipe, increase the saturation current of the second pull-down NMOS pipe, namely the pull-down current in read operation is increased, no matter be that the transmission transistor depending merely on certain Single port reads storage node data, still the transmission transistor simultaneously opening two-port reads data, reading electric current can be strengthened, improve noise margin.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Be the dual-port SRAM structural circuit figure that the embodiment of the present invention provides shown in Fig. 1, Fig. 2 is the Integrated circuit layouts vertical view of the SRAM structure that in Fig. 1, circuit is corresponding.With reference to shown in Fig. 1 and Fig. 2, dual-port SRAM structure, comprising:
First phase inverter and the second phase inverter, described first phase inverter comprises the first pull-up PMOS PU1 and the first pull-down NMOS pipe PD1, described second phase inverter comprises the second pull-up PMOS PU2 and the second pull-down NMOS pipe PD2, described first phase inverter has the first storage node (sign), and described second phase inverter has the second storage node (sign);
The the first transmission transistor PG1 be connected with described first storage node and the second transmission transistor PG2, the 3rd transmission transistor PG3 be connected with described second storage node and the 4th transmission transistor PG4, described first transmission transistor PG1 first port Port-A corresponding to the 3rd transmission transistor PG3, described second transmission transistor PG2 second port Port-B corresponding to the 4th transmission transistor PG4;
Wherein, the active area of the described active area of the first transmission transistor PG1, the active area of the first pull-down NMOS pipe PD1 and the second transmission transistor PG2 physically connects; The active area of the described active area of the 3rd transmission transistor PG3, the active area of the second pull-down NMOS pipe PD2 and the 4th transmission transistor PG4 physically connects.
In order to the connection between each transistor of SRAM structure in clear display Fig. 2, present embodiments provide the method for making of SRAM structure.
Particularly, with reference to shown in Fig. 3, first provide substrate, substrate makes each well region, respectively the active area 10 of corresponding each transistor.Comprising two U-shaped active areas 101,102, active area 101 is for the formation of the source-drain area of the first transmission transistor PG1, the first pull-down NMOS pipe PD1 and the second transmission transistor PG2; Active area 102 is for the formation of the source-drain area of the 3rd transmission transistor PG3, the second pull-down NMOS pipe PD2 and the 4th transmission transistor PG4.In addition, also comprise for the formation of the active area 103 of the first pull-up PMOS PU1 source-drain area and the active area 104 for the formation of the second pull-up PMOS PU2 source-drain area.
Be understandable that, in read operation process, the width of the saturation current of pull-down transistor PD1, PD2 and the active area width W(transistor gate of this transistor, Width) be directly proportional, thus the active area width of pull-down transistor PD1, PD2 is increased, this pull-down transistor PD1, PD2 read current in read operation can be increased, improve SNM.In addition, in SRAM structure, the probability of mismatch of two phase inverters and the evolution of pull-down transistor active area width are inversely proportional to, and thus, increase pull-down transistor active area width, can reduce the probability of mismatch of two phase inverters in SRAM structure, improve the yield rate of SRAM structure.
In specific implementation process, in order to reduce the area of SRAM structure, if the active area of the first pull-down NMOS pipe PD1 connects physically with the active area of the first transmission transistor PG1, but not by arranging conductive plunger to be connected by metal interconnect structure on respective active area, for above-mentioned situation, then extend the active area of the first pull-down NMOS pipe PD1 to physically connecting with the active area of the second transmission transistor PG2.Similarly, if the active area of described first pull-down NMOS pipe PD1 connects physically with the active area of the second transmission transistor PG2, then extend the active area of described first pull-down NMOS pipe PD1 to physically connecting with the active area of the first transmission transistor PG1.Such scheme provides the method for a kind of increase the first pull-down NMOS pipe PD1 active area width, and three transistor PG1, PG2, PD1 active areas that the first storage node is connected share.
Similarly, in order to reduce the area of SRAM structure, if the active area of described second pull-down NMOS pipe PD2 connects physically with the active area of the 3rd transmission transistor PG3, then extend the active area of described second pull-down NMOS pipe PD2 to physically connecting with the active area of the 4th transmission transistor PG4; If the active area of described second pull-down NMOS pipe PD2 physically connects with the active area of the 4th transmission transistor PG4, then extend the active area of described second pull-down NMOS pipe PD2 to physically connecting with the active area of the 3rd transmission transistor PG3.Such scheme provides the method for a kind of increase the second pull-down NMOS pipe PD2 active area width, and three transistor PG3, PG4, PD2 active areas that the second storage node is connected share.
With reference to shown in Fig. 1, the first transmission transistor PG1, the second transmission transistor PG2, the 3rd transmission transistor PG3 and the 4th transmission transistor PG4 can be nmos pass transistor, and in other embodiment, above-mentioned transistor can be also all PMOS transistor.
Then with reference to shown in Fig. 4, at deposited on substrates oxide layer and polysilicon, grid oxic horizon (not shown) and the grid 20 of each transistor after patterning etching, is formed.
Wherein, the first pull-down NMOS pipe PD1 is connected with the grid 20 of the first pull-up PMOS PU1, and the second pull-down NMOS pipe PD2 is connected with the grid 20 of the second pull-up PMOS PU2.
Afterwards with reference to shown in Fig. 5, in deposited on substrates oxide layer (not shown) and after planarization, in oxide layer, form through hole, and after inserting metal, removing outside through hole excess metal, formed and be positioned at each active area 10(Fig. 3) or grid 20(Fig. 4) conductive plunger 30 at place.
Composition graphs 5 is with shown in Fig. 2, wherein, the conductive plunger 30 at grid 20 place of the first transmission transistor PG1 is for accessing this grid 20 by the word-line signal Port-A WL of the first port Port-A, the conductive plunger 30 at drain region place is for accessing this drain region by the bit line signal Port-A BL of the first port Port-A, and the drain region of source region and the first pull-down NMOS pipe PD1 shares.
The conductive plunger 30 at grid 20 place of the second transmission transistor PG2 is for accessing this grid 20 by the word-line signal Port-B WL of the second port Port-B, the conductive plunger 30 at drain region place is for accessing this drain region by the bit line signal Port-B BL of the second port Port-B, and the conductive plunger 30 at source region place is for being connected the conductive plunger 30 of this source region with grid 20 place of conductive plunger 30, the second pull-up PMOS PU2 at the source region place of the first pull-up PMOS PU1 respectively; In addition, the source region of the second transmission transistor PG2 and the drain region of the first pull-down NMOS pipe PD1 share.
The conductive plunger 30 in the first pull-down NMOS pipe PD1 source region place is for accessing this source region by earthing power supply VSS.
The conductive plunger 30 at the drain region place of the first pull-up PMOS PU1 is for accessing this source region by supply voltage VDD.
The conductive plunger 30 at grid 20 place of the 4th transmission transistor PG4 is for accessing this grid 20 by the word-line signal Port-B WL of the second port Port-B, the conductive plunger 30 at drain region place is for accessing this drain region by the bit line opposite signal Port-B BLB of the second port Port-B, and the drain region of source region and the second pull-down NMOS pipe PD2 shares.
The conductive plunger 30 at grid 20 place of the 3rd transmission transistor PG3 is for accessing this grid 20 by the word-line signal Port-A WL of the first port Port-A, the conductive plunger 30 at drain region place is for accessing this drain region by the bit line opposite signal Port-A BLB of the first port Port-A, and the conductive plunger 30 at source region place is for being connected the conductive plunger 30 of this source region with grid 20 place of conductive plunger 30, the first pull-up PMOS PU1 at the source region place of the second pull-up PMOS PU2 respectively; In addition, the source region of the 3rd transmission transistor PG3 and the drain region of the second pull-down NMOS pipe PD2 share.
The conductive plunger 30 in the second pull-down NMOS pipe PD2 source region place is for accessing this source region by earthing power supply VSS.
The conductive plunger 30 at the drain region place of the second pull-up PMOS PU2 is for accessing this source region by supply voltage VDD.
Composition graphs 6, with shown in Fig. 2, deposited on substrates metal level (not shown), forms the metal level 40 of metal interconnect structure after selective removal.
Wherein, the conductive plunger 30 at the conductive plunger 30 at the source region place of conductive plunger 30, the first pull-up PMOS PU1 at the second transmission transistor PG2 source region place and grid 20 place of the second pull-up PMOS PU2 is connected by place's metal level 40.The conductive plunger 30 at grid 20 place of conductive plunger 30, the first pull-up PMOS PU1 at the source region place of conductive plunger 30, the second pull-up PMOS PU2 at the 3rd transmission transistor PG3 source region place is connected by place's metal level 40 respectively.
For verifying that dual-port SRAM structure provided by the invention can improve the noise resisting ability in read operation process, improving noise margin, inventors performed comparative simulation experiment.Wherein, the butterfly curve that the second curve is structure shown in Fig. 2, to the first phase inverter access input voltage vin, the output of the first phase inverter is the input of the second phase inverter, measures the output voltage Vout of the first phase inverter and the second phase inverter respectively.The SRAM structure that first Curves is measured is roughly the same with the SRAM structure that the second Curves is surveyed, and difference is only: the active area of the first pull-down NMOS pipe PD1 is connected with in the active area non-physical of the first transmission transistor PG1, but adopts conductive plunger to be connected; The active area of the second pull-down NMOS pipe PD2 is connected with in the active area non-physical of the 4th transmission transistor PG4, but adopts conductive plunger to be connected.
If open the word-line signal Port-A WL of the first port Port-A, conducting first transmission transistor PG1 and the 3rd transmission transistor PG3, close the word-line signal Port-B WL of the second port Port-B, close the second transmission transistor PG2 and the 4th transmission transistor PG4, in other words, the first port Port-A is only adopted to carry out read operation.The butterfly curve of above-mentioned read procedure as shown in Figure 7.Can find out, the noise margin of the first curve is 215mV, and the noise margin of the second curve is 190mV, and after adopting the active area width of extension first pull-down NMOS pipe PD1 and the second pull-down NMOS pipe PD2, noise margin can improve 16%.
If open the word-line signal Port-A WL of the first port Port-A, conducting first transmission transistor PG1 and the 3rd transmission transistor PG3, while opening the word-line signal Port-B WL of the second port Port-B, open the second transmission transistor PG2 and the 4th transmission transistor PG4, in other words, adopt the first port Port-A and the second port Port-B to carry out read operation simultaneously.The butterfly curve of above-mentioned read procedure as shown in Figure 8.Can find out, the noise margin of the first curve is 170mV, and the noise margin of the second curve is 145mV, and after adopting the active area width of extension first pull-down NMOS pipe PD1 and the second pull-down NMOS pipe PD2, noise margin can improve 31%.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a dual-port SRAM structure, comprising:
First phase inverter and the second phase inverter, described first phase inverter comprises the first pull-up PMOS and the first pull-down NMOS pipe, described second phase inverter comprises the second pull-up PMOS and the second pull-down NMOS pipe, described first phase inverter has the first storage node, and described second phase inverter has the second storage node;
The first transmission transistor be connected with described first storage node and the second transmission transistor, the 3rd transmission transistor be connected with described second storage node and the 4th transmission transistor, described first transmission transistor and corresponding first port of the 3rd transmission transistor, described second transmission transistor and corresponding second port of the 4th transmission transistor;
It is characterized in that, the active area of the active area of described first transmission transistor, the active area of the first pull-down NMOS pipe and the second transmission transistor physically connects; The active area of the described active area of the 3rd transmission transistor, the active area of the second pull-down NMOS pipe and the 4th transmission transistor physically connects.
2. dual-port SRAM structure according to claim 1, it is characterized in that, the active area of described first pull-down NMOS pipe physically connects with the active area of the first transmission transistor, and the active area of described first pull-down NMOS pipe extends to and physically connects with the active area of the second transmission transistor.
3. dual-port SRAM structure according to claim 1, it is characterized in that, the active area of described second pull-down NMOS pipe physically connects with the active area of the 3rd transmission transistor, and the active area of described second pull-down NMOS pipe extends to and physically connects with the active area of the 4th transmission transistor.
4. dual-port SRAM structure according to claim 1, is characterized in that, described first transmission transistor is NMOS tube.
5. dual-port SRAM structure according to claim 1, is characterized in that, described second transmission transistor is NMOS tube.
6. dual-port SRAM structure according to claim 1, is characterized in that, described 3rd transmission transistor is NMOS tube.
7. dual-port SRAM structure according to claim 1, is characterized in that, described 4th transmission transistor is NMOS tube.
8. dual-port SRAM structure according to claim 1, is characterized in that, in the reading process of described first storage node and the second storage node, described first transmission transistor and the 3rd transmission transistor are opened.
9. dual-port SRAM structure according to claim 1, is characterized in that, in the reading process of described first storage node and the second storage node, described second transmission transistor and the 4th transmission transistor are opened.
10. dual-port SRAM structure according to claim 1, is characterized in that, in the reading process of described first storage node, described first transmission transistor, the 3rd transmission transistor, the second transmission transistor and the 4th transmission transistor are opened simultaneously.
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| CN110364530A (en) * | 2018-04-11 | 2019-10-22 | 中芯国际集成电路制造(上海)有限公司 | Memory and forming method thereof |
| CN110910943A (en) * | 2018-09-14 | 2020-03-24 | 爱思开海力士有限公司 | Fuse latch of semiconductor device |
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| CN110910943A (en) * | 2018-09-14 | 2020-03-24 | 爱思开海力士有限公司 | Fuse latch of semiconductor device |
| CN110910943B (en) * | 2018-09-14 | 2023-06-09 | 爱思开海力士有限公司 | Fuse latch of semiconductor device |
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