CN106952917A - A kind of layer transistor SRAM units of SOI six and preparation method thereof - Google Patents
A kind of layer transistor SRAM units of SOI six and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 239000002184 metal Substances 0.000 claims description 26
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- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 238000002955 isolation Methods 0.000 claims description 15
- 150000002500 ions Chemical class 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
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- 230000008859 change Effects 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 20
- 238000000034 method Methods 0.000 abstract description 9
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- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000003860 storage Methods 0.000 abstract description 4
- 238000004904 shortening Methods 0.000 abstract description 3
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- 238000005516 engineering process Methods 0.000 description 7
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- 238000012986 modification Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- -1 Phosphonium ion Chemical class 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
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- 239000011810 insulating material Substances 0.000 description 2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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Abstract
The present invention provides a kind of layer transistor SRAM units of SOI six and preparation method thereof, and the unit includes：First phase inverter, is made up of the first PMOS transistor and the first nmos pass transistor；Second phase inverter, is made up of the second PMOS transistor and the second nmos pass transistor；Pipe is obtained, is made up of the 3rd nmos pass transistor and the 4th nmos pass transistor.In the layer transistor SRAM units of SOI six of the present invention, the source electrode for constituting four transistors of the first phase inverter and the second phase inverter is embedded with tunnel-through diode structure, the leakage power consumption that can trigger in the floater effect in effectively suppressing PD SOI devices in the case of not increasing device area and parasitic triode effect and transistor threshold voltage drift, improve the noise resisting ability of unit.And the preparation method of the present invention also has the advantages that manufacturing process is simple, completely compatible with existing logic process, using the shared structure between centrosymmetric structure and unit inside unit, it is conveniently formed storage array, be conducive to shortening the cycle of design sram chip.
Description
Technical field
The invention belongs to reservoir designs and making field, it is related to a kind of layer transistor SRAM units of SOI six and its making side
Method.
Background technology
SOI technology is since the invention eighties in last century, and it is relative to common bulk silicon technological, with parasitic capacitance is small, work(
Consume fast and natural anti-single particle breech lock (Single-Event-Latchup, the SEL) ability of low, speed so that SOI technology is very suitable
Together in being operated in the occasions such as on-chip system (System-on-Chips, SoC), low-power consumption and radioresistance；In addition, static random
Memory (Static Random Access Memory, SRAM) is widely used in consumer electronics, automotive electronics, processor one
In level caching and L2 cache；So, SOI technology is applied in SRAM design, with some superiority.
According to the degree of exhaustion in metal-oxide-semiconductor body area, SOI can further be divided into fully- depleted (Full-Depleted, FD) SOI and
Part depletion (Partially-Depleted, FD) SOI.For part depletion SOI technology, due to its body area of metal-oxide-semiconductor and source region
Electrically separate, it is hanging to cause body area；In normal work, drain potentials are higher, and the electronics of inversion channel is transported from source electrode
When moving drain electrode, by electric field acceleration, when moving to by close to leakage body knot, now because most strong in electric field, electronics obtains volume
Outer energy, and collide to form electron-hole pair with the atom on lattice；Velocity of electrons is fast, in a short period of time by
Accelerate to drain electrode；But cavity speed is relatively slow, the low potential such as body area, source region region is slowly moved to along direction of an electric field,
The electronics that the hole in body area is easy to be provided by source electrode is moved to be combined, and when being moved to body area, because of its potential floating
And make it that hole accumulates gradually in body area, can directly influence the threshold voltage of metal-oxide-semiconductor, so that metal-oxide-semiconductor performance changes, this
It is exactly floater effect.In addition, there is parasitic triode effect in PD SOI metal-oxide-semiconductors, refer to source electrode, body area and the leakage of metal-oxide-semiconductor
Pole is respectively N, P and N, similar to the emitter stage in triode, base stage and colelctor electrode, that is, the parasitic day of metal-oxide-semiconductor
Right NPN triode；This base stage is hanging.Usually, when base stage does not have positive charge, its potential and transmitting electrode potential phase
Together, thus its triode is not turned on；If floater effect occurs, when base stage positive charge is accumulated to a certain extent, base stage and emitter stage
When potential is reached to a certain degree, its triode can be turned on, and the phenomenon of high current can be produced in drain electrode.Floater effect and parasitic three pole
Tube effect can cause the performance change of PD SOI sram cells, such as electric leakage increase, noise resisting ability reduction.
Static random access memory cell conventional at present mainly uses six transistor types, by two pull-up P-type transistors,
Two drop-down N-type transistors and two transmission gate N-type transistors are constituted, and wordline controls the switch of two transmission gate N-type transistors,
Data storage is write or read by bit line, wherein, this six transistors use common metal-oxide-semiconductor.
Usually, due to floater effect and parasitic triode effect in PD SOI metal-oxide-semiconductors, designer usually can be by metal-oxide-semiconductor
Body area extract (NMOS bodies area is connected to low potential, that is, with source region potential short circuit；PMOS bodies area is connected to high level), by potential
Keep fixed so as to suppress both effect；Common body contact is exactly T- type grid metal-oxide-semiconductors and H- type grid metal-oxide-semiconductors, but this and phase
Compared with the non-body of size contact metal-oxide-semiconductor, its area can be higher by a lot.If T- type metal-oxide-semiconductors directly are applied into sram cell
Central, cellar area can increase 1 times or so, even more many (application H- types grid).
Therefore, how a kind of layer transistor SRAM units of SOI six and preparation method thereof are provided, is ensureing not increase chip area
On the premise of effectively suppress the floater effect of metal-oxide-semiconductor, parasitic triode effect, so as to strengthen six transistor static random access memory
The stability and drop low leakage power consumption of unit, as those skilled in the art's important technological problems urgently to be resolved hurrily.
The content of the invention
The shortcoming of prior art in view of the above, it is an object of the invention to provide a kind of layer transistor SRAM lists of SOI six
Member and preparation method thereof, for solving, the layer transistor SRAM unit areas occupied of SOI six are larger, stability is poor in the prior art, leakage
The problem of power consumption height and weak noise resisting ability.
In order to achieve the above objects and other related objects, the present invention provides a kind of layer transistor SRAM units of SOI six, described
The layer transistor SRAM units of SOI six include：
First phase inverter, is made up of the first PMOS transistor and the first nmos pass transistor；
Second phase inverter, is made up of the second PMOS transistor and the second nmos pass transistor；
Pipe is obtained, is made up of the 3rd nmos pass transistor and the 4th nmos pass transistor；The source electrode connection of 3rd NMOS tube
To the output end and the input of second phase inverter of first phase inverter, grid is connected to the wordline of memory, drains
It is connected to the bit line of memory；The source electrode of 4th nmos pass transistor is connected to the output end of second phase inverter and described
The input of first phase inverter, grid is connected to the wordline of memory, and drain electrode is connected to the antiposition line of memory；
Wherein：
It is respectively connected between the source electrode and body area of first, second PMOS transistor and first, second nmos pass transistor
One tunnel-through diode；For PMOS transistor, its source electrode is connected with the anode of the tunnel-through diode, body area and the tunnelling two
The negative electrode connection of pole pipe；For nmos pass transistor, its source electrode is connected with the negative electrode of the tunnel-through diode, body area and the tunnelling
The anode connection of diode.
Alternatively, the tunnel-through diode is formed by connecting by p-type heavy doping anode with N-type heavy doping negative electrode.
Alternatively, for PMOS transistor, p-type heavy doping anode and the PMOS transistor of the tunnel-through diode
P-type heavy doping source region is shared, and the N-type heavy doping negative electrode of the tunnel-through diode is located at the p-type heavy doping source region bottom, and with
The body area of the PMOS transistor is in contact；For nmos pass transistor, the N-type heavy doping negative electrode of the tunnel-through diode with it is described
The N-type heavy doping source region of nmos pass transistor is shared, and the p-type heavy doping anode of the tunnel-through diode is located at the N-type heavy doping
Source region bottom, and be in contact with the body area of the nmos pass transistor.
Alternatively, the p-type heavy doping source region and the N-type heavy doping source region top are each formed with metal silicide.
Alternatively, any one of the metal silicide in cobalt silicide and titanium silicide.
Alternatively, the layer transistor SRAM units of SOI six are using from bottom to top successively including backing bottom, insulating buried layer and top
Between the SOI substrate of layer silicon, active area where each transistor by up and down through the top layer silicon fleet plough groove isolation structure every
From.
Alternatively, it is respectively connected with a tunnel-through diode between the source electrode of the three, the 4th nmos pass transistor and body area.
Alternatively, at least one in the three, the 4th nmos pass transistor uses common grid NMOS tube, T-shaped grid NMOS
Pipe or H type grid NMOS tubes.
The present invention also provides a kind of preparation method of the layer transistor SRAM units of SOI six, comprises the following steps：
S1：There is provided one includes the SOI substrate at backing bottom, insulating buried layer and top layer silicon successively from bottom to top, in the top layer
Fleet plough groove isolation structure is made in silicon, active area is defined；
S2：Position according to the active area makes N traps, the first p-well and the second p-well in the top layer silicon, wherein, institute
N traps are stated to be located between first p-well and the second p-well；
S3：The first PMOS transistor and the second PMOS transistor are made in the N traps；Made in first p-well
First nmos pass transistor and the 3rd nmos pass transistor；The second nmos pass transistor is made in second p-well and the 4th NMOS is brilliant
Body pipe；Wherein, it is all connected between the source electrode and body area of first, second PMOS transistor and first, second nmos pass transistor
There is a tunnel-through diode；For PMOS transistor, its source electrode is connected with the anode of the tunnel-through diode, body area and the tunnelling
The negative electrode connection of diode；For nmos pass transistor, its source electrode is connected with the negative electrode of the tunnel-through diode, body area and the tunnel
Wear the anode connection of diode；
S4：Metallic vias and respective metal line are made, to complete the making of the memory cell.
Alternatively, the tunnel-through diode is formed by connecting by p-type heavy doping anode with N-type heavy doping negative electrode.
Alternatively, for PMOS transistor, p-type heavy doping anode and the PMOS transistor of the tunnel-through diode
P-type heavy doping source region is shared, and the N-type heavy doping negative electrode of the tunnel-through diode is located at the p-type heavy doping source region bottom, and with
The body area of the PMOS transistor is in contact；For nmos pass transistor, the N-type heavy doping negative electrode of the tunnel-through diode with it is described
The N-type heavy doping source region of nmos pass transistor is shared, and the p-type heavy doping anode of the tunnel-through diode is located at the N-type heavy doping
Source region bottom, and be in contact with the body area of the nmos pass transistor.
Alternatively, the step S3 includes step：
S3-1：Form first grid across first p-well and the N traps and the across the N traps and the second p-well
Two grids, and in the first p-well predeterminated position the 3rd grid of formation, in the second p-well predeterminated position the 4th grid of formation；
The first grid is shared by first nmos pass transistor and first PMOS transistor；The second grid is described
Second nmos pass transistor and second PMOS transistor are shared；
S3-2：The first, second p-well predeterminated position carry out N-type be lightly doped, formed described first, second, third and
The shallow n-type area of 4th nmos pass transistor；P-type is carried out in the N traps predeterminated position to be lightly doped, and forms first, second PMOS
The shallow p type island region of transistor；
S3-3：Side wall isolation structure is formed around first, second, third, fourth grid；
S3-4：P-type heavy doping is carried out in the first, second p-well predeterminated position, the p-type heavy doping anode is formed；
The N traps predeterminated position carries out N-type heavy doping, forms the N-type heavy doping negative electrode；
S3-5：The region progress N-type being located in first, second p-well above the p-type heavy doping anode is heavily doped
It is miscellaneous, form the N-type heavy doping source region of first, second nmos pass transistor；It is located at the N-type heavy doping in the N traps cloudy
Region above pole carries out p-type heavy doping, forms the p-type heavy doping source region of first, second PMOS transistor.
Alternatively, in the step S3-4, opening is provided with the first, second p-well predeterminated position using one
Mask plate, ion implanting is vertically carried out via the mask plate, completes the p-type heavy doping or the N-type heavy doping.
Alternatively, the concentration range of the ion implanting is 1E15-9E15/cm2。
Alternatively, in the step S3-4 or step S3-5, it is additionally included in the first, second p-well predeterminated position and enters
The heavy doping of row N-type is to form first, second, third, fourth nmos transistor drain and the three, the 4th NMOS crystal
Pipe source electrode, carries out p-type heavy doping to form the step of first, second PMOS transistor drains in the N traps predeterminated position.
Alternatively, the drain electrode of first nmos pass transistor is shared with the source electrode of the 3rd nmos pass transistor；Described
The drain electrode of bi-NMOS transistor is shared with the source electrode of the 4th nmos pass transistor.
Alternatively, in the step S3, it is additionally included in the p-type heavy doping source region and the N-type heavy doping source region
The step of portion forms metal silicide.
Alternatively, by being formed in the p-type heavy doping source region and the N-type heavy doping source region at metal level, and heat
Reason makes the metal level be reacted with the Si materials under it, generates the metal silicide.
Alternatively, the temperature range of the heat treatment is 700-900 DEG C, and the time is 50-70 seconds.
Alternatively, first nmos pass transistor is interconnected and form the first phase inverter with first PMOS transistor；It is described
Second nmos pass transistor is interconnected and form the second phase inverter with second PMOS transistor；The source electrode connection of 3rd NMOS tube
To the output end and the input of second phase inverter of first phase inverter, grid is connected to the wordline of memory, drains
It is connected to the bit line of memory；The source electrode of 4th nmos pass transistor is connected to the output end of second phase inverter and described
The input of first phase inverter, grid is connected to the wordline of memory, and drain electrode is connected to the antiposition line of memory.
As described above, layer transistor SRAM units of SOI six of the present invention and preparation method thereof, have the advantages that：Institute
State in the layer transistor SRAM units of SOI six, the source electrode of four transistors of the first phase inverter of composition and the second phase inverter is embedded with tunnel
Diode structure is worn, can effectively suppress the floater effect in PD SOI devices in the case of not adding unit area and post
Leakage power consumption and transistor threshold voltage drift that raw triode effect triggers, improve the noise resisting ability of unit.And this hair
The preparation method of the bright layer transistor SRAM units of SOI six also has manufacturing process simple and existing logic process is completely compatible etc.
Centrosymmetric structure is used inside advantage, unit, the influence that process deviation is caused can be reduced, meanwhile, have between unit fine
Shared structure, the effective area of unit can be reduced, it is conveniently formed storage array, and further reduce memory array
Area, is conducive to shortening the cycle of design sram chip.
Brief description of the drawings
Fig. 1 is shown as the circuit theory schematic diagram of the layer transistor SRAM units of SOI six of the present invention.
Fig. 2 is shown as being embedded with the PMOS transistor of tunnel-through diode structure in the layer transistor SRAM units of SOI six of the present invention
Sectional view.
Fig. 3 is shown as being embedded with the nmos pass transistor of tunnel-through diode structure in the layer transistor SRAM units of SOI six of the present invention
Sectional view.
Fig. 4-Fig. 6 is respectively indicated as the overlooking the structure diagram of the nmos pass transistor using common grid, T-shaped grid and H type grid.
Fig. 7-Figure 14 is shown as bowing of being presented of each step in the preparation method of the layer transistor SRAM units of SOI six of the present invention
Depending on structural representation.
Figure 15-Figure 16 is shown as the performance pair of the layer transistor SRAM units of SOI six and conventional floating body unit that the present invention makes
Compare result figure.
Component label instructions
1 first phase inverter
101 first PMOS transistors
102 first nmos pass transistors
2 second phase inverters
201 second PMOS transistors
202 second nmos pass transistors
3 obtain pipe
301 the 3rd nmos pass transistors
302 the 4th nmos pass transistors
4 tunnel-through diodes
41 p-type heavy doping anodes
42 N-type heavy doping negative electrodes
5 are embedded with the PMOS transistor of tunnel-through diode
51 p-type heavy doping source regions
The body area of 52 PMOS transistors
The drain electrode of 53 PMOS transistors
54 shallow p type island regions
6 are embedded with the nmos pass transistor of tunnel-through diode
61 N-type heavy doping source regions
The body area of 62 nmos pass transistors
The drain electrode of 63 nmos pass transistors
64 shallow n-type areas
7 metal silicides
8 backing bottoms
9 insulating buried layers
10 fleet plough groove isolation structures
11 gate dielectric layers
12 polysilicon layers
13 side wall isolation structures
14 common grid
15 T-shaped grid
16 H type grid
17 body contact zones
18 source regions
19 drain regions
20a, 20b, 20c, 20d active area
30 N traps
The p-wells of 40a first
The p-wells of 40b second
50a first grids
50b second grids
The grids of 50c the 3rd
The grids of 50d the 4th
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also be by different specific in addition
Embodiment is embodied or practiced, and the various details in this specification can also not carried on the back based on different viewpoints and application
Various modifications or alterations are carried out under spirit from the present invention.
Fig. 1 is referred to Figure 16.It should be noted that the diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, then in schema only display with relevant component in the present invention rather than according to package count during actual implement
Mesh, shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
The present invention provides a kind of layer transistor SRAM units of SOI six, referring to Fig. 1, being shown as the layer transistor SRAMs of SOI six
The circuit theory schematic diagram of unit, including：
First phase inverter 1, is made up of the first PMOS transistor 101 and the first nmos pass transistor 102；
Second phase inverter 2, is made up of the second PMOS transistor 201 and the second nmos pass transistor 202；
Pipe 3 is obtained, is made up of the 3rd nmos pass transistor 301 and the 4th nmos pass transistor 302；3rd NMOS tube 301
Source electrode be connected to the output end of first phase inverter and the input of second phase inverter, grid is connected to memory
Wordline WL, drain electrode is connected to the bit line BL of memory；It is anti-phase that the source electrode of 4th nmos pass transistor 302 is connected to described second
The input of the output end of device and first phase inverter, grid is connected to the wordline of memory, and drain electrode is connected to memory
Antiposition line BLB.
As an example, the source electrode of the PMOS transistor 201 of the first PMOS transistor 101 and second with power end VDD
Connection, the drain electrode respectively with the nmos pass transistor 202 of the first nmos pass transistor 102 and second that drains is connected, and is used as phase inverter
Output end.The grid of the PMOS transistor 201 of first PMOS transistor 101 and second respectively with the first NMOS crystal
The grid of the nmos pass transistor 202 of pipe 102 and second is connected, and is used as the input of phase inverter.First nmos pass transistor 102 and
The source grounding line GND of second nmos pass transistor 202, to realize the function of the first phase inverter 1 and the second phase inverter 2.In Fig. 1
It also show the first memory node Q and the second memory node QB position.
Particularly, in the phase inverter 2 of the first phase inverter 1 and second, first, second PMOS transistor 101,201
And first, second nmos pass transistor 102,202 source electrode and body area between be respectively connected with a tunnel-through diode 4；It is brilliant for PMOS
Body pipe, its source electrode is connected with the anode of the tunnel-through diode, and body area is connected with the negative electrode of the tunnel-through diode；For NMOS
Transistor, its source electrode is connected with the negative electrode of the tunnel-through diode, and body area is connected with the anode of the tunnel-through diode.
As an example, Fig. 2 and Fig. 3 is referred to, wherein, Fig. 2 is shown as being embedded with the PMOS transistor 5 of tunnel-through diode structure
The sectional view of (first, second PMOS transistor 101,201), Fig. 3 is shown as being embedded with the nmos pass transistor 6 of tunnel-through diode structure
The sectional view of (first, second nmos pass transistor 102,202).As an example, the tunnel-through diode 4 is by p-type heavy doping anode
41 are formed by connecting with N-type heavy doping negative electrode 42.
As an example, the layer transistor SRAM units of SOI six are using from bottom to top successively including backing bottom 8, insulating buried layer 9
And the SOI substrate of top layer silicon, by running through the shallow trench isolation junction of the top layer silicon up and down between active area where each transistor
Structure 10 is isolated.The backing bottom 8 includes but is not limited to the conventional semiconductor substrates such as Si, Ge, and can have the doping of certain type.
In the present embodiment, the backing bottom 8 uses p-type Si substrates, and the insulating buried layer 9 uses silica.
As shown in Fig. 2 for PMOS transistor, the p-type heavy doping anode 41 and PMOS of the tunnel-through diode is brilliant
The p-type heavy doping source region 51 of body pipe is shared, and the N-type heavy doping negative electrode 42 of the tunnel-through diode is located at the p-type heavy-doped source
The bottom of area 51, and be in contact with the body area 52 of the PMOS transistor, meanwhile, the bottom of the N-type heavy doping negative electrode 42 and institute
Insulating buried layer 9 is stated to be in contact.
As shown in figure 3, for nmos pass transistor, the N-type heavy doping negative electrode 42 and NMOS of the tunnel-through diode is brilliant
The N-type heavy doping source region 61 of body pipe is shared, and the p-type heavy doping anode 41 of the tunnel-through diode is located at the N-type heavy-doped source
The bottom of area 61, and be in contact with the body area 62 of the nmos pass transistor, meanwhile, the bottom of the p-type heavy doping anode 41 and institute
Insulating buried layer 9 is stated to be in contact.
Further, the p-type heavy doping source region 51 and the top of N-type heavy doping source region 61 are each formed with metal silication
Thing 7.The metal silicide 7 includes but is not limited to the conductive silicide such as cobalt silicide and titanium silicide, itself and the p-type heavy-doped source
Area 51 or the N-type heavy doping source region 61 formation Ohmic contact.
Drain electrode 53, shallow p type island region 54, grid and the nmos pass transistor of PMOS transistor are also respectively illustrated in Fig. 2 and Fig. 3
Drain electrode 63, shallow n-type area 64, grid.In the present embodiment, the grid of the PMOS transistor and NMOS tube includes gate dielectric layer 11
And it is formed at the polysilicon layer 12 on the gate dielectric layer 11.Side wall isolation structure 13, the side are additionally provided with around the grid
Wall isolation structure 13 covers the shallow p type island region 54 or the part of shallow n-type area 64.In the present embodiment, the PMOS transistor
And the drain electrode of NMOS tube and grid top are also each formed with metal silicide 7, for reduce drain electrode and grid and extraction electrode it
Between contact resistance.
In the layer transistor SRAM units of SOI six of the present invention, four transistors of the first phase inverter of composition and the second phase inverter
Source electrode be embedded with tunnel-through diode structure, wherein, the body area of the first nmos pass transistor and the second nmos pass transistor passes through tunnelling
Diode forward is connected to low level, and the body area of the first PMOS transistor and the second PMOS transistor is reverse by tunnel-through diode
Be connected to high level, the body deriving structure using tunnel-through diode with tunneling characteristics, can not adding unit area feelings
Effectively suppress leakage power consumption and transistor threshold that floater effect and parasitic triode effect in PD SOI devices trigger under condition
Threshold voltage drifts about, and improves the noise resisting ability of unit.
For acquisition pipe 3 the 3rd nmos pass transistor 301 and the 4th nmos pass transistor 302 that are used, its source electrode with
Tunnel-through diode described in one can be respectively connected between body area.It is pointed out that the nmos pass transistor obtained in pipe 3 is embedded
The tunnel-through diode favorably also has disadvantage, can be selected according to specific application.
In another embodiment, but at least one in the 3rd nmos pass transistor 301 and the 4th nmos pass transistor 302
Using common grid NMOS tube, T-shaped grid NMOS tube or H type grid NMOS tubes.As Figure 4-Figure 6, it is respectively indicated as using common grid
14th, the overlooking structure figure of the nmos pass transistor of T-shaped grid 15 and H types grid 16, wherein grid both sides are respectively source region 18 and drain region 19, right
In T-shaped grid NMOS and H type grid nmos pass transistors, also there is body contact zone 17 respectively.Common grid NMOS tube, T-shaped grid NMOS tube and H
Type grid NMOS tube is known in the art, and here is omitted.
Embodiment two
The present invention also provides a kind of preparation method of the layer transistor SRAM units of SOI six, comprises the following steps：
Step S1 is first carried out：There is provided one, the SOI including backing bottom, insulating buried layer and top layer silicon is served as a contrast successively from bottom to top
Bottom, makes fleet plough groove isolation structure in the top layer silicon, defines active area.
As an example, as shown in fig. 7, defining four active areas 20a, 20b, 20c, 20d, this four active areas are put down successively
Row arrangement, each active area surrounding is formed with shallow channel, the shallow channel and constitutes fleet plough groove isolation structure filled with insulating materials.
In the present embodiment, the insulating materials is silica.
Then step S2 is performed：As shown in figure 8, the position according to the active area made in the top layer silicon N traps 30,
First p-well 40a and the second p-well 40b, wherein, the N traps 30 are located between the first p-well 40a and the second p-well 40b.
Specifically, forming the N traps and first, second p-well using ion injection method.As an example, the N traps are used
Phosphonium ion injects, and the p-well is injected using boron ion.The N traps are used to make PMOS transistor, and its subregion is used as PMOS
The body area of transistor；First, second p-well be used for make nmos pass transistor, its subregion as nmos pass transistor body
Area.
Step S3 is performed again：As shown in Fig. 9 to Figure 14, the first PMOS transistor 101 and second is made in the N traps 30
PMOS transistor 201；The first nmos pass transistor 102 and the 3rd nmos pass transistor 301 are made in the first p-well 40a；Institute
State and the second nmos pass transistor 202 and the 4th nmos pass transistor 302 are made in the second p-well 40b；Wherein, dotted line frame is used in Figure 10
Show each transistor region.
Particularly, the source of first, second PMOS transistor 101,201 and first, second nmos pass transistor 201,202
A tunnel-through diode is respectively connected between Ji Yuti areas；For PMOS transistor, the anode of its source electrode and the tunnel-through diode
Connection, body area is connected with the negative electrode of the tunnel-through diode；For nmos pass transistor, the moon of its source electrode and the tunnel-through diode
Pole is connected, and body area is connected with the anode of the tunnel-through diode.
As an example, the tunnel-through diode is formed by connecting by p-type heavy doping anode 41 with N-type heavy doping negative electrode 42.It is right
In PMOS transistor, the p-type heavy doping anode 41 of the tunnel-through diode and the p-type heavy doping source region 51 of the PMOS transistor
Share, the N-type heavy doping negative electrode 42 of the tunnel-through diode is located at the bottom of p-type heavy doping source region 51, and with the PMOS
The body area of transistor is in contact, meanwhile, the bottom of the N-type heavy doping negative electrode 42 is in contact with the insulating buried layer.For
Nmos pass transistor, the N-type heavy doping negative electrode 42 of the tunnel-through diode is total to the N-type heavy doping source region 61 of the nmos pass transistor
With the p-type heavy doping anode 41 of the tunnel-through diode is located at the bottom of N-type heavy doping source region 61, and brilliant with the NMOS
Ti Guanti areas are in contact, meanwhile, the bottom of the p-type heavy doping anode 41 is in contact with the insulating buried layer.
As an example, the step S3 includes step：
S3-1：As shown in figure 9, forming the first grid 50a across the first p-well 40a and the N traps 30 and crossing over institute
The p-well 40b of N traps 30 and second second grid 50b is stated, and the 3rd grid 50c is formed in the first p-well 40a predeterminated positions,
The 4th grid 50d of the second p-well 40b predeterminated positions formation；The first grid 50a is first nmos pass transistor 102
And first PMOS transistor 101 is shared；The second grid 50b is second nmos pass transistor 202 and described the
Two PMOS transistors 201 are shared.
Specifically, described first, second, third, fourth grid 50a, 50b, 50c, 50d include gate dielectric layer and are located at
Polysilicon layer on the gate dielectric layer.
S3-2：As shown in figure 11, carry out N-type in first, second p-well 40a, the 40b predeterminated position to be lightly doped, form institute
State the shallow n-type area of first, second, third, fourth nmos pass transistor 102,202,301,302；Enter in the predeterminated position of N traps 30
Row p-type is lightly doped, and forms the shallow p type island region of first, second PMOS transistor 101,201.
It is pointed out that illustrate only for ease of illustration, in Figure 11 first, second nmos pass transistor 102,
In shallow n-type area 64 and first, second PMOS transistor 101,201 source region regions in 202 source region region
Shallow p type island region 54.
S3-3：As shown in figure 12, formed around described first, second, third, fourth grid 50a, 50b, 50c, 50d
Side wall isolation structure 13.The side wall isolation structure 13 covers the shallow p type island region 54 or the part of shallow n-type area 64.
S3-4：As shown in figure 13, p-type heavy doping is carried out in first, second p-well 40a, the 40b predeterminated position, is formed embedding
Enter the p-type heavy doping anode 64 of the tunnel-through diode of first, second nmos pass transistor 102,202；It is default in the N traps 30
Position carries out N-type heavy doping, and the N-type for forming the tunnel-through diode of embedded first, second PMOS transistor 101,201 is heavily doped
Miscellaneous negative electrode 42.
Specifically, using the mask plate for being provided with opening in the first, second p-well predeterminated position together, via the mask
Version vertically carries out ion implanting, completes the p-type heavy doping or the N-type heavy doping.In the present embodiment, the ion implanting
Concentration range be 1E15-9E15/cm2.By the energy for controlling ion implanting so that ion concentration peak value is close to source transistor
The bottom of area region.
S3-5：As shown in figure 14, it is located in first, second p-well 40a, 40b on the p-type heavy doping anode 41
The region of side carries out N-type heavy doping, forms the N-type heavy doping source region 61 of first, second nmos pass transistor 102,202；
The region for being located at the top of N-type heavy doping negative electrode 42 in the N traps 30 carries out p-type heavy doping, forms described first, second
The p-type heavy doping source region 51 of PMOS transistor 101,201.
Specifically, in the step S3-4 or step S3-5, being additionally included in first, second p-well 40a, 40b and presetting
Position carry out N-type heavy doping with formed first, second, third, fourth nmos pass transistor 102,202,301,302 drain electrode and
Three, the 4th nmos pass transistor 301,302 source electrodes, carry out p-type heavy doping described to be formed in the predeterminated position of N traps 30
The step of first, second PMOS transistor 101,201 drains.
In the present embodiment, the drain electrode of first nmos pass transistor 102 is total to the source electrode of the 3rd nmos pass transistor 301
With；The drain electrode of second nmos pass transistor 302 is shared with the source electrode of the 4th nmos pass transistor 202.
Further, in this step, it is additionally included in the p-type heavy doping source region 51 and the N-type heavy doping source region 61
The step of portion forms metal silicide (is unillustrated).
Specifically, by forming metal level in the p-type heavy doping source region 51 and the N-type heavy doping source region 61, and
Heat treatment makes the metal level be reacted with the Si materials under it, generates the metal silicide.In the present embodiment, the heat treatment
Temperature range be 700-900 DEG C, the time be 50-70 seconds.
Specifically, forming metal silicide in the p-type heavy doping source region 51 and the top of N-type heavy doping source region 61
At the same time it can also in the drain electrode of first, second PMOS transistor 101,201 and first, second nmos pass transistor 102,202
Metal silicide is formed with grid top, and on the source-drain electrode and grid of the three, the 4th nmos pass transistor 301,302
Portion forms metal silicide, to reduce the contact resistance between source-drain electrode and grid and extraction electrode.
Finally perform step S4：Metallic vias and respective metal line are made, to complete the making of the memory cell.
Specifically, to be interconnected and form first with first PMOS transistor 101 anti-phase for first nmos pass transistor 102
Device；Second nmos pass transistor 202 is interconnected and form the second phase inverter with second PMOS transistor 201；Described 3rd
The source electrode of NMOS tube 301 is connected to the output end of first phase inverter and the input of second phase inverter, grid connection
To the wordline of memory, drain electrode is connected to the bit line of memory；The source electrode of 4th nmos pass transistor 302 is connected to described
The input of the output end of two phase inverters and first phase inverter, grid is connected to the wordline of memory, and drain electrode, which is connected to, deposits
The antiposition line of reservoir.
So far, the making of the layer transistor SRAM units of SOI six is completed.The layer transistor SRAM units of SOI six of the present invention
Preparation method have the advantages that manufacturing process is simple, completely compatible with existing logic process, unit inside uses Central Symmetry
Structure, can reduce the influence that process deviation is caused, meanwhile, there is good shared structure between unit, having for unit can be reduced
Area is imitated, it is conveniently formed storage array, and further reduce memory array area, it is adaptable to harsh to cellar area,
The occasions such as low-power consumption.
In order to verify the performance for the layer transistor SRAM units of SOI six that the present invention makes, enter in 130nm SOI CMOS technologies
Row flow, experimental result is as shown in Figure 15,16；Known by Figure 15 drain current versus, conventional floating body unit and the SOI of the present invention
The quiescent dissipation of six layer transistor SRAM units is respectively 191pA and 88pA, therefore the layer transistor SRAM units of SOI six of the present invention are relative
54% is reduced in conventional floating body unit quiescent dissipation；In addition, passing through Figure 16 comparison unit butterfly diagram results, conventional floating body list
The corresponding static noise margin value of member is 199mV, and the static noise margin value of the layer transistor SRAM units of SOI six of the present invention is
250mV, therefore the layer transistor SRAM units of SOI six of the present invention improve 25% relative to conventional floating body unit crystal noise margin values,
I.e. unit noise resisting ability improves 25%.
In summary, in the layer transistor SRAM units of SOI six of the invention, the four of the first phase inverter and the second phase inverter are constituted
The source electrode of individual transistor is embedded with tunnel-through diode structure, effectively can suppress PD SOI in the case where not increasing device area
Leakage power consumption and transistor threshold voltage drift that floater effect and parasitic triode effect in device trigger, improve unit
Noise resisting ability.And the preparation method of the layer transistor SRAM units of SOI six of the present invention also have manufacturing process it is simple, with it is existing
Centrosymmetric structure is used inside the advantages of logic process is completely compatible, unit, the influence that process deviation is caused can be reduced, together
When, there is between unit good shared structure, the effective area of unit can be reduced, it is conveniently formed storage array, one is gone forward side by side
Step reduces memory array area, is conducive to shortening the cycle of design sram chip.So, the present invention effectively overcomes existing skill
Various shortcoming in art and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (20)
1. a kind of layer transistor SRAM units of SOI six, the layer transistor SRAM units of SOI six include：
First phase inverter, is made up of the first PMOS transistor and the first nmos pass transistor；
Second phase inverter, is made up of the second PMOS transistor and the second nmos pass transistor；
Pipe is obtained, is made up of the 3rd nmos pass transistor and the 4th nmos pass transistor；
Wherein, the source electrode of the 3rd NMOS tube be connected to first phase inverter output end and second phase inverter it is defeated
Enter end, grid is connected to the wordline of memory, and drain electrode is connected to the bit line of memory；
The source electrode of 4th nmos pass transistor be connected to second phase inverter output end and first phase inverter it is defeated
Enter end, grid is connected to the wordline of memory, and drain electrode is connected to the antiposition line of memory；
It is characterized in that：
A tunnel is respectively connected between the source electrode and body area of first, second PMOS transistor and first, second nmos pass transistor
Wear diode；For PMOS transistor, its source electrode is connected with the anode of the tunnel-through diode, body area and the tunnel-through diode
Negative electrode connection；For nmos pass transistor, its source electrode is connected with the negative electrode of the tunnel-through diode, body area and the pole of tunnelling two
The anode connection of pipe.
2. the layer transistor SRAM units of SOI six according to claim 1, it is characterised in that：The tunnel-through diode is by p-type weight
Doping anode is formed by connecting with N-type heavy doping negative electrode.
3. the layer transistor SRAM units of SOI six according to claim 2, it is characterised in that：For PMOS transistor, the tunnel
Wear the p-type heavy doping anode of diode to share with the p-type heavy doping source region of the PMOS transistor, the N of the tunnel-through diode
Type heavy doping negative electrode is located at the p-type heavy doping source region bottom, and is in contact with the body area of the PMOS transistor；For NMOS
Transistor, the N-type heavy doping negative electrode of the tunnel-through diode is shared with the N-type heavy doping source region of the nmos pass transistor, described
The p-type heavy doping anode of tunnel-through diode be located at the N-type heavy doping source region bottom, and with the body area phase of the nmos pass transistor
Contact.
4. the layer transistor SRAM units of SOI six according to claim 3, it is characterised in that：The p-type heavy doping source region and institute
State N-type heavy doping source region top and be each formed with metal silicide.
5. the layer transistor SRAM units of SOI six according to claim 4, it is characterised in that：The metal silicide is selected from silicon
Change any one in cobalt and titanium silicide.
6. the layer transistor SRAM units of SOI six according to claim 1, it is characterised in that：The layer transistor SRAM lists of SOI six
Member is used includes the SOI substrate at backing bottom, insulating buried layer and top layer silicon successively from bottom to top, between active area where each transistor
Isolated by the fleet plough groove isolation structure up and down through the top layer silicon.
7. the layer transistor SRAM units of SOI six according to claim 1, it is characterised in that：Three, the 4th NMOS crystal
A tunnel-through diode is respectively connected between the source electrode of pipe and body area.
8. the layer transistor SRAM units of SOI six according to claim 1, it is characterised in that：Three, the 4th NMOS crystal
At least one in pipe uses common grid NMOS tube, T-shaped grid NMOS tube or H type grid NMOS tubes.
9. a kind of preparation method of the layer transistor SRAM units of SOI six, it is characterised in that comprise the following steps：
S1：There is provided one includes the SOI substrate at backing bottom, insulating buried layer and top layer silicon successively from bottom to top, in the top layer silicon
Fleet plough groove isolation structure is made, active area is defined；
S2：Position according to the active area makes N traps, the first p-well and the second p-well in the top layer silicon, wherein, the N
Trap is located between first p-well and the second p-well；
S3：The first PMOS transistor and the second PMOS transistor are made in the N traps；First is made in first p-well
Nmos pass transistor and the 3rd nmos pass transistor；The second nmos pass transistor and the 4th nmos pass transistor are made in second p-well；
Wherein, it is respectively connected with a tunnel between the source electrode and body area of first, second PMOS transistor and first, second nmos pass transistor
Wear diode；For PMOS transistor, its source electrode is connected with the anode of the tunnel-through diode, body area and the tunnel-through diode
Negative electrode connection；For nmos pass transistor, its source electrode is connected with the negative electrode of the tunnel-through diode, body area and the pole of tunnelling two
The anode connection of pipe；
S4：Metallic vias and respective metal line are made, to complete the making of the memory cell.
10. the preparation method of the layer transistor SRAM units of SOI six according to claim 10, it is characterised in that：The tunnelling
Diode is formed by connecting by p-type heavy doping anode with N-type heavy doping negative electrode.
11. the preparation method of the layer transistor SRAM units of SOI six according to claim 10, it is characterised in that：For PMOS
Transistor, the p-type heavy doping anode of the tunnel-through diode is shared with the p-type heavy doping source region of the PMOS transistor, described
The N-type heavy doping negative electrode of tunnel-through diode be located at the p-type heavy doping source region bottom, and with the body area phase of the PMOS transistor
Contact；For nmos pass transistor, the N-type heavy doping negative electrode of the tunnel-through diode and the N-type heavy doping of the nmos pass transistor
Source region is shared, and the p-type heavy doping anode of the tunnel-through diode is located at the N-type heavy doping source region bottom, and with the NMOS
The body area of transistor is in contact.
12. the preparation method of the layer transistor SRAM units of SOI six according to claim 11, it is characterised in that：The step
S3 includes step：
S3-1：Form the first grid across first p-well and the N traps and cross over the N traps and the second gate of the second p-well
Pole, and in the first p-well predeterminated position the 3rd grid of formation, in the second p-well predeterminated position the 4th grid of formation；It is described
First grid is shared by first nmos pass transistor and first PMOS transistor；The second grid is described second
Nmos pass transistor and second PMOS transistor are shared；
S3-2：N-type is carried out in the first, second p-well predeterminated position to be lightly doped, and forms described first, second, third and the 4th
The shallow n-type area of nmos pass transistor；P-type is carried out in the N traps predeterminated position to be lightly doped, and forms the first, second PMOS crystal
The shallow p type island region of pipe；
S3-3：Side wall isolation structure is formed around first, second, third, fourth grid；
S3-4：P-type heavy doping is carried out in the first, second p-well predeterminated position, the p-type heavy doping anode is formed；Described
N traps predeterminated position carries out N-type heavy doping, forms the N-type heavy doping negative electrode；
S3-5：It is located at the region above the p-type heavy doping anode in first, second p-well and carries out N-type heavy doping, shape
Into the N-type heavy doping source region of first, second nmos pass transistor；It is located in the N traps above the N-type heavy doping negative electrode
Region carry out p-type heavy doping, form the p-type heavy doping source region of first, second PMOS transistor.
13. the preparation method of the layer transistor SRAM units of SOI six according to claim 12, it is characterised in that：In the step
It is vertical via the mask plate using the mask plate for being provided with opening in the first, second p-well predeterminated position together in rapid S3-4
Ground carries out ion implanting, completes the p-type heavy doping or the N-type heavy doping.
14. the preparation method of the layer transistor SRAM units of SOI six according to claim 13, it is characterised in that：The ion
The concentration range of injection is 1E15-9E15/cm2。
15. the preparation method of the layer transistor SRAM units of SOI six according to claim 12, it is characterised in that：In the step
In rapid S3-4 or step S3-5, it is additionally included in the first, second p-well predeterminated position and carries out N-type heavy doping to form described the
First, second, third, the 4th nmos transistor drain and the three, the 4th nmos pass transistor source electrode, preset position in the N traps
Progress p-type heavy doping is put to form the step of first, second PMOS transistor drains.
16. the preparation method of the layer transistor SRAM units of SOI six according to claim 15, it is characterised in that：Described first
The drain electrode of nmos pass transistor is shared with the source electrode of the 3rd nmos pass transistor；The drain electrode of second nmos pass transistor with it is described
The source electrode of 4th nmos pass transistor is shared.
17. the preparation method of the layer transistor SRAM units of SOI six according to claim 11, it is characterised in that：In the step
In rapid S3, the step of being additionally included in the p-type heavy doping source region and N-type heavy doping source region top formation metal silicide.
18. the preparation method of the layer transistor SRAM units of SOI six according to claim 17, it is characterised in that：By institute
State and metal level is formed in p-type heavy doping source region and the N-type heavy doping source region, and heat treatment makes the metal level and the Si under it
Material reacts, and generates the metal silicide.
19. the preparation method of the layer transistor SRAM units of SOI six according to claim 18, it is characterised in that：At the heat
The temperature range of reason is 700-900 DEG C, and the time is 50-70 seconds.
20. the preparation method of the layer transistor SRAM units of SOI six according to claim 9, it is characterised in that：Described first
Nmos pass transistor is interconnected and form the first phase inverter with first PMOS transistor；Second nmos pass transistor and described second
PMOS transistor is interconnected and form the second phase inverter；The source electrode of 3rd NMOS tube is connected to the output end of first phase inverter
And the input of second phase inverter, grid is connected to the wordline of memory, and drain electrode is connected to the bit line of memory；Described
The source electrode of four nmos pass transistors is connected to the output end of second phase inverter and the input of first phase inverter, and grid connects
The wordline of memory is connected to, drain electrode is connected to the antiposition line of memory.
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| CN109461732A (en) * | 2018-10-18 | 2019-03-12 | 中国科学院上海微系统与信息技术研究所 | Static ram cell and preparation method thereof |
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| US20110006379A1 (en) * | 2009-07-07 | 2011-01-13 | Fujitsu Semiconductor Limited | Semiconductor device and manufacturing method thereof |
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| CN101159256A (en) * | 2006-10-04 | 2008-04-09 | 国际商业机器公司 | Sub-lithographic local interconnects, and methods for forming same |
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