CN109461732A - Static ram cell and preparation method thereof - Google Patents
Static ram cell and preparation method thereof Download PDFInfo
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- CN109461732A CN109461732A CN201811212888.XA CN201811212888A CN109461732A CN 109461732 A CN109461732 A CN 109461732A CN 201811212888 A CN201811212888 A CN 201811212888A CN 109461732 A CN109461732 A CN 109461732A
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- nmos
- trombone slide
- pmos
- access pipe
- heavy doping
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present invention provides a kind of static ram cell and preparation method thereof, pulls up transistor and is embedded with tunnel-through diode structure with the source electrode of pull-down transistor, can (final effective cellar area is smaller than 7.5 μm in the case where not increasing device area2) the leakage power consumption and transistor threshold voltage of the floater effect in PDSOI device and the initiation of parasitic triode effect is effectively inhibited to drift about, improve the noise resisting ability of unit.And the production method of six layer transistor SRAM unit of SOI of the invention also has many advantages, such as that manufacturing process is simple, completely compatible with existing logic process, using the shared structure between centrosymmetric structure and unit inside unit, make it facilitate to form storage array, is conducive to the period for shortening design sram chip.
Description
Technical field
The present invention relates to reservoir designs and production fields, more particularly to a kind of static ram cell and its production
Method.
Background technique
With the development of semiconductor technology, the size of transistor comes into deep-submicron, the answering property of scale of memory module
The requirement of energy constantly expands.In the bad environments of avionics equipment work, memory cell endures the spoke of various high energy particles to the fullest extent
It penetrates, and storage unit is more sensitive to high particle radiation.Traditional memory cell is generally difficult to meet anti-radiation requirement, so
Designer is usually improved on the basis of conventional elements, to improve the capability of resistance to radiation of unit.
Single particle effect and total dose effect be in radiation effect it is most common be also most important two kinds.
Single particle effect, which refers to, to be incident on sensitive volume by high energy particle (for body silicon device, sensitive volume refers to its drain terminal
Reverse biased pn junction；And for SOI device, refer to the area device closed state Shi Ti) when, the energy quilt of particle
Silicon materials absorb, and according to band theory of solid, the electronics for being in valence band can obtain energy jump to conduction band, corresponding hole
Then transit to the position of higher energy downwards in valence band, such electrons and holes are all at free-moving carrier；Due to
Surrounding voltages apply the presence of electric field, so that free-moving carrier does displacement, form electric current, but the longevity of carrier
Order it is limited, so finally formed electric current is transient current；Transient current causes voltage drop in the circuit in unit, so that institute
The data of storage change, and this effect for causing storage unit that logic error occurs due to single particle is called single-particle effect
It answers.
There are many method that single-particle is reinforced, and most of thinking is exactly to extend the time of feedback loop, reduce single-particle and make
At influence；As added resistance or addition capacitor in the loop, there are also the circuits RC that addition resistance and capacitor are constituted.
Although introducing the passive devices such as resistance or capacitor in the memory unit, anti-single particle effect can be improved,
The resistance value of resistance and the capacitance order of magnitude of capacitor are larger, it must produce resistance and capacitor using additional technique；Moreover,
Even if being manufactured that these passive devices, but its area is also that storage unit is intolerable, and for sram cell, it is
Fatal influence.
SOI technology is since the invention eighties in last century, it is relative to common bulk silicon technological, the small, function with parasitic capacitance
Anti-single particle latch (Single-Event-Latchup, SEL) ability low, that speed is fast and natural is consumed, so that SOI technology is very suitable
Together in work in system on chip (System-on-Chips, SoC), low-power consumption and the occasions such as anti-radiation；In addition, static random
It is slow that memory (StaticRandomAccessMemory, SRAM) is widely used in consumer electronics, automotive electronics, processor level-one
Deposit in L2 cache；So SOI technology is applied in SRAM design, there is some superiority.
According to the degree of exhaustion in metal-oxide-semiconductor body area, SOI can further be divided into fully- depleted (Full-Depleted, FD) SOI and
Part depletion (Partially-Depleted, PD) SOI.For part depletion SOI technology, due to its body area of metal-oxide-semiconductor and source region
It electrically separates, it is hanging for leading to body area；In normal work, drain potentials are higher, and the electronics of inversion channel is transported from source electrode
When moving drain electrode, by electric field acceleration, when moving to by close to leakage body knot, at this time because electric field is most strong, electronics is obtained additionally
Energy, and collide to form electron-hole pair with the atom on lattice；Velocity of electrons is fast, is added in a short period of time
Speed arrives drain electrode；However cavity speed is relatively slow, and the low potentials such as body area, source region region is slowly moved to along direction of an electric field, moves
The hole in the area Dong Daoti be easy to the electronics provided by source electrode carry out it is compound fall, and when being moved to body area, due to its potential floating
So that hole accumulates gradually in body area, the threshold voltage of metal-oxide-semiconductor directly will affect, so that metal-oxide-semiconductor performance be made to change, this is just
It is floater effect.In addition, there are also parasitic triode effects in PD SOI metal-oxide-semiconductor, refer to source electrode, body area and the drain electrode of metal-oxide-semiconductor
Respectively N, P and N, similar to emitter, base stage and the collector in triode, that is, parasitic one of metal-oxide-semiconductor is naturally
NPN triode；This base stage is hanging.Generally, when base stage does not have positive charge, potential is identical as transmitting electrode potential,
Therefore its triode does not turn on；If floater effect occurs, when base stage positive charge is accumulated to a certain extent, base stage and transmitting electrode potential
When reaching a certain level, triode can be connected, the phenomenon that drain electrode can generate high current.Floater effect and parasitic triode effect
The performance change of PD SOI sram cell should be will cause, such as electric leakage increases, noise resisting ability reduces.
Currently used static random access memory cell mainly uses six transistor types, by two pull-up P-type transistors,
Two drop-down N-type transistors and two transmission gate N-type transistors are constituted, and wordline controls the switch of two transmission gate N-type transistors,
Storing data is written or read by bit line, wherein this six transistors are all made of common metal-oxide-semiconductor.
Generally, due to floater effect and parasitic triode effect in PD SOI metal-oxide-semiconductor, designer usually can be by metal-oxide-semiconductor
Body area extracts that (NMOS body area is connected to low potential, that is, is shorted with source region potential；PMOS body area is connected to high level), by potential
It is kept fixed to inhibit the two effect；Common body contact is exactly T- type grid metal-oxide-semiconductor and H- type grid metal-oxide-semiconductor, but this and phase
Compared with the non-body of size contacts metal-oxide-semiconductor, area can be higher by very much.If T- type metal-oxide-semiconductor is directly applied to sram cell
In the middle, cellar area will increase 1 times or so, even more (applying H- type grid).
Therefore, how a kind of static ram cell and preparation method thereof is provided, sram cell key can be not only extended
The feedback time that memory node disturbs external high energy, and can effectively inhibit under the premise of minimizing chip area
The floater effect of metal-oxide-semiconductor, parasitic triode effect, thus enhance six-transistor static random access memory unit stability and
Low leakage power consumption is dropped, those skilled in the art's important technological problems urgently to be resolved are become.
Summary of the invention
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of static ram cell and
Its production method, for extending the sram cell critical storage node feedback of sram cell for external disturbance in hold mode
Time improves the stability of storage unit, while sram cell area occupied is larger in the prior art, stability is poor, leakage for solution
The problem that power consumption is high and noise resisting ability is weak.
In order to achieve the above objects and other related objects, the present invention provides a kind of static ram cell, the static state
Random memory unit includes at least:
Trombone slide on first PMOS, trombone slide, the first NMOS under trombone slide, the 2nd NMOS under trombone slide, the first NMOS on the 2nd PMOS
Access pipe, the 2nd NMOS access pipe, the 3rd NMOS access pipe and the 4th NMOS access pipe；
The grid of trombone slide is connected with the drain electrode of trombone slide on the 2nd PMOS on first PMOS, the first PMOS
The drain electrode of upper trombone slide is connected with the grid of trombone slide on the 2nd PMOS, the source electrode and described second of trombone slide on the first PMOS
The source electrode of the upper trombone slide of PMOS connects high level；
The grid of trombone slide is connected with the source electrode of the 2nd NMOS access pipe under first NMOS, the first NMOS
The drain electrode of lower trombone slide is connected with the drain electrode of trombone slide on the first PMOS, the first NMOS source electrode for accessing pipe, and described second
The source electrode of the grid of trombone slide and the 3rd NMOS access pipe is connected under NMOS, under the 2nd NMOS drain electrode of trombone slide with it is described
The drain electrode of trombone slide on 2nd PMOS, the 4th NMOS access pipe source electrode be connected, under the first NMOS source electrode of trombone slide and
The source electrode of trombone slide connects low level under 2nd NMOS；
The source electrode of the first NMOS access pipe is connected with the drain electrode of the 3rd NMOS access pipe, the first NMOS
The bit line of the drain electrode connection storage unit of pipe is accessed, the leakage of trombone slide on the source electrode and the first PMOS of the first NMOS access pipe
The drain electrode of trombone slide, which is connected, under pole, the first NMOS constitutes the first memory node, the grid and second of the first NMOS access pipe
The grid of NMOS access pipe is controlled by wordline；
The source electrode of the 4th NMOS access pipe is connected with the drain electrode of the 2nd NMOS access pipe, the 4th NMOS
The antiposition line of the drain electrode connection storage unit of pipe is accessed, the leakage of trombone slide on the source electrode and the 2nd PMOS of the 4th NMOS access pipe
The drain electrode of trombone slide, which is connected, under pole, the 2nd NMOS constitutes the second memory node, the grid and the 4th of the 3rd NMOS access pipe
The grid of NMOS access pipe is controlled by wordline；
Wherein, trombone slide on the first PMOS, trombone slide and described second under trombone slide, the first NMOS on the 2nd PMOS
A tunnel-through diode is respectively connected under NMOS between the source electrode of trombone slide and body area；For PMOS transistor, source electrode and the tunnel
The anode connection of diode is worn, body area is connect with the cathode of the tunnel-through diode；For NMOS transistor, source electrode with it is described
The cathode of tunnel-through diode connects, and body area is connect with the anode of the tunnel-through diode.
Optionally, the tunnel-through diode is formed by connecting by p-type heavy doping anode and N-type heavy doping cathode.
More optionally, for trombone slide on PMOS, p-type heavy doping anode and the trombone slide on the PMOS of the tunnel-through diode
P-type heavy doping source region share, the N-type heavy doping cathode of the tunnel-through diode is located at the p-type heavy doping source region bottom, and
It is in contact with the body area of trombone slide on the PMOS；For trombone slide under NMOS, the N-type heavy doping cathode of the tunnel-through diode and institute
The N-type heavy doping source region for stating trombone slide under NMOS shares, and it is heavily doped that the p-type heavy doping anode of the tunnel-through diode is located at the N-type
Miscellaneous source region bottom, and be in contact with the body area of trombone slide under the NMOS.
More optionally, the p-type heavy doping source region and the N-type heavy doping body contact zone top are formed with metal silication
Object.
More optionally, any one of the metal silicide in cobalt silicide and titanium silicide.
More optionally, the static ram cell is using from bottom to top successively including backing bottom, insulating buried layer and top
The SOI substrate of layer silicon, where each transistor between active area by up and down through the fleet plough groove isolation structure of the top layer silicon every
From.
More optionally, the first NMOS access pipe, the 2nd NMOS access pipe, the 3rd NMOS access pipe and institute
The 4th NMOS access pipe is stated using the combination of one or more of common grid NMOS tube, T-type grid NMOS tube or H-type grid NMOS tube.
In order to achieve the above objects and other related objects, the present invention also provides a kind of production sides of static ram cell
The production method of method, the static ram cell includes at least:
1) one is provided from bottom to top successively including the SOI substrate at backing bottom, insulating buried layer and top layer silicon, in the top layer silicon
Middle production fleet plough groove isolation structure, defines active area；
2) N trap, the first p-well and the second p-well are made in the top layer silicon according to the position of the active area, wherein institute
N trap is stated between first p-well and the second p-well；
3) trombone slide on trombone slide and the 2nd PMOS is made on the first PMOS in the N trap；Is made in first p-well
Trombone slide, the first NMOS access pipe and the 2nd NMOS access pipe under one NMOS；The 2nd NMOS drop-down is made in second p-well
Pipe, the 3rd NMOS access pipe and the 4th NMOS access pipe；Wherein, trombone slide on the first PMOS, trombone slide on the 2nd PMOS,
A tunnel-through diode is respectively connected between the source electrode and body area of trombone slide under trombone slide and the 2nd NMOS under first NMOS；It is right
In trombone slide on PMOS, source electrode is connect with the anode of the tunnel-through diode, and body area is connect with the cathode of the tunnel-through diode；
For trombone slide under NMOS, source electrode is connect with the cathode of the tunnel-through diode, and the anode of body area and the tunnel-through diode connects
It connects；
4) metallic vias and respective metal line are made, to complete the production of the static ram cell.
More optionally, the tunnel-through diode is formed by connecting by p-type heavy doping anode and N-type heavy doping cathode.
More optionally, for trombone slide on PMOS, p-type heavy doping anode and the trombone slide on the PMOS of the tunnel-through diode
P-type heavy doping source region share, the N-type heavy doping cathode of the tunnel-through diode is located at the p-type heavy doping source region bottom, and
It is in contact with the body area of the PMOS transistor；For trombone slide under NMOS, the N-type heavy doping cathode of the tunnel-through diode and institute
The N-type heavy doping source region for stating trombone slide under NMOS shares, and it is heavily doped that the p-type heavy doping anode of the tunnel-through diode is located at the N-type
Miscellaneous source region bottom, and be in contact with the body area of trombone slide under the NMOS.
Optionally, the step 3) comprising steps of
31) trombone slide on the grid and the 2nd PMOS of trombone slide is formed on the first PMOS in the N trap predeterminated position
Grid, the grid of trombone slide in the case where the first p-well predeterminated position forms the first NMOS, and default in second p-well
Position forms the grid of trombone slide under the 2nd NMOS；
32) N-type is carried out in first p-well and the second p-well predeterminated position to be lightly doped, form the first NMOS
Trombone slide, the first NMOS access pipe, the 2nd NMOS access pipe, the 3rd NMOS under lower trombone slide, the 2nd NMOS
The shallow n-type area of access pipe and the 4th NMOS access pipe；P-type is carried out in the N trap predeterminated position to be lightly doped, and forms described the
On one PMOS on trombone slide and the 2nd PMOS trombone slide shallow p type island region；
33) on the first PMOS grid of trombone slide, on the 2nd PMOS trombone slide grid, the first NMOS
Side wall isolation structure is formed under the grid of lower trombone slide and the 2nd NMOS around the grid of trombone slide；
34) it is located at the region above the p-type heavy doping anode in first p-well and second p-well and carries out N-type
Heavy doping forms the N-type heavy doping source region of trombone slide under first, second NMOS；It is heavily doped to be located at the N-type in the N trap
Region above miscellaneous cathode carries out p-type heavy doping, forms the p-type heavy doping source region of trombone slide on first, second PMOS.
Optionally, in Yu Suoshu step 34), using the covering equipped with opening in the first, second p-well predeterminated position together
Film version vertically carries out ion implanting via the mask plate, completes the p-type heavy doping or the N-type heavy doping.
More optionally, the concentration range of the ion implanting is 1E15-9E15/cm2。
It more optionally, further include pre- in first p-well and second p-well in Yu Suoshu step 34) or step 35)
If position carries out N-type heavy doping to form under the first NMOS trombone slide, the first NMOS under trombone slide, the 2nd NMOS
The drain electrode of access pipe, the 2nd NMOS access pipe, the 3rd NMOS access pipe and the 4th NMOS access pipe, Yi Jisuo
State the first NMOS access pipe, the 2nd NMOS access pipe, the 3rd NMOS access pipe and the 4th NMOS access pipe
Source electrode carries out p-type heavy doping in the N trap predeterminated position to form the step of trombone slide drains under first, second PMOS.
It optionally, further include in the p-type heavy doping source region and the N-type heavy doping source region in Yu Suoshu step 3)
Portion forms the step of metal silicide.
Optionally, by forming metal layer in the p-type heavy doping source region and the N-type heavy doping source region, and at heat
Reason reacts the metal layer with the Si material under it, generates the metal silicide.
More optionally, the temperature range of the heat treatment is 700-900 DEG C, and the time is 50-70 seconds.
More optionally, the grid of trombone slide is connected with the drain electrode of trombone slide on the 2nd PMOS on the first PMOS, described
The drain electrode of trombone slide is connected with the grid of trombone slide on the 2nd PMOS on first PMOS, on the first PMOS source electrode of trombone slide and
The source electrode of trombone slide connects high level on 2nd PMOS；
The grid of trombone slide is connected with the source electrode of the second access pipe under first NMOS, trombone slide under the first NMOS
Drain electrode be connected with the drain electrode of trombone slide on the first PMOS, the first NMOS source electrode for accessing pipe, under the 2nd NMOS
The grid of trombone slide is connected with the source electrode of the 3rd NMOS access pipe, the drain electrode and described second of trombone slide under the 2nd NMOS
The drain electrode of the upper trombone slide of PMOS, the 4th NMOS access pipe source electrode be connected, the source electrode of trombone slide and described under the first NMOS
The source electrode of trombone slide connects low level under 2nd NMOS；
The source electrode of the first NMOS access pipe is connected with the drain electrode of the 3rd NMOS access pipe, the first NMOS access pipe
Drain electrode connection storage unit bit line, the grid of the first NMOS access pipe and the grid of the 2nd NMOS access pipe are equal
It is controlled by wordline；
The source electrode of the 4th NMOS access pipe is connected with the drain electrode of the 2nd NMOS access pipe, the leakage of the 4th access pipe
Pole connects the antiposition line of storage unit, the grid of the grid of the 3rd NMOS access pipe and the 4th NMOS access pipe by
Wordline control.
As described above, static ram cell and preparation method thereof of the invention, has the advantages that
It pulls up transistor in static ram cell of the invention and is embedded with two pole of tunnelling with the source electrode of pull-down transistor
Pipe structure, can (final effective cellar area be smaller than 7.5 μm in the case where not increasing device area2) effectively inhibit
The leakage power consumption and transistor threshold voltage drift that floater effect and parasitic triode effect in PDSOI device cause, mention
The noise resisting ability of high unit；And the production method of static ram cell of the invention do not introduce extra mask plate, with
Existing logic process is completely compatible, and centrosymmetric structure is used inside unit, not only contributes to the size and threshold voltage of metal-oxide-semiconductor
Deng matching, also helps to form array, facilitate full custom sram chip.
Detailed description of the invention
Fig. 1 is shown as the circuit theory schematic diagram of static ram cell of the invention.
Fig. 2 is shown as cuing open for the PMOS transistor in static ram cell of the invention embedded with tunnel-through diode structure
View.
Fig. 3 is shown as cuing open for the NMOS transistor in static ram cell of the invention embedded with tunnel-through diode structure
View.
Fig. 4~Fig. 6 is respectively indicated as the plan structure signal of the NMOS transistor using common grid, T-type grid H-type grid
Figure.
Fig. 7-Figure 12 is shown as the vertical view that each step is presented in the production method of static ram cell of the invention
Structural schematic diagram.
Component label instructions
Trombone slide on 101 the oneth PMOS
Trombone slide under 102 the oneth NMOS
Trombone slide on 201 the 2nd PMOS
Trombone slide under 202 the 2nd NMOS
301~304 the first~the 4th NMOS access pipe
4 tunnel-through diodes
41 p-type heavy doping anodes
42 N-type heavy doping cathodes
5 are embedded with the PMOS transistor of tunnel-through diode
51 p-type heavy doping source regions
The body area of 52 PMOS transistors
The drain electrode of 53 PMOS transistors
54 shallow p type island regions
6 are embedded with the NMOS transistor of tunnel-through diode
61 N-type heavy doping source regions
The body area of 62 NMOS transistors
The drain electrode of 63 NMOS transistors
64 shallow n-type areas
7 metal silicides
8 backing bottoms
9 insulating buried layers
10 fleet plough groove isolation structures
11 gate dielectric layers
12 polysilicon layers
13 side wall isolation structures
14 common grid
15 T-type grid
16 H-type grid
17 body contact zones
18 source regions
19 drain regions
20a, 20b, 20c, 20d active area
30 N traps
40 first p-wells, the first p-well predeterminated position
50 second p-wells
60a first grid
60b second grid
60c third grid
The 4th grid of 60d
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from
Various modifications or alterations are carried out under spirit of the invention.
Please refer to Fig. 1~Figure 12.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way
The basic conception of invention, only shown in schema then with related component in the present invention rather than package count when according to actual implementation
Mesh, shape and size are drawn, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its
Assembly layout kenel may also be increasingly complex.
Embodiment one
The present invention provides a kind of static ram cell, and uses eight transistors, referring to Fig. 1, being shown as described
The circuit theory schematic diagram of static ram cell, comprising:
Trombone slide 101 on first PMOS, trombone slide under trombone slide 102, the 2nd NMOS under trombone slide 201, the first NMOS on the 2nd PMOS
202, the first NMOS accesses pipe 301, the 2nd NMOS access pipe 302, the 3rd NMOS access pipe 303 and the 4th NMOS and accesses pipe 304.
Specifically, the grid of trombone slide 101 is connected with the drain electrode of trombone slide 201 on the 2nd PMOS on the first PMOS,
The drain electrode of trombone slide 101 is connected with the grid of trombone slide 201 on the 2nd PMOS on first PMOS, on the first PMOS
The source electrode of trombone slide 201 meets high level VDD on the source electrode of trombone slide 101 and the 2nd PMOS；
The grid of trombone slide 102 is connected with the source electrode of the 2nd NMOS access pipe 302 under first NMOS, and first
The drain electrode of trombone slide 102 accesses the source electrode of pipe 301 with the drain electrode of the upper trombone slide 101 of the first PMOS, the first NMOS under NMOS
It is connected, the grid of trombone slide 202 is connected with the source electrode of the 3rd NMOS access pipe 303 under the 2nd NMOS, and described second
The drain electrode of trombone slide 202 accesses the source electrode of pipe 304 with the drain electrode of the upper trombone slide 201 of the 2nd PMOS, the 4th NMOS under NMOS
It is connected, the source electrode of trombone slide meets low level GND under the source electrode and the 2nd NMOS of trombone slide under the first NMOS；
The source electrode of the first NMOS access pipe 301 is connected with the drain electrode of the 3rd NMOS access pipe 303, and described first
NMOS accesses the bit line BL of the drain electrode connection storage unit of pipe 301, the grid and described second of the first NMOS access pipe 301
The grid of NMOS access pipe 302 is controlled by wordline WL；
The source electrode of the 4th NMOS access pipe 304 is connected with the drain electrode of the 2nd NMOS access pipe 302, and the described 4th
NMOS accesses the antiposition line BLB of the drain electrode connection storage unit of pipe 304, the grid of the 3rd NMOS access pipe 303 and described
The grid of 4th NMOS access pipe 304 is controlled by wordline WL.
As shown in Figure 1, the drain electrode of trombone slide 101, institute on the source electrode and the first PMOS of the first NMOS access pipe 301
The drain electrode for stating trombone slide 102 under the first NMOS, which is connected, constitutes the first memory node Q, the source electrode of the 4th NMOS access pipe 304 with
The drain electrode of trombone slide 202 is connected under the drain electrode of trombone slide 201, the 2nd NMOS on 2nd PMOS constitutes the second memory node
QB。
Particularly, in the present embodiment, trombone slide 101 on the first PMOS, trombone slide 201, the first NMOS on the 2nd PMOS
A tunnel-through diode 4 is respectively connected between the source electrode and body area of trombone slide 202 under lower trombone slide 102 and the 2nd NMOS.Described first
Trombone slide 102 and the 2nd NMOS drop-down under trombone slide 201, the first NMOS on the upper trombone slide 101 of PMOS, the 2nd PMOS
One or more transistors can be arbitrarily chosen in pipe 202 using being connected with a tunnel-through diode 4 between source electrode and body area, not with
The present embodiment is limited.For PMOS transistor, source electrode is connect with the anode of the tunnel-through diode 4, body area and the tunnelling
The cathode of diode 4 connects；For NMOS transistor, source electrode is connect with the cathode of the tunnel-through diode 4, body area with it is described
The anode of tunnel-through diode 4 connects.
As an example, please refer to figs. 2 and 3, wherein Fig. 2 is shown as the PMOS transistor embedded with tunnel-through diode structure
The cross-sectional view of 5 (the first PMOS transistors 11, the second PMOS transistor 21), Fig. 3 are shown as embedded with tunnel-through diode structure
The cross-sectional view of NMOS transistor 6 (the first NMOS transistor 12, the second NMOS transistor 22).As an example, two pole of tunnelling
Pipe 4 is formed by connecting by p-type heavy doping anode 41 and N-type heavy doping cathode 42.
As an example, the static ram cell using successively include from bottom to top backing bottom 8, insulating buried layer 9 and
The SOI substrate of top layer silicon, by up and down through the fleet plough groove isolation structure of the top layer silicon between active area where each transistor
10 isolation.The backing bottom 8 includes but is not limited to the conventional semiconductors substrates such as Si, Ge, and can have the doping of certain type.This
In embodiment, the backing bottom 8 uses p-type Si substrate, and the insulating buried layer 9 uses silica.
As shown in Fig. 2, the p-type heavy doping anode 41 of the tunnel-through diode and the PMOS are brilliant for PMOS transistor
The p-type heavy doping source region 51 of body pipe shares, and the N-type heavy doping cathode 42 of the tunnel-through diode is located at the p-type heavy-doped source
51 bottom of area, and be in contact with the body area 52 of the PMOS transistor, meanwhile, the bottom of the N-type heavy doping cathode 42 and institute
Insulating buried layer 9 is stated to be in contact.
As shown in figure 3, the N-type heavy doping cathode 42 of the tunnel-through diode and the NMOS are brilliant for NMOS transistor
The N-type heavy doping source region 61 of body pipe shares, and the p-type heavy doping anode 41 of the tunnel-through diode is located at the N-type heavy-doped source
61 bottom of area, and be in contact with the body area 62 of the NMOS transistor, meanwhile, the bottom of the p-type heavy doping anode 41 and institute
Insulating buried layer 9 is stated to be in contact.
Further, the p-type heavy doping source region 51 and 61 top of N-type heavy doping source region are each formed with metal silication
Object 7.The metal silicide 7 includes but is not limited to the conductive silicides such as cobalt silicide and titanium silicide, with the p-type heavy doping
Source region 51 or the N-type heavy doping source region 61 form Ohmic contact.
The drain electrode 53 of PMOS transistor, shallow p type island region 54, grid and NMOS transistor are also respectively illustrated in Fig. 2 and Fig. 3
Drain 63, shallow n-type area 64, grid.In the present embodiment, the grid of the PMOS transistor and NMOS tube includes gate dielectric layer 11
And it is formed in the polysilicon layer 12 on the gate dielectric layer 11.Side wall isolation structure 13, the side are additionally provided with around the grid
Wall isolation structure 13 covers the shallow p type island region 54 or 64 part of shallow n-type area.In the present embodiment, the PMOS transistor
And the drain electrode of NMOS tube and grid top are also each formed with metal silicide 7, for reducing drain electrode and grid and extraction electrode it
Between contact resistance.
In static ram cell of the invention, trombone slide 101 on the first PMOS, trombone slide 201, first on the 2nd PMOS
The source electrode of trombone slide 202 is embedded with tunnel-through diode structure under trombone slide 102 and the 2nd NMOS under NMOS, can be in not adding unit
The leakage power consumption that effectively inhibits floater effect in PD SOI device and parasitic triode effect to cause in the case where area and
Transistor threshold voltage drift, improves the noise resisting ability of unit.
It should be pointed out that in Fig. 1, the first NMOS access pipe 301, the 2nd NMOS access pipe 302, described the
Three NMOS access pipe 303 and the 4th NMOS access pipe 304 are all made of float structure (area Ji Ti is hanging), unit performance
Reading rate is very fast, and it is big to write noise margin, and read noise tolerance is small.
In other embodiments, the first NMOS access pipe 301, the 2nd NMOS access pipe 302, the third
NMOS access pipe 303 and the 4th NMOS access pipe 304, and but at least one uses common grid NMOS tube, T-type grid NMOS tube
Or H-type grid NMOS tube.As shown in Figure 4-Figure 6, it is respectively indicated as brilliant using the NMOS of common grid 14, T-type grid 15 and H-type grid 16
The overlooking structure figure of body pipe, wherein grid two sides are respectively source region 17 and drain region 18, for T type grid NMOS and H-type grid NMOS crystal
Pipe, is also respectively provided with body contact zone 19.Using with body contact (obtain and take Guan Yuanduan or even GND) unit, reading rate compared with
It is small, it is small to write noise margin, but read noise tolerance is big.
The specific working mode of the static ram cell is described in detail below, the static random storage
There are three types of working conditions for unit:
Write state (write " 0 " data instance): first bit line BL is dragged down, antiposition line BLB is raised, then again by wordline WL
It raises, the first NMOS accesses pipe 301 and is connected, and the first memory node Q accesses pipe 301 by the first NMOS and discharges；3rd NMOS is deposited
Pipe 303 is taken to be connected, the 4th NMOS accesses pipe 304 and is connected, and antiposition line accesses pipe 303 and the 4th NMOS access pipe by the 3rd NMOS
304 raise the grid voltage of trombone slide 102 under the first NMOS, then by trombone slide 102 under the first NMOS to the first memory node Q into
The electric discharge of one step；Antiposition line BLB accesses pipe 304 by the 4th NMOS and charges to the second memory node QB, the first memory node Q
Current potential reduce, charged by trombone slide 101 on the first PMOS to QB.
Read states, (with reading " 0 " data instance) first pass through pre-charge circuit for bit line BL and antiposition line BLB and lift Cheng Gao electricity
It is flat, then wordline is raised, the first NMOS accesses pipe 301 and is connected, and is discharged by bit line BL, so that bit line BL current potential declines, then leads to
It crosses sense amplifier to amplify the potential difference between antiposition line BLB and bit line BL, the data stored to judge is " 0 " numbers
According to；
Hold mode: only needing to drag down wordline WL, and the first NMOS accesses pipe 301, the 4th NMOS accesses pipe 304
Cut-off, so bit line BL, antiposition line BLB data do not interfere with the first memory node Q and the second memory node QB.
Assuming that the data that storage unit is deposited are " 1 " data, it is the first memory node Q for high level, the second storage saves
Point QB is low level；Wordline WL is low level；If the body area of trombone slide 102 under the first NMOS of high-energy particle bombardment, at this time first
Trombone slide 201 is in off state on trombone slide 102 and the 2nd PMOS under NMOS, trombone slide 202 and the first PMOS pull-up under the 2nd NMOS
Pipe 101 is in the conductive state；After high-energy particle bombardment, the body area of trombone slide 102 forms Transient Currents at the first NMOS, at this time
One part of current can flow to the low spot position end GMD by the body deriving structure in body area；Another part electric current causes the first memory node Q
Current potential reduces.At this time, on the one hand, the second memory node QB is still low potential, and trombone slide 101 is conducting on the first PMOS, is passed through
High potential VDD charges to the first memory node Q, prevents the reduction of its current potential；On the other hand, the MOS being connect with the first memory node Q
Pipe source electrode or drain electrode, because the 2nd NMOS access pipe 302 is off, equivalent resistance is in a megohm grade, and due to the
What the first NMOS access pipe 301 that two NMOS access pipe 302 connects was off, what is connect with trombone slide under the 2nd NMOS is its grid
Pole, equivalent resistance several magnitudes also higher than megohm rank, so this just substantially prolongs its feedback time, to improve storage
The hold mode stability of unit in turn ensures that static ram cell read or write speed of the invention and traditional six transistors are quiet
State random memory unit is close.
Embodiment two
The present invention also provides a kind of production methods of static ram cell, include the following steps:
Be first carried out step 1) provide one from bottom to top successively include backing bottom, insulating buried layer and top layer silicon SOI substrate,
Fleet plough groove isolation structure is made in the top layer silicon, defines active area.
Specifically, as shown in fig. 7, defining four active areas 20a, 20b, 20c and 20d, wherein this four active areas
20a, 20b, 20c and 20d are arranged successively, and each active area surrounding is formed with shallow channel, are filled with insulating materials in the shallow channel
Constitute fleet plough groove isolation structure.In the present embodiment, the insulating materials is silica.
Then execute step 2), as shown in figure 8, the position according to the active area made in the top layer silicon N trap 30,
First p-well 40a and the second p-well 40b, wherein the N trap 30 is between the first p-well 40a and the second p-well 40b.
Specifically, the N trap 30 and the first p-well 40a, the second p-well 40b are formed using ion injection method.As an example,
The N trap 30 is injected using phosphonium ion, and the first p-well 40a and the second p-well 40b are injected using boron ion.The N trap
For making PMOS transistor, body area of the partial region as PMOS transistor；The first, second P trap is for making
NMOS transistor, body area of the partial region as NMOS transistor.
Step 3) is executed again, and as shown in Fig. 9 to Figure 12, trombone slide 101 and second on the first PMOS is made in the N trap 30
The upper trombone slide 201 of PMOS；Trombone slide 102 under the first NMOS is made in the first p-well 40a, the first NMOS accesses pipe 301 and second
NMOS accesses pipe 302；Trombone slide 202 under the 2nd NMOS is made in the second p-well 40b, the 3rd NMOS accesses pipe 303 and the 4th
NMOS accesses pipe 304；Wherein, Figure 10 is all made of dotted line frame into Figure 12 and shows each transistor region.
Particularly, trombone slide 101 on the first PMOS, trombone slide under trombone slide 201, the first NMOS on the 2nd PMOS
A tunnel-through diode 4 is respectively connected between the source electrode and body area of trombone slide 202 under 102 and the 2nd NMOS；For PMOS crystal
Pipe, source electrode are connect with the anode of the tunnel-through diode 4, and body area is connect with the cathode of the tunnel-through diode 4；For NMOS
Transistor, source electrode are connect with the cathode of the tunnel-through diode 4, and body area is connect with the anode of the tunnel-through diode 4.
As an example, the tunnel-through diode 4 is formed by connecting by p-type heavy doping anode 41 and N-type heavy doping cathode 42.It is right
In PMOS transistor, the p-type heavy doping anode 41 of the tunnel-through diode 4 and the p-type heavy doping source region of the PMOS transistor
51 share, and the N-type heavy doping cathode 42 of the tunnel-through diode 4 is located at 51 bottom of p-type heavy doping source region, and with it is described
The body area of PMOS transistor is in contact, meanwhile, the bottom of the N-type heavy doping cathode 42 is in contact with the insulating buried layer.It is right
In NMOS transistor, the N-type heavy doping cathode 42 of the tunnel-through diode 4 and the N-type heavy doping source region of the NMOS transistor
61 share, and the p-type heavy doping anode 41 of the tunnel-through diode 4 is located at 61 bottom of N-type heavy doping source region, and with it is described
The body area of NMOS transistor is in contact, meanwhile, the bottom of the p-type heavy doping anode 41 is in contact with the insulating buried layer.
As an example, the step 3) comprising steps of
31) as shown in FIG. 9 and 10, predeterminated position forms third grid 60c and the 4th grid 60d in Yu Suoshu N trap 30,
Predeterminated position forms first grid 60a in the first p-well 40a, and predeterminated position forms second in the second p-well of Yu Suoshu 40b
Grid 60b；Wherein, the first grid 60a is the grid of trombone slide 102 under the first NMOS, and the second grid 60b is
The grid of trombone slide 202 under 2nd NMOS, the third grid 60c are the grid of trombone slide 101 on the first PMOS, institute
State the grid that second grid 60d is trombone slide 201 on the 2nd PMOS；Predeterminated position forms the 5th in the first p-well 40a
Grid 60e, and predeterminated position forms the 6th grid 60f in the second p-well 40b；The 5th grid 60e is described first
NMOS access pipe 301 and the 2nd NMOS access pipe 302 share；The 6th grid 60f is the 3rd NMOS access
Pipe 303 and the 4th NMOS access pipe 304 share, and the 6th grid 60f is accessed in the 3rd NMOS manage respectively
303 and the 4th NMOS, which is accessed, has T-type bending part at 304 position of pipe.
More specifically, the first grid 60a, the second grid 60b, the third grid 60c, the 4th grid
60d, the 5th grid 60e and the 6th grid 60f include gate dielectric layer 11 and on the gate dielectric layer 11
Polysilicon layer 12.
32) N-type is carried out in the first p-well 40a, the second p-well 40b predeterminated position to be lightly doped, form described first
Trombone slide 202, the first NMOS access pipe 301, the 2nd NMOS access pipe 302, the 3rd NMOS under trombone slide 201, the 2nd NMOS under NMOS
Access the shallow n-type area 401 of pipe 303 and the 4th NMOS access pipe 304；It carries out p-type in 30 predeterminated position of N trap to be lightly doped, shape
At the shallow p type island region (being unillustrated) of trombone slide 201 on trombone slide 101 on the first PMOS and the 2nd PMOS.
33) the first grid 60a, the second grid 60b, the third grid 60c, the 4th grid 60d,
Side wall isolation structure (being unillustrated) is formed around the 5th grid 60e and the 6th grid 60f.The side wall isolation junction
Structure covers the shallow p type island region or 13 part of shallow n-type area.
34) p-type heavy doping as shown in figure 11, is carried out in the first p-well 40a and the second p-well 40b predeterminated position,
Form the p-type heavy doping sun for being embedded in the tunnel-through diode of first NMOS transistor 102 and second NMOS transistor 202
Pole 64；N-type heavy doping is carried out in 30 predeterminated position of N trap, is formed and is embedded in first PMOS transistor 101 and described the
The N-type heavy doping cathode 42 of the tunnel-through diode of two PMOS transistors 201.
Specifically, being covered in the mask plate that the first p-well 40a and the second p-well 40b predeterminated position are equipped with opening via this
Film version vertically carries out ion implanting, completes the p-type heavy doping or the N-type heavy doping.In the present embodiment, the ion note
The concentration range entered is 1E15-9E15/cm2, preferably 3E15/cm2、5E15/cm2、7E15/cm2；By controlling ion implanting
Energy so that lower part of the ion concentration peak value close to transistor source region region.
35) as shown in figure 12, it is located at the p-type heavy doping anode in the first p-well 40a and the second p-well 40b
The region of 41 tops carries out N-type heavy doping, forms the N of first NMOS transistor 12 and second NMOS transistor 22
Type heavy doping source region 61；It is located at the region above the N-type heavy doping cathode 42 in the N trap 30 and carries out the heavy doping of P type,
Form the p-type heavy doping source region 51 of first PMOS transistor 11 and second PMOS transistor 21.In first p-well
40a and the second p-well 40b predeterminated position carry out p-type heavy doping, form the first NMOS and access pipe 301, the 2nd NMOS
Access the p-type heavy doping body contact zone of pipe 302, the 3rd NMOS access pipe 303 and the 4th NMOS access pipe 304.
Specifically, further including pre- in the first p-well 40a and the second p-well 40b in the step 34) or step 35)
If position carries out N-type heavy doping to form under the first NMOS trombone slide 202, institute under trombone slide 102, the 2nd NMOS
State the first NMOS access pipe 301, the 2nd NMOS access pipe 302, the 3rd NMOS access pipe 303 and the described 4th
NMOS accesses the drain electrode of pipe 304 and the first NMOS access pipe 301, the 2nd NMOS access pipe 302, the 3rd NMOS
The source electrode for accessing pipe 303 and the 4th NMOS access pipe 304 carries out p-type heavy doping in the N trap predeterminated position to be formed
State the step of trombone slide 201 drains under trombone slide 101 and the 2nd PMOS under the first PMOS.
It further, further include in the p-type heavy doping source region 51 and the N-type heavy doping source region 61 in this step
The step of portion's formation metal silicide, (is unillustrated).
Specifically, by forming metal layer in the p-type heavy doping source region 51 and the N-type heavy doping source region 61, and
Heat treatment reacts the metal layer with the Si material under it, generates the metal silicide.In the present embodiment, the heat treatment
Temperature range be 700-900 DEG C, the time be 50-70 seconds.
Specifically, forming metal silicide in the p-type heavy doping source region 51 and 61 top of N-type heavy doping source region
At the same time it can also on the first PMOS trombone slide 101, trombone slide 102 under trombone slide 201 and the first NMOS on the 2nd PMOS,
Metal silicide formed at the drain electrode of trombone slide 202 and grid top under 2nd NMOS, and the first NMOS access pipe 301,
Gold is formed at the 2nd NMOS access pipe 302, the 3rd NMOS access pipe 303, the source-drain electrode of the 4th NMOS access pipe 304 and grid top
Belong to silicide, to reduce the contact resistance between source-drain electrode and grid and extraction electrode.
Step 4) production metallic vias and respective metal line are executed, finally to complete the system of the static storage cell
Make.
Specifically, the grid of trombone slide 101 is connected with the drain electrode of trombone slide 201 on the 2nd PMOS on the first PMOS, the first PMOS
The drain electrode of upper trombone slide 101 is connected with the grid of trombone slide 201 on the 2nd PMOS, the source electrode and second of trombone slide 101 on the first PMOS
The source electrode of the upper trombone slide 201 of PMOS meets high level VDD；The grid of trombone slide 102 and the 2nd NMOS access pipe 302 under first NMOS
Source electrode be connected, drain electrode of the drain electrode of trombone slide 102 with the upper trombone slide 101 of the first PMOS, the first NMOS access pipe 301 under the first NMOS
Source electrode be connected, the source electrode of the grid of trombone slide 202 and the 3rd NMOS access pipe 303 is connected under the 2nd NMOS, and the 2nd NMOS is pulled down
The drain electrode of pipe 202 is connected with the drain electrode of trombone slide 201 on the 2nd PMOS, the 4th the NMOS source electrode for accessing pipe 304, under the first NMOS
The source electrode of trombone slide meets low level GND under the source electrode of trombone slide and the 2nd NMOS；The source electrode and third of first NMOS access pipe 301
The drain electrode that NMOS accesses pipe 303 is connected, and the first NMOS accesses the bit line BL, the first NMOS of the drain electrode connection storage unit of pipe 301
The grid of the grid and the 2nd NMOS access pipe 302 that access pipe 301 is controlled by wordline WL；The source of 4th NMOS access pipe 304
Pole is connected with the drain electrode of the 2nd NMOS access pipe 302, and the 4th NMOS accesses the antiposition line of the drain electrode connection storage unit of pipe 304
The grid of BLB, the 3rd NMOS access pipe 303 and the grid of the 4th NMOS access pipe 304 are controlled by wordline WL.First NMOS is deposited
The p-type heavy doping body of pipe 301, the 2nd NMOS access pipe 302, the 3rd NMOS access pipe 303, the 4th NMOS access pipe 304 is taken to connect
Touching area 7 is connected to GND.
So far, the production of the static ram cell is completed.The production of static ram cell of the invention
Method does not introduce extra mask plate, completely compatible with existing logic process, uses centrosymmetric structure inside unit, not only favorably
It is matched in the size of MOS pipe and threshold voltage etc., also helps to form array, facilitate full custom sram chip, be suitable for list
The occasions such as elemental area harshness, low-power consumption.
In conclusion pulling up transistor in static ram cell of the invention and being embedded with tunnelling with pull-down transistor
Diode structure can effectively inhibit floater effect and parasitism in PD SOI device in the case where not increasing device area
Leakage power consumption and the transistor threshold voltage drift that triode effect causes, improve the noise resisting ability of unit.And it is of the invention
The production method of six layer transistor SRAM unit of SOI also has many advantages, such as that manufacturing process is simple, completely compatible with existing logic process,
Centrosymmetric structure is used inside unit, can reduce influence caused by process deviation, meanwhile, have between unit shared well
Structure, can reduction unit effective area, make it facilitate to form storage array, and further decrease memory array area, have
Conducive to the period for shortening design sram chip.So the present invention effectively overcomes various shortcoming in the prior art and has height
Value of industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (18)
1. a kind of static ram cell, which is characterized in that the static ram cell includes at least:
Trombone slide on first PMOS, trombone slide, the first NMOS access under trombone slide, the 2nd NMOS under trombone slide, the first NMOS on the 2nd PMOS
Pipe, the 2nd NMOS access pipe, the 3rd NMOS access pipe and the 4th NMOS access pipe；
The grid of trombone slide is connected with the drain electrode of trombone slide on the 2nd PMOS on first PMOS, trombone slide on the first PMOS
Drain electrode be connected with the grid of trombone slide on the 2nd PMOS, on the first PMOS on the source electrode and the 2nd PMOS of trombone slide
The source electrode of trombone slide connects high level；
The grid of trombone slide is connected with the source electrode of the 2nd NMOS access pipe under first NMOS, trombone slide under the first NMOS
Drain electrode be connected with the drain electrode of trombone slide on the first PMOS, the first NMOS source electrode for accessing pipe, under the 2nd NMOS
The grid of trombone slide is connected with the source electrode of the 3rd NMOS access pipe, the drain electrode and described second of trombone slide under the 2nd NMOS
The drain electrode of the upper trombone slide of PMOS, the 4th NMOS access pipe source electrode be connected, the source electrode of trombone slide and described under the first NMOS
The source electrode of trombone slide connects low level under 2nd NMOS；
The source electrode of the first NMOS access pipe is connected with the drain electrode of the 3rd NMOS access pipe, the first NMOS access pipe
Drain electrode connection storage unit bit line, the drain electrode of trombone slide, first on the source electrode and the first PMOS of the first NMOS access pipe
The drain electrode of trombone slide, which is connected, under NMOS constitutes the first memory node, the grid and the 2nd NMOS access pipe of the first NMOS access pipe
Grid controlled by wordline；
The source electrode of the 4th NMOS access pipe is connected with the drain electrode of the 2nd NMOS access pipe, the 4th NMOS access pipe
Drain electrode connection storage unit antiposition line, the drain electrode of trombone slide on the source electrode and the 2nd PMOS of the 4th NMOS access pipe, the
The drain electrode of trombone slide, which is connected, under two NMOS constitutes the second memory node, the grid of the 3rd NMOS access pipe and the 4th NMOS access
The grid of pipe is controlled by wordline.
Wherein, trombone slide on the first PMOS, on the 2nd PMOS under trombone slide, the first NMOS under trombone slide and the 2nd NMOS
A tunnel-through diode is respectively connected between the source electrode and body area of trombone slide；For PMOS transistor, source electrode and two pole of tunnelling
The anode of pipe connects, and body area is connect with the cathode of the tunnel-through diode；For NMOS transistor, source electrode and the tunnelling two
The cathode of pole pipe connects, and body area is connect with the anode of the tunnel-through diode.
2. static ram cell according to claim 1, it is characterised in that: the tunnel-through diode is heavily doped by p-type
Miscellaneous anode is formed by connecting with N-type heavy doping cathode.
3. static ram cell according to claim 2, it is characterised in that: for trombone slide on PMOS, the tunnelling
The p-type heavy doping anode of diode and the p-type heavy doping source region of the PMOS transistor share, the N-type of the tunnel-through diode
Heavy doping cathode is located at the p-type heavy doping source region bottom, and is in contact with the body area of trombone slide on the PMOS；For under NMOS
Trombone slide, the N-type heavy doping cathode of the tunnel-through diode are shared with the N-type heavy doping source region of trombone slide under the NMOS, the tunnel
The p-type heavy doping anode for wearing diode is located at the N-type heavy doping source region bottom, and connects with the body area of trombone slide under the NMOS
Touching.
4. static ram cell according to claim 3, it is characterised in that: the p-type heavy doping source region and the N
Type heavy doping source region top is each formed with metal silicide.
5. static ram cell according to claim 4, it is characterised in that: the metal silicide is selected from cobalt silicide
And any one in titanium silicide.
6. static ram cell according to claim 1, it is characterised in that: the static ram cell uses
It from bottom to top successively include the SOI substrate at backing bottom, insulating buried layer and top layer silicon, by upper between active area where each transistor
It is isolated through the fleet plough groove isolation structure of the top layer silicon down.
7. static ram cell according to claim 1, it is characterised in that: the first NMOS access manages, is described
2nd NMOS access pipe, the 3rd NMOS access pipe and the 4th NMOS access pipe use common grid NMOS tube, T-type grid
The combination of one or more of NMOS tube or H-type grid NMOS tube.
8. a kind of production method of static ram cell, which comprises the steps of:
1) one is provided from bottom to top successively including the SOI substrate at backing bottom, insulating buried layer and top layer silicon, is made in the top layer silicon
Make fleet plough groove isolation structure, defines active area；
2) N trap, the first p-well and the second p-well are made in the top layer silicon according to the position of the active area, wherein the N trap
Between first p-well and the second p-well；
3) trombone slide on trombone slide and the 2nd PMOS is made on the first PMOS in the N trap；First is made in first p-well
Trombone slide, the first NMOS access pipe and the 2nd NMOS access pipe under NMOS；In second p-well make the 2nd NMOS under trombone slide,
3rd NMOS access pipe and the 4th NMOS access pipe；Wherein, trombone slide on the first PMOS, trombone slide, institute on the 2nd PMOS
It states and is respectively connected with a tunnel-through diode between the source electrode and body area of trombone slide under trombone slide and the 2nd NMOS under the first NMOS；For
The upper trombone slide of PMOS, source electrode are connect with the anode of the tunnel-through diode, and body area is connect with the cathode of the tunnel-through diode；It is right
The trombone slide under NMOS, source electrode are connect with the cathode of the tunnel-through diode, and body area is connect with the anode of the tunnel-through diode；
4) metallic vias and respective metal line are made, to complete the production of the memory cell.
9. the production method of static ram cell according to claim 8, it is characterised in that: the tunnel-through diode
It is formed by connecting by p-type heavy doping anode and N-type heavy doping cathode.
10. the production method of static ram cell according to claim 9, it is characterised in that: PMOS is pulled up
Pipe, the p-type heavy doping anode of the tunnel-through diode are shared with the p-type heavy doping source region of trombone slide on the PMOS, the tunnelling
The N-type heavy doping cathode of diode is located at the p-type heavy doping source region bottom, and connects with the body area of trombone slide on the PMOS
Touching；For trombone slide under NMOS, the N-type heavy-doped source of trombone slide under the N-type heavy doping cathode and the NMOS of the tunnel-through diode
Area shares, and the p-type heavy doping anode of the tunnel-through diode is located at the N-type heavy doping source region bottom, and under the NMOS
The body area of trombone slide is in contact.
11. the production method of static ram cell according to claim 9, it is characterised in that: the step 3) packet
Include step:
31) grid of trombone slide on the grid and the 2nd PMOS of trombone slide on the first PMOS are formed in the N trap predeterminated position
Pole, the grid of trombone slide in the case where the first p-well predeterminated position forms the first NMOS, and in the second p-well predeterminated position
Form the grid of trombone slide under the 2nd NMOS；
32) N-type is carried out in first p-well and the second p-well predeterminated position to be lightly doped, form the first NMOS drop-down
Trombone slide, the first NMOS access pipe, the 2nd NMOS access pipe, the 3rd NMOS access under pipe, the 2nd NMOS
The shallow n-type area of pipe and the 4th NMOS access pipe；P-type is carried out in the N trap predeterminated position to be lightly doped, and forms described first
The shallow p type island region of trombone slide on the upper trombone slide of PMOS and the 2nd PMOS；
33) grid of trombone slide, trombone slide under the grid of trombone slide, the first NMOS on the 2nd PMOS on the first PMOS
Grid and the 2nd NMOS under trombone slide grid around formed side wall isolation structure；
34) p-type heavy doping is carried out in first p-well, the second p-well predeterminated position, forms the p-type heavy doping anode；
N-type heavy doping is carried out in the N trap predeterminated position, forms the N-type heavy doping cathode；
35) it is located at the region above the p-type heavy doping anode in first, second p-well and carries out N-type heavy doping, is formed
The N-type heavy doping source region of trombone slide under first, second NMOS；It is located above the N-type heavy doping cathode in the N trap
Region carries out p-type heavy doping, forms the p-type heavy doping source region of trombone slide on first, second PMOS.
12. the production method of static ram cell according to claim 11, it is characterised in that: Yu Suoshu step
34) in, using together the first, second p-well predeterminated position be equipped with opening mask plate, via the mask plate vertically into
Row ion implanting completes the p-type heavy doping or the N-type heavy doping.
13. the production method of static ram cell according to claim 12, it is characterised in that: the ion implanting
Concentration range be 1E15-9E15/cm2。
14. the production method of static ram cell according to claim 11, it is characterised in that: Yu Suoshu step
It 34) further include carrying out N-type heavy doping in first p-well and the second p-well predeterminated position to be formed or in step 35)
State trombone slide under the first NMOS, trombone slide, the first NMOS access pipe, the 2nd NMOS access pipe, institute under the 2nd NMOS
State drain electrode and the first NMOS access pipe, described second of the 3rd NMOS access pipe and the 4th NMOS access pipe
The source electrode of NMOS access pipe, the 3rd NMOS access pipe and the 4th NMOS access pipe, carries out in the N trap predeterminated position
P-type heavy doping is to form the step of trombone slide drains under first, second PMOS.
15. the production method of static ram cell according to claim 10, it is characterised in that: Yu Suoshu step 3)
In, further include the steps that forming metal silicide in the p-type heavy doping source region and the N-type heavy doping source region top.
16. the production method of static ram cell according to claim 15, it is characterised in that: by the P
Metal layer is formed in type heavy doping source region and the N-type heavy doping source region, and heat treatment makes the metal layer and the Si material under it
Material reaction, generates the metal silicide.
17. the production method of static ram cell according to claim 16, it is characterised in that: the heat treatment
Temperature range is 700-900 DEG C, and the time is 50-70 seconds.
18. the production method of static ram cell according to claim 8, it is characterised in that:
The grid of trombone slide is connected with the drain electrode of trombone slide on the 2nd PMOS on first PMOS, trombone slide on the first PMOS
Drain electrode be connected with the grid of trombone slide on the 2nd PMOS, on the first PMOS on the source electrode and the 2nd PMOS of trombone slide
The source electrode of trombone slide connects high level；
The grid of trombone slide is connected with the source electrode of the second access pipe under first NMOS, the leakage of trombone slide under the first NMOS
Pole is connected with the source electrode of the drain electrode of trombone slide on the first PMOS, the first NMOS access pipe, trombone slide under the 2nd NMOS
The source electrode of grid and the 3rd NMOS access pipe be connected, under the 2nd NMOS drain electrode of trombone slide on the 2nd PMOS
The drain electrode of trombone slide, the source electrode of the 4th NMOS access pipe are connected, the source electrode and described second of trombone slide under the first NMOS
The source electrode of trombone slide connects low level under NMOS；
The source electrode of the first NMOS access pipe is connected with the drain electrode of the 3rd NMOS access pipe, the leakage of the first NMOS access pipe
Pole connects the bit line of storage unit, and the grid of the first NMOS access pipe and the grid of the 2nd NMOS access pipe are by word
Line traffic control；
The source electrode of the 4th NMOS access pipe is connected with the drain electrode of the 2nd NMOS access pipe, and the drain electrode of the 4th access pipe connects
The antiposition line of storage unit is connect, the grid of the 3rd NMOS access pipe and the grid of the 4th NMOS access pipe are by wordline
Control.
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| CN112562756A (en) * | 2020-12-15 | 2021-03-26 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant static random access memory cell and memory |
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| US20060081930A1 (en) * | 2004-10-18 | 2006-04-20 | Renesas Technology Corp. | Semiconductor device, manufacturing method thereof, and memory circuit |
| JP2008027493A (en) * | 2006-07-19 | 2008-02-07 | Toshiba Corp | Semiconductor memory device |
| CN106952917A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of layer transistor SRAM units of SOI six and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20060081930A1 (en) * | 2004-10-18 | 2006-04-20 | Renesas Technology Corp. | Semiconductor device, manufacturing method thereof, and memory circuit |
| JP2008027493A (en) * | 2006-07-19 | 2008-02-07 | Toshiba Corp | Semiconductor memory device |
| CN106952917A (en) * | 2016-01-07 | 2017-07-14 | 中国科学院上海微系统与信息技术研究所 | A kind of layer transistor SRAM units of SOI six and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112562756A (en) * | 2020-12-15 | 2021-03-26 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant static random access memory cell and memory |
| CN112562756B (en) * | 2020-12-15 | 2024-03-08 | 中国科学院上海微系统与信息技术研究所 | Radiation-resistant sram cell and memory |
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