CN102856357B - Heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on buried layer N-type trap and preparation method thereof - Google Patents
Heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on buried layer N-type trap and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title abstract description 19
- 229910052710 silicon Inorganic materials 0.000 claims description 64
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 63
- 239000010703 silicon Substances 0.000 claims description 63
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 19
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 11
- 238000011049 filling Methods 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 3
- 239000002210 silicon-based material Substances 0.000 claims 2
- 150000002500 ions Chemical class 0.000 claims 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 abstract description 56
- 238000005036 potential barrier Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 230000014759 maintenance of location Effects 0.000 abstract description 4
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- 238000005530 etching Methods 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000008929 regeneration Effects 0.000 description 2
- 238000011069 regeneration method Methods 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- 229910005793 GeO 2 Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
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Abstract
The invention provides a heterojunction 1T-DRAM (One Transistor Dynamic Random Access Memory) structure based on a buried layer N-type trap and a preparation method thereof. According to the invention, hole potential barriers between a bulk and the buried layer N-type trap and between the bulk and a source region are effectively increased, thus the bulk potential variation range of a 1T-DRAM unit is effectively increased, and further the threshold voltage variation range is effectively increased, so that the read signal current increases, that is, the signal margin is increased. At the same time, as the hole potential barriers between the bulk and the buried layer N-type trap and between the bulk and the source region are effectively increased, the drain currents between the bulk and the buried layer N-type trap and between the bulk and the source region are effectively decreased, and the retention time of the 1T-DRAM is increased. In addition, as narrow bandgap SiGe is adopted as a bulk layer and a drain region, impact ionization effect is effectively increased, so as to improve bulk hole production rate and increase the read-write velocity of the 1T-DRAM unit.
Description
Technical field
The present invention relates to a kind of 1T-DRAM structure and preparation method thereof, particularly relate to a kind of heterojunction 1T-DRAM structure based on buried regions N-type trap and preparation method thereof.
Background technology
Along with constantly reducing of semiconductor device characteristic size, tradition 1T/1C embedded DRAM unit is in order to obtain enough amount of storage capacity (General Requirements 30fF/cell), its electric capacity preparation technology (stack capacitor or deep-trench capacitor) will become increasingly complex, and with logical device processing compatibility worse and worse.Therefore, compatible good in electric capacity DRAM(Capacitorless DRAM with logical device) in VLSI, good development prospect will be had in high-performance embedded DRAM field.Wherein 1T-DRAM(one transistor dynamic random access memory) only have 4F because of its cell size
2and become at present without the study hotspot of electric capacity DRAM.
1T-DRAM is generally the NMOSFET transistor of a SOI buoyancy aid (floating body) NMOSFET transistor or band buried regions N-type trap, when charging to its tagma, namely the accumulation in hole, tagma completes one writing, at this moment cause substrate bias effect due to the accumulation of hole, tagma, cause the threshold voltage of transistor to reduce.When discharging to its tagma, namely bled off by the hole of its tagma of the positive assistant general of body drain PN junction accumulation and write " 0 ", at this moment body effect disappears, and threshold voltage recovering is normal.And read operation is source-drain current when reading this transistor opening, because " 1 " is different with the threshold voltage of " 0 " state, both source-drain currents are also different, when large namely expression reading be " 1 ", and what represent reading time less is " 0 ".
The operating characteristic of 1T-DRAM has a detailed description in following paper:
ohsawa, T.; Et al. Memory design using a one-transistor gain cell on SOI, Solid-State Circuits, IEEE Journal, Nov 2002, Volume:37 Issue:11, page:1510 – 1522.
According to the difference of one writing method of operation, 1T-DRAM can be divided into two classes, and a class adopts transistor when saturation region, to pass through ionization by collision (impact-ionization) in accumulation hole, tagma, and a class adopts GIDL effect to make accumulation hole, tagma.The 1T-DRAM of employing impact ionization is the study hotspot of current 1T-DRAM.
But the NMOSFET transistor 1T-DRAM structure of band buried regions N-type trap conventional at present also needs to do in following several respects to improve to improve performance further:
1, the hole potential barrier in the hole potential barrier of body potential receptor area and buried regions N-type trap, tagma and source limits, because conventional Si semiconductor energy gap is limited, the change of bulk potential is restricted, and the change of threshold voltage is less (generally only having about 0.3V), and this makes the signal code of reading less;
2, when this 1T-DRAM works, buried regions N-type trap needs to connect positive voltage, reverse-biased with the PN junction making P type tagma and buried regions N-type trap be formed, but it must have a PN junction pull-down current, thus running off in the hole of causing tagma to accumulate, therefore, need reduce this pull-down current as far as possible.In like manner, the leakage current as far as possible reducing tagma and source is also needed, to improve the retention time (retention time) of 1T-DRAM.
3, increase impact ionization, produce speed to increase hole, tagma, increase the read-write speed of 1T-DRAM unit.
Summary of the invention
For the band buried regions N-type trap of above-described current routine NMOSFET transistor 1T-DRAM structure required for three aspects improving further, from energy band engineering, the semi-conducting material of a kind of buried regions N-type trap and employing broad stopband, source region is proposed, and tagma and drain region adopt the semi-conducting material of low energy gap, namely adopt the method for heterojunction to improve the performance of conventional 1T-DRAM, and propose its preparation method:
Wherein, tagma and drain region adopt the germanium silicon (SiGe) narrower than the energy gap of Si, to increase impact ionization, thus increase hole, tagma generation speed, increase the read-write speed of 1T-DRAM unit.For body trap, body source PN junction, in order to increase hole potential barrier, theoretically, if just can realize with the energy band engineering material wider than the forbidden band of SiGe.Meanwhile, in order to not affect the threshold voltage of NMOS, the conduction band needs of this wide-band gap material and the identical or close of silicon, namely only need valence band lower than SiGe, carborundum (SiC) just has this characteristic.
The present invention's first object is to provide a kind of heterojunction 1T-DRAM structure based on buried regions N-type trap, comprises bottom silicon, is positioned at the buried regions N-type trap layer above described bottom silicon and is positioned at the top layer silicon above described buried regions N-type trap layer; Also include grid and the shallow trench being positioned at grid both sides, described grid is positioned at the upper surface of described top layer silicon, and described shallow trench upper surface and described top layer silicon upper surface are in same plane, and described shallow trench bottom surface is arranged in described buried regions N-type trap; Source region and drain region is respectively in tagma layer between described grid and shallow trench.
Wherein, described top layer silicon comprises P type SiGe layer, and described source region material is N
+type SiC, described drain region material is N
+type SiGe, described buried regions N-type trap layer material is N-type SiC.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, in described buried regions N-type trap layer and/or source region, the molar content of carbon is preferably 0.01% ~ 10%.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, described buried regions N-type trap layer thickness is preferably >=10nm.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, can also comprise the P-type silicon thin layer be positioned at below described grid above described top layer silicon, or also comprises the gate oxide between described grid and described P shape silicon thin layer.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, in described P type SiGe layer and described drain region, the molar content of Ge is preferably 0.1 ~ 100%.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, described P type SiGe layer thickness >=30nm.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, described source region thickness is 1/5 ~ 4/5 of described P type SiGe layer thickness.
The heterojunction 1T-DRAM structure that the present invention is above-mentioned, described grid both sides also comprise side wall, and described source region can extend to below side wall from described shallow trench, or extends to side wall outward flange.Refer to centered by grid central shaft outside described, point to the direction of shallow trench.
Described drain region can be made up of shallow doped region and heavily doped region, but also can not comprise shallow doped region.
Similarly, also can there is shallow doped region between described source region and grid, this shallow doped region material also can be N
+type SiGe.
The present invention's second object is to provide a kind of method prepared as the above-mentioned heterojunction 1T-DRAM structure based on buried regions N-type trap, and step comprises:
Step 1, provides bottom silicon; Described bottom silicon generates N-type SiC layer; P type SiGe layer is generated above described N-type SiC layer; Can also above described P type SiGe layer regeneration skim P-type silicon;
Step 2, prepares shallow trench, and makes described shallow trench bottom surface be arranged in described N-type SiC layer;
Step 3, prepares grid between adjacent two shallow trenchs;
Step 4, photoresist cover gate, shallow trench and described P type SiGe layer (or thin layer P-type silicon), the first opening is formed in grid side, P type SiGe layer between the shallow trench of grid and described grid side ((or thin layer P-type silicon)) is come out, by the first opening, the P type SiGe layer exposed (with (or thin layer P-type silicon)) is etched, but be not etched to described N-type SiC layer, form source region groove, remove residue photoresist; Selective growth N in the source region groove formed
+type SiC, to filling up described source region groove, forms source region;
Photoresist cover gate, shallow trench and described P type SiGe layer, form the second opening at grid opposite side, the P type SiGe layer between the shallow trench of grid and described grid opposite side come out, carries out N by the second opening to the P type SiGe layer exposed
+type ion implantation, forms drain region; Remove residue photoresist.
Step 5, annealing, activates the foreign ion injected.
In said method of the present invention, preferably, the molar content of described N-type SiC layer thickness >=10nm, C is 0.01% ~ 10%; The molar content of described P type SiGe layer thickness >=30nm, Ge is 0.1% ~ 100%.
The method that the present invention is above-mentioned, also comprises the technique preparing grid curb wall, and the preparation of described side wall can be carried out before preparation drain region and source region, or after preparation source region or carry out before drain region.
Drain region of the present invention can be successively be prepared by light dope (and injecting low energy Ge ion) and heavy doping (and injecting high energy Ge ion), and now, side wall should be prepared before heavy doping.
In said method of the present invention, described source region, before carrying out etching formation source region groove, also first can be carried out light dope, and inject low energy Ge ion.
In step 6, in described etching P type SiGe layer process, the P type SiGe layer thickness etched away preferably accounts for 1/5 ~ 4/5 of described P type SiGe layer gross thickness.
In heterojunction 1T-DRAM structure based on buried regions N-type trap that the present invention is above-mentioned and preparation method thereof, described bottom silicon can be P-type silicon.
The present invention adopts SiGe as top layer silicon (comprising tagma) and drain region, adopt N-type SiC as buried regions N-type trap, adopt N+ type SiC as source region, increase effectively the hole potential barrier between tagma and buried regions N-type trap, between tagma and source region, thus effectively increase the excursion of the bulk potential of 1T-DRAM unit, and then effectively increase the excursion of its threshold voltage, make the signal code read become large, namely increase signal margin (margin).Meanwhile, owing to increasing the hole potential barrier between tagma and buried regions N-type trap, between tagma and source region, effectively reduce the leakage current between tagma and buried regions N-type trap, between tagma and source region, increase the retention time of 1T-DRAM.In addition, owing to adopting the SiGe of low energy gap as tagma layer and drain region, effectively increase impact ionization, produce speed to increase hole, tagma, increase the read-write speed of 1T-DRAM unit.
Accompanying drawing explanation
Fig. 1 is the method flow diagram that the embodiment of the present invention 1 prepares the heterojunction 1T-DRAM structure based on buried regions N-type trap, wherein:
Figure 1A is for preparing bottom silicon, N-type SiC layer, P type SiGe layer and P-type silicon thin layer;
Figure 1B is for forming shallow trench;
Fig. 1 C is for forming grid;
Fig. 1 D is etching formation source region groove;
Fig. 1 E is for filling source region groove;
Fig. 1 F is that light dope forms shallow doped region, drain region;
Fig. 1 G is for preparing grid curb wall;
Fig. 1 H is for carry out heavy doping to drain region;
Fig. 1 I is the heterojunction 1T-DRAM structural representation based on buried regions N-type trap;
Fig. 1 J is the 1T-DRAM cellular construction schematic diagram formed after wiring;
Fig. 2 is the method flow diagram that the embodiment of the present invention 2 prepares the heterojunction 1T-DRAM structure based on buried regions N-type trap, wherein:
Fig. 2 A is that light dope is carried out in grid both sides;
Fig. 2 B is etching formation source region groove;
Fig. 2 C is for filling source region groove;
Fig. 2 D is for carry out heavy doping to drain region;
Fig. 2 E is the heterojunction 1T-DRAM structural representation based on buried regions N-type trap;
Fig. 3 is the heterojunction 1T-DRAM structural representation of the embodiment of the present invention 3 based on buried regions N-type trap;
Fig. 4 is the heterojunction 1T-DRAM structural representation of the embodiment of the present invention 4 based on buried regions N-type trap.
Embodiment
The invention provides a kind of heterojunction 1T-DRAM structure based on buried regions N-type trap, comprise bottom silicon, be positioned at the buried regions N-type trap layer above described silicon base and be positioned at the top layer silicon above described buried regions N-type trap layer; Also include grid and the shallow trench being positioned at grid both sides, described grid is positioned at the upper surface of described top layer silicon, and described shallow trench upper surface and described top layer silicon upper surface are in same plane, and described shallow trench bottom surface is arranged in described buried regions N-type trap; Source region and drain region is respectively equipped with in top layer silicon between described grid and shallow trench.
Present invention also offers a kind of method based on the heterojunction 1T-DRAM structure of buried regions N-type trap described in preparation, step comprises:
Step 1, provides bottom silicon; Described bottom silicon generates N-type SiC layer; P type SiGe layer is generated above described N-type SiC layer; Can also above described P type SiGe layer regeneration skim P-type silicon;
Step 2, prepares shallow trench, and makes described shallow trench bottom surface be arranged in described N-type SiC layer;
Step 3, prepares grid between adjacent two shallow trenchs;
Step 4, photoresist cover gate, shallow trench and described P type SiGe layer (or thin layer P-type silicon), the first opening is formed in grid side, P type SiGe layer between the shallow trench of grid and described grid side ((or thin layer P-type silicon)) is come out, by the first opening, the P type SiGe layer exposed (with (or thin layer P-type silicon)) is etched, but be not etched to described N-type SiC layer, form source region groove, remove residue photoresist; Selective growth N in the source region groove formed
+type SiC, to filling up described source region groove, forms source region;
Photoresist cover gate, shallow trench and described P type SiGe layer, form the second opening at grid opposite side, the P type SiGe layer between the shallow trench of grid and described grid opposite side come out, carries out N by the second opening to the P type SiGe layer exposed
+type injection technology, forms drain region; Remove residue photoresist.
Step 5, annealing, activates the foreign ion injected.
With reference to the accompanying drawings, be described in detail by specific embodiment and describe heterojunction 1T-DRAM structure that the present invention is based on buried regions N-type trap and preparation method thereof, to make better to understand content of the present invention, but following embodiment does not limit the scope of the invention.
embodiment 1
With reference to Fig. 1, in the present embodiment, preparation is described as follows based on the preparation method of the heterojunction 1T-DRAM structure of buried regions N-type trap:
Step 1
As shown in Figure 1A, P type bottom silicon 1 is provided; Extension one deck N-type SiC layer 2 in P-type silicon substrate 1, and make the molar content of N-type SiC layer 2 thickness>=10nm, C between 0.01% ~ 10%; Above N-type SiC layer 2, extension one deck P type SiGe layer 3, and make the molar content of P type SiGe layer 3 thickness>=30nm, Ge (when the molar content of Ge is 100%, be pure ge layer) between 0.1% ~ 100%; Finally, due to GeO
2unsteadiness, can also extension skim P-type silicon layer 4 above P type SiGe layer, this layer thickness is far smaller than aforementioned three layers.
Step 2
With reference to Figure 1B, prepare shallow trench 5, formed shallow trench isolation from, and make the lower bottom part of shallow trench 5 be arranged in N-type SiC layer 2, namely the lower bottom part of shallow trench 5 lower than the upper surface of N-type SiC layer 2 higher than the lower surface of N-type SiC layer 2; The upper bottom surface of shallow trench 5 is concordant with P-type silicon layer 4 upper surface, is namely in same level.
The concrete preparation technology of shallow trench 5 can refer to prior art and implements.
Step 3
With reference to Fig. 1 C, between adjacent two shallow trenchs 5, form grid 6, the concrete preparation technology of grid 6 implements with reference to prior art.
After forming grid, gate oxide 60 can be retained as subsequent selective epitaxial barrier layer in etch areas.
Step 4
With reference to Fig. 1 D, photoresist 10 cover gate 6, shallow trench 5 and P-type silicon layer 4, the first opening (in Fig. 1 D arrow locations) is formed in the side of grid 6 by photoetching, P-type silicon layer 4 between the shallow trench 5 of grid 6 and grid 6 side is come out, remove the P-type silicon layer 4 exposed in the first opening, expose P type SiGe layer 3, Plasma Etch technique is adopted to carry out selectivity Self-aligned etching by the first opening to the P type SiGe layer 3 exposed, make the P type SiGe layer thickness etched away account for P type SiGe layer gross thickness 1/5 to 4/5 between, form source region groove 70.
Remove residue photoresist 10.
With reference to Fig. 1 E, in the source region groove 70 formed, carry out selective epitaxial growth N
+type SiC, to filling up source region groove 70, forms source region 7, and makes the molar content of C between 0.01% to 10%.
With reference to Fig. 1 F, photoresist 10 cover gate 6, shallow trench 5 and P-type silicon layer 4 and source region 7, the second opening (in Fig. 1 F arrow locations) is formed at the opposite side of grid 6 by photoetching, P-type silicon layer 4 between the shallow trench 5 of grid 6 and grid 6 opposite side is come out, drain region LDD injection technology is carried out to the P-type silicon layer exposed and SiGe layer below 3, form shallow doped region 81, drain region, this technique can refer to prior art and implements.Remove light residue and carve glue 10.
With reference to Fig. 1 G, in the outside of grid 6, form side wall 62, the concrete formation process of side wall 62 can refer to prior art and implements.
With reference to Fig. 1 H and figure I, photoresist 10 cover gate 6, shallow trench 5 and P type SiGe layer 3(comprise P-type silicon layer 4) and source region 7, again form opening (in Fig. 1 F arrow locations) by photoetching at the opposite side of grid 6, coming out in shallow doped region, drain region, carries out drain region N to exposed region
+type ion implantation technology, forms heavily doped region, drain region 82, and this technique can refer to prior art and implements.Remove light residue and carve glue 10.
Those skilled in the art it is understood that in this step source region and drain region formation order can exchange.
Step 5
Finally carry out annealing process, activate the foreign ion injected, form N
+type SiGe drain region 8.
Adopt conventional NMOS technique, by source ground (GND), drain electrode connects bit line (Bit Line, BL), grid connects wordline (Word Line, WL), forms 1T-DRAM unit.
With reference to Fig. 1 I and Fig. 1 J, the heterojunction 1T-DRAM structure based on buried regions N-type trap that the present embodiment above-mentioned steps is formed, comprise silicon base 1, N-type SiC layer 2(also can be called " buried regions N-type trap layer "), the tagma layer that forms of P type SiGe layer 3 and thin layer P-type silicon layer 4, it is grid 6 above the layer of tagma, the both sides of grid 6 are side wall 62, centered by grid, be respectively source region 7, drain region 8 outside the side wall 62 of grid 6 both sides, source region 7 is N
+type SiC material, drain region 8 is N
+type SiGe material, and drain region 8 is made up of shallow doped region 81 and heavily doped region 82.
The gate oxide formed in preparation gate process is also had below grid.
Source region and drain region again outside are shallow trench 5, and the bottom surface of shallow trench 5 is positioned at N-type SiC layer 2.
embodiment 2
With reference to Fig. 2, the present embodiment preparation is as follows based on the method for the heterojunction 1T-DRAM structure of buried regions N-type trap:
Step 1
With reference to method described in embodiment 1 step 1, provide P-type silicon substrate 1, N-type SiC layer 2, P type SiGe layer 3 and thin layer P-type silicon layer 4.
Step 2
With reference to the method described in embodiment 1 step 2, form shallow trench 5.
Step 3
With reference to Fig. 2 A, between adjacent two shallow trenchs 5, form grid 6.With reference to the method described in embodiment 1 step 3, similarly, gate oxide also can be retained as subsequent selective epitaxial barrier layer.
Then carry out LDD technique respectively in the both sides of grid 6, and carry out low energy Ge ion implantation, form shallow doped region, source region 71 and shallow doped region 81, drain region.
Form side wall 62.
Step 4
With reference to Fig. 2 B and the method described in embodiment 1 step 4, photoresist 10 cover gate 6, shallow trench 5 and P-type silicon layer 4, the first opening (in Fig. 2 B arrow locations) is formed in the side of grid 6 by photoetching, P-type silicon layer 4 between the shallow trench 5 of grid 6 and grid 6 side is come out, remove the P-type silicon layer 4 exposed in P first opening, P type SiGe layer 3 is come out, Plasma Etch technique is adopted to carry out selectivity Self-aligned etching by the first opening to the P type SiGe layer 3 exposed, make the P type SiGe layer thickness etched away account for P type SiGe layer gross thickness 1/5 to 4/5 between, form source region groove 70.Remove residue photoresist 10.
With reference to Fig. 2 C, in the source region groove 70 formed, carry out selective epitaxial growth N
+type SiC, to filling up source region groove 70, forms source region 7, and makes the molar content of C between 0.01% to 10%.
With reference to Fig. 1 F, photoresist 10 cover gate 6, shallow trench 5 and P type SiGe layer 3(comprise P-type silicon layer 4) and source region 7, form the second opening (in Fig. 1 F arrow locations) by photoetching at the opposite side of grid 6, being come out in shallow doped region 81, source region, carrying out drain region N to exposing region
+ion implantation technology, inject high energy Ge ion and form heavily doped region, drain region 81, this technique can refer to prior art and implements.Remove light residue and carve glue 10.
Step 5
Annealing, activates implanting impurity ion, forms N
+type SiGe drain region.
Adopt conventional NMOS technique, by source ground (GND), drain electrode connects bit line (Bit Line, BL), grid connects wordline (Word Line, WL), forms 1T-DRAM unit.
With reference to Fig. 2 E, the heterojunction 1T-DRAM structure based on buried regions N-type trap prepared by the present embodiment, compared with embodiment 1, difference is:
Between source region 7 and grid 6, there is shallow doped region, source region, and described shallow doped region is N
+type SiGe; N
+type SiC source region 7 exists only in the region between grid curb wall 62 and shallow trench 5, and the below of grid curb wall 62 does not exist N
+type SiC source region.
embodiment 3
Also can not implement LDD technique in the above embodiment of the present invention 1, but directly carry out N after forming grid curb wall 62
+ion implantation, in the case, as shown in Figure 3, the heterojunction 1T-DRAM structure based on buried regions N-type trap prepared by the present embodiment, compared with the heterojunction 1T-DRAM structure prepared in embodiment 1, difference is, there is not shallow doped region 81, drain region.
embodiment 4
Similarly, in the embodiment of the present invention 2, also can not implement LDD technique, but directly carry out N after forming grid curb wall 62
+ion implantation, in the case, as shown in Figure 4, heterojunction 1T-DRAM structure based on buried regions N-type trap prepared by the present embodiment, compared with the heterojunction 1T-DRAM structure prepared in embodiment 2, difference is, there is not the shallow doped region 71 in shallow doped region, drain region 81 and source region.
In foregoing of the present invention, symbol SiGe refers to SiGe (Silicon-germanium) alloy, and not representing Si and Ge mol ratio is 1:1, also can be other mol ratios; Similarly, symbol SiC does not also represent carbon and silicon mol ratio is 1:1, also can be other mol ratios.
Be described in detail specific embodiments of the invention above, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and substituting also all among category of the present invention.Therefore, equalization conversion done without departing from the spirit and scope of the invention and amendment, all should contain within the scope of the invention.
Claims (10)
1., based on a heterojunction 1T-DRAM structure for buried regions N-type trap, it is characterized in that, comprise bottom silicon, be positioned at the buried regions N-type trap layer above described bottom silicon and be positioned at the top layer silicon above described buried regions N-type trap layer; Also include grid and the shallow trench being positioned at grid both sides, described grid is positioned at the upper surface of described top layer silicon, and described shallow trench upper surface and described top layer silicon upper surface are in same plane, and described shallow trench bottom surface is arranged in described buried regions N-type trap; Source region and drain region is respectively in tagma layer between described grid and shallow trench;
Wherein, described top layer silicon material is P type germanium silicon, and described source region material is N
+type carborundum, described drain region material is the N after annealing
+type germanium silicon, described buried regions N-type trap layer material is N-type carborundum.
2. heterojunction 1T-DRAM structure according to claim 1, is characterized in that, described bottom silicon material is P-type silicon.
3. heterojunction 1T-DRAM structure according to claim 1, is characterized in that, in described buried regions N-type trap layer and/or source region, the molar content of carbon is 0.01% ~ 10%.
4. the heterojunction 1T-DRAM structure according to claim 1 or 3, is characterized in that, described buried regions N-type trap layer thickness >=10nm.
5. heterojunction 1T-DRAM structure according to claim 1, is characterized in that, also comprises the P-type silicon thin layer be positioned at below described grid above described top layer silicon.
6. heterojunction 1T-DRAM structure according to claim 1, is characterized in that, in described P type germanium silicon layer and described drain region, the molar content of germanium is 0.1 ~ 100%.
7. the heterojunction 1T-DRAM structure according to claim 5 or 6, is characterized in that, described P type germanium silicon layer thickness >=30nm.
8. heterojunction 1T-DRAM structure according to claim 1, is characterized in that, described source region thickness is 1/5 ~ 4/5 of described P type germanium silicon layer thickness.
9. prepare a method for heterojunction 1T-DRAM structure as claimed in claim 1, it is characterized in that, step comprises: at the bottom of underlying silicon substrate; Described silicon base generates N-type silicon carbide layer; P type germanium silicon layer is generated above described N-type silicon carbide layer;
Step 2, prepares shallow trench, and makes described shallow trench bottom surface be arranged in described N-type silicon carbide layer;
Step 3, prepares grid between adjacent two shallow trenchs;
Step 4, photoresist cover gate, shallow trench and described P type germanium silicon layer, the first opening is formed in grid side, P type germanium silicon layer between the shallow trench of grid and described grid side is come out, by the first opening, the P type germanium silicon layer exposed is etched, but be not etched to described N-type silicon carbide layer, form source region groove, remove residue photoresist; Selective growth N in the source region groove formed
+type carborundum, to filling up described source region groove, forms source region;
Photoresist cover gate, shallow trench and described P type germanium silicon layer, form the second opening at grid opposite side, the P type germanium silicon layer between the shallow trench of grid and described grid opposite side come out, carries out N by the second opening to the P type germanium silicon layer exposed
+type ion implantation, forms drain region; Remove residue photoresist;
Step 5, annealing, activates the foreign ion injected and forms N
+type germanium silicon drain region.
10. method according to claim 9, is characterized in that, described N-type silicon carbide layer thickness>=10nm, and carbon molar content is 0.01% ~ 10%; Described P type germanium silicon layer thickness>=30nm, germanium molar content is 0.1% ~ 100%; Described N
+in type germanium silicon drain region, germanium molar content is 0.1% ~ 100%.
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