CN102412204A - Single-transistor DRAM (dynamic random access memory) and preparation method thereof - Google Patents
Single-transistor DRAM (dynamic random access memory) and preparation method thereof Download PDFInfo
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- CN102412204A CN102412204A CN2011103916976A CN201110391697A CN102412204A CN 102412204 A CN102412204 A CN 102412204A CN 2011103916976 A CN2011103916976 A CN 2011103916976A CN 201110391697 A CN201110391697 A CN 201110391697A CN 102412204 A CN102412204 A CN 102412204A
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Abstract
The invention discloses a single-transistor DRAM (dynamic random access memory) and a preparation method thereof. The transistor is an NMOS (N-channel metal oxide semiconductor) transistor. The preparation method comprises the following steps: forming a P-type SiGe epitaxial layer on the part, corresponding to the drain region of the NMOS transistor, in a P-type silicon top layer of an SOI (signal operation instruction) wafer; carrying out global wafer surface dry-oxygen oxidation on the surface of the SOI chip until the content of the germanium in the P-type SiGe epitaxial layer reaches a preset mol ratio; injecting high-concentration N<+> ions into the source zone of the NMOS transistor and the P-type SiGe epitaxial layer, forming an N-type silicon source region and an N-type SiGe drain region, and then injecting C ions into the N-type silicon source region until the content of carbon in the source zone reaches a preset mol ratio; and forming an N-type SiC source zone, thus a carbon silicon-silicon-germanium silicon heterojunction single-transistor DRAM structure on an insulator is formed. The preparation method provided by the invention has the advantages that the current carrier generation speed is increased, and the current gain is increased, thereby effectively reducing the operating voltage and meanwhile increasing the signal margin.
Description
Technical field
The present invention relates generally to a kind of non-capacitor type dynamic random access memory (Capacitorless DRAM) preparation method, relate in particular to carbon silicon-silicon on a kind of insulator-Ge-Si heterojunction single-transistor dynamic random access memory (1T-DRAM) and preparation method thereof.
Background technology
Along with constantly dwindling of semiconductor device characteristic size, for traditional single-transistor/single capacitor (1T/1C) embedded (embedded) DRAM unit, (generally require 30 * 10 in order to obtain enough amount of storage capacity
-15Method/unit (fF/cell)), the preparation technology of its electric capacity (for example, stack electric capacity (stack capacitor) or zanjon slot type electric capacity (deep-trench capacitor)) becomes and becomes increasingly complex, and with the compatibility of logical device technology also worse and worse.Therefore, will in the high-performance embedded DRAM field of very lagre scale integrated circuit (VLSIC) (VLSI), good development prospect be arranged with the compatible good no electric capacity DRAM of logical device.
In recent years, 1T-DRAM (one transistor dynamic random access memory) has only 4F because of its cell size
2And become the research focus of capless DRAM.Here; 1T-DRAM is generally a silicon-on-insulator (SOI; Silicon-On-Insulator) buoyancy aid (floating body) transistor when charged in its tagma, is promptly accomplished the one writing operation through the accumulation in hole, tagma; At this moment because the accumulation in hole, tagma causes body effect, cause transistorized threshold voltage to reduce; When discharged in its tagma, the hole that promptly through body drain or body source PN junction forward bias (forward bias) its tagma is accumulated bleeds off to accomplish writes " 0 " operation, and at this moment body effect disappears, and threshold voltage recovering is normal.And read operation is the source-drain current when reading said transistor and opening, because " 1 " is different with the threshold voltage of " 0 " state, so the source-drain current of the two is also different, and when source-drain current greatly the time, what promptly represent to read is " 1 "; And when source-drain current hour, what promptly expression was read is " 0 ".
In addition, the operating characteristic about 1T-DRAM has detailed description: Ohsawa, T. in following paper; Et al.Memory design using a one-transistor gain cell on SOI (adopting the reservoir designs of silicon-on-insulator single-transistor gain unit); Solid-State Circuits; IEEE Journal; Nov2002, Volume:37Issue:11, pages:1510-1522.
At present, the maximum 1T-DRAM that is based on soi structure of research.Because the existence of oxygen buried layer (BOX) can effectively realize the accumulation in hole, tagma, therefore, has increased the difference of reading " 0 " and reading output current between " 1 ", has promptly increased signal margin (margin).But, still there is the problem of following two aspects based on the 1T-DRAM of soi structure:
1. the hole potential barrier restriction in body potential receptor area and source region and drain region; That is to say that because conventional Si semiconductor energy gap is limited, the variation of body potential is restricted; Variations in threshold voltage less (generally having only about 0.3V), this makes that the signal code of reading is less;
2. ionization by collision is controlled by the body drain potential barrier, therefore, should adopt than the narrower semiconductor of conventional Si semiconductor energy gap as the drain region, to increase the ionization by collision effect, increases the hole, tagma and produces speed, increases the read-write speed of 1T-DRAM unit.
In addition, prior art (Chinese patent, application number: 200910088876.5) also disclose source region and the drain region of a kind of SiC of employing,, improved signal code and retention time (retention time) to improve the hole potential barrier of body source, body drain as 1T-DRAM.But its body drain knot ionization by collision effect can be affected because of barrier height rises, thereby has reduced the generation speed in hole, tagma, has reduced the read-write speed of 1T-DRAM unit.
Summary of the invention
In order to overcome the defective of prior art; Main purpose of the present invention is to provide carbon silicon-silicon on a kind of insulator-Ge-Si heterojunction single-transistor DRAM structure and preparation method thereof; More specifically; The capless 1T-DRAM cellular construction that has good development prospect to high-performance embedded DRAM field among the VLSI; Propose the method that a kind of body source and body drain adopt different heterojunction respectively, realize running off through source body PN junction in the high hole potential barrier hole, tagma when suppressing one state between body source, thus the retention time that effectively increases 1T-DRAM; And the low potential barrier between the realization body drain increases thereby make charge carrier produce speed to increase the ionization by collision effect, and current gain increases.
For realizing above-mentioned purpose; The invention provides a kind of single-transistor DRAM preparation method; Said transistor is a nmos pass transistor, and said method comprises the steps: that the position, drain region corresponding to nmos pass transistor forms P type SiGe epitaxial loayer in the P type silicon top layer of silicon-on-insulator SOI wafer; Said SOI wafer surface is carried out overall waferization surface dry-oxygen oxidation, and the Ge content in said P type SiGe epitaxial loayer reaches preset mol ratio; And the source region and the said P type SiGe epitaxial loayer that high concentration N+ ion are injected said nmos pass transistor; Form N type silicon source region and N type SiGe drain region; Again the C ion is injected said N type silicon source region; Carbon content in said N type SiC source region reaches preset mol ratio, forms N type SiC source region, to form carbon silicon-silicon-Ge-Si heterojunction single-transistor DRAM structure on the insulator.
The present invention also provides a kind of single-transistor DRAM, comprising: silicon-on-insulator SOI wafer comprises P type silicon top layer; N type SiC source region and N type SiGe drain region are formed in the P type silicon top layer of said SOI wafer, and Ge content reaches preset mol ratio in the said N type SiGe drain region.
In sum, the present invention is directed to the capless 1T-DRAM cellular construction that high-performance embedded DRAM field has good development prospect among the VLSI, propose a kind of based on P-Si tagma (body)+N
+-SiC source region+N
+The 1T-DRAM cell process preparation method in-SiGe drain region.Because the PN junction between body and the source is P-Si/N
+-SiC heterojunction, SiC are a kind of wide bandgap semiconductors, and its conduction band and Si's is close, and valence band less than between the about 0eV～0.5eV of the valence band of silicon (through regulating Si
1-yC
yThe chemistry mole of middle Si and C is recently realized different value), thus make P-Si and N
+The valence band of-SiC with a bigger skew (offset) is arranged, therefore, in the time of can effectively suppressing one state run off through source body PN junction in the hole, tagma, thus the retention time that effectively increases 1T-DRAM.Simultaneously, because N is adopted in the drain region
+-SiGe, its energy gap is come narrowly than Si, makes the ionization by collision effect of 1T-DRAM increase, and increases thereby make charge carrier produce speed, and current gain increases, and effectively reduces operating voltage.In a word, based on P-Si tagma+N
+-SiC source region+N
+The 1T-DRAM cellular construction in-SiGe drain region can reduce operating voltage effectively, has increased the difference of reading " 0 " and reading the output current between " 1 " again simultaneously, has promptly increased signal margin (margin).
Description of drawings
Fig. 1 to Fig. 3 is the figure that the read-write operation method of the 1T-DRAM that adopts the ionization by collision effect is shown;
Fig. 4 illustrates the figure that transistor is in source-drain current when opening and difference thereof;
Fig. 5 to Figure 15 is the cutaway view that illustrates according to carbon silicon-silicon-Ge-Si heterojunction single-transistor DRAM on the insulator among the preparation method of carbon silicon-silicon on the insulator of the embodiment of the invention-Ge-Si heterojunction single-transistor DRAM.
Embodiment
To describe specific embodiment of the present invention in detail below.Should be noted that the embodiments described herein only is used to illustrate, be not limited to the present invention.
Usually; Difference according to the one writing method of operation; 1T-DRAM can be divided into two types; Accumulate the hole in the tagma through ionization by collision (impact-ionization) when one type of employing transistor works in the saturation region, (GIDL, gate-induced-drain-leakage) effect accumulates the hole in the tagma in another kind of employing gate-induced drain leakage.Wherein, for the 1T-DRAM that adopts the ionization by collision effect, its read-write operation method such as Fig. 1 are to shown in Figure 4.
Fig. 1 to Fig. 3 is the figure that the read-write operation method of the 1T-DRAM that adopts the ionization by collision effect is shown.
As shown in Figure 1, in carrying out the one writing operation, the 1T-DRAM cell operation is injected the tagma with the hole when the saturation region.
As shown in Figure 2, in writing " 0 " operation, the PN junction forward bias discharges the hole from the tagma.
As shown in Figure 3, in carrying out read operation, the 1T-DRAM cell operation is in linear zone, makes the generation of difference of drain current depend on the number (bulk effect) in the hole of tagma accumulation.
Fig. 4 illustrates the figure that transistor is in source-drain current when opening and difference thereof.
As shown in the figure, wherein, V
GsBe the voltage between transistorized gate terminal and the source terminal, I
DsBe the electric current between transistor drain end and the source terminal (being source-drain current), I
0And I
1Be respectively V
GsReach V
WLreadThe time source-drain current and the source-drain current under the one state under " 0 " state of reading, Δ I
DsBe the difference of source-drain current under the above-mentioned two states, and satisfy following formula:
ΔI
ds＝I
1-I
0＝f(V
WLraad，ΔV
body，t
ax，N
A)
Wherein, V
WLraadWL institute making alive during the expression read operation, Δ V
BodyThe expression body potential is poor, t
OxExpression grid oxide layer thickness, N
AExpression tagma acceptor (acceptor) concentration, f (V
WLraad, Δ V
Body, t
Ax, N
A) function of difference of expression source-drain current, yet, the invention is not restricted to this, anyly can realize that function of the present invention all can be applied to the present invention.
The present invention is directed to the capless 1T-DRAM cellular construction that high-performance embedded DRAM field has good development prospect among the VLSI, propose a kind of based on P-Si tagma (body)+N
+-SiC source region+N
+The 1T-DRAM cell process preparation method in-SiGe drain region.Because the PN junction between tagma and the source region is P-Si/N
+-SiC heterojunction, SiC are a kind of wide bandgap semiconductors, and its conduction band and Si's is close, and valence band less than between the about 0eV～0.5eV of the valence band of silicon (through regulating Si
1-yC
yThe chemistry mole of middle Si and C is recently realized different value), thus make P-Si and N
+The valence band of-SiC with a bigger skew (offset) is arranged, therefore, in the time of can effectively suppressing one state run off through source body PN junction in the hole, tagma, thus the retention time that effectively increases 1T-DRAM.Simultaneously, because N is adopted in the drain region
+-SiGe, its energy gap is come narrowly than Si, makes the ionization by collision effect of 1T-DRAM increase, and increases thereby make charge carrier produce speed, and current gain increases, and effectively reduces operating voltage.In a word, based on P-Si tagma+N
+-SiC source region+N
+The 1T-DRAM cellular construction in-SiGe drain region can reduce operating voltage effectively, has increased the difference of reading " 0 " and reading output current between " 1 " again simultaneously, has promptly increased signal margin.
Fig. 5 to Figure 15 is the cutaway view that illustrates according to carbon silicon-silicon-Ge-Si heterojunction single-transistor DRAM on the insulator among the preparation method of carbon silicon-silicon on the insulator of the embodiment of the invention-Ge-Si heterojunction single-transistor DRAM.
As shown in the figure, according to a particular embodiment of the invention, the preparation method of carbon silicon-silicon on the said insulator-Ge-Si heterojunction single-transistor DRAM cellular construction comprises the steps:
At first, preparation silicon-on-insulator (SOI) wafer, because the technology of preparing of SOI wafer is very ripe now, the present invention can select for use one of existing SOI wafer preparation technology to accomplish said step.As shown in Figure 5, formed SOI wafer comprises substrate, be positioned at the oxygen buried layer (BOX) on the said substrate and be positioned at the P-Si layer (i.e. the first conduction type Si layer) as the top layer of SOI wafer on the BOX layer.
Next; As shown in Figure 6, on formed SOI wafer, carry out hard mask (HM, Hard Mask) layer deposition; Wherein said hard mask layer generally adopts silicon nitride; Then, the most said hard mask layer is carried out technologies such as photoetching, etching, have hard mask layer corresponding to the drain region window in the drain region of nmos pass transistor with formation.
Then, as shown in Figure 7, in the window of drain region, top layer (being the P-Si layer) is etched into to a certain degree, make above the BOX layer, to stay skim that as the inculating crystal layer of follow-up SiGe epitaxial loayer, wherein said thin layer can be silicon layer.
Then, as shown in Figure 8, carry out SiGe selective epitaxial growth (SEG, selective epitaxial growth) based on said inculating crystal layer, make the full Si of growth in the extension window (being aforesaid drain region window)
1-xGe
xLayer.
Then, as shown in Figure 9, through wet-etching technology, remove said hard mask layer.
Next, shown in figure 10, carry out globalize wafer surface dry-oxygen oxidation, here " globalize wafer surface dry-oxygen oxidation " is meant Si layer and SiGe laminar surface carried out dry-oxygen oxidation.Si
1-xGe
xLayer concentrates (being that germanium concentrates) downwards through oxidation, and the silicon seed layer below getting into, thereby obtains the higher germanium silicon layer of concentration, and forms SiO on the surface
2Layer is up to Si
1-xGe
xGe content in the layer reaches required mol ratio (Si for example
0.9Ge
0.1) after just stop dry-oxygen oxidation technology, wherein, through regulating this mol ratio scalable Si
1-xGe
xThe energy gap of layer, wherein, x is big more, and energy gap is more little.
Then, shown in figure 11, through wet-etching technology, remove said surperficial SiO
2Layer.Owing to simultaneously Si layer and SiGe laminar surface are carried out dry-oxygen oxidation, are therefore removing surperficial SiO
2Behind the layer, Si layer and SiGe laminar surface are also basically on same plane.
Then; Shown in figure 12; Prepare shallow trench isolation region through on the P-Si laminar surface of the SOI wafer that is positioned at both sides, P-Si tagma, forming photoresist film (PR); And carry out the preparation of subsequent P D (Partial Depletion, part depletion) nmos pass transistor in the zone between said isolated area, up to N
+Ion is injected into till source region and the drain region; Obtain shown in figure 13 thus by N
+The source region that-Si material is processed and by N
+The drain region that-SiGe material is processed, wherein said source region and said drain region lay respectively at the both sides in said P-Si tagma.
Next, shown in figure 13, through photoetching process, to open the source region window, and carry out the C ion and inject, the carbon content in said source region reaches preset mol ratio (Si for example
0.99C
0.01) till, obtain shown in figure 14 thus by N
+The source region that-SiC material is processed, wherein, through regulating this mol ratio scalable N
+Si
1-yC
yThe valence band offset amount in source region and P-Si tagma, wherein, y is big more, and the valence band offset amount is big more, and body source hole potential barrier is big more.
Then, shown in figure 14, through annealing process, activate the ion that injects, to form p-Si tagma+N
+SiC source region+N
+-SiGe drain structure.
At last, of Figure 15, carry out being about to source region ground connection (GND) with the normal identical subsequent technique of NMOS technology, the drain region connect bit line (Bit line, BL) and the grid region connect word line (Word line WL), thereby form the 1T-DRAM unit.
Continuation in one embodiment, shows a kind of single-transistor DRAM structure with reference to Figure 14, comprising: the silicon-on-insulator SOI wafer that includes P type silicon top layer; And be formed on N type SiC source region and the N type SiGe drain region in the P type silicon top layer of said SOI wafer, and Ge content reaches preset mol ratio in the said N type SiGe drain region, and carbon content reaches preset mol ratio in the said N type SiC source region.
In one embodiment, the preset mol ratio of the SiGe in the N type SiGe drain region is meant, when SiGe with Si
1-xGe
xDuring expression, the span of x satisfies 0.01≤x＜1.
In one embodiment, the preset mol ratio of the SiC in the N type SiC source region is meant, when SiC with Si
1-yC
yDuring expression, the span of y satisfies 0.001≤y＜0.1.
In sum, carbon silicon-silicon on the insulator that embodiments of the invention provide-Ge-Si heterojunction single-transistor DRAM and preparation method thereof can effectively increase the retention time of 1T-DRAM, reduces operating voltage, and increases signal margin simultaneously.
Though described the present invention with reference to exemplary embodiments, should be appreciated that used term is explanation and exemplary and nonrestrictive term.Because the present invention's practical implementation and do not break away from the spirit or the essence of invention in a variety of forms; So be to be understood that; The foregoing description is not limited to any aforesaid details; And should in enclose spirit that claim limited and scope, explain widely, therefore fall into whole variations and remodeling in claim or its equivalent scope and all should be the claim of enclosing and contain.
Claims (9)
1. single-transistor DRAM preparation method, said transistor is a nmos pass transistor, said method comprises the steps:
Position, drain region corresponding to nmos pass transistor in the P type silicon top layer of silicon-on-insulator SOI wafer forms P type SiGe epitaxial loayer;
Said SOI wafer surface is carried out overall waferization surface dry-oxygen oxidation, and the Ge content in said P type SiGe epitaxial loayer reaches preset mol ratio; And
With high concentration N
+Ion injects the source region and the said P type SiGe epitaxial loayer of said nmos pass transistor; Form N type silicon source region and N type SiGe drain region; Again the C ion is injected said N type silicon source region; Form N type SiC source region, the carbon content in said N type SiC source region reaches preset mol ratio, to form carbon silicon-silicon-Ge-Si heterojunction single-transistor DRAM structure on the insulator.
2. preparation method according to claim 1 wherein may further comprise the steps when forming P type SiGe epitaxial loayer:
P type silicon top layer to said SOI wafer carries out the hard mask layer deposition, and forms the drain region window corresponding to the drain region of said nmos pass transistor;
The P type silicon top layer of the said SOI wafer in the window of said drain region is etched to stays skim, as the silicon seed layer of said P type SiGe epitaxial loayer; And
On said silicon seed layer, carry out the SiGe selective epitaxial growth, make said P type SiGe epitaxial loayer in the window of said drain region, grow up to the topsheet surface of said SOI wafer on same plane.
3. preparation method according to claim 2, further comprising the steps of:
After forming said P type SiGe epitaxial loayer, remove said hard mask layer through etching technics.
4. according to claim 1 or 2 or 3 described preparation methods, wherein carry out may further comprise the steps after the dry-oxygen oxidation technology of overall waferization surface in said SOI wafer surface:
Remove the surperficial SiO that in dry-oxygen oxidation technology, forms through etching technics
2Layer.
5. preparation method according to claim 1, the Ge content in the wherein said P type SiGe epitaxial loayer reaches preset mol ratio and is meant, when SiGe with Si
1-xGe
xDuring expression, the span of x satisfies 0.01≤x＜1.
6. preparation method according to claim 1, the carbon content in the wherein said N type SiC source region reaches preset mol ratio and is meant, when SiC with Si
1-yC
yDuring expression, the span of y satisfies 0.001≤y＜0.1.
7. single-transistor DRAM comprises:
Silicon-on-insulator SOI wafer comprises P type silicon top layer;
N type SiC source region and N type SiGe drain region are formed in the P type silicon top layer of said SOI wafer, and Ge content reaches preset mol ratio in the said N type SiGe drain region, and carbon content reaches preset mol ratio in the said N type SiC source region.
8. single-transistor DRAM according to claim 7, the preset mol ratio of the SiGe in the wherein said N type SiGe drain region is meant, when SiGe with Si
1-xGe
xDuring expression, the span of x satisfies 0.01≤x＜1.
9. single-transistor DRAM according to claim 7, the preset mol ratio of the SiC in the wherein said N type SiC source region is meant, when SiC with Si
1-yC
yDuring expression, the span of y satisfies 0.001≤y＜0.1.
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