JP2009290069A - Semiconductor device, and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can operate at a high speed effectively, and to provide a method of manufacturing the same. <P>SOLUTION: The semiconductor device is embedded in an n-type Si substrate 2, and includes a source and a drain which are formed separately from each other so as to sandwich a channel between them, and further, has a gate formed on the channel. Each of the source and the drain includes the laminate of: a SiC material 3; and a p-type SiGe material which is formed on the whole top surface of the SiC material 3 and is made of a semiconductor material capable of giving a stress to the channel. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that applies stress to a channel.

  As a general transistor, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is widely known.

  In a conventional p-type MOSFET, the mobility of carriers is improved by forming a SiGe (silicon-germanium) layer in the source / drain regions and applying a compressive stress to the channel region (see, for example, Patent Document 1). .

US Pat. No. 6,621,131

  However, in Patent Document 1, the relative permittivity of p-type SiGe used for the source / drain regions is larger than the relative permittivity of Si (silicon) which is an n-type substrate, so that the pn between p-type SiGe and n-type Si is used. There is a problem in that a large junction capacitance is generated at the junction, which hinders high-speed operation of the transistor.

  The present invention has been made to solve these problems, and an object of the present invention is to provide a semiconductor device capable of effectively operating at high speed and a method for manufacturing the same.

  In order to solve the above problems, a semiconductor device according to an embodiment of the present invention is formed on a channel, and a source and a drain that are embedded in a semiconductor substrate of a first conductivity type and spaced apart with a channel interposed therebetween. A second conductivity type semiconductor comprising a low relative dielectric constant layer and a semiconductor material formed on the entire surface of the low relative dielectric constant layer and capable of applying stress to the channel. It consists of lamination | stacking with a layer, It is characterized by the above-mentioned.

  In one embodiment of the present invention, the semiconductor device includes a source and a drain embedded in a semiconductor substrate of the first conductivity type and spaced apart from each other with a channel interposed therebetween, and a gate formed on the channel. Effectively high speed because it consists of a laminate of a low relative dielectric constant layer and a second conductivity type semiconductor layer made of a semiconductor material that is formed on the entire surface of the low relative dielectric constant layer and can apply stress to the channel. Operation is possible.

  Embodiments of the present invention will be described below with reference to the drawings.

  First, the technology that is the premise of the present invention will be described.

  In the conventional p-type MOSFET, the carrier mobility is improved by applying compressive stress to the channel with SiGe as the source and drain. However, there is a problem in that a large junction capacitance is generated at the pn junction between the p-type SiGe as the source / drain and the n-type Si as the substrate, preventing high-speed operation of the transistor.

  As a countermeasure against this problem, MOSFETs have been proposed that reduce junction capacitance by forming SiC (silicon carbide) or C (carbon) having a low relative dielectric constant between p-type SiGe and n-type Si. .

  FIG. 13 is a configuration diagram of a conventional semiconductor device. As shown in FIG. 13, a transistor 10 that is a p-type MOSFET is embedded in an n-type Si substrate 11, and a source and a drain are formed so as to be separated with a channel interposed therebetween. In each of the source and drain, p-type SiGe 14 is formed on the upper surface of SiC 12 or C in which no impurity is implanted, and p-type SiC 13 is formed so as to surround the side surface of p-type SiGe 14. That is, the p-type SiC 13 is interposed between the p-type SiGe 14 and the n-type Si substrate 11. The gate is formed by sequentially forming a gate insulating film 15 and a gate electrode 16 on a channel, and forming a sidewall 17 on the side surfaces thereof.

  Next, a method for forming the transistor 10 illustrated in FIGS. First, recesses are formed spaced apart across the channel of the Si substrate. SiC or C is epitaxially grown on the bottom and side surfaces of the formed recess. Subsequently, SiGe is epitaxially grown so as to fill the recess portion remaining after the formation of SiC. After the formation of SiGe, p-type impurities are implanted under predetermined conditions. At this time, impurities are prevented from being implanted into SiC or C formed on the bottom surface of the recess. That is, p-type SiGe 14 is formed on the upper surface of SiC 12 or C on which no impurity is implanted, and p-type SiC 13 or C is formed so as to surround the side surface of p-type SiGe 14. Thereafter, the aforementioned gate is formed.

  In the above MOSFET, the lattice constant of Si used for the substrate is 5.43Å, and the lattice constant of SiGe used for the source and drain is greater than 5.43Å and less than or equal to 5.64Å (the lattice constant of SiGe is Si Depending on the composition ratio of Ge and Ge. Therefore, since SiGe has a larger lattice constant than Si, channel Si is compressed by SiGe. In this way, the channel is distorted by being compressed, and the mobility of carriers passing through the channel can be improved.

  The relative dielectric constant of p-type SiGe used for the source and drain is larger than 11.9 and not more than 16.0, which is higher than the relative dielectric constant of n-type Si used for the substrate. Therefore, when p-type SiGe and n-type Si are joined, a large junction capacitance is generated at the pn junction during operation. When the junction capacitance is increased, the high-speed operation of the transistor is hindered. In order to solve this problem, SiC or C is formed between p-type SiGe and n-type Si as in the above structure. Since the relative permittivity of SiC is 10.0 and the relative permittivity of C is 5.7, both have a relative permittivity lower than that of SiGe and Si. Thus, by providing the low relative dielectric constant layer, the junction capacitance of the pn junction can be reduced and the operation speed of the transistor can be improved.

  On the other hand, in the low relative dielectric constant layer, p-type SiC or p-type C is also formed between the p-type SiGe and the channel. The lattice constant of SiC is 3.08Å and the lattice constant of C is 3.56Å, which is smaller than the lattice constant of SiGe and Si. Therefore, the effect of compressing n-type Si by p-type SiGe is reduced, and the effect of improving carrier mobility in the channel is insufficient. For this reason, it is preferable to reduce the film thickness of p-type SiC or p-type C formed between p-type SiGe and n-type Si, or not to form p-type SiC or p-type C.

  The present invention is for solving the above problems, and the configuration and operation thereof will be described below.

<Embodiment 1>
1 to 5 are views showing a manufacturing process of a semiconductor device according to Embodiment 1 of the present invention. The transistor 1 according to the first embodiment includes a source and a drain that are embedded in an n-type (first conductivity type) Si substrate 2 (semiconductor substrate) and spaced apart from each other, and a gate that is formed on the channel. The source and drain are formed of SiC3 (low relative dielectric constant layer) and p-type (second conductivity type) SiGe4 (semiconductor material formed on the entire surface of SiC3 and capable of applying stress to the channel). It is characterized by comprising a laminate with a semiconductor layer. Hereinafter, a method for forming the transistor 1 according to the first embodiment will be described in detail.

  As shown in FIG. 1, a recess (first recess) is formed so as to be separated with the channel of the n-type Si substrate 2 interposed therebetween. Next, as shown in FIG. 2, SiC3 is formed by epitaxial growth in the formed recess. Then, as shown in FIG. 3, a recess (second recess) is formed again so that SiC3 has a predetermined thickness. It is desirable that the SiC3 film be etched to such a thickness that the junction capacity between the source and the drain can be reduced by the SiC3 depletion layer.

  Thereafter, as shown in FIG. 4, p-type SiGe4 made of a semiconductor material capable of applying stress to the channel is formed on the entire surface of SiC3 by epitaxial growth. The p-type impurity may be implanted simultaneously with the epitaxial growth of SiGe, or the p-type impurity may be implanted under predetermined conditions after the formation of SiGe. At this time, p-type impurities are not implanted into SiC3.

  After the formation of the p-type SiGe 4, as shown in FIG. 5, the gate insulating film 5 and the gate electrode 6 are laminated on the channel of the n-type Si substrate 2, and the side walls 7 are provided on the side surfaces thereof to form the gate. Thus, the transistor 1 is completed.

  From the above, compressive stress is applied to the channel by p-type SiGe4 to improve carrier mobility, and junction capacity is reduced by SiC3 to improve the operation speed of the transistor 1. In addition, since SiC is not formed between the p-type SiGe4 and the channel, a compressive stress can be applied to the channel more effectively, and high-speed operation can be effectively performed.

<Embodiment 2>
6 to 12 are views showing a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention. The second embodiment is characterized by further comprising n-type SiGe8 made of a semiconductor material between SiC3 and formed in the lower layer of the channel. Other configurations are the same as those of the first embodiment. Hereinafter, a method for forming the transistor 1 according to the second embodiment will be described in detail.

  As shown in FIGS. 6 and 7, n-type SiGe 8 and n-type Si 9 are sequentially formed on the n-type Si substrate 2. At this time, after forming SiGe and Si in order, the n-type impurity may be implanted into the two layers. Next, as shown in FIG. 8, recesses are formed so as to be separated with a channel formed later in n-type Si 9 interposed therebetween. After the formation of the recess, SiC is formed by epitaxial growth as shown in FIG. Then, as shown in FIG. 10, the recess is formed again so that the SiC3 has a predetermined film thickness. It is desirable that the SiC3 film be etched to such a thickness that the junction capacity between the source and the drain can be reduced by the SiC3 depletion layer.

  Thereafter, as shown in FIG. 11, p-type SiGe4 made of a semiconductor material capable of applying stress to the channel is formed on the entire surface of SiC3 by epitaxial growth. The p-type impurity may be implanted simultaneously with the epitaxial growth of SiGe, or the p-type impurity may be implanted under predetermined conditions after the formation of SiGe. At this time, p-type impurities are not implanted into SiC3.

  After forming the p-type SiGe4, as shown in FIG. 12, the gate insulating film 5 and the gate electrode 6 are laminated on the channel of the n-type Si9, and the side walls 7 are provided on the side surfaces thereof to form the gate. Transistor 1 is completed.

  From the above, since the channel is further given a compressive stress from the n-type SiGe in addition to the compressive stress from the p-type SiGe4 formed in the source / drain, the carrier movement in the channel is higher than that in the first embodiment. The degree is further improved. Therefore, high-speed operation can be performed more effectively.

  In the embodiment of the present invention, SiC3 is used as the low relative dielectric constant layer, but any layer having a low relative dielectric constant such as C may be used. Moreover, although p-type SiGe4 is used as a semiconductor material capable of applying stress to the channel, any material may be used as long as it provides a compression effect to the channel.

  In the present embodiment, the p-type MOSFET has been described, but the same effect can be achieved with an n-type MOSFET. In the case of an n-type MOSFET, a p-type Si substrate may be used, and the p-type SiGe in this embodiment may be n-type SiC.

It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 1 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is a figure which shows the manufacturing process of the semiconductor device by Embodiment 2 of this invention. It is a block diagram of the conventional semiconductor device.

Explanation of symbols

  1 transistor, 2 n-type Si substrate, 3 SiC, 4 p-type SiGe, 5 gate insulating film, 6 gate electrode, 7 sidewall, 8 n-type SiGe, 9 n-type Si, 10 transistor, 11 n-type Si substrate, 12 SiC, 13 p-type SiC, 14 p-type SiGe, 15 gate insulating film, 16 gate electrode, 17 sidewall.

Claims (8)

A source and a drain embedded in a semiconductor substrate of the first conductivity type and spaced apart with a channel interposed therebetween;
A gate formed on the channel;
With
The source and the drain are formed of a low relative dielectric constant layer and a second conductivity type semiconductor layer formed on the entire surface of the low relative dielectric constant layer and made of a semiconductor material capable of applying stress to the channel. A semiconductor device comprising a stack.   2. The semiconductor device according to claim 1, further comprising a semiconductor layer of a first conductivity type made of the semiconductor material formed between the low relative dielectric constant layers and under the channel.   The semiconductor device according to claim 1, wherein the semiconductor material is made of SiGe.   The semiconductor device according to claim 1, wherein the low relative dielectric constant layer is made of SiC or C. (A) forming a first recess so as to be spaced apart across a channel of a first conductivity type semiconductor substrate;
(B) after the step (a), forming a low relative dielectric constant layer in each of the first recesses;
(C) after the step (b), forming a second recess so that the low relative dielectric constant layer has a predetermined thickness;
(D) after the step (c), forming a second conductivity type semiconductor layer made of a semiconductor material capable of applying stress to the channel over the entire surface of the low relative dielectric constant layer;
(E) after the step (d), forming a gate on the channel;
A method for manufacturing a semiconductor device.   6. The semiconductor according to claim 5, further comprising a step of forming a first conductivity type semiconductor layer made of the semiconductor material between the low dielectric constant layers and below the channel. Device manufacturing method.   The method for manufacturing a semiconductor device according to claim 5, wherein the semiconductor material is made of SiGe.   The method of manufacturing a semiconductor device according to claim 5, wherein the low relative dielectric constant layer is made of SiC or C.

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