JP5166789B2 - Semiconductor device - Google Patents

Description

The present invention is an invention relating to a semiconductor equipment, for example, by generating a strain in the channel region, can be applied to a semiconductor equipment which can improve the carrier mobility.

  As a transistor used in a semiconductor device, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is widely known. In addition, in order to improve the carrier mobility in the channel region, there is a technique for forming a SiGe layer in the source / drain region in the P-MOSFET.

  In the P-MOSFET, a stacked body (gate structure) including a gate insulating film and a gate electrode is formed on an n-type silicon substrate. Therefore, the channel region below the gate structure is n-type silicon. Further, source / drain regions made of P-type SiGe are formed in the surface of the semiconductor substrate on both sides of the gate structure. Thus, a SiGe layer containing germanium having a lattice constant larger than that of silicon is formed in the source / drain regions. Therefore, compressive strain is formed in the channel region made of silicon. With the compressive strain, the mobility of holes in the channel region can be improved.

  Note that, in a semiconductor device having a p-type channel, Patent Document 1 discloses a technique for improving the hole mobility in the channel region by applying uniaxial compressive stress to the p-type channel region from the SiGe layer.

JP 2006-186240 A

  As described above, in the P-MOSFET, a p-type SiGe layer is formed in the source / drain regions. Here, the relative dielectric constant of the SiGe layer is larger than the dielectric constant of silicon. Therefore, by adopting the above-described conventional technique, a large junction capacitance exists at the pn junction between the source / drain region composed of the p-type SiGe layer and the n-type silicon substrate during transistor operation. The presence of the large junction capacitance is a cause of hindering high-speed operation of the transistor.

  In view of the above, an object of the present invention is to provide a semiconductor device that can improve carrier mobility in a channel region and can increase the operation speed.

In one embodiment according to the present invention, the following semiconductor device is disclosed. That is, a semiconductor substrate having a first conductivity type, a gate structure formed on the semiconductor substrate, and an electrode region having a second conductivity type formed in the surface of the semiconductor substrate on both sides of the gate structure Is provided. Further, a low relative dielectric constant layer having a relative dielectric constant smaller than the relative dielectric constant of the electrode region or smaller than that of the semiconductor substrate is formed immediately below the electrode region.
The semiconductor substrate is n-type silicon, the electrode region is p-type SiGe, and the low relative dielectric constant layer is SiC or C. Alternatively, the semiconductor substrate is p-type silicon, the electrode region is n-type SiC, and the low relative dielectric constant layer is SiC or C.

  According to the above embodiment, the mobility of carriers in the channel region can be improved. Furthermore, the junction capacitance of the pn junction between the electrode region and the semiconductor substrate can be reduced. Therefore, the operation speed of the semiconductor device can be increased.

  Hereinafter, the present invention will be specifically described with reference to the drawings showing embodiments thereof.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a P-MOSFET 1 according to the present embodiment.

  The P-MOSFET 1 includes a semiconductor substrate 2 containing n-type impurities and made of silicon (that is, the semiconductor substrate 2 is n-type). On the semiconductor substrate 2, a stacked body (hereinafter referred to as a gate structure G1) in which the gate insulating film 3 and the gate electrode 4 are stacked in this order is formed. A sidewall film 10 is formed on the side surface of the gate structure G1.

  A p-type SiGe (silicon germanium) layer (which can be grasped as an electrode region) 5 is formed in the surface of the semiconductor substrate 2 on both sides of the gate structure G1. Here, a p-type SiC (silicon carbide) layer 7 (or a p-type C (carbon) layer 7) is formed adjacent to the SiGe layer 5 so as to surround the SiGe layer 5. The SiGe layer 5 and the SiC layer 7 (or C layer 7) constitute a source / drain region of the P-MOSFET 1.

  Furthermore, in the P-MOSFET 1 according to the present embodiment, the SiC layer 6 (or C layer 6) (low relative dielectric constant layer is grasped adjacent to the bottoms of the SiGe layer 5 and the SiC layer 7 (or C layer 7). Can be formed). Here, both SiC layer 6 and C layer 6 are not doped with impurities having a predetermined conductivity type. A channel region is formed near the surface of the semiconductor substrate 2 below the gate structure G1 (in other words, between the source and drain regions).

  An example of a method for forming the p-type SiGe layer 5, the non-doped SiC layer 6, and the p-type SiC layer 7 is as follows.

  First, the upper surface of the semiconductor substrate 2 on both sides of the gate structure G1 is shaved. That is, a recess is formed in the surface of the semiconductor substrate 2 on both sides of the gate structure G1. Next, SiC is grown on the bottom surface and both side surfaces of the recess by epitaxial growth. Next, SiGe is grown by another epitaxial growth so as to fill the recess in which SiC is partially formed. Thereafter, p-type impurities are implanted under predetermined conditions. The impurities do not reach the position where the reference numeral 6 is formed. Through the above steps, a p-type SiGe layer 5, a non-doped SiC layer 6, and a p-type SiC layer 7 are formed on the semiconductor substrate 2 as shown in FIG.

  As described above, the channel region exists between the SiGe layers 5. Here, the lattice constant of silicon in the channel region is 5.43Å, and the lattice constant of the SiGe layer 5 is greater than 5.43 and less than or equal to 5.64 (depending on the composition ratio of Si and Ge) Also vary within the above range). Therefore, the SiGe layer 5 having a lattice constant larger than that of silicon compresses the silicon in the channel region. Thus, since the channel region is compressed and distortion occurs, the hole mobility in the channel region can be improved.

  Furthermore, the operation of the P-MOSFET 1 according to the present embodiment can be speeded up. The description of the effect will be made in comparison with the prior art shown in FIG.

  In the prior art, as shown in FIG. 2, the P-MOSFET 100 includes an n-type silicon substrate 101, a gate insulating film 102, a gate electrode 103, a p-type SiGe layer 104 formed in the source / drain regions, and a side surface. The wall film 110 is used. As shown in FIG. 2, the channel region made of silicon is surrounded by the SiGe layer 5 having a lattice constant larger than that of silicon. Therefore, as described above, the hole mobility in the channel region can be improved.

  In the configuration shown in FIG. 2, a junction capacitance is generated at the pn junction between the silicon substrate 101 and the SiGe layer 104. Here, the relative dielectric constant of the SiGe layer 104 is larger than 11.9, 16.0 or less, and higher than the relative dielectric constant of silicon of 11.9. Therefore, when the SiGe layer 104 is formed in the source / drain region from the viewpoint of improving the hole mobility in the channel region, the junction at the pn junction is compared with the case where the source / drain region is simply composed of silicon. Capacity becomes large. The large junction capacitance makes it difficult to increase the transistor operation speed.

  On the other hand, in the P-MOSFET 1 according to the present embodiment shown in FIG. 1, a non-doped SiC layer 6 (or a non-doped C layer 6) is formed immediately below the SiGe layer 5. Here, the relative dielectric constant of the SiC layer 6 is 10.0, the relative dielectric constant of the C layer 6 is 5.7, and both are smaller than the relative dielectric constant of the SiGe layer 5 and smaller than the relative dielectric constant of Si. .

  Therefore, the junction capacitance of the pn junction of the source / drain region 5 and the capacitance composed of the SiC layer 6 (or the capacitance composed of the C layer 6) are interchanged, and the source / drain region 5 and the SiC layer 6 (or C layer 6) Will be connected in series. Therefore, the junction capacitance in the pn junction portion of the source / drain region can be reduced as compared with the configuration shown in FIG. Since the junction capacitance can be reduced, the operation speed of the transistor can be increased.

  In addition, when the said formation method is employ | adopted, the SiC layer 7 (or C layer 7) will be formed adjacent to the SiGe layer 5. FIG. However, from the viewpoint of the lattice constant and the occurrence of compressive strain in the channel region due to the lattice constant, it is preferable that the SiC layer 7 (or C layer 7) having a smaller lattice constant than silicon be made thinner. Alternatively, it is more preferable not to form SiC layer 7 (or C layer 7) by adopting another forming method.

  The thickness of the depletion layer when the SiC layer 6 (or C layer 6) is depleted is determined in the source / drain region (more specifically, between the p-type SiGe layer 5 and the n-type silicon substrate 2). It is desirable that the thickness be equal to or greater than the thickness of the depletion layer of the pn junction. By setting the thickness of SiC layer 6 (or C layer 6) as described above, the junction capacitance at the pn junction can be further reduced.

  In the present embodiment, SiC layer 6 (or C layer 6) is non-doped, but may be doped with p-type impurities.

  Further, the low relative dielectric constant layer 6 formed immediately below the SiGe layer 5 (electrode region) is not SiC or C if the relative dielectric constant is smaller than the relative dielectric constant of the electrode region 5 or the relative dielectric constant of the semiconductor substrate 2. It may be configured as follows.

<Embodiment 2>
FIG. 3 is a cross-sectional view showing the configuration of the N-MOSFET 11 according to the present embodiment.

  The N-MOSFET 11 includes a semiconductor substrate 12 containing p-type impurities and made of silicon (that is, the semiconductor substrate 12 is p-type). On the semiconductor substrate 12, a stacked body (hereinafter referred to as a gate structure G2) in which the gate insulating film 13 and the gate electrode 14 are stacked in this order is formed. A sidewall film 20 is formed on the side surface of the gate structure G2.

  An n-type SiC (silicon carbide) layer (which can be grasped as an electrode region) 15 is formed in the surface of the semiconductor substrate 12 on both sides of the gate structure G2. The SiC layer 15 constitutes a source / drain region of the N-MOSFET 11.

  Furthermore, in N-MOSFET 11 according to the present embodiment, SiC layer 16 (or C layer 16) (which can be grasped as a low dielectric constant layer) is formed adjacent to the bottom of SiC layer 15. Here, both SiC layer 16 and C layer 16 are not doped with impurities having a predetermined conductivity type. A channel region is formed near the surface of the semiconductor substrate 12 below the gate structure G2 (in other words, between the source and drain regions).

  An example of a method for forming the n-type SiC layer 15 and the non-doped SiC layer 16 is as follows.

  First, the upper surface of the semiconductor substrate 12 on both sides of the gate structure G2 is shaved. That is, a recess is formed in the surface of the semiconductor substrate 12 on both sides of the gate structure G2. Next, SiC is grown in the recess so as to fill the recess by epitaxial growth. Thereafter, n-type impurities are implanted under predetermined conditions. The impurities do not reach the position where the reference numeral 16 is formed. Through the above steps, as shown in FIG. 3, n-type SiC layer 15 and non-doped SiC layer 16 are formed on semiconductor substrate 12.

  As described above, the channel region exists between the SiC layers 15. Here, the lattice constant of silicon in the channel region is 5.43Å, and the lattice constant of the SiC layer 15 is 3.08. Therefore, SiC layer 15 having a lattice constant smaller than that of silicon pulls silicon in the channel region. Thus, tensile strain occurs in the channel region, so that the electron mobility in the channel region can be improved.

  Further, the N-MOSFET 11 according to the present embodiment can increase the operation speed. The description of the effect will be made in comparison with the configuration shown in FIG.

  The N-MOSFET 200 shown in FIG. 4 includes a p-type silicon substrate 151, a gate insulating film 152, a gate electrode 153, an n-type SiC layer 154 formed in the source / drain regions, and a sidewall film 160. Yes. As shown in FIG. 4, a channel region made of silicon is surrounded by a SiC layer 154 having a lattice constant smaller than that of silicon. Therefore, as described above, the electron mobility in the channel region can be improved. In the configuration shown in FIG. 4, a junction capacitance is generated at the pn junction between silicon substrate 151 and SiC layer 154.

  On the other hand, in the N-MOSFET 11 according to the present embodiment shown in FIG. 3, a non-doped SiC layer 16 (or a non-doped C layer 16) is formed immediately below the n-type SiC layer 15. Here, the relative permittivity of the SiC layer 16 is 10.0, the relative permittivity of the C layer 16 is 5.7, and both are smaller than the relative permittivity of Si (= 11.9) (in the C layer 16). Is smaller than the relative dielectric constant of the SiC layer 15).

  Therefore, the source / drain region 15 and the non-doped SiC layer 16 (or the non-doped SiC layer 16) are interchanged by switching the junction capacitance of the pn junction of the source / drain region 15 and the capacitance (or the capacitance consisting of the non-doped C layer 16). A capacitor composed of the C layer 16) is connected in series. Therefore, the junction capacitance at the pn junction in the source / drain region can be reduced as compared with the configuration shown in FIG. Since the junction capacitance can be reduced, the operation speed of the transistor can be increased.

  The thickness of the depletion layer when the non-doped SiC layer 16 (or the non-doped C layer 16) is depleted is determined in the source / drain regions (more specifically, the n-type SiC layer 15 and the p-type silicon substrate). It is desirable that the thickness be equal to or greater than the thickness of the depletion layer of the pn junction (between 12). By setting the thickness of SiC layer 16 (or C layer 16) as described above, the junction capacitance at the pn junction can be further reduced.

  Further, the low relative dielectric constant layer 16 formed immediately below the SiC layer (electrode region) 15 is non-doped SiC or C if the relative dielectric constant is smaller than the relative dielectric constant of the electrode region 15 or the relative dielectric constant of the semiconductor substrate 12. Other configurations may be used. The low relative dielectric constant layer 16 may be non-doped or doped with n-type impurities.

<Embodiment 3>
The semiconductor device 21 according to the present embodiment is the same as the configuration of the semiconductor device 1 according to the first embodiment except for the following configuration.

  That is, as shown in FIG. 5, in the semiconductor device 21 according to the present embodiment, in the semiconductor substrate 2 below the gate structure G1, the n-type silicon layer 8 (or n-type silicon) is arranged in order from the gate structure G1. The layer 8 is not formed), the n-type SiGe layer 9, and the n-type silicon layer 2 are formed in a three-layer structure (or a two-layer structure).

  Here, the SiGe layer 9 may contain an n-type impurity, or the SiGe layer 9 may be non-doped. However, it is more desirable that the SiGe layer 9 contains an n-type impurity from the viewpoint of improving the mobility in the channel region.

  Next, an example of a method for forming the n-type SiGe layer 9 and the n-type silicon layer 8 will be described.

  An n-type SiGe layer 9 is formed on the upper surface of the semiconductor substrate 2 by performing an epitaxial growth process on the upper surface of the semiconductor substrate 2 made of n-type silicon. Next, the n-type SiGe layer 9 is subjected to an epitaxial growth process under different conditions. Thereby, the n-type silicon layer 8 is formed on the n-type SiGe layer 9. Alternatively, a predetermined impurity implantation process is performed on the non-doped epitaxial two-layer film. Thereby, for example, the n-type SiGe layer 9 and the n-type silicon layer 8 are formed (the above-mentioned three-layer structure).

  In the case of the two-layer structure, the upper n-type silicon layer 8 is not formed.

  Thereafter, a gate structure G1 is formed on the silicon layer 8. Then, the semiconductor substrate 2 (more specifically, the silicon layer 8 or the SiGe layer 9) on both sides of the gate structure G1 is partially removed to form a recess portion. Since the subsequent formation methods of reference numerals 5 to 7 are the same as those in the first embodiment, description thereof is omitted here.

  As described above, in this embodiment, the SiGe layer 9 is formed below the silicon layer 8 where the channel region is formed. Here, due to compression of the source / drain regions, strong compressive strain is generated in the SiGe layer 9 and the silicon layer 8 (only the SiGe layer 9 when the silicon layer 8 is not formed). Furthermore, the lattice constant of the SiGe layer 9 is larger than that of silicon. Therefore, the silicon layer 8 in which the channel region is formed is induced by the SiGe layer 9 having a larger lattice constant, and a stronger compressive strain is generated. Therefore, compared with the structure of Embodiment 1, this Embodiment can improve the mobility of the hole in a channel area | region more.

  Needless to say, the P-MOSFET 21 according to the third embodiment has the effect of the P-MOSFET 1 according to the first embodiment.

<Embodiment 4>
The semiconductor device 31 according to the present embodiment is the same as the configuration of the semiconductor device 11 according to the second embodiment except for the following configuration.

  That is, as shown in FIG. 6, in the semiconductor device 31 according to the present embodiment, in the semiconductor substrate 12 below the gate structure G2, the p-type silicon layer 18 (or p-type silicon layer) is arranged in order from the gate structure G2. 18), a p-type SiC layer 19 and a p-type silicon layer 12 are formed in a three-layer structure (or a two-layer structure).

  Here, the SiC layer 19 may contain p-type impurities, or the SiC layer 19 may be non-doped. However, from the viewpoint of improving the mobility in the channel region, it is more desirable that the SiC layer 19 contains a p-type impurity.

  Next, an example of a method for forming the p-type SiC layer 19 and the p-type silicon layer 18 will be described.

  By performing an epitaxial growth process on the upper surface of the semiconductor substrate 12 made of p-type silicon, a p-type SiC layer 19 is formed on the upper surface of the semiconductor substrate 12. Next, an epitaxial growth process is performed on the p-type SiC layer 19 under different conditions. Thereby, the p-type silicon layer 18 is formed on the p-type SiC layer 19. Alternatively, a predetermined impurity implantation process is performed on the non-doped epitaxial two-layer film. Thereby, for example, p-type SiC layer 19 and p-type silicon layer 18 are formed (the above three-layer structure).

  In the case of the two-layer structure, the upper p-type silicon layer 18 is not formed.

  Thereafter, the gate structure G <b> 2 is formed on the silicon layer 18. Then, the semiconductor substrate 12 (more specifically, the silicon layer 18 or the SiC layer 19) on both sides of the gate structure G2 is partially removed to form a recess portion. Since the subsequent formation methods of reference numerals 15 and 16 are the same as those of the second embodiment, description thereof is omitted here.

  As described above, in the present embodiment, SiC layer 19 is formed below silicon layer 18 where the channel region is formed. Here, due to the pulling of the source / drain regions 15, a strong tensile strain is generated in the SiC layer 19 and the silicon layer 18 (only the SiC layer 19 when the silicon layer 18 is not formed). Furthermore, the lattice constant of SiC layer 19 is smaller than the lattice constant of silicon. Therefore, the silicon layer 18 in which the channel region is formed is induced by the SiC layer 19 having a smaller lattice constant, and a stronger tensile strain is generated. Therefore, compared with the structure of Embodiment 2, the mobility of electrons in the channel region can be improved more in this embodiment.

  Needless to say, the N-MOSFET 31 according to the fourth embodiment has the effect of the N-MOSFET 11 according to the second embodiment.

<Embodiment 5>
The present embodiment relates to a CMOSFET provided with the configuration according to the first embodiment and the configuration according to the second embodiment. FIG. 7 is a cross-sectional view showing the configuration of the CMOSFET 50 according to the present embodiment.

  As shown in FIG. 7, the semiconductor substrate 51 made of silicon has a first region and a second region. In the first region, the P-MOSFET according to the first embodiment is formed. In the second region, the N-MOSFET according to the second embodiment is formed. As shown in FIG. 7, each transistor is electrically isolated from the element isolation film 52. A first well region 53 into which an n-type impurity is implanted is formed in the semiconductor substrate 51 in the first region. On the other hand, in the semiconductor substrate 51 in the second region, a second well region 54 into which p-type impurities are implanted is formed.

  The configuration of the P-MOSFET formed in the first region is the same as that in the first embodiment.

  That is, on the first well region 53 of the first region, a stacked body (hereinafter referred to as a gate structure G1) in which the gate insulating film 3 and the gate electrode 4 are stacked in this order is formed. A sidewall film 10 is formed on the side surface of the gate structure G1.

  A p-type SiGe (silicon-germanium) layer 5 is formed in the surface of the first well region 53 on both sides of the gate structure G1. Here, in the present embodiment, a case where the p-type SiC layer 7 (or the p-type C layer 7) described in the first embodiment is not formed will be described. Therefore, the SiGe layer 5 constitutes the first source / drain region of the P-MOSFET.

  Further, an SiC layer 6 (or C layer 6) is formed adjacent to the bottom of the SiGe layer 5. Here, both SiC layer 6 and C layer 6 are not doped with impurities having a predetermined conductivity type. A channel region is formed near the surface of the first well region 53 below the gate structure G1 (in other words, between the first source / drain regions).

  Here, the SiC layer 6 (or C layer 6) can be grasped as the first low relative dielectric constant layer. The first low relative dielectric constant layer 6 formed immediately below the first source / drain region is smaller than the relative dielectric constant of the SiGe layer 5 constituting the first source / drain region. Alternatively, the first low relative dielectric constant layer 6 is smaller than the relative dielectric constant of the first well region 53.

  The configuration of the N-MOSFET formed in the second region is the same as that in the second embodiment.

  That is, on the second well region 54 in the second region, a stacked body (hereinafter referred to as a gate structure G2) in which the gate insulating film 13 and the gate electrode 14 are stacked in this order is formed. A sidewall film 20 is formed on the side surface of the gate structure G2.

  An n-type SiC (silicon carbide) layer 15 is formed in the surface of the second well region 54 on both sides of the gate structure G2. The SiC layer 15 forms a second source / drain region of the N-MOSFET.

  Further, SiC layer 16 (or C layer 16) is formed adjacent to the bottom of SiC layer 15. Here, both SiC layer 16 and C layer 16 are not doped with impurities having a predetermined conductivity type. A channel region is formed near the surface of the second well region 54 below the gate structure G2 (in other words, between the second source / drain regions).

  Here, the SiC layer 16 (or C layer 16) can be grasped as a second low relative dielectric constant layer. The second low relative dielectric constant layer 16 formed immediately below the second source / drain region is smaller than the relative dielectric constant of the SiC layer 15 constituting the first source / drain region. Alternatively, the second low relative dielectric constant layer 16 is smaller than the relative dielectric constant of the second well region 54.

  In the present embodiment, reference is made to the CMOSFET in which the configuration according to the first embodiment and the configuration according to the second embodiment are combined. However, the P-MOSFET may be replaced with the configuration according to the third embodiment. Similarly, the N-MOSFET may be replaced with the configuration according to the fourth embodiment.

2 is a cross-sectional view showing a configuration of a P-MOSFET according to the first embodiment. FIG. It is a figure which shows the comparison object for demonstrating the effect of P-MOSFET which concerns on Embodiment 1. FIG. FIG. 6 is a cross-sectional view showing a configuration of an N-MOSFET according to a second embodiment. It is a figure which shows the comparison object for demonstrating the effect of N-MOSFET which concerns on Embodiment 2. FIG. 7 is a cross-sectional view showing a configuration of a P-MOSFET according to a third embodiment. FIG. FIG. 6 is a cross-sectional view showing a configuration of an N-MOSFET according to a fourth embodiment. FIG. 9 is a cross-sectional view showing a configuration of a CMOSFET according to a fifth embodiment.

Explanation of symbols

  1,21 P-MOSFET, 2,12,51 Semiconductor substrate, 3,13 Gate insulating film, 4,14 Gate electrode, 5,9 SiGe layer, 6,16 Non-doped SiC layer (or C layer), 11, 31 N MOSFET, 15 n-type SiC layer (or C layer), 19 SiC layer, 50 CMOSFET, 52 element isolation film, 53 first well region, 54 second well region, G1, G2 gate structure.

Claims (6)

A semiconductor substrate having a first conductivity type;
A gate structure formed on the semiconductor substrate, the gate structure being a stacked body in which a gate insulating film and a gate electrode are stacked in that order;
An electrode region having a second conductivity type formed in the surface of the semiconductor substrate on both sides of the gate structure;
A low relative dielectric constant layer having a relative dielectric constant, which is formed immediately below the electrode region, smaller than the relative dielectric constant of the electrode region, or smaller than the relative dielectric constant of the semiconductor substrate. And
The semiconductor substrate is
n-type silicon,
The electrode region is
p-type SiGe,
The low dielectric constant layer is:
SiC or C.
A semiconductor device. In the semiconductor substrate below the gate structure,
  A stacked structure of an n-type SiGe layer and an n-type silicon layer is formed in order from the gate structure.
The semiconductor device according to claim 1. In the semiconductor substrate below the gate structure,
  A stacked structure of an n-type silicon layer, an n-type SiGe layer, and an n-type silicon layer is formed in the order from the gate structure.
The semiconductor device according to claim 1.   A semiconductor substrate having a first conductivity type;
  A gate structure formed on the semiconductor substrate, the gate structure being a stacked body in which a gate insulating film and a gate electrode are stacked in that order;
  An electrode region having a second conductivity type formed in the surface of the semiconductor substrate on both sides of the gate structure;
  A low relative dielectric constant layer having a relative dielectric constant, which is formed immediately below the electrode region, smaller than the relative dielectric constant of the electrode region, or smaller than the relative dielectric constant of the semiconductor substrate. And
  The semiconductor substrate is
  p-type silicon,
  The electrode region is
  n-type SiC,
  The low dielectric constant layer is:
  SiC or C.
A semiconductor device. In the semiconductor substrate below the gate structure,
  A stacked structure of a p-type SiC layer and a p-type silicon layer is formed in order from the gate structure.
The semiconductor device according to claim 4. In the semiconductor substrate below the gate structure,
  A stacked structure of a p-type silicon layer, a p-type SiC layer, and a p-type silicon layer is formed in order from the gate structure.
The semiconductor device according to claim 4.

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