JP2004319988A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can enhance operation speed and can suppress variation in the threshold voltage. <P>SOLUTION: In this semiconductor device, fluorine is introduced in at least one of the following parts, namely, regions that straddle the junction interfaces formed between an n-type single-crystal silicon substrate 1 and source/drain regions 5 of a second conductivity type, and at least one of the interface between at least the central part between a gate insulating film 3 and the channel region 1a, and the gate insulating film 3, and a sidewall insulating film 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a field-effect transistor (MOS transistor) and a method of manufacturing a semiconductor device.

  In recent years, miniaturization of MOS transistors and the like has been promoted along with high integration of semiconductor devices. When the MOS transistor is miniaturized in accordance with the scaling rule, the impurity concentration of the semiconductor substrate increases, so that the parasitic capacitance at the pn junction of the source / drain region of the MOS transistor formed in the semiconductor substrate increases. When the parasitic capacitance increases in this way, there arises a disadvantage that the operation speed of the MOS transistor decreases. For this reason, reduction in parasitic capacitance has become very important in realizing high-speed semiconductor integrated circuits.

  Therefore, a method has been proposed for reducing the parasitic capacitance of the pn junction by injecting impurities of the same conductivity type as the impurities of the semiconductor substrate into the vicinity of the pn junction interface (for example, see Patent Document 1).

  In Patent Document 1 described above, a high-concentration impurity forming a second-conductivity-type source / drain region is formed by implanting the same impurity of the first-conductivity-type as the impurity of the first-conductivity-type semiconductor substrate using the gate electrode as a mask. A first conductivity type low concentration impurity region is formed around a lower portion of the region. This reduces the difference in impurity concentration near the pn junction interface of the high-concentration impurity region in the source / drain region of the second conductivity type, thereby reducing the parasitic capacitance. By reducing the parasitic capacitance, the operation speed of the semiconductor device can be improved.

  Further, in recent years, miniaturization of MOS transistors and the like has been promoted with high integration of semiconductor devices. When the MOS transistor is miniaturized, the distance between the gate electrode and the source / drain region becomes smaller due to the thinner gate insulating film. Accordingly, parasitic capacitance (overlap capacitance) generated via an insulating film formed between the gate electrode and the source / drain region increases. When the overlap capacitance increases in this way, there arises a disadvantage that the operation speed of the MOS transistor decreases. For this reason, reducing the overlap capacitance has become very important in realizing a high-speed semiconductor integrated circuit. Therefore, in order to reduce the overlap capacitance between the gate electrode and the source / drain region, a method has been proposed in which both ends of the gate insulating film are formed of a low-dielectric-constant oxide film into which fluorine has been implanted ( For example, see Patent Document 2).

Conventionally, when a MOS transistor is used for a long time, the threshold voltage greatly changes due to dangling bonds of silicon atoms generated in the gate insulating film and at the interface between the gate insulating film and the silicon substrate. There is a disadvantage of becoming. In order to solve such inconvenience, a technique has been proposed in which fluorine injected into the surface of the source / drain region is thermally diffused into the channel region to terminate dangling bonds in the channel region with fluorine (for example, see Patent Reference 3).
JP-A-5-102477 JP 2000-323710 A JP 2001-156291 A

  However, in recent years, the thickness of the gate electrode of a MOS transistor has become extremely small with the reduction in transistor size. For this reason, when the impurity of the first conductivity type is implanted using the gate electrode as a mask as in Patent Document 1, the impurity of the first conductivity type penetrates the gate electrode and enters the channel region of the first conductivity type below the gate electrode. Is disadvantageously injected. As a result, the impurity concentration of the channel region fluctuates, so that the threshold voltage of the transistor fluctuates.

  Further, in the method of manufacturing a semiconductor device described in Patent Document 2, since the region where the low dielectric constant oxide film is formed is small, it is difficult to sufficiently reduce the overlap capacitance between the gate electrode and the source / drain region. Have difficulty. Therefore, there is a problem that it is difficult to improve the operation speed by reducing the overlap capacitance.

  Further, in the technique of Patent Document 3, when the channel length (gate length) is long, fluorine does not sufficiently diffuse to the central region of the channel region, so that the dangling at the interface between the gate insulating film and the central region of the channel region. There is a disadvantage that the ring bond is not terminated by fluorine. As a result, there is a problem that the threshold voltage fluctuates greatly due to dangling bonds at the interface in the central region of the channel region.

Means for Solving the Problems and Effects of the Invention

  An object of the present invention is to provide a semiconductor device capable of improving the operation speed and suppressing a change in threshold voltage.

  Another object of the present invention is to provide a method of manufacturing a semiconductor device capable of improving the operation speed and suppressing a change in threshold voltage.

  In order to achieve the above object, a semiconductor device according to a first aspect of the present invention includes a semiconductor region of a first conductivity type having a main surface, and a channel region interposed at a predetermined interval on the main surface of the semiconductor region. A source / drain region of the second conductivity type, a gate electrode formed on the channel region via a gate insulating film, and a sidewall insulating film formed on the side surface of the gate electrode. . A region extending over a junction interface between the semiconductor region of the first conductivity type and the source / drain region of the second conductivity type; an interface between the gate insulating film and at least a central region of the channel region; a gate insulating film; Fluorine is introduced into at least one of the film and the film.

  In the semiconductor device according to the first aspect, as described above, the region extending over the junction interface between the semiconductor region of the first conductivity type and the source / drain region of the second conductivity type, and at least the center of the gate insulating film and the channel region. By introducing fluorine into at least one of the interface with the region, the gate insulating film, and the sidewall insulating film, for example, a semiconductor region of the first conductivity type and a source / drain region of the second conductivity type In the case where fluorine is introduced into a region straddling the junction interface between the semiconductor region and the source / drain region, the junction capacitance (pn junction capacitance) between the semiconductor region and the source / drain region can be reduced by the fluorine. Can be improved. Further, even if the fluorine introduced into the junction interface reaches the channel region, the fluorine does not serve as a donor or an acceptor, and thus does not affect the impurity concentration of the first conductivity type in the channel region. Thus, a change in the threshold voltage due to a change in the impurity concentration of the channel region can be suppressed. In the case where fluorine is introduced into the interface between the gate insulating film and at least the central region of the channel region and the gate insulating film, dangling bonds at the interface between the gate insulating film and at least the central region of the channel region are caused by fluorine. In addition, dangling bonds in the gate insulating film can be terminated. As a result, the fluctuation of the threshold voltage is large due to the dangling bond in the gate insulating film and the dangling bond at the interface between the gate insulating film and the central region of the channel region when the gate length (channel length) is large. Can be suppressed. This can also suppress fluctuations in the threshold voltage. Further, when fluorine is introduced into the sidewall insulating film, the dielectric constant of the sidewall insulating film can be sufficiently reduced, so that the dielectric constant of the insulating film between the gate electrode and the source / drain region can be reduced. Can be made sufficiently small. As a result, the overlap capacitance between the gate electrode and the source / drain region can be sufficiently reduced, so that the operation speed of the semiconductor device can be improved.

  A semiconductor device according to a second aspect of the present invention includes a first conductivity type semiconductor region having a main surface and a second conductivity type impurity region formed on the main surface of the semiconductor region. Then, at least one element of fluorine and carbon is introduced into a region straddling the junction interface between the semiconductor region of the first conductivity type and the impurity region of the second conductivity type.

  In the semiconductor device according to the second aspect, as described above, at least one element of fluorine and carbon is placed in a region that straddles the junction interface between the semiconductor region of the first conductivity type and the impurity region of the second conductivity type. With the introduction, the capacity (pn junction capacity) at the junction interface between the semiconductor region of the first conductivity type and the impurity region of the second conductivity type can be reduced, so that the operation speed of the semiconductor device can be improved. . Further, even if fluorine introduced into the junction interface reaches the channel region, the fluorine does not serve as a donor or an acceptor, and thus does not affect the impurity concentration of the semiconductor region of the first conductivity type forming the channel region. Thus, a change in the threshold voltage due to a change in the impurity concentration of the channel region can be suppressed.

  In the semiconductor device according to the second aspect, preferably, the impurity region includes a low-concentration impurity region and a high-concentration impurity region, and at least one element of fluorine and carbon is at least a first conductivity type semiconductor region. And a high concentration impurity region. According to this structure, fluorine can be introduced into a region across the junction interface between the semiconductor region having a large junction capacitance and the high-concentration impurity region, so that the junction capacitance between the semiconductor region and the impurity region can be effectively reduced. Can be. Thus, the operation speed of the semiconductor device can be easily improved.

  A semiconductor device according to a third aspect of the present invention is a semiconductor device having a first conductivity type having a main surface and a second conductivity type formed so as to sandwich a channel region at a predetermined interval on the main surface of the semiconductor region. A source / drain region, a gate electrode formed on the channel region via a gate insulating film, and a sidewall insulating film formed on the side surface of the gate electrode. Then, an element for reducing the dielectric constant is introduced into the sidewall insulating film.

  In the semiconductor device according to the third aspect, as described above, the dielectric constant of the sidewall insulating film can be sufficiently reduced by introducing the element that reduces the dielectric constant into the sidewall insulating film. The dielectric constant of the insulating film between the gate electrode and the source / drain region can be sufficiently reduced. As a result, the overlap capacitance between the gate electrode and the source / drain region can be sufficiently reduced, so that the operation speed of the semiconductor device can be improved.

  In the semiconductor device according to the third aspect, the element that reduces the dielectric constant may include at least one of fluorine and carbon. According to this structure, the dielectric constant of the sidewall insulating film can be easily reduced by introducing at least one element of fluorine and carbon into the sidewall insulating film.

  A semiconductor device according to a fourth aspect of the present invention includes a semiconductor region of a first conductivity type having a main surface and a second conductivity type formed on a main surface of the semiconductor region at a predetermined interval to sandwich a channel region. And a gate electrode formed on the channel region via a gate insulating film. Then, a halogen element is introduced into the interface between the gate insulating film and at least the central region of the channel region and the gate insulating film.

  In the semiconductor device according to the fourth aspect, the halogen element is introduced into the gate insulating film by introducing the halogen element into the interface between the gate insulating film and at least the central region of the channel region and the gate insulating film as described above. The dangling bonds in the inside and the dangling bonds at the interface between the gate insulating film and at least the central region of the channel region can be terminated. As a result, the fluctuation of the threshold voltage is large due to the dangling bond in the gate insulating film and the dangling bond at the interface between the gate insulating film and the central region of the channel region when the gate length (channel length) is large. Can be suppressed.

  In the semiconductor device according to the fourth aspect, the halogen element may be fluorine. According to this structure, the dangling bond in the gate insulating film and the dangling bond at the interface between the gate insulating film and at least the central region of the channel region can be easily terminated by fluorine.

  In a method of manufacturing a semiconductor device according to a fifth aspect of the present invention, a source / drain region of a second conductivity type is formed on a main surface of a semiconductor region of a first conductivity type so as to sandwich a channel region at a predetermined interval. Forming a gate electrode on the channel region with a gate insulating film interposed therebetween, forming a sidewall insulating film on the side surface of the gate electrode, forming a first conductive type semiconductor region and a second conductive type Introducing fluorine into at least one of a region extending over a junction interface with a source / drain region, an interface between a gate insulating film and at least a central region of a channel region, a gate insulating film, and a sidewall insulating film. And

  In the method of manufacturing a semiconductor device according to the fifth aspect, as described above, the region extending over the junction interface between the semiconductor region of the first conductivity type and the source / drain region of the second conductivity type, the gate insulating film and the channel region By introducing fluorine into at least one of the interface with at least the central region, the gate insulating film, and the sidewall insulating film, for example, a semiconductor region of the first conductivity type and a source of the second conductivity type are introduced. In the case where fluorine is introduced into a region across the junction interface between the semiconductor region and the drain region, the junction capacitance (pn junction capacitance) between the semiconductor region and the source / drain region can be reduced by the fluorine. The operation speed can be improved. Further, even if the fluorine introduced into the junction interface reaches the channel region, the fluorine does not serve as a donor or an acceptor, and thus does not significantly affect the impurity concentration of the first conductivity type in the channel region. Thus, a change in the threshold voltage due to a change in the impurity concentration of the channel region can be suppressed. When fluorine is introduced into the interface between the gate insulating film and at least the central region of the channel region and the gate insulating film, dangling bonds in the gate insulating film and at least the gate insulating film and the channel region are caused by fluorine. Dangling bonds at the interface with the central region can be terminated. As a result, the fluctuation of the threshold voltage is large due to the dangling bond in the gate insulating film and the dangling bond at the interface between the gate insulating film and the central region of the channel region when the gate length (channel length) is large. Can be suppressed. This can also suppress fluctuations in the threshold voltage. Further, when fluorine is introduced into the sidewall insulating film, the dielectric constant of the sidewall insulating film can be sufficiently reduced, so that the dielectric constant of the insulating film between the gate electrode and the source / drain region can be reduced. Can be made sufficiently small. As a result, the overlap capacitance between the gate electrode and the source / drain region can be sufficiently reduced, so that the operation speed of the semiconductor device can be improved.

  In the method of manufacturing a semiconductor device according to the fifth aspect, preferably, in the step of introducing fluorine, the fluorine is diffused from the gate electrode to the sidewall insulating film by performing a heat treatment after ion-implanting fluorine into the gate electrode. And a step of diffusing fluorine from the gate electrode to the gate insulating film and the interface between the gate insulating film and at least the central region of the channel region. According to this structure, fluorine can be easily introduced into the sidewall insulating film and at least the central region of the gate insulating film and the channel region.

  In the method of manufacturing a semiconductor device according to the fifth aspect, preferably, the step of introducing fluorine includes the step of introducing fluorine into a region across a junction interface between the semiconductor region of the first conductivity type and the source / drain region of the second conductivity type. It includes a step of ion implantation. According to this structure, fluorine can be easily introduced into a region across a junction interface between the semiconductor region of the first conductivity type and the source / drain region of the second conductivity type.

  A method of manufacturing a semiconductor device according to a sixth aspect of the present invention includes a step of forming an impurity region of a second conductivity type on a main surface of a semiconductor region of a first conductivity type; Ion-implanting at least one element of fluorine and carbon into a region straddling the junction interface with the semiconductor region of the mold.

  In the method of manufacturing a semiconductor device according to the sixth aspect, as described above, at least one of fluorine and carbon is formed in the region straddling the junction interface between the impurity region of the second conductivity type and the semiconductor region of the first conductivity type. By introducing two elements, the junction capacitance (pn junction capacitance) between the semiconductor region and the impurity region can be reduced by fluorine or carbon, so that the operation speed of the semiconductor device can be improved. Further, even if fluorine or carbon introduced into the junction interface reaches the channel region, the fluorine or carbon does not become a donor or an acceptor, and thus affects the impurity concentration of the first conductivity type semiconductor region forming the channel region. Do not give. Thus, a change in threshold voltage due to a change in the impurity concentration of the channel region can be suppressed.

  A method of manufacturing a semiconductor device according to a seventh aspect of the present invention includes a step of forming a gate electrode on a surface of a semiconductor region of a first conductivity type via a gate insulating film, and reducing a dielectric constant of at least the gate electrode. Ion-implanting the element to be formed, forming a sidewall insulating film on the side surface of the gate electrode, forming a silicon nitride film on at least the sidewall insulating film, and removing the element for reducing the dielectric constant by heat treatment. Diffusing from the gate electrode into the sidewall insulating film.

  In the method of manufacturing a semiconductor device according to the seventh aspect, as described above, the element that reduces the dielectric constant by the heat treatment is diffused from the gate electrode to the sidewall insulating film, so that the dielectric constant of the sidewall insulating film can be easily adjusted. Can be sufficiently reduced, and the dielectric constant of the insulating film between the gate electrode and the source / drain region can be sufficiently reduced. As a result, the overlap capacitance between the gate electrode and the source / drain region can be sufficiently reduced, so that the operation speed of the semiconductor device can be improved. In addition, by performing heat treatment after forming a silicon nitride film on at least the sidewall insulating film, the silicon nitride film can suppress outward diffusion of an element that reduces the dielectric constant during the heat treatment.

  A method for manufacturing a semiconductor device according to an eighth aspect of the present invention includes a step of forming a gate electrode on a main surface of a silicon substrate via a gate insulating film; a step of ion-implanting a halogen element into the gate electrode; A step of diffusing the halogen element in the gate electrode into the gate insulating film and the interface between the gate insulating film and the silicon substrate by heat-treating the substrate.

  In the method of manufacturing a semiconductor device according to the eighth aspect, as described above, the halogen element in the gate electrode is formed on the gate insulating film and the interface between the gate insulating film and the silicon substrate by heat-treating the silicon substrate. By diffusing, the halogen element in the gate electrode can be easily diffused in the gate insulating film and the entire channel region located at the interface between the gate insulating film and the silicon substrate. Accordingly, the dangling bond in the gate insulating film and the dangling bond in the entire channel region including the central region of the channel region can be terminated by the halogen element. Therefore, even when the gate length (channel length) is large, Increase in fluctuation of the threshold voltage due to dangling bonds in the central region of the channel region can be suppressed.

  The invention according to the first to ninth aspects may be configured as follows.

  That is, in the semiconductor device according to the first aspect, preferably, a region extending over a junction interface between the semiconductor region of the first conductivity type and the source / drain region of the second conductivity type, and at least a center of the gate insulating film and the channel region. Fluorine is introduced into the interface with the region, the gate insulating film, and the sidewall insulating film. With this configuration, the parasitic capacitance of the source / drain region is reduced, the threshold voltage is prevented from changing due to the change in the impurity concentration of the channel region, and the interface between the gate insulating film and the central region of the channel region is reduced. It is possible to simultaneously suppress the fluctuation of the threshold voltage due to the dangling bond and reduce the overlap capacitance between the gate electrode and the source / drain region. Thus, the operation speed of the semiconductor device can be improved and the fluctuation of the threshold voltage can be further suppressed.

  In the semiconductor device according to the first aspect, the semiconductor region of the first conductivity type may include a silicon region of the first conductivity type. With this configuration, it is possible to easily terminate the dangling bond of silicon with fluorine and reduce the junction capacitance at the pn junction interface of the source / drain region (silicon region) with fluorine.

  In the semiconductor device according to the first aspect, the sidewall insulating film may be made of an insulating film containing Si. According to this structure, the dielectric constant of the sidewall insulating film can be easily reduced by introducing fluorine into the sidewall insulating film made of the insulating film containing Si.

  The semiconductor device according to the second aspect preferably further includes a gate electrode formed on the main surface of the semiconductor region via the gate insulating film, and a sidewall insulating film formed on a side surface of the gate electrode. , Fluorine, and / or carbon are also introduced into the sidewall insulating film. According to this structure, the dielectric constant of the sidewall insulating film can be reduced, so that the junction capacitance between the semiconductor region and the impurity region can be reduced and the overlap between the gate electrode and the source / drain region can be reduced. The capacity can be reduced. Thus, the operation speed of the semiconductor device can be further improved.

  In the semiconductor device according to the second aspect, preferably, the impurity region includes a second conductivity type source / drain region formed on a main surface of the semiconductor region at a predetermined interval so as to sandwich the channel region, At least one element of fluorine and carbon is fluorine, and fluorine is also introduced into the interface between the gate insulating film and at least the central region of the channel region and the gate insulating film. According to this structure, dangling bonds at the interface between the gate insulating film and at least the central region of the channel region and dangling bonds in the gate insulating film can be terminated by fluorine. In the case where the ring bond and the gate length (channel length) are large, the fluctuation of the threshold voltage due to the dangling bond at the interface between the gate insulating film and the central region of the channel region can be suppressed from increasing. This suppresses not only fluctuations in the threshold voltage due to fluctuations in the impurity concentration of the channel region, but also fluctuations in the threshold voltage due to dangling bonds at the interface between the gate insulating film and the central region of the channel region. can do.

  In the semiconductor device according to the third aspect, the sidewall insulating film may be made of an insulating film containing Si. According to this structure, the dielectric constant of the sidewall insulating film can be easily reduced by introducing an element for reducing the dielectric constant into the sidewall insulating film formed of the insulating film containing Si.

  In the semiconductor device according to the third aspect, wherein at least one element of fluorine and carbon is included as the element for reducing the dielectric constant, at least one element of fluorine and carbon is a first conductive type semiconductor region. It is also introduced into a region straddling the junction interface with the two-conductivity type source / drain region. According to this structure, the capacity (pn junction capacity) at the junction interface between the semiconductor region of the first conductivity type and the impurity region of the second conductivity type can be reduced, so that the operation speed of the semiconductor device is further improved. be able to. Further, even if at least one element of fluorine and carbon introduced into the junction interface reaches the channel region, the fluorine does not become a donor or an acceptor, and thus the first conductivity type semiconductor region forming the channel region Does not affect the impurity concentration. Thus, a change in threshold voltage due to a change in the impurity concentration of the channel region can be suppressed.

  In the semiconductor device according to the fourth aspect, the first conductivity type semiconductor region may include a first conductivity type silicon region. With this configuration, the dangling bond in the gate insulating film and the dangling bond in silicon in the channel region can be easily terminated by the halogen element.

  The semiconductor device according to the fourth aspect, wherein the halogen element is fluorine, preferably further includes a sidewall insulating film formed on a side surface of the gate electrode, and the fluorine is also introduced into the sidewall insulating film. With this configuration, the dielectric constant of the sidewall insulating film can be sufficiently reduced, so that the dielectric constant of the insulating film between the gate electrode and the source / drain region can be sufficiently reduced. As a result, in addition to suppressing the fluctuation of the threshold voltage due to dangling bonds in the gate insulating film and at the interface between the gate insulating film and the channel region, the operation speed of the semiconductor device is also improved by reducing the overlap capacitance. Can be planned.

  In the semiconductor device according to the fourth aspect, wherein the halogen element is fluorine, preferably, the fluorine is also introduced into a region across a junction interface between the semiconductor region of the first conductivity type and the source / drain region of the second conductivity type. ing. With this configuration, the capacitance (pn junction capacitance) at the junction interface between the first conductivity type semiconductor region and the second conductivity type impurity region can be reduced, so that the operation speed of the semiconductor device can be further improved. Can be done. Further, even if fluorine introduced into the junction interface reaches the channel region, the fluorine does not serve as a donor or an acceptor, and thus does not affect the impurity concentration of the semiconductor region of the first conductivity type forming the channel region. Thus, a change in threshold voltage due to a change in the impurity concentration of the channel region can be suppressed. As a result, the threshold voltage not only changes due to dangling bonds in the gate insulating film and at the interface between the gate insulating film and the central region of the channel region, but also changes due to the change in impurity concentration in the channel region. Voltage fluctuation can also be suppressed.

  In the method of manufacturing a semiconductor device according to the sixth aspect, preferably, the step of forming the second conductivity type impurity region includes the step of forming the second conductivity type source / drain region including the low concentration impurity region and the high concentration impurity region. Wherein the step of introducing at least one element of fluorine and carbon includes at least one of fluorine and carbon in a region straddling at least a junction interface between the semiconductor region of the first conductivity type and the high-concentration impurity region. And introducing a single element. According to this structure, at least one of fluorine and carbon can be introduced into a region across the junction interface between the semiconductor region having a large junction capacitance and the high-concentration impurity region. The junction capacitance can be effectively reduced. Thus, the operation speed of the semiconductor device can be easily improved.

In the method for manufacturing a semiconductor device according to the sixth aspect, preferably, the step of introducing at least one element of fluorine and carbon includes a step of joining the impurity region of the second conductivity type and the semiconductor region of the first conductivity type. The method includes a step of ion-implanting fluorine with a dose of about 1.5 × 10 ¹⁵ cm ⁻² or more and about 3 × 10 ¹⁵ cm ⁻² or less in a region across the interface. If fluorine is ion-implanted at such an implantation amount, the junction capacitance at the junction interface between the second conductivity type impurity region and the first conductivity type semiconductor region can be easily reduced.

  In the method of manufacturing a semiconductor device according to the seventh aspect, preferably, the step of ion-implanting includes the step of injecting an element for reducing the dielectric constant also into the semiconductor region of the first conductivity type to reduce the dielectric constant. The step of diffusing the element from the gate electrode into the sidewall insulating film includes a step of diffusing the element for reducing the dielectric constant by heat treatment from the semiconductor region of the first conductivity type into the sidewall insulating film. According to this structure, more elements that reduce the dielectric constant can be diffused into the sidewall insulating film, so that the dielectric constant of the sidewall insulating film can be more sufficiently reduced. As a result, the operation speed of the semiconductor device can be further improved.

  In the method for manufacturing a semiconductor device according to the eighth aspect, the halogen element may be fluorine. According to this structure, dangling bonds in the gate insulating film and in the channel region can be easily terminated by fluorine.

In the method for manufacturing a semiconductor device according to the eighth aspect, the step of ion-implanting preferably includes the step of ion-implanting fluorine with an implantation amount of about 1.5 × 10 ¹⁵ cm ^{−2 to} about 5 × 10 ¹⁵ cm ^−2. An injection step may be included. If fluorine is ion-implanted at such an implantation amount, a halogen element can be easily introduced into the gate electrode. Therefore, the halogen element is transferred from the gate electrode to the gate insulating film, the gate insulating film and the silicon substrate. Can be diffused to the interface.

  In the method of manufacturing a semiconductor device according to the eighth aspect, the heat treatment for diffusing the halogen element is preferably performed only once after the ion implantation of the halogen element. With this configuration, the number of heat treatment steps may be one, so that the manufacturing process can be simplified.

  Further, according to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a gate electrode on a main surface of a first conductivity type silicon substrate via a gate insulating film; Forming a pair of second conductivity type source / drain regions so as to sandwich the channel region; implanting a halogen element into the source / drain regions and the gate electrode; and heat-treating the silicon substrate to form a gate. Diffusing the halogen element in the electrode into the gate insulating film and the channel region at the interface between the gate insulating film and the silicon substrate, and diffusing the halogen element in the source / drain region into the channel region below the gate insulating film; It has.

  In the method of manufacturing a semiconductor device according to this other aspect, as described above, the halogen element in the gate electrode is subjected to the heat treatment of the silicon substrate to remove the halogen element in the gate electrode and the channel region at the interface between the gate insulating film and the silicon substrate. By diffusing the halogen element in the source / drain region into the channel region below the gate insulating film, the halogen element can be diffused into the gate insulating film, and the channel including the central region of the channel region can be diffused. More halogen elements can be diffused over the entire region. Thereby, more dangling bonds existing in the gate insulating film and in the entire channel region can be terminated by the halogen element. As a result, the threshold voltage greatly changes due to the dangling bond in the gate insulating film and the dangling bond at the interface between the gate insulating film and the central region of the channel region when the gate length (channel length) is large. Can be further suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(1st Embodiment)
FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. The structure of the semiconductor device (p-channel MOS transistor) according to the first embodiment will be described with reference to FIG.

In the semiconductor device according to the first embodiment, as shown in FIG. 1, an STI (Shallow Trench) for separating an adjacent element formation region (active region) is formed in a predetermined region on a main surface of an n-type single crystal silicon substrate 1. Element isolations 2a and 2b having an Isolation structure are formed. The n-type single crystal silicon substrate 1 is an example of the “first conductive type semiconductor region” of the present invention. A pair of p-type source / drain regions 5 are formed in the element formation region sandwiched between the element isolations 2a and 2b so as to sandwich the channel region 1a. The source / drain region 5 of this p-channel MOS transistor has an LDD (Lightly Doped Drain) structure including a low concentration impurity region 5a and a high concentration impurity region 5b. Note that the source / drain region 5 is an example of the “impurity region” in the present invention. On the channel region 1a, a gate electrode 4 made of a polycrystalline silicon layer of about 150 nm to about 200 nm is formed via a gate insulating film 3 made of a SiO ₂ film having a thickness of about 2 nm to about 10 nm. A pair of p-type source / drain regions 5, gate insulating film 3 and gate electrode 4 constitute a p-channel MOS transistor.

  Here, in the first embodiment, a fluorine region 6 into which fluorine is introduced is formed so as to cross over a junction interface between high-concentration impurity region 5b forming source / drain region 5 and n-type single-crystal silicon substrate 1. ing. This fluorine region 6 is formed so as to extend in a direction parallel to the main surface of n-type single-crystal silicon substrate 1 at least below low-concentration impurity region 5a constituting source / drain region 5.

A side wall insulating film 7 made of silicon oxide is formed on a side surface of the gate electrode 4. Silicide films 9a and 9b made of CoSi ₂ are formed on the upper surface of the gate electrode 4 and the upper surface of the high-concentration impurity region 5b constituting the source / drain region 5, respectively.

  Further, an interlayer insulating film 10 made of a silicon oxide film having a thickness of about 1000 nm is formed so as to cover the entire surface. This interlayer insulating film 10 has contact holes 10a and 10b reaching silicide films 9a and 9b, respectively. Plugs 11a and 11b made of tungsten are buried in the contact holes 10a and 10b, respectively. Wirings 12a and 12b are formed to be connected to plugs 11a and 11b, respectively. The wirings 12a and 12b are composed of a Ti layer having a thickness of about 30 nm, a TiN layer having a thickness of about 30 nm, and an AlCu layer having a thickness of about 400 nm from the lower layer to the upper layer.

  In the semiconductor device according to the first embodiment, as described above, the fluorine region 6 into which fluorine is introduced is formed around the lower portion (pn junction) of the high-concentration impurity region 5b constituting the p-type source / drain region 5. By providing, the relative dielectric constant of the silicon substrate 1 in the vicinity of the fluorine region 6 becomes smaller than the relative dielectric constant of the active region in the n-type single crystal silicon substrate 1.

  On the other hand, the parasitic capacitance Cd generated near the pn junction is generally expressed by the following equation (1).

ここでε_０は、真空の誘電率、ε_Ｓは、シリコンの比誘電率、Ｘｄは、ｐｎ接合の空乏層の幅である。また、Ｘｄは、次の式（２）で表される。

Here, ε ₀ is the dielectric constant of vacuum, ε _S is the relative dielectric constant of silicon, and Xd is the width of the depletion layer of the pn junction. Xd is expressed by the following equation (2).

ここで、ｑは、電荷素量、ＮＢは、空乏層付近の基板不純物濃度、Ｖｂｉは、ビルトインポテンシャル、Ｖｂｓは、基板バイアス電圧（ソース基板間電圧）をそれぞれ示す。これらの式を用いると、次の式（３）が導出される。

Here, q is the elementary charge, NB is the substrate impurity concentration near the depletion layer, Vbi is the built-in potential, and Vbs is the substrate bias voltage (source-substrate voltage). Using these equations, the following equation (3) is derived.

上記式（３）に示すように、ｐｎ接合近傍に生じる寄生容量Ｃｄは、シリコン基板の比誘電率ε_Ｓの平方根に比例することが分かる。すなわち、ｐｎ接合付近にフッ素イオンをイオン注入することにより、シリコン基板の比誘電率ε_Ｓが小さくなるので、ｐｎ接合部分に生じる寄生容量Ｃｄを低減することができる。なお、上記式（３）において、寄生容量Ｃｄは、空乏層付近の基板濃度ＮＢに依存するが、フッ素イオンは、ドナーやアクセプタとはならないため、フッ素イオン注入による基板濃度ＮＢの変化は考慮する必要がない。

As shown in the equation (3), a parasitic capacitance Cd generated in the vicinity of the pn junction is found to be proportional to the square root of the dielectric constant epsilon _S of the silicon substrate. That is, by ion-implanting fluorine ions in the vicinity of the pn junction, since the dielectric constant epsilon _S of the silicon substrate is reduced, it is possible to reduce the parasitic capacitance Cd caused pn junction. In the above equation (3), the parasitic capacitance Cd depends on the substrate concentration NB near the depletion layer. However, since the fluorine ions do not become donors or acceptors, the change in the substrate concentration NB due to the fluorine ion implantation is taken into account. No need.

FIG. 2 is measured data showing a change in parasitic capacitance when the amount of fluorine ions (F ⁺ ) implanted near the pn junction is changed. As can be seen from FIG. 2, when fluorine is ion-implanted at an implantation amount of 1.5 × 10 ¹⁵ cm ^{−2 to} 3 × 10 ¹⁵ cm ⁻² , the parasitic capacitance of the pn junction could be reduced by about 3%. .

  In the semiconductor device according to the first embodiment, as described above, the fluorine region 6 into which fluorine ions are introduced is provided around the lower portion (pn junction) of the high-concentration impurity region 5b constituting the source / drain region 5, thereby providing fluorine. Since the relative permittivity of the region 6 is reduced, the parasitic capacitance can be reduced.

  Next, FIGS. 3 to 11 are cross-sectional views for explaining the manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. The manufacturing process of the semiconductor device (p-channel MOS transistor) according to the first embodiment will be described with reference to FIGS.

  First, as shown in FIG. 3, element isolations 2a and 2b having an STI structure for isolating an active region are formed in a predetermined region on the main surface of n-type single crystal silicon substrate 1. Thereafter, the surface of n-type single crystal silicon substrate 1 is oxidized to form sacrificial oxide film 13 made of a silicon oxide film.

Next, as shown in FIG. 4, arsenic (As) is implanted into the n-type single-crystal silicon substrate 1 through the above-described sacrificial oxide film 13 at an implantation energy of about 100 keV to about 140 keV and about 0.5 × 10 Ion implantation is performed at an implantation amount of ¹² cm ⁻² to about 1 × 10 ¹³ cm ⁻² . Thus, the threshold voltage is optimized by adjusting the impurity concentration of the channel region 1a. Thereafter, the sacrificial oxide film 13 is removed.

  Next, as shown in FIG. 5, a gate made of a silicon oxide film having a thickness of about 2 nm to about 10 nm is formed on the surface of the n-type single crystal silicon substrate 1 by thermal oxidation at about 800 ° C. to about 900 ° C. An insulating film 3 is formed. Thereafter, a polycrystalline silicon film (not shown) is deposited on the entire surface to a thickness of about 150 nm to about 200 nm by a CVD method, and then, using a normal photolithography process and an etching technique by RIE (Reactive Ion Etching). Then, the polycrystalline silicon film is patterned. Thus, a gate electrode 4 made of a polycrystalline silicon film is formed. Since the gate insulating film 3 is greatly damaged by the above-described etching, the gate insulating film 3 is re-oxidized after the formation of the gate electrode 4.

Next, as shown in FIG. 6, using the gate electrode 4 as a mask, boron (B), which is a p-type impurity, is implanted into the main surface of the n-type single crystal silicon substrate 1 with an implantation energy of about 5 keV to about 10 keV and By ion-implanting with an implantation amount of about 1 × 10 ¹³ cm ⁻² to about 5 × 10 ¹⁴ cm ⁻² , a p-type low-concentration impurity region 5a is formed so as to sandwich the channel region 1a.

Next, as shown in FIG. 7, fluorine (F) is ion-implanted over the entire surface at an implantation energy of about 20 keV and an implantation amount of about 3 × 10 ¹⁵ cm ⁻² , thereby forming a fluorine region 6 into which fluorine has been introduced. Is formed.

  Next, an insulating film (not shown) made of a silicon oxide film or the like is deposited on the entire surface by using the CVD method, and the insulating film is etched back by using the RIE method, as shown in FIG. Then, a sidewall insulating film 7 is formed on the side surface of the gate electrode 4. At the time of the above-described etchback, the gate insulating film 3 other than the region immediately below the gate electrode 4 and the sidewall insulating film 7 is removed from the gate insulating film 3.

  Next, as shown in FIG. 9, a silicon nitride film 8 having a thickness of about 5 nm to about 20 nm is deposited on the entire surface. The silicon nitride film 8 is used to prevent channeling during ion implantation for forming the high-concentration impurity regions 5b constituting the source / drain regions 5 to be performed in a later step, and to prevent outward diffusion of implanted fluorine. Form.

Next, as shown in FIG. 10, boron (B) is implanted into the n-type single crystal silicon substrate 1 through the silicon nitride film 8 at an implantation energy of about 5 keV to about 10 keV and about 1 × 10 ¹⁵ cm ⁻² . By ^performing ion implantation at an implantation amount of about 5 × 10 ¹⁵ cm ⁻² , a p-type high-concentration impurity region 5b is formed. At this time, the fluorine region 6 into which fluorine has been introduced is located in a region straddling the junction interface between the p-type high-concentration impurity region 5b and the n-type single-crystal silicon substrate 1.

  Then, a heat treatment is performed at about 700 ° C. to about 1100 ° C. for about 0.1 second to about 60 seconds by RTA (Rapid Thermal Annealing) to thereby obtain the impurity (B) implanted into the p-type high-concentration impurity region 5b. Activate).

  Further, when the p-type high-concentration impurity region 5b is formed by the boron ion implantation, the fluorine region 6 does not straddle the junction interface between the p-type high-concentration impurity region 5b and the n-type single-crystal silicon substrate 1. Also in this case, the p-type high-concentration impurity region 5b and the fluorine region 6 are widened by this activation step by RTA, so that the fluorine region 6 is And straddles the bonding interface.

  Note that a pair of p-type source / drain regions 5 having an LDD structure are formed by the p-type low-concentration impurity regions 5a and the p-type high-concentration impurity regions 5b. After that, the silicon nitride film 8 is removed.

Next, as shown in FIG. 11, a p-type high-concentration impurity region 5b forming the source / drain region 5 on the upper surface of the gate electrode 4 and the source / drain region 5 using a salicide (self-aligned silicide) process. Are formed in a self-aligned manner on the upper surface of the substrate, respectively, with silicide films 9a and 9b made of cobalt silicide (CoSi ₂ ).

  Thereafter, as shown in FIG. 1, after an interlayer insulating film 10 is formed using a CVD method, contact holes 10a and 10b are formed in predetermined regions using a photolithography technique and a dry etching technique such as RIE. Form. Plugs 11a and 11b are formed by burying tungsten in the contact holes 10a and 10b by using the CVD method. Lastly, a Ti layer having a thickness of about 30 nm, a TiN layer having a thickness of about 30 nm, and an AlCu layer having a thickness of about 400 nm are formed on the upper surface of the interlayer insulating film 10 from the lower layer to the upper layer. After forming a laminated film (not shown), the laminated film is patterned to form upper wirings 12a and 12b. Thus, the p-channel MOS transistor (semiconductor device) according to the first embodiment is formed.

  In the first embodiment, as described above, fluorine is introduced so as to straddle the junction interface between the p-type high-concentration impurity region 5 b constituting the p-type source / drain region 5 and the n-type single-crystal silicon substrate 1. By providing the fluorine region 6 thus formed, the parasitic capacitance around the lower portion (pn junction) of the high-concentration impurity region 5b can be reduced. Thereby, the operation speed of the semiconductor device (p-channel MOS transistor) can be improved.

  In the first embodiment, the ion implantation method is used as the method of introducing fluorine, so that fluorine can be introduced into a predetermined region of the n-type single crystal silicon substrate 1 with high accuracy. Thus, the parasitic capacitance at the pn junction of the source / drain region 5 can be reduced without variation.

FIG. 12 shows actual measurement data showing a change in the threshold voltage of the p-channel MOS transistor when the amount of fluorine ions (F ⁺ ) implanted near the pn junction is changed. Under these measurement conditions, fluorine has reached the channel region. Usually, the allowable range of the threshold voltage variation is about ± 50 mV in consideration of an error in the implantation amount of the ion implantation performed for adjusting the threshold voltage and a variation in the thickness of the gate insulating film. FIG. 12 shows that the variation in threshold voltage when fluorine ions are implanted at a dose of about 1.5 × 10 ¹⁵ cm ^{−2 to} 3 × 10 ¹⁵ cm ⁻² is 3.5 mV or less, and fluorine ion implantation is performed. It is clear that the variation of the threshold value due to the above does not substantially matter.

  Therefore, in the first embodiment, even when fluorine reaches the channel region 1a under the gate electrode 4 during ion implantation using the gate electrode 4 as a mask, the p-channel MOS No problem is caused by the fluctuation of the threshold voltage of the transistor.

  As described above, in the first embodiment, the operation speed is improved by reducing the parasitic capacitance at the pn junction of the source / drain region 5 while suppressing the fluctuation of the threshold voltage of the p-channel MOS transistor. Can be.

(2nd Embodiment)
FIG. 13 is a sectional view showing the semiconductor device according to the second embodiment of the present invention. In the second embodiment, an example in which the present invention is applied to a CMOS inverter in which an n-channel MOS transistor and a p-channel MOS transistor function complementarily will be described with reference to FIG.

  In the semiconductor device according to the second embodiment, as shown in FIG. 13, a predetermined region on the main surface of a p-type single crystal silicon substrate 21 has an STI structure for separating an adjacent element formation region (active region). Element isolations 22a, 22b and 22c are formed. A p-well region 14a is formed in a region of the p-type single crystal silicon substrate 21 where an n-channel MOS transistor is formed, and an n-well region 14b is formed in a region where a p-channel MOS transistor is formed. Have been. The p-well region 14a and the n-well region 14b are examples of the “semiconductor region” of the present invention. A pair of n-type source / drain regions 25 are formed in the p-well region 14a so as to sandwich the channel region 21a. The n-type source / drain region 25 has an LDD structure including an n-type low concentration impurity region 25a and an n-type high concentration impurity region 25b. The n-type source / drain region 25 is an example of the “impurity region” of the present invention. On the channel region 21a, a gate electrode 24a made of a polycrystalline silicon layer of about 150 nm to about 200 nm is formed via a gate insulating film 23 made of a silicon oxynitride film having a thickness of about 2 nm to about 10 nm. . The pair of n-type source / drain regions 25, the gate insulating film 23, and the gate electrode 24a form an n-channel MOS transistor.

  A pair of p-type source / drain regions 35 are formed in the n-well region 14b so as to sandwich the channel region 21b. The p-type source / drain region 35 has an LDD structure including a p-type low-concentration impurity region 35a and a p-type high-concentration impurity region 35b. The p-type source / drain region 35 is an example of the “impurity region” in the present invention. A gate electrode 24b made of a polycrystalline silicon layer of about 150 nm to about 200 nm is formed on the channel region 21b via a gate insulating film 23 made of a silicon oxynitride film having a thickness of about 2 nm to about 10 nm. . A pair of p-type source / drain regions 35, gate insulating film 23, and gate electrode 24b form a p-channel MOS transistor.

  Here, in the second embodiment, the lower part (pn junction) of the high-concentration impurity region 25b forming the source / drain region 25 of the n-channel MOS transistor and the source / drain region 35 of the p-channel MOS transistor are formed. Fluorine regions 26a and 26b into which fluorine is introduced are formed around the lower portion (pn junction) of the high-concentration impurity region 35b, respectively. In other words, fluorine regions 26a and 26b straddle the junction interface between n-type high-concentration impurity region 25b and p-well region 14a and the junction interface between p-type high-concentration impurity region 35b and n-well region 14b, respectively. It is formed as follows. Fluorine regions 26a and 26b extend in a direction parallel to the main surface of p-type single crystal silicon substrate 21 at least below low concentration impurity regions 25a and 35a forming source / drain regions 25 and 35, respectively. Is formed.

Further, on the side surfaces of the gate electrodes 24a and 24b constituting the n-channel MOS transistor and the p-channel MOS transistor, sidewall insulating films 27 made of a silicon oxide film or the like are formed, respectively. Silicide films 29a and 29b made of CoSi ₂ are formed on the upper surfaces of gate electrodes 24a and 24b and on the upper surfaces of high-concentration impurity regions 25b and 35b constituting source / drain regions 25 and 35, respectively.

  Further, an interlayer insulating film 30 made of a silicon oxide film having a thickness of about 1000 nm is formed so as to cover the entire surface. This interlayer insulating film 30 has contact holes 30a, 30b, 30c and 30d reaching silicide films 29a and 29b, respectively. Plugs 31a, 31b, 31c and 31d made of tungsten are buried in the contact holes 30a, 30b, 30c and 30d, respectively. Wirings 32a and 32b are formed to connect to plugs 31a, 31b, 31c and 31d, respectively. The wirings 32a and 32b are composed of a Ti layer having a thickness of about 30 nm, a TiN layer having a thickness of about 30 nm, and an AlCu layer having a thickness of about 400 nm from the lower layer to the upper layer.

  The n-type source / drain region 25 of the n-channel MOS transistor and the source / drain region 35 of the p-channel MOS transistor are connected via a plug 31b, a plug 31d, and an upper wiring 32b. Further, the gate electrode 24a of the n-channel MOS transistor and the gate electrode 24b of the p-channel MOS transistor are connected via a plug 31a, a plug 31c, an upper wiring 32a, and a wiring (not shown) located in a further upper layer. . Thereby, a CMOS inverter is configured.

  In the semiconductor device according to the second embodiment, as described above, the high-concentration impurity regions 25b and 35b forming the source / drain regions 25 and 35 of the n-channel MOS transistor and the p-channel MOS transistor straddle the pn junction interface. By providing fluorine regions 26a and 26b into which fluorine is introduced, respectively, the relative dielectric constant in the vicinity of fluorine regions 26a and 26b becomes smaller than that in p-well region 14a and n-well region 14b. This reduces both the parasitic capacitance at the pn junction interface of the n-type source / drain region 25 of the n-channel MOS transistor and the parasitic capacitance at the pn junction interface of the p-type source / drain region 35 of the p-channel MOS transistor. be able to. Thereby, the operation speed of the semiconductor device (CMOS inverter) can be improved.

  Next, FIGS. 14 to 26 are cross-sectional views for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. The manufacturing process of the semiconductor device (CMOS inverter) according to the second embodiment will be described with reference to FIGS.

  First, as shown in FIG. 14, device isolations 22a, 22b and 22c having an STI structure for isolating an active region are formed in a predetermined region on a main surface of a p-type single crystal silicon substrate 21. Thereafter, by oxidizing the surface of the p-type single crystal silicon substrate 21, a sacrificial oxide film 36 made of a silicon oxide film is formed.

Next, as shown in FIG. 15, a resist film 15a is formed using a lithography technique so as to cover a region where the n-channel MOS transistor is formed. Thereafter, using the resist film 15a as a mask, phosphorus (P) is implanted into the p-type single-crystal silicon substrate 21 through the above-described sacrificial oxide film 36 at an implantation energy of about 380 keV and a dose of about 4 × 10 ¹³ cm ⁻² . The n-well region 14b is formed by ion implantation at an implantation amount. Further, arsenic (As) is ion-implanted at an implantation energy of about 100 keV to about 140 keV and an implantation amount of about 0.5 × 10 ¹² cm ⁻² to about 1 × 10 ¹³ cm ⁻² , thereby forming the channel region 21b. The threshold voltage is optimized by adjusting the impurity concentration. Thereafter, the resist film 15a is removed.

Next, as shown in FIG. 16, a resist film 15b is formed using lithography technology so as to cover a region where the p-channel MOS transistor is formed. Thereafter, boron (B) is ion-implanted into the p-type single crystal silicon substrate 21 through the sacrificial oxide film 36 at an implantation energy of about 190 keV and an implantation amount of about 4 × 10 ¹³ cm ^−2. Thus, a p-well region 14a is formed. Further, boron (B) is ion-implanted with an implantation energy of about 10 keV to about 30 keV and an implantation amount of about 1 × 10 ¹² cm ⁻² to about 1 × 10 ¹³ cm ⁻² , whereby the impurity concentration of the channel region 21a is increased. Is adjusted to optimize the threshold voltage. After that, the resist film 15b is removed.

  Next, as shown in FIG. 17, a silicon oxide film having a thickness of about 2 nm to about 10 nm is formed on the surface of the p-type single crystal silicon substrate 21 by performing a heat treatment in an oxidizing atmosphere. By annealing, a gate insulating film 23 made of a silicon oxynitride film having a thickness of about 2 nm to about 10 nm is formed on the surface of the p-type single crystal silicon substrate 21. Thereafter, a polycrystalline silicon film (not shown) is deposited on the entire surface to a thickness of about 150 nm to about 200 nm by a CVD method, and then the polycrystalline silicon film is formed using a normal photolithography process and an etching technique by RIE. Pattern the film. Thus, gate electrodes 24a and 24b made of a polycrystalline silicon film are formed. Since the gate insulating film 23 is greatly damaged by the above-described etching, the gate insulating film 23 is re-oxidized after forming the gate electrodes 24a and 24b.

Next, as shown in FIG. 18, a resist film 16a is formed so as to cover a region where the p-channel MOS transistor is formed. Then, phosphorus (P) is implanted into the main surface of the p-well region 14a at an implantation energy of about 30 keV, an implantation amount of about 0.5 × 10 ¹³ cm ⁻² to about 5 × 10 ¹⁴ cm ⁻² , and an incidence of about 7 degrees. At the corner, ion implantation is performed four times while rotating the p-type single crystal silicon substrate 21 by 90 degrees. Thus, an n-type low-concentration impurity region 25a forming source / drain region 25 of the n-channel MOS transistor is formed. Thereafter, the resist film 16a is removed.

Next, as shown in FIG. 19, a resist film 16b is formed so as to cover a region where the n-channel MOS transistor is formed. Then, boron difluoride (BF ₂ ) is implanted into the main surface of the n-well region 14b at an implantation energy of about 15 keV, an implantation amount of about 1 × 10 ¹³ cm ⁻² to about 5 × 10 ¹⁴ cm ^{−2, and} an implantation amount of about 7 degrees. Ion implantation is performed four times while rotating the p-type single-crystal silicon substrate 21 by 90 degrees at an incident angle. As a result, a p-type low-concentration impurity region 35a forming the source / drain region 35 of the p-channel MOS transistor is formed. Thereafter, the state shown in FIG. 20 is obtained by removing the resist film 16b.

Next, as shown in FIG. 21, fluorine (F) is ion-implanted into the entire surface at an implantation energy of about 20 keV and an implantation amount of about 3 × 10 ¹⁵ cm ⁻² . Thus, fluorine regions 26a and 26b into which fluorine is introduced are formed in p well region 14a and n well region 14b, respectively.

  Next, an insulating film (not shown) made of silicon oxide or the like is deposited on the entire surface by using the CVD method, and the insulating film is etched back by using the RIE method, as shown in FIG. Next, a sidewall insulating film 27 is formed on the side surfaces of the gate electrodes 24a and 24b. At the time of the above-described etch-back, a region of the gate insulating film 23 other than a region immediately below the gate electrodes 24a and 24b and the sidewall insulating film 27 is removed.

  Next, as shown in FIG. 23, a silicon nitride film 28 having a thickness of about 5 nm to about 20 nm is deposited on the entire surface. As in the first embodiment, the silicon nitride film 28 also has a function of preventing channeling during ion implantation performed in a later step and a function of preventing outward diffusion of the implanted fluorine.

Next, as shown in FIG. 24, a resist film 17a is formed so as to cover a region where the p-channel MOS transistor is formed. Thereafter, arsenic (As) is ion-implanted into the p-type single crystal silicon substrate 21 at an implantation energy of about 45 keV and an implantation amount of about 1 × 10 ¹⁵ cm ⁻² to about 5 × 10 ¹⁵ cm ⁻² . Thus, an n-type high-concentration impurity region 25b constituting source / drain region 25 of the n-channel MOS transistor is formed. At this time, the fluorine region 26a into which fluorine has been introduced crosses the junction interface between the n-type high-concentration impurity region 25b and the p-well region 14a. After that, the resist film 17a is removed.

Next, as shown in FIG. 25, a resist film 17b is formed so as to cover a region where the n-channel MOS transistor is formed. Using the resist film 17b as a mask, boron (B) is ion-implanted with an implantation energy of about 7 keV and an implantation amount of about 1 × 10 ¹⁵ cm ⁻² to about 5 × 10 ¹⁵ cm ⁻² . Thus, a p-type high-concentration impurity region 35b constituting the p-type source / drain region 35 is formed. At this time, the fluorine region 26b into which fluorine has been introduced straddles the junction interface between the p-type high-concentration impurity region 35b and the n-well region 14b. After that, the resist film 17b is removed.

  Then, the implanted impurities are activated by performing a heat treatment at about 700 ° C. to about 1100 ° C. for about 0.1 second to about 60 seconds by the RTA method.

  When the high-concentration impurity regions 25b and 35b are formed, the fluorine regions 26a and 26b form a junction interface between the high-concentration impurity region 25b and the p-well region 14a and a junction between the high-concentration impurity region 35b and the n-well region 14b. Even when the interface does not cross the interface, the activation step by RTA causes the high-concentration impurity regions 25b and 35b and the fluorine regions 26a and 26b to spread. Thereby, fluorine regions 26a and 26b straddle the junction interface between high-concentration impurity region 25b and p-well region 14a and the junction interface between high-concentration impurity region 35b and n-well region 14b.

  The low-concentration impurity regions 25a and 35a and the high-concentration impurity regions 25b and 35b form a pair of source / drain regions 25 and 35 having an LDD structure.

After that, the silicon nitride film 28 is removed. Then, as shown in FIG. 26, using a salicide process, the upper surfaces of gate electrodes 24a and 24b made of polycrystalline silicon and the upper surfaces of high concentration impurity regions 25b and 35b forming source / drain regions 25 and 35 are formed. Then, cobalt silicide (CoSi ₂ ) films 29a and 29b are formed in a self-aligned manner.

  Thereafter, as shown in FIG. 13, after the interlayer insulating film 30 is formed by using the CVD method, contact holes 30a, 30b, and 30 are formed in predetermined regions by using photolithography technology and dry etching technology such as RIE. Form 30c and 30d. Plugs 31a, 31b, 31c and 31d are formed by embedding tungsten in the contact holes 30a, 30b, 30c and 30d using the CVD method. Finally, on the upper surface of the interlayer insulating film 30, from the lower layer to the upper layer, a Ti layer having a thickness of about 30 nm, a TiN layer having a thickness of about 30 nm, and an AlCu layer having a thickness of about 400 nm After a laminated film (not shown) is formed, the laminated film is patterned to form upper wirings 32a and 32b. Thus, the CMOS inverter (semiconductor device) according to the second embodiment is formed.

  In the second embodiment, as described above, the fluorine regions 26a and 26b are formed at the junction interface between the n-type high-concentration impurity region 25b and the p-well region 14a and at the p-type high-concentration impurity region 35b and the n-well region 14b. As in the first embodiment, the parasitic capacitance at the lower periphery (pn junction portion) of the high-concentration impurity regions 25b and 35b constituting the source / drain regions 25 and 35 is reduced, as in the first embodiment. can do. As a result, the operation speed of the CMOS inverter can be improved.

  Also in the second embodiment, as in the first embodiment, since the ion implantation method is used as the method for introducing fluorine, fluorine is precisely injected into predetermined portions of the p-well region 14a and the n-well region 14b. Can be introduced. Thereby, similarly to the first embodiment, the parasitic capacitance at the pn junction of the source / drain regions 25 and 35 can be reduced without variation.

  Further, also in the second embodiment, when the ion implantation of fluorine is performed using the gate electrodes 24a and 24b as a mask, the fluorine is deposited on the channel regions 21a and 24b under the gate electrodes 24a and 24b because the thickness of the gate electrodes 24a and 24b is small. Even if the threshold voltage reaches 21b, no problem occurs due to the fluctuation of the threshold voltage of the p-channel MOS transistor. Therefore, the reliability of the CMOS inverter can be improved.

(Third embodiment)
FIG. 27 is a sectional view showing the semiconductor device according to the third embodiment of the present invention. FIG. 28 is an enlarged view around the MOS transistor of the semiconductor device according to the third embodiment of the present invention shown in FIG. Referring to FIGS. 27 and 28, in the third embodiment, an example in which the overlap capacitance between the gate electrode and the source / drain region is reduced by introducing fluorine into the sidewall insulating film will be described.

  In the semiconductor device according to the third embodiment, as shown in FIG. 27, a predetermined region on the main surface of a p-type single crystal silicon substrate 41 has an STI structure for separating an adjacent element formation region (active region). Element isolations 42a, 42b and 42c are formed. A p-well region 52a is formed in a region of the p-type single crystal silicon substrate 41 where an n-channel MOS transistor is formed, and an n-well region 52b is formed in a region where a p-channel MOS transistor is formed. Have been. In the p well region 52a, a pair of n-type source / drain regions 45 are formed at predetermined intervals so as to sandwich the channel region 41a.

  The n-type source / drain region 45 has an LDD structure including an n-type low concentration impurity region 45a and an n-type high concentration impurity region 45b. On the channel region 41a, a gate electrode 44a made of a polycrystalline silicon layer of about 150 nm to about 200 nm is formed via a gate insulating film 43 made of a silicon oxynitride film having a thickness of about 2 nm to about 10 nm. . The pair of n-type source / drain regions 45, the gate insulating film 43, and the gate electrode 44a form an n-channel MOS transistor.

  In the n-well region 52b, a pair of p-type source / drain regions 55 are formed at predetermined intervals so as to sandwich the channel region 41b. The p-type source / drain region 55 has an LDD structure including a p-type low concentration impurity region 55a and a p-type high concentration impurity region 55b. A gate electrode 44b made of a polycrystalline silicon layer of about 150 nm to about 200 nm is formed on the channel region 41b via a gate insulating film 43 made of a silicon oxynitride film having a thickness of about 2 nm to about 10 nm. . A pair of p-type source / drain regions 55, gate insulating film 43, and gate electrode 44b form a p-channel MOS transistor.

Further, sidewall insulating films 46 made of a silicon oxide film are formed on the side surfaces of the gate electrodes 44a and 44b constituting the n-channel MOS transistor and the p-channel MOS transistor, respectively. Silicide films 48a and 48b made of CoSi ₂ are formed on the upper surfaces of the gate electrodes 44a and 44b and the upper surfaces of the high concentration impurity regions 45b and 55b, respectively.

  An interlayer insulating film 49 made of a silicon oxide film having a thickness of about 1000 nm is formed so as to cover the entire surface. This interlayer insulating film 49 has contact holes 49a, 49b, 49c and 49d reaching silicide films 48a and 48b, respectively. Plugs 50a, 50b, 50c and 50d made of tungsten are buried in the contact holes 49a, 49b, 49c and 49d, respectively. Wirings 51a and 51b are formed to connect to plugs 50a, 50b, 50c and 50d, respectively. The wirings 51a and 51b are composed of a Ti layer having a thickness of about 30 nm, a TiN layer having a thickness of about 30 nm, and an AlCu layer having a thickness of about 400 nm from the lower layer to the upper layer.

  The above-described n-type source / drain region 45 of the n-channel MOS transistor and the p-type source / drain region 55 of the p-channel MOS transistor are connected via a plug 50b, a plug 50d, and an upper wiring 51b. . Further, the gate electrode 44a of the n-channel MOS transistor and the gate electrode 44b of the p-channel MOS transistor are connected via a plug 50a, a plug 50c, an upper layer wiring 51a, and a wiring (not shown) located in a further upper layer. . Thereby, a CMOS inverter is configured.

  Here, in the semiconductor device according to the third embodiment, as shown in FIG. 28, the inside of the sidewall insulating film 46 of the n-channel MOS transistor and the n-type low-concentration impurities forming the n-type source / drain regions 45 Fluorine is introduced into each of the region 45a and the region near the gate insulating film 43 in the n-type high-concentration impurity region 45b. Accordingly, the dielectric constant of the sidewall insulating film 46 and the peripheral regions of the gate insulating film 43 of the n-type low-concentration impurity regions 45a and the n-type high-concentration impurity regions 45b forming the n-type source / drain regions 45 are formed. The dielectric constant becomes sufficiently small. Similarly, for the p-channel MOS transistor, the inside of the sidewall insulating film 46 and the gates of the p-type low-concentration impurity regions 55a and the p-type high-concentration impurity regions 55b forming the p-type source / drain regions 55 are formed. Fluorine is introduced into the region near the insulating film 43, respectively. For this reason, the dielectric constant of the sidewall insulating film 46 and the p-type low-concentration impurity region 55 a and the p-type high-concentration impurity region 55 b constituting the p-type source / drain region 55 around the gate insulating film 43. The dielectric constant becomes sufficiently small.

  FIG. 29 shows the overlap capacitance between the gate electrode and the source / drain region between the case where fluorine is introduced and the case where fluorine is not introduced around the sidewall insulating film and the source / drain region of the p-channel MOS transistor. The actual measurement data shown is shown. As can be seen from FIG. 29, when the peripheral length of the gate electrode is in the range of about 13.4 mm to about 130.4 mm, the overlap capacitance between the gate electrode and the source / drain region when fluorine ions are implanted is as follows. The overlap capacitance between the gate electrode and the source / drain region when no implantation is performed is smaller by about 10%.

  As described above, in the semiconductor device according to the third embodiment, the overlap capacitance between the source / drain region 45 of the n-channel MOS transistor and the gate electrode 44a, and the source / drain region 55 and the gate of the p-channel MOS transistor It is possible to reduce both the overlap capacitance generated with the electrode 44b.

  Next, FIGS. 30 to 43 are cross-sectional views for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. The manufacturing process of the semiconductor device (CMOS inverter) according to the third embodiment will be described with reference to FIGS.

  First, as shown in FIG. 30, device isolations 42a, 42b and 42c having an STI structure for isolating an active region are formed in a predetermined region on the main surface of p-type single crystal silicon substrate 41. Thereafter, by oxidizing the surface of the p-type single crystal silicon substrate 41, a sacrificial oxide film 53 made of a silicon oxide film is formed.

Next, as shown in FIG. 31, a resist film 54a is formed using lithography technology so as to cover a region where the n-channel MOS transistor is formed. Thereafter, using the resist film 54a as a mask, phosphorus (P) is implanted into the p-type single crystal silicon substrate 41 through the sacrificial oxide film 53 at an implantation energy of about 380 keV and an implantation amount of about 4 × 10 ¹³ cm ⁻² . The n-well region 52b is formed by ion-implanting. Further, arsenic (As) is ion-implanted at an implantation energy of about 100 keV to about 140 keV and an implantation amount of about 0.5 × 10 ¹² cm ⁻² to about 1 × 10 ¹³ cm ⁻² , so that the channel region 41 b is ion-implanted. Adjust the impurity concentration. Thereby, the threshold voltage is optimized. After that, the resist film 54a is removed.

Next, as shown in FIG. 32, a resist film 54b is formed using lithography technology so as to cover a region where the p-channel MOS transistor is formed. Thereafter, using the resist film 54b as a mask, boron (B) is implanted into the p-type single-crystal silicon substrate 41 through the sacrificial oxide film 53 at an implantation energy of about 190 keV and an implantation amount of about 4 × 10 ¹³ cm ⁻² . The p-well region 52a is formed by ion-implantation. Further, boron (B) is ion-implanted with an implantation energy of about 10 keV to about 30 keV and an implantation amount of about 1 × 10 ¹² cm ⁻² to about 1 × 10 ¹³ cm ⁻² , whereby the impurity concentration of the channel region 41a is increased. To adjust. Thereby, the threshold voltage is optimized. Thereafter, the resist film 54b is removed.

  Next, as shown in FIG. 33, a silicon oxide film having a thickness of about 2 nm to about 10 nm is formed on the surface of the single crystal silicon substrate 41 by performing a heat treatment in an oxidizing atmosphere, and then annealing is performed in a NO atmosphere. Thus, a gate insulating film 43 made of a silicon oxynitride film having a thickness of about 2 nm to about 10 nm is formed on the surface of the p-type single crystal silicon substrate 41. Thereafter, a polycrystalline silicon film (not shown) is deposited on the entire surface to a thickness of about 150 nm to about 200 nm by a CVD method, and then the polycrystalline silicon film is formed using a normal photolithography process and an etching technique by RIE. Pattern the film. Thus, gate electrodes 44a and 44b made of a polycrystalline silicon film are formed. Since the gate insulating film 43 is greatly damaged by the above-described etching, the gate insulating film 43 is re-oxidized after forming the gate electrodes 44a and 44b.

Next, as shown in FIG. 34, a resist film 56a is formed so as to cover a region where the p-channel MOS transistor is formed. Thereafter, using the resist film 56a as a mask, phosphorus (P) is implanted into the main surface of the p-well region 52a at an implantation energy of about 30 keV and an implantation energy of about 0.5 × 10 ¹³ cm ⁻² to about 5 × 10 ¹⁴ cm ⁻² . The ion implantation is performed four times at an incident angle of about 7 degrees while rotating the p-type single crystal silicon substrate 41 by 90 degrees. Thus, an n-type low concentration impurity region (extension region) 45a is formed. Thereafter, the resist film 56a is removed.

Next, as shown in FIG. 35, a resist film 56b is formed so as to cover a region where the n-channel MOS transistor is formed. Thereafter, using the resist film 56b as a mask, boron difluoride (BF ₂ ) is implanted into the main surface of the n-well region 52b at an implantation energy of about 15 keV and about 1 × 10 ¹³ cm ⁻² to about 5 × 10 ¹⁴ cm ^−2. The ion implantation is performed four times while rotating the p-type single crystal silicon substrate 41 by 90 degrees at an implantation amount of about 7 degrees. Thus, a p-type low concentration impurity region 55a is formed. After that, the resist film 56b is removed. This results in the state shown in FIG.

Next, as shown in FIG. 37, fluorine (F) is ion-implanted into the entire surface at an implantation energy of about 10 keV and an implantation amount of about 3 × 10 ¹⁵ cm ⁻² . Thus, fluorine ions are implanted into gate electrodes 44a and 44b, and fluorine regions 57 in which fluorine is introduced into p well region 52a and n well region 52b are formed.

  Next, as shown in FIG. 38, an insulating film 46a made of a silicon oxide film is deposited on the entire surface by using a thermal CVD method. By etching back the insulating film 46a using RIE, a sidewall insulating film 46 made of a silicon oxide film is formed on the side surfaces of the gate electrodes 44a and 44b as shown in FIG. Note that, during the above-described etchback, the gate insulating film 43 is removed except for the region immediately below the gate electrodes 44a and 44b and the sidewall insulating film 46.

  Next, as shown in FIG. 40, a silicon nitride film 47 having a thickness of about 5 nm to about 20 nm is deposited on the entire surface. This silicon nitride film 47 prevents channeling during ion implantation for forming high-concentration impurity regions 45b and 55b performed in a later step, and suppresses outward diffusion of fluorine during a subsequent heat treatment. Formed in order to

Next, as shown in FIG. 41, a resist film 58a is formed so as to cover a region where the p-channel MOS transistor is formed. Thereafter, using the resist film 58a as a mask, arsenic (As) is ion-implanted into the p-type single-crystal silicon substrate 41 at an implantation energy of about 45 keV at an implantation energy of about 1 × 10 ¹⁵ cm ⁻² to about 5 × 10 ¹⁵ cm ^−2. Inject. Thus, an n-type high-concentration impurity region 45b constituting source / drain region 45 of the n-channel MOS transistor is formed. Thereafter, the resist film 58a is removed.

Next, as shown in FIG. 42, a resist film 58b is formed so as to cover a region where the n-channel MOS transistor is formed. Thereafter, using the resist film 58b as a mask, boron (B) is ion-implanted with an implantation energy of about 7 keV and an implantation amount of about 1 × 10 ¹⁵ cm ⁻² to about 5 × 10 ¹⁵ cm ⁻² , thereby forming a p-type. The p-type high-concentration impurity region 55b constituting the source / drain region 55 is formed. Thereafter, the resist film 58b is removed. Then, the implanted impurities are activated by performing a heat treatment at about 700 ° C. to about 1100 ° C. for about 0.1 seconds to about 60 seconds by the RTA method.

  The low-concentration impurity regions 45a and 55a and the high-concentration impurity regions 45b and 55b form a pair of source / drain regions 45 and 55 having an LDD structure.

  Note that fluorine existing in the gate electrodes 44a and 44b is diffused into the sidewall insulating film 46 by the above-described heat treatment by the RTA method. Further, the fluorine in the fluorine region 57 existing in the p-well region 52a and the n-well region 52b also depends on the side wall insulating film 46 and the low-concentration impurity regions 45a and 55a and the high-concentration impurity regions 45b and 55b in the gate insulating film 43. It is diffused to the neighboring area. At this time, the silicon nitride film 47 prevents fluorine from diffusing out of the p-type single crystal silicon substrate 41. This makes it possible to introduce fluorine into at least the region shown in FIG. 28 of the n-channel MOS transistor. The same applies to the distribution of fluorine in the p-channel MOS transistor. After that, the silicon nitride film 47 is removed.

Next, as shown in FIG. 43, the upper surfaces of gate electrodes 44a and 44b made of polycrystalline silicon and the upper surfaces of high-concentration impurity regions 45b and 55b forming source / drain regions 45 and 55 are formed using a salicide process. On the top, silicide films 48a and 48b made of cobalt silicide (CoSi ₂ ) are formed in a self-aligned manner.

  Thereafter, as shown in FIG. 27, after an interlayer insulating film 49 is formed by using a CVD method, contact holes 49a, 49b, and 49b are formed in predetermined regions by using a photolithography technique and a dry etching technique such as RIE. 49c and 49d are formed. Plugs 50a, 50b, 50c and 50d are formed by burying tungsten in the contact holes 49a, 49b, 49c and 49d by using the CVD method. Finally, a Ti layer having a thickness of about 30 nm, a TiN layer having a thickness of about 30 nm, and an AlCu layer having a thickness of about 400 nm are formed on the upper surface of the interlayer insulating film 49 from the lower layer to the upper layer. After the formation of the laminated film, the upper wirings 51a and 51b are formed by patterning the laminated film. Thus, the CMOS inverter (semiconductor device) according to the third embodiment is formed.

  In the third embodiment, as described above, fluorine ion-implanted into the gate electrodes 44a and 44b is diffused by thermal diffusion into the sidewall insulating film 46 made of the silicon oxide film of the n-channel MOS transistor and the p-channel MOS transistor. Thereby, the dielectric constant of sidewall insulating film 46 can be reduced, so that an overlap capacitance generated between gate electrodes 44a and 44b of n-channel MOS transistor and p-channel MOS transistor and source / drain regions 45 and 55 is formed. Can be sufficiently reduced. As a result, the operation speed of the semiconductor device (CMOS inverter) can be improved.

  In the third embodiment, as described above, fluorine is also supplied to the sidewall insulating films 46 of the n-channel MOS transistor and the p-channel MOS transistor from the fluorine region 57 existing in the p-well region 52a and the n-well region 52b. By the diffusion, the dielectric constant of the sidewall insulating film 46 can be further reduced. Thus, the overlap capacitance generated between gate electrodes 44a and 44b of n-channel MOS transistor and p-channel MOS transistor and source / drain regions 45 and 55 can be reduced more sufficiently. Further, since fluorine is also introduced into the low-concentration impurity regions 45a and 55a and the regions near the gate insulating film 43 in the high-concentration impurity regions 45b and 55b, the overlap capacitance can be further reduced. As a result, the operation speed of the semiconductor device can be further improved.

  Further, in the third embodiment, a silicon nitride film 47 is formed on the entire surface after the formation of the sidewall insulating film 46, so that fluorine ion-implanted into the gate electrodes 44a and 44b can be treated by heat treatment in the sidewall insulating film 46. Can be prevented from diffusing out of the side wall insulating film 46 when diffusing. Thereby, the dielectric constant of the silicon oxide film forming side wall insulating film 46 can be sufficiently reduced, so that source / drain regions 45 and 55 of n-channel MOS transistor and p-channel MOS transistor and gate electrodes 44a and 44b are formed. , The overlap capacity generated between them can be further reduced sufficiently. As a result, the operation speed of the semiconductor device can be further improved.

(Fourth embodiment)
FIG. 44 is a sectional view showing the semiconductor device according to the fourth embodiment of the present invention. Referring to FIG. 44, in the fourth embodiment, an example will be described in which fluorine for terminating dangling bonds is introduced into the gate insulating film and the interface between the gate insulating film and the center of the channel region.

  In the semiconductor device according to the fourth embodiment, as shown in FIG. 44, an STI structure for separating an adjacent element formation region (active region) is formed in a predetermined region on a main surface of a p-type single crystal silicon substrate 61. Element isolations 62a, 62b and 62c having the same are formed. A p-well region 73 is formed in a region of the p-type single crystal silicon substrate 61 where an n-channel MOS transistor is formed, and an n-well region 74 is formed in a region where a p-channel MOS transistor is formed. Have been. Note that the p-well region 73 and the n-well region 74 are examples of the “semiconductor region” of the present invention. In the p well region 73, a pair of n-type source / drain regions 65 are formed at predetermined intervals so as to sandwich the channel region 61a. The n-type source / drain region 65 has an LDD structure including an n-type low concentration impurity region (extension region) 65a and an n-type high concentration impurity region 65b. The n-type source / drain region 65 is an example of the “impurity region” of the present invention. On the channel region 61a, a gate electrode 64a made of polycrystalline silicon is formed via a gate insulating film 63 made of a silicon oxynitride film. The pair of n-type source / drain regions 65, the gate insulating film 63, and the gate electrode 64a form an n-channel MOS transistor.

  In the n-well region 74, a pair of p-type source / drain regions 75 are formed at predetermined intervals so as to sandwich the channel region 61b. The p-type source / drain region 75 has an LDD structure including a p-type low concentration impurity region (extension region) 75a and a p-type high concentration impurity region 75b. The p-type source / drain region 75 is an example of the “impurity region” of the present invention. On the channel region 61b, a gate electrode 64b made of a polycrystalline silicon layer is formed via a gate insulating film 63 made of a silicon oxynitride film. A pair of p-type source / drain regions 75, gate insulating film 63, and gate electrode 64b form a p-channel MOS transistor.

  Here, in the fourth embodiment, fluorine is introduced into the gate insulating film 63 and the interface between the gate insulating film and the entire region of the channel regions 61a and 61b.

A sidewall insulating film 66 made of a silicon oxide film or the like is formed on side surfaces of the gate electrodes 64a and 64b constituting the n-channel MOS transistor and the p-channel MOS transistor. Silicide films 67a and 67b made of CoSi ₂ are formed on the upper surfaces of the gate electrodes 64a and 64b and on the upper surfaces of the high-concentration impurity regions 65b and 75b forming the source / drain regions 65 and 75, respectively.

  Further, an interlayer insulating film 68 made of a silicon oxide film is formed so as to cover the entire surface. This interlayer insulating film 68 has contact holes 68a, 68b, 68c and 68d reaching the silicide films 67a and 67b, respectively. Plugs 69a, 69b, 69c and 69d made of tungsten are buried in the contact holes 68a, 68b, 68c and 68d, respectively. Wirings 70a, 70b, 70c and 70d are formed to be connected to plugs 69a, 69b, 69c and 69d, respectively.

  In the semiconductor device according to the fourth embodiment, as described above, fluorine is introduced over the interface between the gate insulating film and the entire region of the channel regions 61a and 61b, so that the dangling is caused by the fluorine over the entire region of the channel regions 61a and 61b. The bond can be terminated. Further, by introducing fluorine into the gate insulating film 63, dangling bonds in the gate insulating film 63 can also be terminated by fluorine. Thereby, the fluctuation of the threshold voltage due to the dangling bond can be suppressed. In addition, a change in saturation current due to dangling bonds can be suppressed.

  Further, in the fourth embodiment, as described above, the termination of the dangling bond is performed by using the fluorine ion that bonds to the silicon atom with a binding energy stronger than that of hydrogen, so that the characteristics of the transistor are stabilized for a long time. be able to.

  Next, FIGS. 45 to 52 are cross-sectional views for explaining the manufacturing process of the semiconductor device according to the fourth embodiment of the present invention shown in FIG. FIG. 53 is a correlation diagram showing the relationship between the dose of fluorine ions and the NBTI lifetime of the PMOSFET. FIG. 54 is a correlation diagram showing the relationship between the voltage application time and the amount of change in the threshold voltage. The manufacturing process of the semiconductor device according to the fourth embodiment will be explained with reference to FIGS.

First, as shown in FIG. 45, element isolations 62a, 62b and 62c are formed on a p-type single crystal silicon substrate 61 by STI. Then, a resist film 76 is formed on the region where the n-channel MOS transistor is formed. Using resist film 76 as a mask, phosphorus (P) is ion-implanted into p-type single-crystal silicon substrate 61 to form n-well region 74. Further, using resist film 76 as a mask, arsenic (As) is ion-implanted from above n-well region 74 to adjust the threshold voltage. At this time, the implantation conditions of arsenic (As) are as follows: implantation amount: about 0.5 × 10 ¹² cm ⁻² to about 1 × 10 ¹³ cm ⁻² , and implantation energy: about 120 keV. After that, the resist film 76 is removed.

Next, as shown in FIG. 46, a resist film 77 is formed so as to cover the formation region of the p-channel MOS transistor. Using the resist film 77 as a mask, boron (B) is ion-implanted into the p-type single-crystal silicon substrate 61 to form a p-well region 73. Then, using the resist film 77 as a mask, boron (B) ions are implanted into the surface of the p-well region 73 to adjust the threshold voltage. At this time, the implantation conditions of boron (B) are as follows: implantation amount: about 1 × 10 ¹² cm ⁻² to about 1 × 10 ¹³ cm ⁻² , and implantation energy: about 20 keV. After that, the resist film 77 is removed.

  Next, as shown in FIG. 47, a heat treatment is performed in an oxidizing atmosphere to form a silicon oxide film with a thickness of about 2 nm to about 10 nm on the surface of the p-type single crystal silicon substrate 61. This forms a gate insulating film 63 made of a silicon oxynitride film having a thickness of about 2 nm to about 10 nm on the surface of the p-type single crystal silicon substrate 61. Thereafter, a polycrystalline silicon film (not shown) is deposited on the entire surface to a thickness of about 150 nm to about 200 nm using a CVD method, and then the polycrystalline silicon film is formed using a normal photolithography process and an etching technique by RIE. The crystalline silicon film is patterned. Thus, gate electrodes 64a and 64b made of a polycrystalline silicon film are formed. The gate electrodes 64a and 64b according to the fourth embodiment are formed so as to have a thickness of about 200 nm and a gate length of about 0.3 μm to about 1 μm.

  Note that since the gate insulating film 63 is greatly damaged by etching when forming the gate electrodes 64a and 64b, the gate insulating film 63 is re-oxidized after forming the gate electrodes 64a and 64b.

Next, as shown in FIG. 48, a resist film 78 is formed so as to cover the region where the p-channel MOS transistor is formed. Using the resist film 78 as a mask, phosphorus (P) is implanted at an implantation energy of about 30 keV, an implantation amount of about 0.5 × 10 ¹³ cm ⁻² to about 5 × 10 ¹⁴ cm ⁻² , and an incident angle of about 7 degrees. Ion implantation is performed four times while rotating the p-type single crystal silicon substrate 61 by 90 degrees. Thus, an n-type low concentration impurity region 65a is formed. Thereafter, the resist film 78 is removed.

Next, as shown in FIG. 49, a resist film 79 is formed so as to cover a region where the n-channel MOS transistor is formed. Then, boron difluoride (BF ₂ ) is implanted into the main surface of the p-well region 74 at an implantation energy of about 15 keV, an implantation amount of about 1 × 10 ¹³ cm ⁻² to about 5 × 10 ¹⁴ cm ^{−2, and} an implantation amount of about 7 degrees. The ion implantation is performed four times while rotating the p-type single-crystal silicon substrate 61 at an angle of 90 degrees. Thus, a p-type low concentration impurity region 75a is formed.

Then, as shown in FIG. 50, using resist film 79 as a mask, fluorine (F) is implanted into low-concentration impurity region 75a and gate electrode 64b constituting the p-channel MOS transistor with an implantation energy of about 20 keV and about 3 × 10 Ion implantation is performed at an implantation amount of ¹⁵ cm ⁻² to about 5 × 10 ¹⁵ cm ⁻² . The conditions for the fluorine implantation are set so that the fluorine ions do not penetrate through the gate electrode 64b and reach the gate insulating film 63. Therefore, the fluorine ions are implanted into the gate electrode 64b to a position near the gate insulating film 63.

Next, as shown in FIG. 51, an insulating film (not shown) made of a silicon oxide film or the like is deposited on the entire surface by using the CVD method, and the insulating film is etched back by using the RIE method. A sidewall insulating film 66 is formed on side surfaces of the gate electrodes 64a and 64b. Thereafter, a resist film 80 is formed so as to cover the formation region of the pMOS transistor. Then, using the resist film 80 as a mask, arsenic (As) is implanted into the main surface of the p-well region 73 at an implantation energy of about 45 keV and about 1 ×. Ion implantation is performed at a dose of 10 ¹⁵ cm ⁻² to about 5 × 10 ¹⁵ cm ⁻² . Thus, an n-type high-concentration impurity region 65b constituting the n-type source / drain region 65 is formed. After that, the resist film 80 is removed.

Next, as shown in FIG. 52, a resist film 81 is formed so as to cover a region where the n-channel MOS transistor is formed. Using the resist film 81 as a mask, boron (B) is ion-implanted with an implantation energy of about 7 keV and an implantation amount of about 5 × 10 ¹⁵ cm ⁻² , thereby forming a p-type source / drain region 75 constituting the p-type source / drain region 75. A high concentration impurity region 75b is formed. After that, the resist film 81 is removed.

  Thereafter, a heat treatment by RTA is performed to activate the implanted impurities and diffuse the fluorine implanted into the gate electrode 64b. This heat treatment by RTA is performed at an ambient temperature of about 1050 ° C. for about 5 seconds. By the heat treatment by the RTA, fluorine is diffused from the gate electrode 64b and the low-concentration impurity regions 75a. The diffusion speed of fluorine is faster inside the gate electrode 64b than inside the p-type silicon substrate 61. Therefore, fluorine is diffused from the gate electrode 64b via the gate insulating film 63 to the channel region 61b located at the interface between the gate insulating film 63 and the n-well region 74. At this time, fluorine is diffused gradually from the low-concentration impurity region 75a toward the central region of the channel region 61b.

  By diffusing fluorine from the gate electrode 64b to the interface between the gate insulating film and the channel region 61b via the gate insulating film 63, even if the channel length of the p-channel MOS transistor is long, the channel region 61b can be easily formed. Can be diffused over the entire region. In this case, the time required for diffusing fluorine from the gate electrode 64b to the interface between the gate insulating film 63 and the p-type single crystal silicon substrate 61 is much longer than the time required for diffusing fluorine only from the low concentration impurity region 75a. short. Further, fluorine can be diffused from the gate electrode 64b and the low-concentration impurity region 75a by one heat treatment by RTA, so that the manufacturing process can be simplified.

As shown in FIG. 44, the salicide process is used to self-align on the upper surfaces of polycrystalline silicon gate electrodes 64a and 64b and the upper surfaces of high concentration impurity regions 65b and 75b, respectively. Then, cobalt silicide (CoSi ₂ ) films 67a and 67b are formed. Then, after the interlayer insulating film 68 is formed by using the CVD method, contact holes 68a, 68b, 68c, and 68d are formed in predetermined regions by using a photolithography technique and a dry etching technique such as RIE. Plugs 69a, 69b, 69c and 69d are formed by embedding tungsten in the contact holes 68a, 68b, 68c and 68d using the CVD method. Finally, upper wirings 70a, 70b, 70c and 70d made of aluminum or the like are formed on the upper surface of the interlayer insulating film 68 so as to be connected to the plugs 69a, 69b, 69c and 69d, respectively.

FIG. 53 shows the relationship between the dose (implantation amount) of fluorine ions and the life of NBTI (Negative Bias Temperature Instability). Note that NBTI refers to a phenomenon in which the characteristics of a transistor fluctuate when a negative voltage is continuously applied to a gate electrode with respect to a substrate at a high temperature. The horizontal axis of FIG. 53 shows the dose (atom / cm ² ) of fluorine ions, and the vertical axis shows time (lifetime until the characteristic deterioration of the semiconductor device). Referring to FIG. 53, it can be seen that in the measured range, the life of the semiconductor device up to the characteristic deterioration becomes longer as the dose amount (implantation amount) of fluorine ions increases.

  FIG. 54 shows the change amount (ΔVt) of the threshold voltage with the voltage application time (T) in the semiconductor device. In FIG. 54, the horizontal axis indicates time, and the vertical axis indicates the amount of change in threshold voltage (ΔVt). The change in threshold voltage (ΔVt) is a value measured by applying a voltage of 0 V to the source / drain regions and the substrate of the p-channel MOS transistor and applying a voltage of −4.6 V to the gate electrode. Referring to FIG. 54, it can be seen that the semiconductor device according to the fourth embodiment in which fluorine is implanted has a smaller threshold voltage change (ΔVt) than the conventional semiconductor device in which fluorine is not implanted. . Thus, it was confirmed that the amount of change in the threshold voltage (ΔVt) can be reduced by performing fluorine implantation.

  In the manufacturing process of the semiconductor device according to the fourth embodiment, the fluorine of the gate electrode 64b is diffused into the channel region 61b via the gate insulating film 63, and the fluorine of the low concentration impurity region 75a is diffused into the channel region 61b. Thus, fluorine can be diffused into the gate insulating film 63 and more fluorine can be diffused into the entire channel region 61b. Thereby, more dangling bonds existing in the gate insulating film 63 and in the entire channel region 61b can be terminated by fluorine. As a result, due to the dangling bond in the gate insulating film 63 and the dangling bond at the interface between the gate insulating film and the central region of the channel region 61b when the gate length (channel length) is large, the formation of the p-channel MOS transistor is reduced. A large fluctuation of the threshold voltage can be further suppressed.

  It should be noted that the embodiments disclosed this time are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

  For example, in the first embodiment, a method of forming a p-channel MOS transistor has been described. However, the present invention is not limited to this, and the present invention may be applied to an n-channel MOS transistor.

  In the first and second embodiments, the parasitic capacitance generated at the pn junction interface of the source / drain region is reduced by introducing fluorine. However, the present invention is not limited to this, and carbon may be introduced. . Carbon, like fluorine, is an element that forms a bond with silicon. Since carbon is lighter than silicon and does not serve as a donor or an acceptor, the relative dielectric constant of the silicon substrate can be reduced. Actually, the relative dielectric constant of SiC is about 7, which is lower than the relative dielectric constant of Si of about 11. Therefore, the parasitic capacitance generated at the pn junction can be reduced. Further, the same effect can be obtained by introducing both fluorine and carbon.

In the first and second embodiments, the fluorine region into which fluorine is introduced is formed by ion-implanting fluorine at an implantation energy of about 20 keV and an implantation amount of about 3 × 10 ¹⁵ cm ^−2. The fluorine region may be formed by ion implantation at an implantation energy of 5 keV to about 30 keV and an implantation amount of about 1.5 × 10 ¹⁵ cm ⁻² to about 3.0 × 10 ¹⁵ cm ⁻² . In this way, the threshold voltage does not fluctuate beyond the allowable range.

  In the first embodiment, as shown in FIG. 7, fluorine is ion-implanted on the entire surface after the formation of the low-concentration impurity region 5a, but the ion implantation is performed at a stage other than after the formation of the low-concentration impurity region 5a. May be. For example, it may be before the formation of the element isolations 2a and 2b shown in FIG. 3, before the ion implantation of arsenic (As) for adjusting the threshold voltage shown in FIG. 4, or after the ion implantation. Further, it may be before forming the gate electrode 4 shown in FIG. 5 or after forming the high-concentration impurity region 5b shown in FIG. Instead of ion-implanting fluorine into the entire surface, an ion-implantation mask may be formed and ion-implanted into a part of the n-type single crystal silicon substrate 1.

  In the second embodiment, as shown in FIG. 21, fluorine is ion-implanted on the entire surface after the low-concentration impurity regions 25a and 35a are formed, but the ion-implantation is performed at a stage other than after the low-concentration impurity regions 25a and 35a are formed. May be. For example, it may be before forming the element isolations 22a, 22b and 22c shown in FIG. 14, or after forming the sacrificial oxide film 36. Further, fluorine may be ion-implanted before or after ion implantation for forming n-well region 14b shown in FIG. 15 and p-well region 14a shown in FIG. Further, before or after ion implantation of arsenic (As) for adjusting the threshold voltage shown in FIG. 15, before ion implantation of boron (B) for adjusting the threshold voltage shown in FIG. It may be after ion implantation. In addition, even before the formation of the gate electrodes 24a and 24b shown in FIG. 17, after the formation of the n-type high-concentration impurity region 25b shown in FIG. 24, or even after the formation of the p-type high-concentration impurity region 35b shown in FIG. Good.

  In the first to fourth embodiments, the plug made of tungsten is directly buried in the contact hole. However, before the plug made of tungsten is buried, a Ti layer having a thickness of about 10 nm and a Ti layer having a thickness of about 10 nm are formed. A barrier layer composed of a TiN layer may be formed.

  In the third embodiment, the case where fluorine is introduced into the sidewall insulating film of the CMOS inverter has been described. However, the present invention is not limited to this, and one of the n-channel MOS transistor and the p-channel MOS transistor may be used. Fluorine may be introduced into the wall insulating film.

  In the third embodiment, the overlap capacitance between the gate electrode and the source / drain region is reduced by introducing fluorine. However, the present invention is not limited to this, and the dielectric constant other than fluorine is reduced. Even if an element is introduced, a similar effect can be obtained. As an element for reducing the dielectric constant other than fluorine, for example, carbon can be considered.

  Further, in the third embodiment, the example in which the silicon oxide film (insulating film) forming the sidewall insulating film is formed by using the thermal CVD method has been described. However, the present invention is not limited to this, and the plasma CVD method is used. After the formation of the sidewall insulating film, heat treatment may be performed at a temperature of about 400 ° C. Even in this case, it is possible to diffuse fluorine in the gate electrode into the sidewall insulating film.

  Further, in the third embodiment, a silicon oxide film is used as a material forming the sidewall insulating film into which fluorine is introduced. However, the present invention is not limited to this, and an insulating film containing Si other than the silicon oxide film may be used. Fluorine may be introduced into the sidewall insulating film made of. Further, fluorine may be introduced into a sidewall insulating film made of an insulating film containing no Si.

In the third embodiment, fluorine is ion-implanted at an implantation energy of about 10 keV and an implantation amount of about 3 × 10 ¹⁵ cm ⁻² , but is implanted at an implantation energy of about 5 keV to about 30 keV and about 1.5 × 10 ¹⁵ cm ^−2. Fluorine may be ion-implanted at a dose of cm ⁻² to about 5.0 × 10 ¹⁵ cm ⁻² .

  In the third embodiment, as shown in FIG. 43, in the salicide process, all of the silicon nitride film 47 (see FIG. 42) is removed, but the silicon nitride film 47 in a region where formation of silicide is unnecessary is left. Is also good. In this case, after removing the resist film 58b in FIG. 42, a silicon oxide film is formed on the entire surface by the CVD method. Then, patterning is performed using a photolithography technique and a wet etching technique so that a stacked film of the silicon nitride film 47 and the silicon oxide film is left in a region where the formation of the silicide film is unnecessary. Thus, in the salicide process, it is possible to prevent the silicide film from being formed in a portion where the stacked film of the silicon nitride film 47 and the silicon oxide film remains. In this manner, as shown in FIG. 42, a region where the silicon nitride film 47 is entirely removed and a region where the silicon nitride film 47 is entirely left (not shown) may be formed.

  In the above-described first to fourth embodiments, the activation of the impurity for fluorine implantation is performed by the heat treatment using the RTA. However, the present invention is not limited to this, and may be performed by furnace annealing. The processing conditions in that case are, for example, heating temperature: about 700 ° C. to about 900 ° C., and processing temperature: about 30 minutes to about 60 minutes.

  Further, in the fourth embodiment, an example in which the dangling bond in the channel region 61b is terminated by fluorine has been described, but the present invention is not limited to this, and the dangling bond is terminated by a halogen element other than fluorine. Is also good.

Further, in the fourth embodiment, fluorine is ion-implanted at an implantation energy of about 20 KeV and an implantation amount of about 3 × 10 ¹⁵ cm ⁻² , but the present invention is not limited to this, and an implantation energy of about 10 KeV to about 20 KeV is used. Fluorine may be ion-implanted at a dose of about 1.5 × 10 ¹⁵ cm ⁻² to about 5.0 × 10 ¹⁵ cm ⁻² .

  Further, in the above embodiment, the source / drain region is constituted by the low-concentration impurity region and the high-concentration impurity region. It is also possible.

  In each of the first and second embodiments, the third embodiment, and the fourth embodiment, a region that straddles a junction interface between a semiconductor substrate (well region) and a source / drain region, and a sidewall insulating film is formed. Although an example in which fluorine is introduced into the film, the channel region, and the gate insulating film has been described, the present invention is not limited to this, and a region straddling the junction interface between the semiconductor substrate (well region) and the source / drain region, Fluorine may be introduced into the entire wall insulating film, the interface between the gate insulating film and the channel region, and the gate insulating film. In addition, any one of a region extending over a junction interface between the semiconductor substrate (well region) and the source / drain region, a sidewall insulating film, an interface between a gate insulating film and a channel region, and a gate insulating film You may make it introduce | transduce fluorine. Further, either fluorine or carbon may be introduced into both the region over the junction interface between the semiconductor substrate (well region) and the source / drain region and the sidewall insulating film.

FIG. 2 is a sectional view showing the semiconductor device according to the first embodiment of the present invention. FIG. 7 is a correlation diagram showing a relationship between the amount of fluorine ions implanted near the pn junction and the parasitic capacitance generated near the pn junction. FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1. FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1. FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1. FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1. FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1. FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1. FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1. FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1. FIG. 2 is a cross-sectional view for explaining a manufacturing process of the semiconductor device according to the first embodiment of the present invention shown in FIG. 1. FIG. 4 is a correlation diagram showing a relationship between the amount of fluorine ions implanted near a pn junction and the threshold voltage of a p-channel MOS transistor. FIG. 5 is a sectional view illustrating a semiconductor device according to a second embodiment of the present invention. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 14 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the second embodiment of the present invention shown in FIG. FIG. 9 is a sectional view showing a semiconductor device according to a third embodiment of the present invention. 28 is an enlarged view around a MOS transistor of the semiconductor device according to the third embodiment shown in FIG. 27. FIG. FIG. 4 is a correlation diagram showing a relationship between a peripheral length of a gate electrode and an overlap capacitance generated between a gate electrode and a source / drain when fluorine ions are implanted and when they are not implanted. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 28 is a cross-sectional view for explaining the manufacturing process of the semiconductor device according to the third embodiment of the present invention shown in FIG. 27. FIG. 11 is a sectional view illustrating a semiconductor device according to a fourth embodiment of the present invention. FIG. 45 is a cross-sectional view for explaining the manufacturing process for the semiconductor device according to the fourth embodiment shown in FIG. 44. FIG. 45 is a cross-sectional view for explaining the manufacturing process for the semiconductor device according to the fourth embodiment shown in FIG. 44. FIG. 45 is a cross-sectional view for explaining the manufacturing process for the semiconductor device according to the fourth embodiment shown in FIG. 44. FIG. 45 is a cross-sectional view for explaining the manufacturing process for the semiconductor device according to the fourth embodiment shown in FIG. 44. FIG. 45 is a cross-sectional view for explaining the manufacturing process for the semiconductor device according to the fourth embodiment shown in FIG. 44. FIG. 45 is a cross-sectional view for explaining the manufacturing process for the semiconductor device according to the fourth embodiment shown in FIG. 44. FIG. 45 is a cross-sectional view for explaining the manufacturing process for the semiconductor device according to the fourth embodiment shown in FIG. 44. FIG. 45 is a cross-sectional view for explaining the manufacturing process for the semiconductor device according to the fourth embodiment shown in FIG. 44. FIG. 4 is a correlation diagram showing a relationship between a dose amount of fluorine ions and an NBTI lifetime of a PMOSFET. FIG. 6 is a correlation diagram showing a relationship between a voltage application time and a threshold voltage change amount.

Explanation of reference numerals

1 n-type single crystal silicon substrate (first conductivity type semiconductor region)
1a, 21a, 21b, 41a, 41b, 61a, 61b Channel region 3, 23, 43, 63 Gate insulating film 4, 24a, 24b, 44a, 44b, 64a, 64b Gate electrode 5, 25, 35, 65, 75 Source / Drain region (impurity region)
5a, 25a, 35a, 45a, 55a, 65a, 75a Low concentration impurity region 5b, 25b, 35b, 45b, 55b, 65b, 75b High concentration impurity region 6, 26a, 26b, 57 Fluorine region 7, 27, 46, 66 Sidewall insulating film 10, 30, 49, 68 Interlayer insulating film 14a, 73 p-well region (semiconductor region)
14b, 74 n-well region (semiconductor region)
21, 41, 61 p-type single-crystal silicon substrate 45, 55 source / drain region 52a p-well region 52b n-well region

Claims (13)

A first conductivity type semiconductor region having a main surface;
A second conductivity type source / drain region formed on a main surface of the semiconductor region at a predetermined interval to sandwich a channel region;
A gate electrode formed on the channel region via a gate insulating film;
A sidewall insulating film formed on a side surface of the gate electrode,
A region extending over a junction interface between the semiconductor region of the first conductivity type and the source / drain region of the second conductivity type, an interface between the gate insulating film and at least a central region of the channel region, and the gate insulating film; A semiconductor device, wherein fluorine is introduced into at least one of the sidewall insulating film. A first conductivity type semiconductor region having a main surface;
A second conductivity type impurity region formed on a main surface of the semiconductor region;
A semiconductor device, wherein at least one element of fluorine and carbon is introduced into a region straddling a junction interface between the semiconductor region of the first conductivity type and the impurity region of the second conductivity type. The impurity region includes a low concentration impurity region and a high concentration impurity region,
3. The semiconductor device according to claim 2, wherein at least one element of fluorine and carbon is introduced into at least a region across a junction interface between the semiconductor region of the first conductivity type and the high-concentration impurity region. 4. A first conductivity type semiconductor region having a main surface;
A second conductivity type source / drain region formed on a main surface of the semiconductor region at a predetermined interval to sandwich a channel region;
A gate electrode formed on the channel region via a gate insulating film;
A sidewall insulating film formed on a side surface of the gate electrode,
A semiconductor device, wherein an element for reducing a dielectric constant is introduced into the sidewall insulating film.   The semiconductor device according to claim 4, wherein the element that reduces the dielectric constant includes at least one element of fluorine and carbon. A first conductivity type semiconductor region having a main surface;
A second conductivity type source / drain region formed on a main surface of the semiconductor region at a predetermined interval to sandwich a channel region;
A gate electrode formed on the channel region via a gate insulating film;
A semiconductor device in which a halogen element is introduced into an interface between the gate insulating film and at least a central region of the channel region and the gate insulating film.   The semiconductor device according to claim 6, wherein the halogen element is fluorine. Forming source / drain regions of the second conductivity type on the main surface of the semiconductor region of the first conductivity type so as to sandwich the channel region at a predetermined interval;
Forming a gate electrode on the channel region via a gate insulating film;
Forming a sidewall insulating film on a side surface of the gate electrode;
A region extending over a junction interface between the semiconductor region of the first conductivity type and the source / drain region of the second conductivity type, an interface between the gate insulating film and at least a central region of the channel region, and the gate insulating film; A step of introducing fluorine into at least one of the sidewall insulating films. The step of introducing fluorine,
After the fluorine is ion-implanted into the gate electrode, the fluorine is diffused from the gate electrode to the sidewall insulating film by performing a heat treatment, and the gate insulating film and the gate insulating film and the channel are diffused from the gate electrode. The method for manufacturing a semiconductor device according to claim 8, further comprising a step of diffusing the fluorine into an interface with at least a central region of the region. The step of introducing fluorine,
The method of manufacturing a semiconductor device according to claim 8, further comprising a step of ion-implanting fluorine into a region straddling a junction interface between the semiconductor region of the first conductivity type and the source / drain region of the second conductivity type. Forming an impurity region of the second conductivity type on the main surface of the semiconductor region of the first conductivity type;
A step of ion-implanting at least one element of fluorine and carbon into a region straddling a junction interface between the impurity region of the second conductivity type and the semiconductor region of the first conductivity type. Method. Forming a gate electrode on the surface of the semiconductor region of the first conductivity type via a gate insulating film;
Ion-implanting at least the gate electrode with an element that reduces the dielectric constant,
Forming a sidewall insulating film on a side surface of the gate electrode;
Forming a silicon nitride film on at least the sidewall insulating film;
Diffusing an element for reducing the dielectric constant from the gate electrode into the sidewall insulating film by heat treatment. Forming a gate electrode on the main surface of the silicon substrate via a gate insulating film;
A step of ion-implanting a halogen element into the gate electrode;
A method of manufacturing a semiconductor device, comprising: diffusing a halogen element in the gate electrode into a gate insulating film and an interface between the gate insulating film and the silicon substrate by heat-treating the silicon substrate.

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