JP2009105163A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having high carrier mobility in a channel region. <P>SOLUTION: The semiconductor device 1 is provided with a semiconductor substrate 2, a semiconductor layer 3 which is formed on the semiconductor substrate and is formed of first crystal whose inner carrier mobility is higher than a Si crystal, a gate insulting film 4 formed on the semiconductor layer, a gate electrode formed on the gate insulating film and source/drain regions which are formed by sandwiching the semiconductor layer, include second crystal giving distortion to the semiconductor layer in a direction where carrier mobility in the semiconductor layer rises and have source/drain extension regions being shallow regions which are brought into contact with the semiconductor layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  As a conventional semiconductor device, there is a semiconductor device in which strain is generated by applying tensile stress to the channel region by epitaxially growing a SiC crystal having a lattice constant smaller than that of the Si crystal at a position sandwiching the channel region of the n-type transistor. (For example, refer to Patent Document 1). According to the semiconductor device described in Patent Document 1, tensile strain is generated in the Si crystal constituting the channel region, thereby improving the mobility of electrons in the channel region and improving the operation speed of the n-type transistor. be able to.

As another conventional semiconductor device, a technique is known in which a Ge crystal whose internal electron mobility is larger than that of a Si crystal is used for a channel region (see, for example, Non-Patent Document 1).
US Pat. No. 6,621,131 S. Takagi et al., SSDM, p. 1056-1057 (2006).

  An object of the present invention is to provide a semiconductor device having high carrier mobility in a channel region.

  One embodiment of the present invention is a semiconductor substrate, a semiconductor layer formed over the semiconductor substrate and including a first crystal in which carrier mobility inside the Si crystal is larger than that of a Si crystal, and a gate formed over the semiconductor layer An insulating film, a gate electrode formed on the gate insulating film, and the semiconductor layer are sandwiched therebetween, and a second strain is applied to the semiconductor layer in a direction in which the mobility of carriers in the semiconductor layer increases. And a source / drain region having a source / drain extension region which is a shallow region in contact with the semiconductor layer.

  According to the present invention, a semiconductor device having high carrier mobility in a channel region can be provided.

[First Embodiment]
(Configuration of semiconductor device)
FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention. The semiconductor device 1 includes a semiconductor substrate 2, a semiconductor layer 3 formed on the semiconductor substrate 2, a gate insulating film 4 formed on the semiconductor layer 3, and a gate electrode 5 formed on the gate insulating film 4. The offset spacer 6 and the gate sidewall 8 formed on the side surface of the gate electrode 5, the epitaxial layer 7 including the extension region 7 e formed with the semiconductor layer 3 interposed therebetween, and the element isolation region 10 formed in the semiconductor substrate 2. And is schematically configured.

  For example, a Si substrate is used as the semiconductor substrate 2.

  The semiconductor layer 3 is made of a crystal such as SiGe, Ge, GaAs, InP, InAs, InSb, or the like, in which the carrier mobility inside is larger than that of the Si crystal. When the semiconductor layer 3 is made of SiGe crystal, the Ge concentration is preferably 10 to 30 atomic%. When the Ge concentration of the SiGe crystal is less than 10 atomic%, the carrier mobility does not increase effectively, and when it exceeds 30 atomic%, a crystal defect is generated in an adjacent crystal or the like, causing a leakage current. There is a risk.

  The semiconductor layer 3 preferably has a thickness equal to or less than the thickness of the inversion layer generated during the operation of the semiconductor device 1. This is because even if the semiconductor layer 3 is thicker than the inversion layer, the carrier does not move in a region thicker than the inversion layer, and the operation speed of the semiconductor device 1 hardly changes. Further, when the semiconductor layer 3 is a crystal that is distorted in the direction in which the carrier mobility in the interior decreases due to the stress received from the semiconductor substrate 2, the thickness of the semiconductor layer 3 increases as the semiconductor layer 3 increases in thickness. This is because the degree decreases. Note that the thickness of the inversion layer is, for example, 2 to 3 nm.

The gate insulating film 4 is made of, for example, SiO ₂ , SiN, SiON, high dielectric material (for example, Hf-based material such as HfSiON, HfSiO, HfO, Zr-based material such as ZrSiON, ZrSiO, ZrO, Y ₂ O _3, etc. Y-based material).

The gate electrode 5 is made of, for example, polycrystalline Si or polycrystalline SiGe containing a conductive impurity. As the conductive impurities contained in the gate electrode 5, p-type impurity ions such as B and BF ₂ are used in the case of a p-type transistor, and n-type impurity ions such as As and P are used in the case of an n-type transistor. Further, the gate electrode 4 may be a metal gate electrode made of W, Ta, Ti, Hf, Zr, Ru, Pt, Ir, Mo, Al or the like or a compound thereof. Moreover, the structure which laminated | stacked the metal gate electrode and the polycrystal Si type | system | group electrode may be sufficient. A silicide layer may be formed on the upper surface of the gate electrode 5.

The offset spacer 6 is made of, for example, SiO ₂ or SiN.

The gate sidewall 8 may have a single-layer structure made of, for example, SiN, a two-layer structure made of a plurality of kinds of insulating materials such as SiN, SiO ₂ , TEOS (Tetraethoxysilane), or a structure having three or more layers.

  In the case of a p-type transistor, the epitaxial layer 7 and its extension region 7e are formed by epitaxially growing a crystal having a lattice constant larger than that of the crystal constituting the semiconductor substrate 2. For example, when the semiconductor substrate 2 is made of Si crystal, SiGe crystal or the like is epitaxially grown. On the other hand, the n-type transistor is formed by epitaxially growing a crystal having a lattice constant smaller than that of the crystal constituting the semiconductor substrate 2. For example, when the semiconductor substrate 2 is made of Si crystal, SiC crystal or the like is epitaxially grown.

  Here, when the epitaxial layer 7 and the extension region 7e are made of a crystal having a larger lattice constant than the crystal constituting the semiconductor substrate 2, the epitaxial layer 7 and the extension region 7e cause compressive strain on the semiconductor layer 3 that functions as a channel region. Thus, the mobility of holes inside the semiconductor layer 3 can be improved. On the other hand, when the epitaxial layer 7 and the extension region 7e are made of a crystal having a lattice constant smaller than that of the crystal constituting the semiconductor substrate 2, the epitaxial layer 7 and the extension region 7e give tensile strain to the semiconductor layer 3 serving as a channel region. Thus, the mobility of electrons in the semiconductor layer 3 can be improved.

  The Ge concentration of the SiGe crystal used for the epitaxial layer 7 and the extension region 7e is preferably 10 to 30 atomic%, and the C concentration of the SiC crystal is preferably 1 to 3 atomic%. When the Ge concentration of the SiGe crystal is less than 10 atomic%, the strain applied to the semiconductor layer 3 is insufficient, and when it exceeds 30 atomic%, a crystal defect is generated in an adjacent crystal or the like, causing a leakage current. There is a fear. Similarly, when the C concentration of the SiC crystal is less than 1 atomic%, the strain applied to the semiconductor layer 3 is insufficient, and when it exceeds 3 atomic%, a crystal defect is generated in an adjacent crystal or the like, causing leakage. May cause current.

The epitaxial layer 7 and the extension region 7e contain a conductive impurity and function as a source / drain region and a source / drain extension region. As the conductive impurities contained in the epitaxial layer 7 and the extension region 7e, p-type impurity ions such as B and BF ₂ are used for p-type transistors, and n-type impurity ions such as As and P are used for n-type transistors. It is done. A silicide layer may be formed on the upper surface of the epitaxial layer 7.

  In order to effectively apply stress from the epitaxial layer 7 to the semiconductor layer 3, the lower end of the extension region 7 e is preferably deeper than the lower end of the semiconductor layer 3.

  Further, the epitaxial layer 7 has a two-stage structure of the extension region 7e and the other deep region, that is, by including an epitaxial crystal in both the extension region of the source / drain region and the other deep region (deep region), Compared with the case where only the deep regions of the source / drain regions are formed by epitaxial crystals, stress can be applied more effectively by the semiconductor layer 3.

  Furthermore, when the epitaxial layer has a two-stage structure of an extension region and a deep region other than that, generally, the region under the gate electrode of the semiconductor substrate is adjusted from the epitaxial layer by adjusting the width, depth, etc. of the extension region. The magnitude of the stress applied to can be changed.

  2A and 2B show, as a reference example, the width and depth of the extension region 7e and the gate of the semiconductor substrate 2 from the epitaxial layer 7 in the semiconductor device 100 equal to the semiconductor device 1 that does not have the semiconductor layer 3. It is the figure and graph which show roughly the relationship of the magnitude | size of the stress added to the area | region under the electrode 5. FIG.

  As shown in FIG. 2A, the width of the extension region 7e in the channel direction is X, and the depth of the extension region 7e from the interface between the semiconductor substrate 2 and the gate insulating film 4 is Y.

  In the graph of FIG. 2B, the horizontal axis represents Y, and the vertical axis represents the magnitude of stress applied from the epitaxial layer 7 to the region under the gate electrode 5 of the semiconductor substrate 2. The magnitude of the stress on the vertical axis represents the magnitude of tensile stress in the case of an n-type transistor, and the magnitude of compressive stress in the case of a p-type transistor. In addition, two curves in the figure represent changes in the magnitude of stress when X is fixed at different predetermined values and Y is changed.

  As can be seen from FIG. 2B, each of the two curves has a maximum value, and as X increases, the value of Y that takes the maximum value increases. That is, as the width (X) of the extension region 7e is increased, the depth (Y) of the extension region 7e at which the magnitude of the stress applied from the epitaxial layer 7 to the region under the gate electrode 5 of the semiconductor substrate 2 is the largest is increased. .

Here, when the semiconductor layer 3 is formed as in the present embodiment, the depth from the interface between the semiconductor layer 3 and the gate insulating film 4 at the lower end of the semiconductor layer 3 is Y _0, and FIG. Shown in b). As described above, in order to effectively apply stress from the epitaxial layer 7 to the semiconductor layer 3, it is preferable that the lower end of the extension region 7 e is located deeper than the lower end of the semiconductor layer 3. it is preferred Y ₀ is larger configuration than.

That is, the epitaxial layer 7 has a two-stage structure of the extension region 7e and other deep regions, and the depth of the extension region 7e where the magnitude of the stress applied from the epitaxial layer 7 to the region under the gate electrode 5 of the semiconductor substrate 2 is the largest. It is preferable to form a structure in which the length (Y) is larger than the depth (Y ₀ ) from the interface between the semiconductor layer 3 and the gate insulating film 4 at the lower end of the semiconductor layer 3.

The element isolation region 10 is made of an insulating material such as SiO ₂ and has an STI (Shallow Trench Isolation) structure.

  A preferable combination of the semiconductor layer 3 and the epitaxial layer 7 including the extension region 7e is a crystal in which the semiconductor layer 3 has a larger lattice constant than a Si crystal such as a SiGe crystal, and has a larger internal carrier mobility than the Si crystal, The combination is such that the epitaxial layer 7 is a crystal having a lattice constant smaller than that of a Si crystal such as a SiC crystal.

  Details of the semiconductor device 1 that is an n-type transistor when the semiconductor layer 3 is a SiGe crystal and the epitaxial layer 7 is a SiC crystal, which is a particularly preferable example, will be described below.

  When the semiconductor layer 3 serving as the channel region is a SiGe crystal, the SiGe crystal has higher electron mobility inside than the Si crystal, and thus the driving speed of the transistor can be improved.

  However, since the SiGe crystal has a larger lattice constant than the Si crystal, compressive strain is generated by receiving stress from the semiconductor substrate 2 made of Si crystal. When compressive strain occurs, the mobility of electrons inside decreases, so that the nature of the mobility of electrons inside the SiGe crystal originally is weakened or may be canceled.

FIG. 3A is a schematic diagram schematically illustrating the relationship between the magnitude of strain generated in the semiconductor layer 3 and the mobility of electrons inside the semiconductor layer 3. When the epitaxial layer 7 is a SiC crystal, the SiC crystal has a lattice constant smaller than that of the SiGe crystal, so that tensile strain is generated in the semiconductor layer 3. As the tensile strain generated in the semiconductor layer 3 increases, the mobility of electrons inside increases, but the increase in mobility saturates at some point. Let δ _{max be} the magnitude of distortion when the electron mobility is saturated.

FIG. 3B is a schematic diagram schematically showing the relationship between the concentration of C contained in the epitaxial layer 7 and the magnitude of strain generated in the semiconductor layer 3. A straight line α in the figure represents the relationship when the semiconductor layer 3 is a SiGe crystal. A straight line β represents a relationship when a Si crystal is used instead of the semiconductor layer 3 as a comparative example. The limit of the C concentration of the epitaxial layer 7 that does not cause crystal defects in the semiconductor substrate 2 or the like is about 3 atomic%. Although the C concentrations c ₁ and c _{2 at} points δ _max on the straight lines α and β vary depending on the configuration of the semiconductor device 1, in the case where the gate length becomes shorter than a predetermined length or the like, FIG. As shown in b), c ₁ and c ₂ are 3 atomic% or less. FIG. 3B is a schematic diagram, and α and β may not be straight lines.

As can be seen from the straight line β in the figure, when the Si crystal is used instead of the semiconductor layer 3, the mobility of electrons in the Si crystal increases before the C concentration of the epitaxial layer 7 reaches 3 atomic%. A distortion δ _max having a saturation magnitude is generated. On the other hand, as described above, when the semiconductor layer 3 is a SiGe crystal, a compressive strain in which the mobility of electrons is reduced is generated inside the semiconductor layer 3 in a state where no stress is received from the epitaxial layer 7. However, as can be seen from the straight line α in the figure, the increase in the electron mobility in the semiconductor layer 3 is saturated by increasing the C concentration of the epitaxial layer 7 and applying a tensile stress from the epitaxial layer 7 to the semiconductor layer 3. It is possible to generate a distortion δ _max having a magnitude of

That is, in both cases where the semiconductor layer 3 is a SiGe crystal and a Si crystal is used instead of the semiconductor layer 3, the magnitude of strain δ _{max at} which the increase in the mobility of electrons inside is saturated is substantially equal. Even if compressive stress is generated in the semiconductor layer 3 made of SiGe crystal, the effect of increasing electron mobility due to strain can be obtained to the same extent.

  Moreover, as described above, the SiGe crystal originally has a higher electron mobility than the Si crystal (in a state where no distortion is generated). For this reason, when combined with the effect of increasing electron mobility due to strain, the semiconductor mobility is higher when the semiconductor layer 3 is a SiGe crystal than when a Si crystal is used instead of the semiconductor layer 3. Can be larger.

  Below, an example of the manufacturing method of the semiconductor device 1 which concerns on this Embodiment is shown.

(Manufacture of semiconductor devices)
4A (a) to 4 (c), 4B (d) to (f), and 4C (g) to (h) are cross-sectional views showing the manufacturing steps of the semiconductor device according to the first embodiment of the present invention. FIG.

  First, as shown in FIG. 4A (a), the element isolation region 10 is formed in the semiconductor substrate 2, and the semiconductor film 11, the gate insulating film 4, the gate electrode 5, and the cap film 12 are formed on the semiconductor substrate 2.

Here, the semiconductor film 11 is formed by an epitaxial growth method or the like. Moreover, although the conductivity type impurity is implanted into the semiconductor film 11, it may be implanted in situ at the time of epitaxial growth, or may be implanted by an ion implantation method or the like after the epitaxial growth. Here, the conductive impurities implanted into the semiconductor film 11 use p-type impurity ions such as B and BF ₂ when forming a p-type transistor, and As and P when forming an n-type transistor. N-type impurity ions are used. Thereafter, heat treatment such as RTA (Rapid Thermal Annealing) is performed to activate the implanted conductive impurities.

  The gate insulating film 4, the gate electrode 5, and the cap film 12 are formed by laminating the respective material films on the semiconductor film 11 by the CVD method or the like, and then, for example, photolithography and RIE (Reactive Ion). Etching) is performed by patterning.

  Before forming the semiconductor film 11, the gate insulating film 4, the gate electrode 5, and the cap film 12, an impurity having a conductivity type different from that implanted into the semiconductor film 11 is implanted into the semiconductor substrate 2 by an ion implantation method. Wells (not shown) may be formed. Thereafter, heat treatment such as RTA is performed to activate the implanted conductivity type impurities.

  Next, as shown in FIG. 4A (b), offset spacers 6 are formed on the side surfaces of the gate insulating film 4, the gate electrode 5, and the cap film 12.

  Here, the offset spacer 6 is formed by covering the surface of the semiconductor substrate 2, the gate insulating film 4, the gate electrode 5 and the cap film 12 with the material film of the offset spacer 6 by the CVD method or the like, and then forming the material film by the RIE method or the like. It is formed by etching.

  Next, as shown in FIG. 4A (c), using the offset spacer 6 and the cap film 12 as a mask, the semiconductor film 11 is etched by the RIE method or the like to be processed into the semiconductor layer 3.

  Next, as shown in FIG. 4B (d), the upper surface of the semiconductor substrate 2 is etched by the RIE method or the like using the offset spacer 6 and the cap film 12 as a mask to form a groove 13. Note that the processing of the semiconductor layer 3 shown in FIG. 4A (c) and the formation of the groove 13 shown in FIG. 4B (d) can be performed continuously by the RIE method or the like.

  Next, as shown in FIG. 4B (e), dummy sidewalls 14 are formed on portions corresponding to the side surfaces of the offset spacer 6 and the semiconductor layer 3 and the inner surface of the groove 13 of the semiconductor substrate 2.

  Here, the dummy sidewall 14 is formed by covering the surfaces of the semiconductor substrate 2, the offset spacer 6 and the cap film 12 with the material film of the dummy sidewall 14 by the CVD method or the like, and then etching it by the RIE method or the like. To form.

  Next, as shown in FIG. 4B (f), the upper surface of the semiconductor substrate 2 is etched by the RIE method or the like using the dummy side wall 14 and the cap film 12 as a mask to make a part of the groove 13 deeper.

  Next, as shown in FIG. 4C (g), after removing the dummy side wall 14, the epitaxial layer 7 which is a crystal containing a conductive impurity is epitaxially grown on the surface exposed by the groove 13 of the semiconductor substrate 2 as a base. Here, the epitaxial layer 7 is grown to a height in contact with the side surface of the semiconductor layer 3.

Here, when forming a p-type transistor, for example, monosilane (SiH ₄ ) or dichlorosilane (SiH ₂ Cl ₂ ) as a Si source, germanium hydride (GeH ₄ ) as a Ge source, and diborane (B) as a B source. Using B ₂ H ₆ ), a SiGe crystal containing B is vapor-phase epitaxially grown at 700 to 850 ° C. in an atmosphere of hydrogen gas or the like to form a p-type epitaxial layer 7.

On the other hand, when forming an n-type transistor, for example, monosilane (SiH ₄ ) or dichlorosilane (SiH ₂ Cl ₂ ) as a Si source, acetylene (C ₂ H ₂ ) as a C source, and arsine (AsH) as an As source. ₃ ), an SiC crystal containing As is vapor-phase epitaxially grown under a temperature condition of 700 to 850 ° C. in an atmosphere of hydrogen gas or the like to form an n-type epitaxial layer 7.

  In addition, after epitaxially growing the epitaxial layer 7 containing no conductive impurities, the conductive impurities may be implanted by an ion implantation method or the like.

  Next, as shown in FIG. 4C (h), the cap layer 12 is removed, and the gate sidewall 8 is formed on the side surface of the offset spacer 6.

  Here, the cap layer 12 is removed by wet etching or the like using phosphoric acid. At this time, the offset spacer 6 may be removed at the same time. In this case, the gate sidewall 8 is formed on the side surface of the gate electrode 5.

  Further, the gate sidewall 8 is formed by depositing the material film of the gate sidewall 8 so as to cover the surfaces of the epitaxial layer 7, the offset spacer 6 and the cap layer 12, and then etching this by the RIE method or the like.

(Effects of the first embodiment)
According to the first embodiment of the present invention, the semiconductor layer 3 having higher carrier mobility inside than the Si crystal, and the epitaxial layer 7 that imparts strain to the semiconductor layer 3 in the direction in which the internal carrier mobility increases are provided. By using in combination, it is possible to cancel the effect of reducing the internal carrier mobility due to the strain that the semiconductor layer 3 receives from the semiconductor substrate 2 and to obtain a large carrier mobility. Thereby, the drive speed of the semiconductor device 1 can be improved.

[Second Embodiment]
The second embodiment of the present invention is different in that a second semiconductor layer is formed between the first semiconductor layer 15 corresponding to the semiconductor layer 3 in the first embodiment and the gate insulating film 4. Different from the first embodiment. In addition, about the point similar to 1st Embodiment, such as a structure of another member and a manufacturing process, description is abbreviate | omitted for simplicity.

(Configuration of semiconductor device)
FIG. 5 is a sectional view of a semiconductor device according to the second embodiment of the present invention.

  The first semiconductor layer 15 is made of the same material as that of the semiconductor layer 3 in the first embodiment, and functions as a channel region like the semiconductor layer 3.

  The second semiconductor layer 16 is made of a material having lower internal carrier mobility than the semiconductor layer 3 such as Si crystal. The second semiconductor layer 16 is formed between the first semiconductor layer 15 and the gate insulating film 4.

  Note that the thickness of the second semiconductor layer 16 is preferably 2 nm or less. This is because if the thickness of the second semiconductor layer 16 exceeds 2 nm, the ratio of the channel region formed in the second semiconductor layer 16 becomes too large.

  The total thickness of the first semiconductor layer 15 and the second semiconductor layer 16 is preferably equal to or less than the thickness of the inversion layer generated during the operation of the semiconductor device 1. When the sum of the thickness of the first semiconductor layer 15 and the thickness of the second semiconductor layer 16 is thicker than the thickness of the inversion layer, carriers do not move in a region below the inversion layer of the first semiconductor layer 15. Therefore, the operation speed of the semiconductor device 1 is hardly changed. In addition, when the first semiconductor layer 15 is a crystal that is distorted in a direction in which the mobility of carriers in the interior decreases due to the stress received from the semiconductor substrate 2, the distortion increases as the thickness of the first semiconductor layer 15 increases. It becomes larger and the mobility of the carrier decreases. Note that the thickness of the inversion layer is, for example, 2 to 3 nm.

  Below, an example of the manufacturing method of the semiconductor device 1 which concerns on this Embodiment is shown.

(Manufacture of semiconductor devices)
6A (a) to (c), FIGS. 6B (d) to (f), and FIGS. 6C (g) to (h) are cross sections showing manufacturing steps of the semiconductor device according to the second embodiment of the present invention. FIG.

  First, as shown in FIG. 6A (a), an element isolation region 10 is formed in a semiconductor substrate 2, and a first semiconductor film 17, a second semiconductor film 18, a gate insulating film 4, a gate are formed on the semiconductor substrate 2. Electrode 5 and cap film 12 are formed.

Here, the first semiconductor film 17 and the second semiconductor film 18 are formed by an epitaxial growth method or the like. The first semiconductor film 17 and the second semiconductor film 18 are implanted with conductive impurities, but may be implanted in situ during epitaxial growth, or may be implanted after the epitaxial growth by an ion implantation method or the like. Here, when forming a p-type transistor, the p-type impurity ions such as B and BF ₂ are used as the conductive impurities implanted into the first semiconductor film 17 and the second semiconductor film 18, and the n-type transistor is used. Is used, n-type impurity ions such as As and P are used. Thereafter, heat treatment such as RTA is performed to activate the implanted conductivity type impurities.

  The gate insulating film 4, the gate electrode 5, and the cap film 12 are formed by laminating respective material films on the semiconductor film 11 by a CVD method or the like, and then patterning these material films by, for example, a photolithography method and an RIE method. It is formed by doing.

  Note that before forming the first semiconductor film 17, the second semiconductor film 18, the gate insulating film 4, the gate electrode 5, and the cap film 12, impurities having a conductivity type different from that implanted into the semiconductor film 11 are introduced. A well (not shown) may be formed by implanting into the semiconductor substrate 2 by ion implantation. Thereafter, heat treatment such as RTA is performed to activate the implanted conductivity type impurities.

  Next, as shown in FIG. 6A (b), offset spacers 6 are formed on the side surfaces of the gate insulating film 4, the gate electrode 5, and the cap film 12.

  Here, the offset spacer 6 is formed by covering the surface of the semiconductor substrate 2, the gate insulating film 4, the gate electrode 5 and the cap film 12 with the material film of the offset spacer 6 by the CVD method or the like, and then forming the material film by the RIE method or the like. It is formed by etching.

  Next, as shown in FIG. 6A (c), the first semiconductor film 17 and the second semiconductor film 18 are etched by the RIE method or the like using the offset spacer 6 and the cap film 12 as a mask. The semiconductor layer 15 and the second semiconductor layer 16 are processed.

  Next, as shown in FIG. 6B (d), the upper surface of the semiconductor substrate 2 is etched by the RIE method or the like using the offset spacer 6 and the cap film 12 as a mask to form the grooves 13. Note that the processing of the first semiconductor layer 15 and the second semiconductor layer 16 shown in FIG. 6A (c) and the formation of the groove 13 shown in FIG. 6B (d) are performed continuously by the RIE method or the like. Can do.

  Next, as shown in FIG. 6B (e), the dummy is formed on portions corresponding to the side surfaces of the offset spacer 6, the first semiconductor layer 15 and the second semiconductor layer 16, and the inner side surface of the groove 13 of the semiconductor substrate 2. Sidewall 14 is formed.

  Here, the dummy sidewall 14 covers the surface of the semiconductor substrate 2, the first semiconductor layer 15, the second semiconductor layer 16, the offset spacer 6, and the cap film 12 by a CVD method or the like. After the formation, this is formed by etching using the RIE method or the like.

  Next, as shown in FIG. 6B (f), the upper surface of the semiconductor substrate 2 is etched by the RIE method or the like using the dummy side wall 14 and the cap film 12 as a mask to make a part of the groove 13 deeper.

  Next, as shown in FIG. 6C (g), after removing the dummy side wall 14, the epitaxial layer 7 which is a crystal containing conductive impurities is epitaxially grown on the surface exposed by the groove 13 of the semiconductor substrate 2 as a base. Here, the epitaxial layer 7 is grown to a height in contact with the side surfaces of the first semiconductor layer 15 and the second semiconductor layer 16.

  Next, as shown in FIG. 6C (h), the cap layer 12 is removed, and the gate sidewall 8 is formed on the side surface of the offset spacer 6.

  Here, the cap layer 12 is removed by wet etching or the like using phosphoric acid. At this time, the offset spacer 6 may be removed at the same time. In this case, the gate sidewall 8 is formed on the side surface of the gate electrode 5.

  Further, the gate sidewall 8 is formed by depositing the material film of the gate sidewall 8 so as to cover the surfaces of the epitaxial layer 7, the offset spacer 6 and the cap layer 12, and then etching this by the RIE method or the like.

(Effect of the second embodiment)
According to the second embodiment of the present invention, the second semiconductor layer 16 having lower internal carrier mobility than the first semiconductor layer 15 between the first semiconductor layer 15 and the gate insulating film 4. As a result, the second semiconductor layer 16 not in contact with the gate insulating film 4 serves as a channel region. For this reason, the scattering of carriers in the channel region due to the surface roughness at the interface between the channel region and the gate insulating film 4 can be suppressed, and the decrease in mobility can be suppressed.

[Other Embodiments]
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention.

  In addition, the constituent elements of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. (A), (b) is the figure and graph which show roughly the relationship of the magnitude | size of the stress added to the area | region under the gate electrode of a semiconductor substrate from the width of an extension area | region, and an epitaxial layer as a reference example. . (A) is the schematic diagram showing the relationship between the magnitude | size of the distortion which generate | occur | produces in a semiconductor layer, and the mobility of the electron inside a semiconductor layer, (b) is C of C contained in an epitaxial layer. It is the schematic diagram which represented roughly the relationship between the density | concentration and the magnitude | size of the distortion generate | occur | produced in a semiconductor layer. (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (D)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (G), (h) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. (A)-(c) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. (D)-(f) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. (G), (h) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor substrate 3 Semiconductor layer 4 Gate insulating film 5 Gate electrode 7 Epitaxial layer 15 1st semiconductor layer 16 2nd semiconductor layer

Claims (5)

A semiconductor substrate;
A semiconductor layer formed on the semiconductor substrate and made of a first crystal in which the mobility of carriers inside is larger than that of the Si crystal;
A gate insulating film formed on the semiconductor layer;
A gate electrode formed on the gate insulating film;
A source that is formed with the semiconductor layer in between and includes a second crystal that distorts the semiconductor layer in a direction in which the mobility of carriers in the semiconductor layer increases, and is a shallow region in contact with the semiconductor layer A source / drain region having a drain extension region;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein when the first crystal is formed over a Si crystal, the first crystal is a crystal that is distorted in a direction in which the mobility of carriers inside the first crystal decreases.   The semiconductor device according to claim 2, wherein the first crystal is a SiGe crystal, and the second crystal is a SiC crystal.   4. The semiconductor device according to claim 1, wherein a lower end of the source / drain extension region is deeper than a lower end of the semiconductor layer. 5.   5. The semiconductor layer according to claim 1, wherein another semiconductor layer made of a crystal having carrier mobility therein smaller than that of the first crystal is formed between the semiconductor layer and the gate insulating film. A semiconductor device according to claim 1.

Images