JP2009176876A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including, in an area under a channel region, a crystal layer for generating distortion to improve charge mobility in a channel region and controlling formation of a leak current route. <P>SOLUTION: The semiconductor device includes a semiconductor substrate 1, a first semiconductor crystal layer 14 formed on the semiconductor substrate, a gate electrode 13 formed on the first semiconductor crystal layer via a gate insulating film 11, a channel region 15 formed in the region under the gate insulating film within the first semiconductor crystal layer, a source/drain region 16 formed in the regions holding the channel region within the first semiconductor crystal layer, a second semiconductor crystal layer formed between the semiconductor substrate and the channel region and is formed of a crystal material having the lattice constant larger than that of the crystal constituting the first semiconductor crystal layer, and an embedded insulating layer 18 formed holding the second semiconductor crystal layer 17 between the semiconductor substrate and the first semiconductor layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device.

  As a conventional semiconductor device, by forming a layer of SiGe crystal having a lattice constant larger than that of the Si crystal under the channel region in the Si crystal layer, the channel region is distorted to improve the charge mobility. A transistor is known (see, for example, Non-Patent Document 1).

However, according to the semiconductor device described in Non-Patent Document 1 and the like, the diffusion rate of n-type impurities such as As and P in the SiGe crystal is larger than the diffusion rate in the Si crystal. Since it is in contact with the source / drain regions, the n-type impurities in the source / drain regions may diffuse into the SiGe crystal layer and a leakage current path may be formed.
Kah-Wee Ang et el., IEEE ELECTRON DEVICE LETTERS, VOL.28, NO.7, JULY 2007, pp.609-612.

  An object of the present invention is to provide a semiconductor device that has a crystal layer under a channel region that generates a strain that improves charge mobility in the channel region, and can suppress the formation of a leakage current path.

  One embodiment of the present invention includes a semiconductor substrate, a first semiconductor crystal layer formed over the semiconductor substrate, a gate electrode formed over the first semiconductor crystal layer with a gate insulating film interposed therebetween, A channel region formed in a region under the gate insulating film in the first semiconductor crystal layer; a source / drain region formed in a region sandwiching the channel region in the first semiconductor crystal layer; Diffusion of conductive impurities formed between the semiconductor substrate and the channel region and made of a crystal having a lattice constant larger than that of the crystal constituting the first semiconductor crystal layer, and contained in the source / drain regions inside the crystal A second semiconductor crystal layer having a speed higher than that of the first semiconductor crystal layer; and a buried insulation formed between the semiconductor substrate and the first semiconductor layer with the second semiconductor crystal layer interposed therebetween. Body layer , To provide a semiconductor device and having a.

  Another aspect of the present invention includes a semiconductor substrate having an n-type transistor region and a p-type transistor region, a first semiconductor crystal layer formed in the n-type transistor region and the p-type transistor region on the semiconductor substrate, First and second gate electrodes formed on the first semiconductor crystal layer of the n-type transistor region and the p-type transistor region via first and second gate insulating films, respectively, First and second channel regions formed in regions under the first and second gate insulating films in one semiconductor crystal layer, respectively, and the first and second channel regions in the first semiconductor crystal layer. First and second source / drain regions formed in a region sandwiching the channel region, and between the semiconductor substrate and the first and second channel regions, respectively. Formed of a crystal having a lattice constant larger than that of the crystal constituting the first semiconductor crystal layer, and the diffusion rate of the conductive impurities contained in the first source / drain region inside the first semiconductor crystal layer is the first semiconductor The second semiconductor crystal layer is sandwiched between the semiconductor substrate and the first semiconductor layer in the second semiconductor crystal layer larger than the crystal layer, and in the n-type transistor region and the p-type transistor region. And a buried insulator layer formed respectively.

  According to the present invention, it is possible to provide a semiconductor device that has a crystal layer under the channel region that generates a strain that improves charge mobility in the channel region and can suppress the formation of a leakage current path.

[First Embodiment]
(Configuration of semiconductor device)
FIG. 1 is a cross-sectional view of a semiconductor device according to the first embodiment of the present invention. The semiconductor device includes an n-type transistor 10 formed on a semiconductor substrate 1 and electrically isolated from other elements by an element isolation region 2.

  As the semiconductor substrate 1, for example, a Si substrate having a {100} plane as a main surface can be used. The {100} plane represents the (100) plane and a plane equivalent to the (100) plane.

The element isolation region 2 is made of an insulating material such as SiO ₂ and has an STI (Shallow Trench Isolation) structure.

  The n-type transistor 10 includes a first semiconductor crystal layer 14 formed on the semiconductor substrate 1, a gate electrode 12 formed on the first semiconductor crystal layer 14 via a gate insulating film 11, and a gate electrode 12. Sandwiching the gate side wall 13 formed on the side surface, the channel region 15 formed in the region under the gate insulating film 11 in the first semiconductor crystal layer 14, and the channel region 15 in the first semiconductor crystal layer 14 A source / drain region 16 formed in the region, a second semiconductor crystal layer 17 formed between the semiconductor substrate 1 and the channel region 15, and between the semiconductor substrate 1 and the first semiconductor layer 14, And a buried insulator layer 18 formed with the second semiconductor crystal layer 17 interposed therebetween.

The gate insulating film 11 is made of, for example, SiO ₂ , SiON, or a high dielectric material (for example, Hf-based materials such as HfSiON, HfSiO, and HfO, Zr-based materials such as ZrSiON, ZrSiO, and ZrO, and Y-based materials such as Y ₂ O _3. ).

  The gate electrode 12 is made of Si-based polycrystal such as polycrystal Si or polycrystal SiGe containing conductive impurities. An n-type impurity such as As or P is used for the gate electrode 12. When the gate electrode 12 is made of Si-based polycrystal, a silicide layer may be formed on the top. Further, the gate electrode 12 may be a metal gate electrode made of W, Ta, Ti, Hf, Zr, Ru, Pt, Ir, Mo, Al or the like, or a compound thereof. Moreover, the structure which laminated | stacked the metal gate electrode and the Si type polycrystalline electrode may be sufficient.

The gate sidewall 13 may have a single layer structure made of, for example, SiN, a _two layer structure made of, for example, SiN and SiO ₂ , or a structure having three or more layers.

  The first semiconductor crystal layer 14 is made of Si-based crystal such as Si crystal, and is formed by, for example, an epitaxial crystal growth method using the surface of the second semiconductor crystal layer 17 as a seed. In this case, the crystal orientation of the second semiconductor crystal layer 17 is reflected.

  For example, when the surface orientation of the upper surface of the first semiconductor crystal layer 14 is {100}, the channel region 15 is formed so that the channel direction is <110> or <100>. In such a case, the mobility of electrons in the channel region 15 is improved when stretching distortion occurs in the channel direction and the channel width direction orthogonal thereto. The <110> axial direction represents the [110] axial direction and the axial direction equivalent to the [110] axial direction, and the <100> axial direction is equivalent to the [100] axial direction and the [100] axial direction. Represents the axial direction.

  The source / drain regions 16 are formed by injecting n-type impurities such as As and P into the first semiconductor crystal layer 14. A silicide layer made of a compound containing Si and a metal such as Ni, Pt, Co, Er, NiPt, or CoNi may be formed on the upper surface of the source / drain region 16.

  The second semiconductor crystal layer 17 is made of a crystal having a lattice constant larger than that of the crystal constituting the first semiconductor crystal layer 14, and the conductivity type contained in the source / drain region 16 inside the second semiconductor crystal layer 17. The diffusion rate of impurities is larger than the diffusion rate inside the first semiconductor crystal layer 14. The second semiconductor crystal layer 17 is formed by, for example, an epitaxial crystal growth method using the surface of the semiconductor substrate 1 as a seed. In this case, the crystal orientation of the semiconductor substrate 1 is reflected.

  Since the second semiconductor crystal layer 17 is made of a crystal having a lattice constant larger than that of the crystal constituting the first semiconductor crystal layer 14, the second semiconductor crystal layer 17 is formed on the first semiconductor crystal layer 14 grown on the second semiconductor crystal layer 17. Causes an in-plane extensional strain. In particular, a large distortion occurs in a region including the channel region 15 and in the vicinity of the interface with the second semiconductor crystal layer 17. For this reason, expansion strain in the channel direction and the channel width direction occurs in the channel region 15. For example, the surface orientation of the upper surface of the first semiconductor crystal layer 14 is {100}, and the channel direction of the channel region 15 When <110> or <100>, the operational performance of the n-type transistor 10 is improved.

  For example, a SiGe crystal can be used as the second semiconductor crystal layer 17. When using a SiGe crystal, the Ge concentration is preferably 10 to 30 atomic%, for example. This is because the strain applied to the channel region 15 becomes insufficient if it is less than 10 atomic%, and the crystal defects tend to increase if it exceeds 30 atomic%.

The buried insulator layer 18 is made of SiO ₂ , a material having a relative dielectric constant substantially equal to or smaller than SiO ₂ (TEOS (Tetraethoxysilane) or the like), or a material having a Young's modulus substantially equal to or smaller than SiO ₂ (TEOS or the like). Become. SiO ₂ has a relatively low dielectric constant among the insulating materials (relative dielectric constant of about 3.9), and can suppress the junction capacitance low. Furthermore, a material having a dielectric constant lower than that of SiO ₂ (relative dielectric constant less than about 3.9) is more preferable. In addition, SiO ₂ has a relatively soft property among the insulating materials (Young's modulus is about 66 GPa), and it is difficult to prevent distortion generated in the first semiconductor crystal layer 14, so that the channel region 15 can be efficiently formed as a result. Distortion can be generated. Furthermore, it is more preferable if the material is softer than SiO ₂ (Young's modulus is less than 66 GPa).

(Manufacture of semiconductor devices)
2A (a) to 2 (d) and FIGS. 2B (e) to (h) are cross-sectional views illustrating the manufacturing steps of the semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 2A (a), a second semiconductor crystal layer 17 and a semiconductor crystal film 3a are stacked on a semiconductor substrate 1, and an element isolation region 2 is formed to form an element region. In the region, a gate insulating film 11, a gate electrode 12, and a gate sidewall 13 are formed on the semiconductor crystal film 3a.

  Here, the second semiconductor crystal layer 17 is formed by an epitaxial crystal growth method or the like using the surface of the semiconductor substrate 1 as a seed, and the semiconductor crystal film 3a is epitaxial using the surface of the second semiconductor crystal layer 17 as a seed. It is formed by a crystal growth method or the like.

When a SiGe crystal is used as the second semiconductor crystal layer 17, it is 700 to 700 in an atmosphere of, for example, monosilane (SiH ₄ ), germanium hydride (GeH ₄ ), hydrogen gas (H ₂ ) in a chemical vapor deposition chamber. Crystal growth is performed under a temperature condition of 750 ° C. When Si crystal is used as the semiconductor crystal film 3a, crystal growth is performed in a chemical vapor deposition chamber, for example, in an atmosphere of monosilane (SiH ₄ ), hydrogen gas (H ₂ ), etc. at a temperature of 700 to 750 ° C. Let

  Next, as shown in FIG. 2A (b), using the gate electrode 12 and the gate sidewall 13 as a mask, the semiconductor crystal film 3a, the second semiconductor crystal layer 17, and the semiconductor substrate 1 are etched to form the trench 4 Form.

Next, as shown in FIG. 2A (c), an insulating film 5 made of SiO ₂ or the like is formed on the entire surface of the semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method or the like so as to fill the trench 4.

  Next, as shown in FIG. 2A (d), the insulating film 5 is etched back until the upper surface reaches a predetermined height by RIE (Reactive Ion Etching) method or the like, and processed into the buried insulator layer 18. Here, the predetermined height is preferably substantially the same as the height of the interface between the second semiconductor crystal layer 17 and the semiconductor crystal film 3a.

  Next, as shown in FIG. 2B (e), a semiconductor crystal film 3b is formed on the entire surface of the semiconductor substrate 1 by a CVD method or the like. Here, the semiconductor crystal film 3b is preferably made of the same material as the semiconductor crystal film 3a.

  Next, as shown in FIG. 2B (f), the semiconductor crystal film 3b is etched back by an RIE method or the like until the upper surface reaches a predetermined height. Here, the predetermined height is preferably higher than the height of the interface between the semiconductor crystal film 3a and the gate insulating film 11 in order to form an elevated source / drain structure.

  Next, as shown in FIG. 2B (g), the portion located on the element isolation region 2 of the semiconductor crystal film 3b is selectively removed by, for example, lithography and RIE. Thereby, the first semiconductor crystal layer 14 composed of the semiconductor crystal films 3a and 3b is formed.

  Next, as shown in FIG. 2B (h), a conductive impurity is implanted into the exposed portion of the first semiconductor crystal layer 14 by ion implantation or the like to form source / drain regions 16. Here, n-type impurity ions such as As and P are used as the conductive impurities.

  Through the above steps, the n-type transistor 10 shown in FIG. 1 is formed.

(Effects of the first embodiment)
According to the first embodiment of the present invention, the formation of the buried insulator layer 18 can reduce the region where the source / drain region 16 and the second semiconductor crystal layer 17 are in contact with each other. It is possible to suppress the formation of a leakage current path due to the diffusion of the conductive impurities in the source / drain region 16 into the second semiconductor crystal layer 17 while generating a distortion that improves the charge mobility.

  Further, since the buried insulator layer 18 made of a material having a relatively low dielectric constant is located below the source / drain region 16, the junction capacitance can be lowered and the driving speed of the n-type transistor 10 can be improved.

[Second Embodiment]
The second embodiment differs from the first embodiment in that a p-type transistor is included in the semiconductor device in addition to the n-type transistor. Note that description of the same parts as those in the first embodiment is omitted or simplified.

(Configuration of semiconductor device)
FIG. 3 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. The semiconductor device has an n-type transistor 10 and a p-type transistor 20 that are electrically isolated by an element isolation region 2 on a semiconductor substrate 1. The configuration of the n-type transistor 10 according to the present embodiment is the same as the configuration of the n-type transistor 10 according to the first embodiment.

  The p-type transistor 20 includes a first semiconductor crystal layer 24 formed on the semiconductor substrate 1, a gate electrode 22 formed on the first semiconductor crystal layer 24 via a gate insulating film 21, and a gate electrode 22. Sandwiching the gate side wall 23 formed on the side surface of the first semiconductor crystal layer 24, the channel region 25 formed in the region under the gate insulating film 11 in the first semiconductor crystal layer 24, and the channel region 25 in the first semiconductor crystal layer 24. A source / drain region 26 formed in the region, a second semiconductor crystal layer 27 formed between the semiconductor substrate 1 and the channel region 25, and between the semiconductor substrate 1 and the first semiconductor layer 24, And a buried insulator layer 28 formed with the second semiconductor crystal layer 27 interposed therebetween.

  The gate insulating film 21, the gate sidewall 23, the first semiconductor crystal layer 24, and the buried insulator layer 28 are respectively the gate insulating film 11, the gate sidewall 13, the first semiconductor crystal layer 14, and the buried insulator layer. The same material as 18 can be formed in the same process.

The gate electrode 22 is made of Si-based polycrystal such as polycrystal Si or polycrystal SiGe containing a conductive impurity. A p-type impurity such as B or BF ₂ is used for the gate electrode 22. Further, when the gate electrode 22 is made of Si-based polycrystal, a silicide layer may be formed on the top. The gate electrode 22 may be a metal gate electrode made of W, Ta, Ti, Hf, Zr, Ru, Pt, Ir, Mo, Al, etc., or a compound thereof. Moreover, the structure which laminated | stacked the metal gate electrode and the Si type polycrystalline electrode may be sufficient.

The source / drain region 26 is formed by injecting a p-type impurity such as B or BF ₂ into the first semiconductor crystal layer 24. A silicide layer made of a compound containing Si and a metal such as Ni, Pt, Co, Er, NiPt, or CoNi may be formed on the upper surface of the source / drain region 26.

  For example, the channel regions 15 and 25 are formed so that the channel direction is <110> when the plane orientation of the upper surfaces of the first semiconductor crystal layers 14 and 24 is {100}. In such a case, when stretching strain occurs in the channel direction and the channel width direction of the n-type channel region 15, the mobility of electrons in the channel region 15 is improved. Further, when compressive strain occurs in the channel direction of the p-type channel region 25 and expansion strain occurs in the channel width direction, the mobility of holes in the channel region 25 is improved.

  Since the second semiconductor crystal layers 17 and 27 are made of crystals having a lattice constant larger than that of the crystals constituting the first semiconductor crystal layers 14 and 24, the first semiconductor crystal layers 17 and 27 grown on the second semiconductor crystal layers 17 and 27 are formed. In the semiconductor crystal layers 14 and 24, an in-plane extensional strain is generated. In particular, a large strain is generated in a region near the interface with the second semiconductor crystal layers 17 and 27 including the channel regions 15 and 25. For this reason, extension strains in the channel direction and the channel width direction are generated in the channel regions 15 and 25. For example, the plane orientation of the upper surfaces of the first semiconductor crystal layers 14 and 24 is {100}, and the channel regions When the channel directions of 15 and 25 are <110>, the operation performance of the n-type transistor 10 is improved. Further, in the p-type transistor 20, although the extension strain in the channel direction tends to decrease the hole mobility, the extension strain in the channel width direction improves the hole mobility. Performance is improved.

(Effect of the second embodiment)
According to the second embodiment of the present invention, in addition to the same effect as that of the first embodiment with respect to the n-type transistor 10, the channel region 25 is distorted so that the operation speed of the p-type transistor 20 is increased. Can be improved.

  In addition, since the structures of the n-type transistor 10 and the p-type transistor 20 are the same except for the conductivity type of the impurities contained, formation processes other than impurity implantation can be performed simultaneously.

[Other Embodiments]
The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the invention.

  In addition, the constituent elements of the above embodiments can be arbitrarily combined without departing from the spirit of the invention.

1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. (A)-(d) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. (E)-(h) is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 10 N-type transistor 20 P-type transistor 11, 21 Gate insulating film 12, 22 Gate electrode 14, 24 First semiconductor crystal layer 15, 25 Channel region 16, 26 Source / drain region 17, 27 Second semiconductor Crystal layer 18, 28 Buried insulator layer

Claims (5)

A semiconductor substrate;
A first semiconductor crystal layer formed on the semiconductor substrate;
A gate electrode formed on the first semiconductor crystal layer via a gate insulating film;
A channel region formed in a region under the gate insulating film in the first semiconductor crystal layer;
A source / drain region formed in a region sandwiching the channel region in the first semiconductor crystal layer;
A crystal formed between the semiconductor substrate and the channel region and having a lattice constant larger than that of the crystal constituting the first semiconductor crystal layer, and conductive impurities contained in the source / drain regions inside the crystal. A second semiconductor crystal layer having a diffusion rate greater than that of the first semiconductor crystal layer;
A buried insulator layer formed by sandwiching the second semiconductor crystal layer between the semiconductor substrate and the first semiconductor layer;
A semiconductor device comprising: a semiconductor substrate having an n-type transistor region and a p-type transistor region;
A first semiconductor crystal layer formed in the n-type transistor region and the p-type transistor region on the semiconductor substrate;
First and second gate electrodes formed on the first semiconductor crystal layer of the n-type transistor region and the p-type transistor region via first and second gate insulating films, respectively;
First and second channel regions respectively formed in regions under the first and second gate insulating films in the first semiconductor crystal layer;
First and second source / drain regions respectively formed in regions of the first semiconductor crystal layer sandwiching the first and second channel regions;
The first source is formed between the semiconductor substrate and the first and second channel regions, and is made of a crystal having a lattice constant larger than that of the crystal constituting the first semiconductor crystal layer. A second semiconductor crystal layer having a diffusion rate of conductive impurities contained in the drain region larger than that of the first semiconductor crystal layer;
A buried insulator layer formed between the semiconductor substrate and the first semiconductor layer with the second semiconductor crystal layer interposed between the n-type transistor region and the p-type transistor region;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the first semiconductor crystal layer is made of Si crystal, and the second semiconductor crystal layer is made of SiGe. 4. The semiconductor device according to claim 1, wherein the embedded insulator layer is made of SiO ₂ or a material having at least one of relative permittivity and Young's modulus smaller than that of SiO ₂ .   The semiconductor device according to claim 1, wherein the conductive impurity includes at least one of As and P.

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