JP2010010403A - Semiconductor device and its method for manufacturing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively apply a stretch stress to a silicon channel region of an N channel insulating gate type field-effect transistor, and further to enhance the mobility of a parasitic transistor. <P>SOLUTION: This semiconductor device includes: a silicon substrate 11; an element forming part 12 divided in the silicon substrate 11; an N channel insulating gate type field-effect transistor 20 formed in the element forming part 12; a trench part 13 formed in the silicon substrate 11 for enclosing the side part of the element forming part 12; an element isolation part 14 formed by embedding an insulating material inside the trench part 13; and a silicon germanium epitaxial growing layer 15 formed at least on the side of the trench part 13 in parallel to a direction of a channel length L in the N channel insulating gate type field-effect transistor 20. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

In the generation of semiconductor devices after the 45 nm node process, it has become impossible to expect performance improvement by a conventional simple scaling rule.
Therefore, as a technique for improving the mobility, a technique for increasing the mobility by applying stress to the channel portion is often used in recent years.

In an NMOS transistor, it is well known that the mobility is increased by applying a tensile stress in the channel length direction connecting the source and the drain.
As an example, as shown in FIG. 19, by covering the NMOSFET 112 with a stress liner film 111 that increases tensile stress and by covering the PMOSFET 114 with a stress liner film 113 that increases compressive stress, The mobility of each transistor is improved (for example, refer nonpatent literature 1).

  However, the stress liner film is often used in combination with various techniques, and at present, the stress by the stress liner film alone is not sufficient as a boost technique for increasing the mobility.

In order to further apply stress, as shown in FIG. 20, an epitaxial layer made of silicon carbide (SiC) having a lattice number smaller than that of silicon (Si) is used for diffusion layers 212 and 213 which become source / drain regions of NMOSFET 211. Yes. A method of applying a tensile stress to the channel region 214 with this silicon carbide epitaxial layer is disclosed (for example, see Non-Patent Document 2).
FIG. 20 is a cross-sectional view taken along the line DD ′ in FIG. 2A and FIG. 2B, and a plan view is shown in FIG.

  However, since the tensile stress due to the silicon carbide (SiC) film changes by finely adjusting the concentration of carbon (C) in the film, it is very difficult to set the conditions for epitaxial growth.

  Further, mobility can be improved by changing the material of the channel itself instead of using stress. For example, as shown in FIG. 21, the channel region 312 of the NMOS transistor 311 is formed of silicon germanium (hereinafter, silicon germanium is referred to as SiGe). By using SiGe for the channel region 312, it is known that the mobility is higher than that in which the channel region 312 is formed of silicon (Si) (see, for example, Non-Patent Document 3).

However, when SiGe is used as the channel, it is difficult to flatten the surface of the channel. This is because, since SiGe is formed by epitaxial growth, the flatness is worse than that of a silicon (Si) channel of a MOSFET that has been used so far.
Further, when the channel is formed of SiGe, the formation of the gate oxide film is different from that of the silicon channel. In order to apply the SiGe channel to the current process, it is necessary to make a major change to the existing process. If possible, a technology that can be introduced into a current process at a minimum cost is desired as a boost technology for increasing mobility.

  Further, as shown in FIG. 22, an isolation insulating film 413 is formed in a trench 412 formed in the upper layer portion of the silicon substrate 411, and the upper layer portion of the silicon substrate 411 is defined as a MOSFET formation region by the isolation insulating film 413. To do. Then, the SiGe layer 414 is thinly formed by ion implantation along the side wall of the trench 412, and a boron (B) -containing SiGe layer 415 is formed by ion implantation in the SiGe layer 414 (inside the trench 412). Thus, it is disclosed that the semiconductor device has an STI (Shallow Trench Isolation) structure capable of effectively suppressing the reverse narrow channel effect (see, for example, Patent Document 1).

  However, since the SiGe layer is formed by ion implantation, the MOSFET formation region is not easily stressed by the SiGe layer. In the first place, since the SiGe layer is not intended to apply stress to the channel formed in the MOSFET formation region, there is no intention to give stress to the SiGe layer.

Further, as shown in FIG. 23, a SiGe buffer layer 512 is formed on a p-type silicon substrate 511, and an element isolation groove 516 for defining an active region 518 is formed on the surface of the SiGe buffer layer 512. On the SiGe buffer layer 512, a SiGe regrowth buffer layer 520 is formed. A strained silicon channel layer 522 is formed on the sidewall of the element isolation trench 516 and the SiGe regrowth buffer layer 520 in the active region 518. Further, a silicon nitride film 524 is formed on the strained silicon channel layer 522 on the side wall of the element isolation trench 516, and an element isolation insulating film 526 is embedded in the element isolation trench 516.
In the MOSFET having such a configuration, compression or tensile strain is applied to the strained silicon channel layer 522, and the formation of a leakage current path at the end of the active region is suppressed, and high-speed operation is possible with low power consumption (for example, , See Patent Document 2).

However, the channel layer of the MOSFET uses SiGe and is not configured to apply stress to the silicon channel. When SiGe is used as a channel, it is difficult to flatten the surface of the channel. This is because, since SiGe is formed by epitaxial growth, the flatness is worse than that of a silicon (Si) channel of a MOSFET that has been used so far.
In addition, when the channel is formed of silicon germanium, the formation of the gate oxide film is different from that of the silicon channel. In order to apply the silicon germanium channel to the current process, it is necessary to make a major change to the existing process. If possible, a technology that can be introduced into a current process at a minimum cost is desired as a boost technology for increasing mobility.

JP 2004-327493 A JP 2004-79874 A E. Leobandung et al. “High Performance 65nm SOI Technology with Dual Stress Liner and low capacitance SRAM cell” 2005 Symposium on VLSI Technology Digest of Technical Papers 8A-1 2005 Kah-Wee Ang et al., "50 nm Silicon-On-Insulator N-MOSFET Featuring Multiple Stressors: Silicon-Carbon Source / Drain Regions and Tensile Stress Silicon Nitride Liner" 2006 Symposium on VLSI Technology Digest of Technical Papers 2006 P.W.Liu et al. “SiGe Channel CMOSFETs Fabricated on (110) Surfaces with TaC / HfO2 Gate Stacks” 2007 IEEE (Institute of Electrical and Electronics Engineers) 2007

  The problem to be solved is that it is difficult to effectively apply tensile stress to the silicon channel region of the N-channel insulated gate field effect transistor.

  The present invention makes it possible to effectively apply a tensile stress to the silicon channel region of an N-channel insulated gate field effect transistor.

  The semiconductor device of the present invention is formed on the silicon substrate, the element forming portion partitioned on the silicon substrate, the N-channel insulated gate field effect transistor formed on the element forming portion, and the silicon substrate. A groove portion surrounding a side portion of the element forming portion; an element isolation portion formed by embedding an insulating material in the groove portion; and a side surface of the groove portion parallel to at least the channel length direction of the N-channel insulated gate field effect transistor The silicon germanium epitaxial growth layer is formed.

In the semiconductor device of the present invention, a silicon germanium epitaxial growth layer is formed on at least a side surface parallel to the channel length direction of the N channel insulated gate field effect transistor in the groove portion surrounding the side portion of the element forming portion made of a silicon substrate. . The silicon germanium epitaxial growth layer has a larger number of lattices than silicon (Si), and tensile stress is applied to the element forming portion by the silicon germanium epitaxial growth layer.
In addition, the silicon germanium epitaxial growth layer not only gives stress to most of the silicon channel portion of the N-channel insulated gate field effect transistor formed in the element forming portion, but also serves as a high mobility channel. .
Therefore, although the portion in contact with the element isolation portion is a parasitic transistor, the characteristics of the N-channel insulated gate field effect transistor are deteriorated. However, the formation of the silicon germanium epitaxial growth layer increases the mobility of the deteriorated parasitic transistor portion. It is done. For this reason, characteristic deterioration of the N-channel insulated gate field effect transistor is suppressed.
Further, as the N-channel insulated gate field effect transistor is miniaturized, the gate width becomes smaller and the stress due to the silicon germanium epitaxial growth layer becomes more effective.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a mask film covering an element forming portion where an N-channel insulated gate field effect transistor of a silicon substrate is formed; and exposing the silicon substrate exposed from the mask film. Forming a trench surrounding the side of the element forming portion, and forming a silicon germanium epitaxial growth layer on at least a side surface of the trench parallel to the channel length direction of the N-channel insulated gate field effect transistor by epitaxial growth. And a step of forming an element isolation portion by embedding an insulating material in the trench, and a step of forming an N-channel insulated gate field effect transistor in the element formation portion.

In the method of manufacturing a semiconductor device according to the present invention, a silicon germanium epitaxial growth layer is formed on at least a side surface parallel to the channel length direction of the N-channel insulated gate field effect transistor in the groove surrounding the side portion of the element forming portion made of a silicon substrate. To do. The silicon germanium epitaxial growth layer has a larger number of lattices than silicon (Si), and a tensile stress is applied to the element forming portion by the silicon germanium epitaxial growth layer.
In addition, the silicon germanium epitaxial growth layer not only gives stress to most of the silicon channel portion of the N-channel insulated gate field effect transistor formed in the element forming portion, but also serves as a high mobility channel. .
Therefore, although the portion in contact with the element isolation portion is a parasitic transistor, the characteristics of the N-channel insulated gate field effect transistor are deteriorated. However, the formation of the silicon germanium epitaxial growth layer increases the mobility of the deteriorated parasitic transistor portion. It is done. For this reason, characteristic deterioration of the N-channel insulated gate field effect transistor is suppressed.
Further, as the N-channel insulated gate field effect transistor is miniaturized, the gate width becomes smaller and the stress due to the silicon germanium epitaxial growth layer becomes more effective.
In addition, since the silicon germanium epitaxial growth layer is formed on a part of the gate end portion, most of the element forming portion is a silicon substrate having a flat surface, so that it matches well with an existing process. .

  In the semiconductor device of the present invention, since the stress of the silicon germanium epitaxial growth layer is directly applied to the channel of the N channel insulated gate field effect transistor, the tensile stress is effectively applied to the channel. Accordingly, the mobility of the transistor can be improved and the on-current can be increased, so that there is an advantage that the transistor performance can be improved.

  According to the method for manufacturing a semiconductor device of the present invention, a tensile stress is effectively applied to the channel by forming a silicon germanium epitaxial growth layer in the channel of the N-channel insulated gate field effect transistor. Accordingly, the mobility of the transistor can be improved and the on-current can be increased, so that there is an advantage that the transistor performance can be improved.

  An embodiment (first example) according to a semiconductor device of the present invention will be described with reference to a schematic cross-sectional view and a plan view of FIG. 1A is a cross-sectional view, and FIG. 1B is a plan view. The cross-sectional view of FIG. 1 is a cross-sectional view taken along the line A-A ′ of FIG.

As shown in FIGS. 1 (1) and (2), a groove portion 13 that partitions the element forming portion 12 is formed in the silicon substrate 11, and an element isolation portion formed by filling the inside of the groove portion 13 with an insulating material. 14 is provided.
An N channel insulated gate field effect transistor (hereinafter referred to as a transistor) 20 is formed in the element forming portion 12. In this transistor 20, a gate electrode 22 is formed on an element forming portion 12 made of a silicon substrate 11 via a gate insulating film 21. The gate electrode 22 is formed to extend from the element forming portion 12 onto the element separating portion 14. Further, source / drain regions 23 and 24 are formed in the element forming portion 12 on both sides of the gate electrode 22.
A silicon germanium epitaxial growth layer (hereinafter referred to as SiGe epilayer) 15 is formed at least on the side surface 13S (first side surface 13SA) of the groove 13 parallel to the channel length L direction of the transistor 20. In the drawing, the configuration in which the SiGe epilayer 15 is formed on the inner surface of the groove 13 is shown. Therefore, it is also formed on the side surface 13S (second side surface 13SB) of the groove 13 parallel to the direction perpendicular to the channel length direction of the transistor 20.

  In the semiconductor device 1 having the above-described configuration, the SiGe epilayer 15 is formed on the side surface 13S (particularly the first side surface 13SA) parallel to the channel length direction of the transistor 20 of the groove portion 13 surrounding the side portion of the element forming portion 12 made of the silicon substrate 11. Is formed. The SiGe epilayer 15 has a larger number of lattices than silicon (Si), and a tensile stress is applied to the element forming portion 12 by the SiGe epilayer 15.

In addition, the SiGe epilayer 15 not only gives stress to most of the silicon channel portion of the transistor 20 formed in the element forming portion 12, but also serves as a channel having high mobility.
Therefore, as shown in FIG. 2, the portion of the element forming portion 12 (the portion indicated by a two-dot chain line in the drawing) in contact with the element isolation portion 14 below the gate electrode 22 is a parasitic transistor 20P, which deteriorates the characteristics of the transistor 20. . However, in the above-described embodiment, the channel of the parasitic transistor 20P that has been deteriorated is formed in the SiGe epilayer 15, so that the mobility of the parasitic transistor 20P is increased. For this reason, the characteristic deterioration of the transistor 20 is suppressed.
Further, as the transistor 20 is miniaturized, the gate width becomes smaller and the stress due to the SiGe epilayer 15 becomes more effective.

  2 shows the configuration in which the SiGe epilayer 15 is formed on the first side surface 13SA of the groove 13, the SiGe epilayer 15 is formed on the entire inner surface of the groove 13 as shown in FIG. However, the characteristic improvement effect of the parasitic transistor 20P can be obtained similarly.

  Next, an embodiment (second example) according to the semiconductor device of the present invention will be described with reference to a schematic sectional view and a plan view of FIG. 3A is a cross-sectional view, and FIG. 3B is a plan view. The cross-sectional view of FIG. 1 is a cross-sectional view taken along the line A-A ′ of FIG.

As shown in FIG. 3, the silicon substrate 11 is provided with a groove portion 13 that partitions the element forming portion 12, and an element isolation portion 14 that is formed by filling the inside of the groove portion 13 with an insulating material.
An N channel insulated gate field effect transistor (hereinafter referred to as a transistor) 20 is formed in the element forming portion 12. In this transistor 20, a gate electrode 22 is formed on an element forming portion 12 made of a silicon substrate 11 via a gate insulating film 21. The gate electrode 22 is formed to extend from the element forming portion 12 onto the element separating portion 14. Further, source / drain regions 23 and 24 are formed in the element forming portion 12 on both sides of the gate electrode 22.
A SiGe epilayer 15 is formed on the side surface 13S (first side surface 13SA) of the groove 13 parallel to the channel length L direction of the transistor 20.

In the semiconductor device 2 configured as described above, the SiGe epilayer 15 is formed on the first side surface 13SA parallel to the channel length direction of the transistor 20 in the groove portion 13 surrounding the side portion of the element forming portion 12 made of the silicon substrate 11. .
The SiGe epilayer 15 has a larger number of lattices than silicon (Si), and a tensile stress is applied to the element forming portion 12 by the SiGe epilayer 15.
The SiGe epilayer 15 is formed on the first side surface 13SA and is not formed on the side surface 13S (second side surface 13SB) of the groove 13 parallel to the direction perpendicular to the channel length direction of the transistor 20. . If the SiGe epi layer 15 is formed on the second side surface 13SB, compressive stress is applied to the element forming portion 12 in a direction that weakens the tensile stress of the SiGe epi layer 15 formed on the first side surface 13SA. become. However, since the compressive stress is smaller than the tensile stress, the tensile stress is not canceled out.
Therefore, in the semiconductor device 2 configured as described above, tensile stress is applied to the element forming portion 12 by the SiGe epi layer 15 more efficiently.

In addition, the SiGe epilayer 15 not only gives stress to most of the silicon channel portion of the transistor 20 formed in the element forming portion 12, but also serves as a channel having high mobility.
Therefore, as described with reference to FIG. 2, the portion of the element forming portion 12 (the portion indicated by a two-dot chain line in the drawing) in contact with the element isolation portion 14 below the gate electrode 22 is the parasitic transistor 20P, and the transistor 20 Deteriorating the characteristics of However, in the above-described embodiment, the channel of the parasitic transistor 20P that has been deteriorated is formed in the SiGe epilayer 15, so that the mobility of the parasitic transistor 20P is increased. For this reason, the characteristic deterioration of the transistor 20 is suppressed.
Further, as the transistor 20 is miniaturized, the gate width becomes smaller and the stress due to the SiGe epilayer 15 becomes more effective.

  Next, an embodiment (third example) according to the semiconductor device of the present invention will be described with reference to a schematic sectional view and a plan view of FIG. 4 (1), (3), and (4) are cross-sectional views, and FIG. 4 (2) is a plan view. The cross-sectional view of FIG. 1 is a cross-sectional view taken along the line A-A ′ of FIG. The cross-sectional view of FIG. 3 is a cross-sectional view taken along line B-B ′ of FIG. 2, and the cross-sectional view of FIG. 4 is a cross-sectional view taken along line C-C ′ of FIG.

As shown in FIGS. 4A and 4B, the silicon substrate 11 is formed with a groove portion 13 that partitions the element forming portion 12, and an element isolation portion formed by filling the inside of the groove portion 13 with an insulating material. 14 is provided.
In the element forming portion 12, a transistor 20 is formed. In this transistor 20, a gate electrode 22 is formed on an element forming portion 12 made of a silicon substrate 11 via a gate insulating film 21. The gate electrode 22 is formed to extend from the element forming portion 12 onto the element separating portion 14. Further, source / drain regions 23 and 24 are formed in the element forming portion 12 on both sides of the gate electrode 22.
A SiGe epi layer 15 is formed on the inner surface of the groove 13. The SiGe epi layer 15 formed on the side surface 13S (first side surface 13SA) of the groove 13 parallel to the channel length L direction of the transistor 20 is parallel to the direction perpendicular to the channel length L direction of the transistor 20. It is formed thicker than the SiGe epilayer 15 formed on the side surface 13S (second side surface 13SB) of the groove 13.

  Next, a means for forming the SiGe epi layer 15 formed on the first side surface 13SA as thicker than the SiGe epi layer 15 formed on the second side surface 13SB as described above will be described below.

The first means will be described below.
As shown in FIG. 4 (3), the first side surface 13 SA of the groove 13 parallel to the channel length L direction of the transistor 20 is formed in a plane perpendicular to the surface of the silicon substrate 11.
4 (4), the second side surface 13SB of the groove 13 parallel to the direction perpendicular to the channel length L direction of the transistor 20 is inclined with respect to the surface of the silicon substrate 11. Is formed.
Usually, the growth rate of the SiGe epilayer 15 is increased in a plane perpendicular to the surface of the silicon substrate 11. In addition, the growth rate of the SiGe epilayer 15 is slow on the inclined surface with respect to the surface of the silicon substrate 11.
As described above, the SiGe epi layer 15 formed on the first side surface 13SA is formed thicker than the SiGe epi layer 15 formed on the second side surface 13SB due to the difference in the growth rate of the SiGe epi layer 15 during epitaxial growth. Yes.

Next, the second means will be described below.
As shown in the plan view of FIG. 5A and the cross-sectional view of the main part of FIG. 5B, the first side surface 13SA of the groove 13 parallel to the channel length L direction of the transistor 20 is in relation to the surface of the silicon substrate 11. Thus, a vertical surface, for example, the first side surface 13SA is formed on the {100} surface.
Usually, the growth rate of the SiGe epilayer 15 in the direction perpendicular to the {100} plane of the silicon substrate 11 is increased. Further, in the second side surface 13SB that is not the {100} plane of the silicon substrate 11, the growth rate of the SiGe epilayer 15 is slower than that of the first side surface 13SA.
As described above, the SiGe epi layer 15 formed on the first side surface 13SA is formed thicker than the SiGe epi layer 15 formed on the second side surface 13SB due to the difference in the growth rate of the SiGe epi layer 15 during epitaxial growth. Yes.

Next, the third means will be described below.
As shown in the plan view of FIG. 6A and the cross-sectional view of the main part of FIG. 6B, the first side surface 13SA of the groove 13 parallel to the channel length direction of the transistor 20 is in relation to the surface of the silicon substrate 11. The vertical surface, for example, the first side surface 13SA is formed on a surface higher than the {100} surface.
Usually, the growth rate of the SiGe epilayer 15 in the direction perpendicular to the plane higher than the {100} plane of the silicon substrate 11 is increased. In addition, in the second side surface 13SB that is not a higher-order surface than the {100} plane of the silicon substrate 11, the growth rate of the SiGe epilayer 15 is slower than that of the first side surface 13SA.
As described above, the SiGe epi layer 15 formed on the first side surface 13SA is formed thicker than the SiGe epi layer 15 formed on the second side surface 13SB due to the difference in the growth rate of the SiGe epi layer 15 during epitaxial growth. Yes.

In the semiconductor device 3 having the above-described configuration, the SiGe epilayer 15 is formed on the side surface 13S (particularly the first side surface 13SA) parallel to the channel length direction of the transistor 20 in the groove portion 13 surrounding the side portion of the element forming portion 12 made of the silicon substrate 11. Is formed. The SiGe epilayer 15 has a larger number of lattices than silicon (Si), and a tensile stress is applied to the element forming portion 12 by the SiGe epilayer 15.
The SiGe epi layer 15 is formed thick on the first side surface 13SA parallel to the channel length direction of the transistor 20, and the second side surface 13SB parallel to the direction perpendicular to the channel length direction of the transistor 20. It is thinly formed. Therefore, even if the SiGe epilayer 15 formed on the second side surface 13SB gives compressive stress to the element forming portion 12 in a direction to weaken the tensile stress of the SiGe epilayer 15 formed on the first side surface 13SA, The effect is small. Therefore, the tensile stress is not canceled by the compressive stress, and the tensile stress increases as the SiGe epilayer 15 is formed thick on the first side surface 13SA.
Therefore, in the semiconductor device 3 configured as described above, tensile stress is applied to the element forming portion 12 by the SiGe epi layer 15 more efficiently.

In addition, the SiGe epilayer 15 not only gives stress to most of the silicon channel portion of the transistor 20 formed in the element forming portion 12, but also serves as a channel having high mobility.
Therefore, as described with reference to FIG. 2, the portion of the element forming portion 12 (the portion indicated by a two-dot chain line in the drawing) in contact with the element isolation portion 14 below the gate electrode 22 is the parasitic transistor 20P, and the transistor 20 Deteriorating the characteristics of However, in the above-described embodiment, the channel of the parasitic transistor 20P that has been deteriorated is formed in the SiGe epilayer 15, so that the mobility of the parasitic transistor 20P is increased. For this reason, the characteristic deterioration of the transistor 20 is suppressed.
Further, as the transistor 20 is miniaturized, the gate width becomes smaller and the stress due to the SiGe epilayer 15 becomes more effective.

  Therefore, a tensile stress is effectively applied to the channel. Accordingly, the mobility of the transistor can be improved and the on-current can be increased, so that there is an advantage that the transistor performance can be improved.

  Next, an embodiment (first example) according to a method for manufacturing a semiconductor device of the present invention will be described with reference to cross-sectional views of manufacturing steps and partial plan views of FIGS.

As shown in FIG. 7A, a mask film 31 is formed on the silicon substrate 11. The mask film 31 is formed in, for example, three layers. For example, it consists of a silicon oxide film 32, a polysilicon film 33, and a silicon nitride film 34. The mask film 31 is not limited to three layers, and may be a two-layer structure of a silicon oxide film and a silicon nitride film, for example.
Next, after forming a resist film on the mask film 31, the resist film is processed by lithography to form the resist film on the mask film 31 above the element forming portion 12 where the N-channel insulated gate field effect transistor is formed. A resist mask (not shown) is formed. Using the resist mask as an etching mask, the mask film 31 is processed to leave the mask film 31 above the element forming portion 12.
Next, the resist mask is removed.

  Next, as shown in FIG. 7B, using the mask film 31 as an etching mask, a groove portion 13 surrounding the side portion of the element forming portion 12 is formed in the silicon substrate 11.

  Next, as shown in FIG. 7 (3), a silicon germanium epitaxial growth layer (hereinafter referred to as a SiGe epitaxial layer) is formed at least on the side surface of the groove 13 parallel to the channel length direction of the N channel insulated gate field effect transistor by an epitaxial growth method. 15) is formed. Here, as an example, the SiGe epilayer 15 is formed by the epitaxial growth method over the entire inner surface of the groove 13 where the silicon substrate 11 is exposed.

The epitaxial growth method is based on selective epitaxial growth in which selective epitaxial growth is performed on the silicon surface of the silicon substrate 11. Hereinafter, an example of selective epitaxial growth conditions will be described.
As the source gas, for example, dichlorosilane (SiH ₂ Cl ₂ : DCS), germane (GeH ₄ ) (for example, 1.5% H ₂ dilution), hydrogen chloride (HCl), and hydrogen (H ₂ ) are used.
The dichlorosilane (SiH ₂ Cl _2: DCS), for example, the supply flow rate and 10cm ³ / min~80cm ³ / min.
The germane _{(GeH 4) (1.5% H} 2 dilution), for example, the supply flow rate and 50cm ³ / min~100cm ³ / min.
The hydrogen chloride (HCl), for example, the supply flow rate and 10cm ³ / min~50cm ³ / min.
The supply flow rate of the hydrogen (H ₂ ) is, for example, 10 cm ³ / min to 50 L / min.
Moreover, the processing temperature at the time of film-forming was set, for example to 650 degreeC-750 degreeC, and the pressure of the atmosphere at the time of film-forming was set to 1.33 kPa-6.67 kPa, for example.

  The SiGe epilayer 15 is made to have an appropriate thickness so that sufficient stress can be expected in the silicon channel portion. For example, the thickness of the SiGe epilayer 15 is about 50 nm with respect to a gate line width of 500 nm.

Next, as shown in FIG. 8 (4), an insulating material is embedded in the groove 13 and a planarization process is performed. This planarization process is performed, for example, by chemical mechanical polishing (CMP). For example, silicon oxide is used as the insulating material.
In this way, the element isolation part 14 in which the insulating material is embedded in the groove part 13 is formed. Therefore, the element forming part 12 is electrically separated by the element separating part 14.

Next, as shown in FIG. 8 (5), the remaining portion of the mask film 31 (see FIG. 7) on the element forming portion 12 of the silicon substrate 11 and excess insulating material, etc. are removed, and the silicon substrate 11 is removed. Expose the surface. Next, after performing cleaning or the like, a gate insulating film 21 is formed on the element forming portion 12 of the silicon substrate 11. The gate insulating film 21 may be formed of, for example, a thermal oxide film in which the surface of the element forming portion 12 is oxidized, or may be formed by chemical vapor deposition or atomic layer deposition.
In addition to the silicon oxide film, a so-called high dielectric constant film can also be used. For example, the high dielectric constant film includes, for example, an oxide, oxysilicide, or oxynitride of hafnium, zirconium, lanthanum, yttrium, tantalum, or aluminum.
Specifically, for example, hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), lanthanum oxide (LaO ₃ ), yttrium oxide (Y ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ) and the like, and is formed from hafnium silicate, zirconium silicate, lanthanum silicate, yttrium silicate, tantalum silicate, aluminum silicate, zirconium titanate, aluminum oxide hafnium or zirconium hafnium oxide, or nitrides of these compounds .

Next, as shown in FIGS. 9 (6) and 9 (7), a gate electrode 22 is formed on the element forming portion 12 via the gate insulating film 21. Here, the gate electrode 22 is formed so as to cross over the SiGe epilayer 15 formed on the first side surface 13SA.
Thereafter, extension regions (not shown) are formed by ion implantation, sidewall spacers (not shown) are formed on the side walls of the gate electrode 22, and source / drain regions 23, 24 are formed in the element forming portion 12 on both sides of the gate electrode 22. And so on.
In this way, the N-channel insulated gate field effect transistor 20 is formed in the element forming portion 12.

In the first embodiment of the semiconductor device manufacturing method, at least a side surface of the groove 13 surrounding the side of the element forming portion 12 made of the silicon substrate 11 is parallel to the channel length direction of the N-channel insulated gate field effect transistor 20. Then, the SiGe epilayer 15 is formed. The SiGe epilayer 15 has a larger number of lattices than silicon (Si), and a tensile stress is applied to the element forming portion 12 by the SiGe epilayer 15.
Further, the SiGe epilayer 15 not only gives stress to most silicon channel portions of the N channel insulated gate field effect transistor 20 formed in the element forming portion 12, but also serves as a channel having high mobility. Also fulfills.
Therefore, although the portion in contact with the element isolation portion 14 is a parasitic transistor, the characteristics of the N-channel insulated gate field effect transistor 20 are deteriorated, but the mobility of the deteriorated parasitic transistor portion due to the formation of the SiGe epilayer 15 is reduced. Is increased. For this reason, characteristic deterioration of the N-channel insulated gate field effect transistor 20 is suppressed.
Further, as the N-channel insulated gate field effect transistor 20 is miniaturized, the width of the gate electrode 22 becomes smaller and the stress due to the SiGe epilayer 15 becomes more effective.
Further, since the SiGe epilayer 15 is formed on a part of the end portion of the gate electrode 22, most of the element forming portion 12 is the silicon substrate 11 having a flat surface. Matches the process well.

  Therefore, a tensile stress is effectively applied to the channel. Accordingly, the mobility of the transistor can be improved and the on-current can be increased, so that there is an advantage that the transistor performance can be improved.

  Next, an embodiment (second embodiment) according to the method for manufacturing a semiconductor device of the present invention will be described with reference to cross-sectional views of manufacturing steps and partial plan views of FIGS.

As shown in FIG. 10A, a mask film 31 is formed on the silicon substrate 11. The mask film 31 is formed in, for example, three layers. For example, it consists of a silicon oxide film 32, a polysilicon film 33, and a silicon nitride film 34. The mask film 31 is not limited to three layers, and may be a two-layer structure of a silicon oxide film and a silicon nitride film, for example.
Next, after forming a resist film on the mask film 31, the resist film is processed by lithography to form the resist film on the mask film 31 above the element forming portion 12 where the N-channel insulated gate field effect transistor is formed. A resist mask (not shown) is formed. Using the resist mask as an etching mask, the mask film 31 is processed to leave the mask film 31 above the element forming portion 12.
Next, the resist mask is removed.

  Next, as shown in FIG. 10B, using the mask film 31 as an etching mask, a groove 13 surrounding the side of the element forming portion 12 is formed in the silicon substrate 11.

Next, as shown in FIG. 10 (3), a sidewall mask film is formed on the second side surface 13SB of the groove 13 parallel to the direction perpendicular to the channel length direction of the N-channel insulated gate field effect transistor of the groove 13. 33 is formed.
In order to form the sidewall mask film 33, for example, a silicon oxide film is formed on the inner surface of the groove 13 by a high density plasma (HDP) CVD method, or a silicon oxide film is formed by a thermal oxidation method. The thickness of the silicon oxide film is, for example, about 50 nm.

  A resist mask (not shown) covering the second side surface 13SB is formed, and the exposed silicon oxide film is removed using the resist mask as an etching mask. This removal method is performed, for example, by wet etching with hydrofluoric acid.

  As shown in the cross-sectional view of FIG. 11 (4) and the plan view of (5), the SiGe epilayer 15 is formed on the exposed first side surface 13SA of the groove 13 by the epitaxial growth method. At this time, the SiGe epilayer 15 is also formed at the bottom of the groove 13.

The epitaxial growth method is based on selective epitaxial growth in which selective epitaxial growth is performed on the silicon surface of the silicon substrate 11. Hereinafter, an example of selective epitaxial growth conditions will be described.
As the source gas, for example, dichlorosilane (SiH ₂ Cl ₂ : DCS), germane (GeH ₄ ) (for example, 1.5% H ₂ dilution), hydrogen chloride (HCl), and hydrogen (H ₂ ) are used.
The dichlorosilane (SiH ₂ Cl _2: DCS), for example, the supply flow rate and 10cm ³ / min~80cm ³ / min.
The germane _{(GeH 4) (1.5% H} 2 dilution), for example, the supply flow rate and 50cm ³ / min~100cm ³ / min.
The hydrogen chloride (HCl), for example, the supply flow rate and 10cm ³ / min~50cm ³ / min.
The supply flow rate of the hydrogen (H ₂ ) is, for example, 10 cm ³ / min to 50 L / min.
Moreover, the processing temperature at the time of film-forming was set, for example to 650 degreeC-750 degreeC, and the pressure of the atmosphere at the time of film-forming was set to 1.33 kPa-6.67 kPa, for example.

  The SiGe epilayer 15 is made to have an appropriate thickness so that sufficient stress can be expected in the silicon channel portion. For example, the thickness of the SiGe epilayer 15 is about 50 nm with respect to a gate line width of 500 nm.

Here, another technique for forming the SiGe epilayer 15 only on the first side surface 13SA will be described below.
As shown in FIG. 12A, a SiGe epilayer 15 is grown on the entire inner surface of the groove 13 to a thickness of about 50 nm, for example.

  Next, as shown in FIG. 12 (2), after forming a resist film on the groove 13 in which the SiGe epilayer 15 is formed, the resist film is processed by a lithography technique, and the first side surface 13 SA is formed. A resist mask 41 to be covered is formed. Using this as an etching mask, the exposed SiGe epilayer 15 is removed. This removal method is performed by, for example, hydrofluoric acid, ammonia addition, or dry etching.

  Next, the resist film 41 is removed. As a result, as shown in FIG. 12 (3), the SiGe epilayer 15 is formed on the first side surface 13 SA of the groove 13. At this time, the SiGe epilayer 15 is also left on the bottom surface of the groove 13.

Next, as shown in FIG. 13 (4), an insulating material is embedded in the groove 13 and a planarization process is performed. This planarization process is performed, for example, by chemical mechanical polishing (CMP). For example, silicon oxide is used as the insulating material.
In this way, the element isolation part 14 in which the insulating material is embedded in the groove part 13 is formed. Therefore, the element forming part 12 is electrically separated by the element separating part 14.

Next, as shown in FIG. 13 (5), the remaining portion of the mask film 31 (see FIG. 7) on the element forming portion 12 of the silicon substrate 11 and excess insulating material, etc. are removed, and the silicon substrate 11 is removed. Expose the surface. Next, after performing cleaning or the like, a gate insulating film 21 is formed on the element forming portion 12 of the silicon substrate 11. The gate insulating film 21 may be formed of, for example, a thermal oxide film in which the surface of the element forming portion 12 is oxidized, or may be formed by chemical vapor deposition or atomic layer deposition.
In addition to the silicon oxide film, a so-called high dielectric constant film can also be used. For example, the high dielectric constant film includes, for example, an oxide, oxysilicide, or oxynitride of hafnium, zirconium, lanthanum, yttrium, tantalum, or aluminum.
Specifically, for example, hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), lanthanum oxide (LaO ₃ ), yttrium oxide (Y ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ) and the like, and is formed from hafnium silicate, zirconium silicate, lanthanum silicate, yttrium silicate, tantalum silicate, aluminum silicate, zirconium titanate, aluminum oxide hafnium or zirconium hafnium oxide, or nitrides of these compounds .

Next, as shown in FIGS. 14 (6) and 14 (7), a gate electrode 22 is formed on the element formation portion 12 via the gate insulating film 21. Here, the gate electrode 22 is formed so as to cross over the SiGe epilayer 15 formed on the first side surface 13SA.
Thereafter, extension regions (not shown) are formed by ion implantation, sidewall spacers (not shown) are formed on the side walls of the gate electrode 22, and source / drain regions 23, 24 are formed in the element forming portion 12 on both sides of the gate electrode 22. And so on.
In this way, the N-channel insulated gate field effect transistor 20 is formed in the element forming portion 12.

In the second embodiment of the semiconductor device manufacturing method, the first side surface of the groove 13 surrounding the side of the element forming portion 12 made of the silicon substrate 11 is parallel to the channel length direction of the N-channel insulated gate field effect transistor 20. The SiGe epilayer 15 is formed on 13SA. The SiGe epilayer 15 has a larger number of lattices than silicon (Si), and a tensile stress is applied to the element forming portion 12 by the SiGe epilayer 15.
The SiGe epilayer 15 is formed on the first side surface 13SA and is not formed on the side surface 13S (second side surface 13SB) of the groove 13 parallel to the direction perpendicular to the channel length direction of the transistor 20. . If the SiGe epi layer 15 is formed on the second side surface 13SB, compressive stress is applied to the element forming portion 12 in a direction that weakens the tensile stress of the SiGe epi layer 15 formed on the first side surface 13SA. become. However, since the compressive stress is smaller than the tensile stress, the tensile stress is not canceled out.
Therefore, in the semiconductor device 2 configured as described above, tensile stress is applied to the element forming portion 12 by the SiGe epi layer 15 more efficiently.

Further, the SiGe epilayer 15 not only gives stress to most silicon channel portions of the N channel insulated gate field effect transistor 20 formed in the element forming portion 12, but also serves as a channel having high mobility. Also fulfills.
Therefore, although the portion in contact with the element isolation portion 14 is a parasitic transistor, the characteristics of the N-channel insulated gate field effect transistor 20 are deteriorated, but the mobility of the deteriorated parasitic transistor portion due to the formation of the SiGe epilayer 15 is reduced. Is increased. For this reason, characteristic deterioration of the N-channel insulated gate field effect transistor 20 is suppressed.
Further, as the N-channel insulated gate field effect transistor 20 is miniaturized, the width of the gate electrode 22 becomes smaller and the stress due to the SiGe epilayer 15 becomes more effective.
Further, since the SiGe epilayer 15 is formed on a part of the end portion of the gate electrode 22, most of the element forming portion 12 is the silicon substrate 11 having a flat surface. Matches the process well.

  Next, an embodiment (third example) according to a method for manufacturing a semiconductor device of the present invention will be described with reference to cross-sectional views of manufacturing steps and partial plan views of FIGS.

  As shown in FIG. 15A, a mask film 31 is formed on the silicon substrate 11. The mask film 31 is formed in, for example, three layers. For example, it consists of a silicon oxide film 32, a polysilicon film 33, and a silicon nitride film 34. The mask film 31 is not limited to three layers, and may be a two-layer structure of a silicon oxide film and a silicon nitride film, for example.

Next, patterning of the mask film 31 is performed by, for example, a lithography technique using a resist mask.
At this time, as shown in FIG. 15B, the first width d1 of the opening of the mask film 31 parallel to the channel length direction of the N-channel insulated gate field effect transistor to be formed later in the element forming portion 12 Is formed to be wider than the second width d2 of the opening of the mask film 31 parallel to the direction perpendicular to the channel length direction of the N-channel insulated gate field effect transistor.

  Next, using the mask film 31 as an etching mask, a groove 13 surrounding the side portion of the element forming portion 12 covered with the mask film 31 is formed in the silicon substrate 11.

As a result, as shown in FIG. 15 (3), the first side surface 13SA of the groove 13 parallel to the channel length direction of the N-channel insulated gate field effect transistor to be formed later in the element forming portion 12 is formed on the silicon substrate. 11 is formed in a plane perpendicular to the surface of 11.
Further, as shown in FIG. 15 (4), the second side surface 13SB parallel to the direction perpendicular to the channel length direction of the N channel insulated gate field effect transistor of the groove portion 13 to be formed later in the element forming portion 12 is formed. , Formed on an inclined surface.

In general, there is a difference in the epitaxial growth rate depending on whether the epitaxial growth surface is perpendicular to the surface of the silicon substrate 11 or an inclined surface, and the surface perpendicular to the surface of the silicon substrate 11 has a higher epitaxial growth rate than the inclined surface. It has been known. This is because an inclined plane causes the growth rate to be slowed because the plane orientation of epitaxial growth deviates from (001).
Accordingly, in the epitaxial growth for a predetermined time, the epitaxial growth film is formed thicker on the vertical surface than on the inclined surface. This principle is used in the following epitaxial growth.

  Next, the SiGe epilayer 15 is formed on the exposed first side surface 13SA and second side surface 13SB of the groove 13 by an epitaxial growth method.

The epitaxial growth method is based on selective epitaxial growth in which selective epitaxial growth is performed on the silicon surface of the silicon substrate 11. Hereinafter, an example of selective epitaxial growth conditions will be described.
As the source gas, for example, dichlorosilane (SiH ₂ Cl ₂ : DCS), germane (GeH ₄ ) (for example, 1.5% H ₂ dilution), hydrogen chloride (HCl), and hydrogen (H ₂ ) are used.
The dichlorosilane (SiH ₂ Cl _2: DCS), for example, the supply flow rate and 10cm ³ / min~80cm ³ / min.
The germane _{(GeH 4) (1.5% H} 2 dilution), for example, the supply flow rate and 50cm ³ / min~100cm ³ / min.
The hydrogen chloride (HCl), for example, the supply flow rate and 10cm ³ / min~50cm ³ / min.
The supply flow rate of the hydrogen (H ₂ ) is, for example, 10 cm ³ / min to 50 L / min.
Moreover, the processing temperature at the time of film-forming was set, for example to 650 degreeC-750 degreeC, and the pressure of the atmosphere at the time of film-forming was set to 1.33 kPa-6.67 kPa, for example.

As a result, the SiGe epilayer 15 is formed on the inner surface of the groove portion 13, and the SiGe epilayer 15 formed on the first side surface 13SA is more than the SiGe epilayer 15 formed on the second side surface 13SB. It is formed thick.
Further, the thickness of the SiGe epilayer 15 formed on the first side surface 13SA is set to an appropriate thickness so that sufficient stress can be expected in the silicon channel portion. For example, the thickness of the SiGe epilayer 15 is about 50 nm with respect to a gate line width of 500 nm.

Next, as shown in FIG. 16 (5), an insulating material is embedded in the groove 13 and planarization is performed. This planarization process is performed, for example, by chemical mechanical polishing (CMP). For example, silicon oxide is used as the insulating material.
In this way, the element isolation part 14 in which the insulating material is embedded in the groove part 13 is formed. Therefore, the element forming part 12 is electrically separated by the element separating part 14.

Next, as shown in FIG. 16 (6), the remaining part of the mask film 31 [see FIG. 7] on the element forming portion 12 of the silicon substrate 11 and the surplus insulating material are removed, and the silicon substrate 11 is removed. Expose the surface. Next, after performing cleaning or the like, a gate insulating film 21 is formed on the element forming portion 12 of the silicon substrate 11. The gate insulating film 21 may be formed of, for example, a thermal oxide film in which the surface of the element forming portion 12 is oxidized, or may be formed by chemical vapor deposition or atomic layer deposition.
In addition to the silicon oxide film, a so-called high dielectric constant film can also be used. For example, the high dielectric constant film includes, for example, an oxide, oxysilicide, or oxynitride of hafnium, zirconium, lanthanum, yttrium, tantalum, or aluminum.
Specifically, for example, hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), lanthanum oxide (LaO ₃ ), yttrium oxide (Y ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), aluminum oxide (Al ₂ O ₃ ) and the like, and is formed from hafnium silicate, zirconium silicate, lanthanum silicate, yttrium silicate, tantalum silicate, aluminum silicate, zirconium titanate, aluminum oxide hafnium or zirconium hafnium oxide, or nitrides of these compounds .

Next, as shown in FIGS. 17 (7) and 17 (8), a gate electrode 22 is formed on the element forming portion 12 via the gate insulating film 21. Here, the gate electrode 22 is formed so as to cross over the SiGe epilayer 15 formed on the first side surface 13SA.
Thereafter, extension regions (not shown) are formed by ion implantation, sidewall spacers (not shown) are formed on the side walls of the gate electrode 22, and source / drain regions 23, 24 are formed in the element forming portion 12 on both sides of the gate electrode 22. And so on.
In this way, the N-channel insulated gate field effect transistor 20 is formed in the element forming portion 12.

Next, another means for forming the SiGe epi layer 15 formed on the first side surface 13SA thicker than the SiGe epi layer 15 formed on the second side surface 13SB will be described below.
As shown in FIG. 18A, the first side surface 13SA of the groove 13 parallel to the channel length direction of the transistor 20 is formed in a plane perpendicular to the surface of the silicon substrate 11, that is, the {100} plane. .
Usually, the growth rate of the SiGe epilayer 15 in the direction perpendicular to the {100} plane of the silicon substrate 11 is increased. Further, in the second side surface 13SB (not shown) that is not the {100} plane of the silicon substrate 11, the growth rate of the SiGe epilayer 15 is slower than that of the first side surface 13SA.
Thus, due to the difference in the growth rate of the SiGe epilayer 15 during the epitaxial growth, the SiGe epilayer 15 formed on the first side surface 13SA is more than the SiGe epilayer 15 formed on the second side surface 13SB (not shown). Is also formed thick.

Next, another means for forming the SiGe epi layer 15 formed on the first side surface 13SA thicker than the SiGe epi layer 15 formed on the second side surface 13SB will be described below.
As shown in FIG. 18 (2), the first side surface 13 SA of the groove 13 parallel to the channel length direction of the transistor 20 is higher than the surface perpendicular to the surface of the silicon substrate 11, that is, the {100} plane. Is formed on the surface. The higher-order surfaces include, for example, {110} plane, {111} plane, {311} plane, {511} plane, and the like.
Usually, the growth rate of the SiGe epilayer 15 in the direction perpendicular to the plane higher than the {100} plane of the silicon substrate 11 is increased. Further, in the second side surface 13SB (not shown) that is not a higher-order surface than the {100} plane of the silicon substrate 11, for example, an inclined surface, the SiGe epilayer 15 is more than in the first side surface 13SA. Slows down the growth rate.
Thus, due to the difference in the growth rate of the SiGe epilayer 15 during the epitaxial growth, the SiGe epilayer 15 formed on the first side surface 13SA is more than the SiGe epilayer 15 formed on the second side surface 13SB (not shown). Is also formed thick.

In the third embodiment of the semiconductor device manufacturing method, the SiGe epilayer 15 is formed on the inner surface of the groove 13 surrounding the side of the element forming portion 12 made of the silicon substrate 11. At that time, the SiGe epilayer 15 formed on the first side surface 13SA parallel to the channel length direction of the transistor 20 is formed thick. On the other hand, the SiGe epilayer 15 formed on the second side surface 13SB parallel to the direction perpendicular to the channel length direction of the transistor 20 is thinly formed. The SiGe epilayer 15 has a larger number of lattices than silicon (Si), and a tensile stress is applied to the element forming portion 12 by the SiGe epilayer 15. At that time, the SiGe epilayer 15 formed on the first side surface 13SA to which the tensile stress is effectively applied is formed thicker than the SiGe epilayer 15 formed on the second side surface 13SB. Compared with the case where the SiGe epilayer 15 is formed on the inner surface with a uniform film thickness, the tensile stress applied to the element forming portion 12 is large.
Further, the SiGe epilayer 15 not only gives stress to most silicon channel portions of the N channel insulated gate field effect transistor 20 formed in the element forming portion 12, but also serves as a channel having high mobility. Also fulfills.
Therefore, although the portion in contact with the element isolation portion 14 is a parasitic transistor, the characteristics of the N-channel insulated gate field effect transistor 20 are deteriorated, but the mobility of the deteriorated parasitic transistor portion due to the formation of the SiGe epilayer 15 is reduced. Is increased. For this reason, characteristic deterioration of the N-channel insulated gate field effect transistor 20 is suppressed.
Further, as the N-channel insulated gate field effect transistor 20 is miniaturized, the width of the gate electrode 22 becomes smaller and the stress due to the SiGe epilayer 15 becomes more effective.
Further, since the SiGe epilayer 15 is formed on a part of the end portion of the gate electrode 22, most of the element forming portion 12 is the silicon substrate 11 having a flat surface. Matches the process well.

  Therefore, a tensile stress is effectively applied to the channel. Accordingly, the mobility of the transistor can be improved and the on-current can be increased, so that there is an advantage that the transistor performance can be improved.

  In each of the above embodiments, when viewed from above the surface of the silicon substrate 11, that is, when seen in a plan view, the SiGe epi layer 15 is also formed at the corners of the element forming portion 12. Layer 15 is not necessarily required. The SiGe epilayer 15 only needs to include at least the channel region in the first side surface 13SA of the groove 13 where the element isolation portion 14 is formed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view and plan view showing an embodiment (first embodiment) according to a semiconductor device of the present invention. It is a top view explaining a parasitic transistor. It is the schematic block diagram and top view which showed one Embodiment (2nd Example) which concerns on the semiconductor device of this invention. It is the schematic block diagram and top view which showed one Embodiment (3rd Example) which concerns on the semiconductor device of this invention. It is the top view and principal part sectional drawing which showed the modification in 3rd Example. It is the top view and principal part sectional drawing which showed the modification in 3rd Example. It is manufacturing process sectional drawing which showed one Embodiment (1st Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (1st Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is a manufacturing process sectional view and a top view showing one embodiment (the 1st example) concerning a manufacturing method of a semiconductor device of the present invention. It is manufacturing process sectional drawing which showed one Embodiment (2nd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (2nd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (2nd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (2nd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing and the top view which showed one Embodiment (2nd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (3rd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing which showed one Embodiment (3rd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is manufacturing process sectional drawing and the top view which showed one Embodiment (3rd Example) which concerns on the manufacturing method of the semiconductor device of this invention. It is principal part sectional drawing which showed the modification in 3rd Example. It is sectional drawing which showed an example of the prior art. It is sectional drawing and the top view which showed an example of the prior art. It is sectional drawing which showed an example of the prior art. It is sectional drawing which showed an example of the prior art. It is sectional drawing which showed an example of the prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 11 ... Silicon substrate, 12 ... Element formation part, 13 ... Groove part, 14 ... Element isolation part, 15 ... Silicon germanium epitaxial growth layer, 20 ... N channel insulated gate field effect transistor

Claims (14)

A silicon substrate;
An element forming section partitioned into the silicon substrate;
An N-channel insulated gate field effect transistor formed in the element forming portion;
A groove portion formed on the silicon substrate and surrounding a side portion of the element forming portion;
An element isolation part formed by embedding an insulating material in the groove part;
A semiconductor device comprising at least a silicon germanium epitaxial growth layer formed on a side surface of the groove parallel to a channel length direction of the N-channel insulated gate field effect transistor. The semiconductor device according to claim 1, wherein the silicon germanium epitaxial growth layer is formed on an inner surface of the groove. The semiconductor device according to claim 1, wherein the silicon germanium epitaxial growth layer is formed only on a first side surface of the groove portion parallel to a channel length direction of the N-channel insulated gate field effect transistor. The silicon germanium epitaxial growth layer is formed on the inner surface of the groove,
The silicon germanium epitaxial growth layer formed on the first side surface of the groove parallel to the channel length direction of the N channel insulated gate field effect transistor is perpendicular to the channel length direction of the N channel insulated gate field effect transistor. The semiconductor device according to claim 1, wherein the semiconductor device is formed thicker than the silicon germanium epitaxial growth layer formed on the second side surface of the groove portion parallel to a specific direction. The silicon germanium epitaxial growth layer is formed on the inner surface of the groove,
A first side surface of the groove parallel to the channel length direction of the N-channel insulated gate field effect transistor is formed in a plane perpendicular to the surface of the silicon substrate;
A second side surface of the groove parallel to a direction perpendicular to the channel length direction of the N-channel insulated gate field effect transistor is formed to be inclined with respect to the surface of the silicon substrate;
The semiconductor device according to claim 1, wherein the silicon germanium epitaxial growth layer formed on the first side surface is formed thicker than the silicon germanium epitaxial growth layer formed on the second side surface. The silicon germanium epitaxial growth layer is formed on the inner surface of the groove,
The first side surface of the groove parallel to the channel length direction of the N-channel insulated gate field effect transistor has a {100} plane.
The silicon germanium epitaxial growth layer formed on the first side surface is formed of the silicon germanium formed on the second side surface of the groove portion parallel to a direction perpendicular to the channel length direction of the N-channel insulated gate field effect transistor. The semiconductor device according to claim 1, wherein the semiconductor device is formed thicker than the epitaxially grown layer. The silicon germanium epitaxial growth layer is formed on the inner surface of the groove,
The first side surface of the groove parallel to the channel length direction of the N-channel insulated gate field effect transistor is formed on a surface whose surface is higher than the {100} surface,
The silicon germanium epitaxial growth layer formed on the first side surface is formed of the silicon germanium formed on the second side surface of the groove portion parallel to a direction perpendicular to the channel length direction of the N-channel insulated gate field effect transistor. The semiconductor device according to claim 1, wherein the semiconductor device is formed thicker than the epitaxially grown layer. Forming a mask film covering an element formation portion on which an N-channel insulated gate field effect transistor is formed on a silicon substrate;
Forming a groove portion surrounding a side portion of the element forming portion in the silicon substrate exposed from the mask film;
Forming a silicon germanium epitaxial growth layer on a side surface of the groove parallel to at least the channel length direction of the N-channel insulated gate field effect transistor by an epitaxial growth method;
Forming an element isolation portion by embedding an insulating material in the groove portion;
A method for manufacturing a semiconductor device, comprising: forming an N-channel insulated gate field effect transistor in the element formation portion. The method for manufacturing a semiconductor device according to claim 8, wherein the silicon germanium epitaxial growth layer is formed on an inner surface of the groove. After forming the groove and before forming the silicon germanium epitaxial growth layer,
Forming a sidewall mask film covering a second side surface of the groove parallel to a direction perpendicular to the channel length direction of the N-channel insulated gate field effect transistor;
The semiconductor device according to claim 8, wherein in the step of forming the silicon germanium epitaxial growth layer, the silicon germanium epitaxial growth layer is formed on a first side surface of the groove portion parallel to a channel length direction of the N-channel insulated gate field effect transistor. Manufacturing method. The groove is
The first width of the groove parallel to the channel length direction of the N-channel insulated gate field effect transistor has a first width parallel to the direction perpendicular to the channel length direction of the N-channel insulated gate field effect transistor. Formed wider than the second width;
The silicon germanium epitaxial growth layer is formed on the inner surface of the groove,
The silicon germanium epitaxial growth layer formed on the first side surface of the groove parallel to the channel length direction of the N channel insulated gate field effect transistor is perpendicular to the channel length direction of the N channel insulated gate field effect transistor. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor germanium epitaxial growth layer is formed thicker than the silicon germanium epitaxial growth layer formed on the second side surface of the groove portion parallel to a specific direction. The groove is
A first side surface of the groove parallel to the channel length direction of the N-channel insulated gate field effect transistor is formed in a plane perpendicular to the surface of the silicon substrate;
A second side surface of the groove parallel to a direction perpendicular to the channel length direction of the N-channel insulated gate field effect transistor is formed to be inclined with respect to the surface of the silicon substrate;
The silicon germanium epitaxial growth layer is formed on the inner surface of the groove,
The method of manufacturing a semiconductor device according to claim 8, wherein the silicon germanium epitaxial growth layer formed on the first side surface is formed thicker than the silicon germanium epitaxial growth layer formed on the second side surface. The groove is
A first side surface of the groove parallel to the channel length direction of the N-channel insulated gate field effect transistor is formed on a {100} plane;
The silicon germanium epitaxial growth layer is formed on the inner surface of the groove,
The silicon germanium epitaxial growth layer formed on the first side surface is formed of the silicon germanium formed on the second side surface of the groove portion parallel to a direction perpendicular to the channel length direction of the N-channel insulated gate field effect transistor. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is formed thicker than the epitaxially grown layer. The groove is
A first side surface of the groove parallel to the channel length direction of the N-channel insulated gate field effect transistor is formed on a surface higher than the {100} surface;
The silicon germanium epitaxial growth layer is formed on the inner surface of the groove,
The silicon germanium epitaxial growth layer formed on the first side surface is formed of the silicon germanium formed on the second side surface of the groove portion parallel to a direction perpendicular to the channel length direction of the N-channel insulated gate field effect transistor. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor device is formed thicker than the epitaxially grown layer.

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