JP2011009580A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device that improves transistor characteristics.SOLUTION: The semiconductor device is manufactured by carrying out a process of preparing an Si substrate 101 including an STI 109, a p-type well 102 and an n-type well 103 separated from each other by the STI 109, and an SiGe film 108 formed on the p-type well 102 and n-type well 103, a process of coating the SiGe film 108 positioned on the n-type well 103 with an SiOfilm 116, a process ((c)) of oxidizing the SiGe film 108 formed on the p-type well 102 through oxidation processing using the SiOfilm 116 as a mask to form an SiGeOfilm 117, and a process ((d)) of removing the SiGeOfilm 117.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  In a state-of-the-art silicon LSI, in particular, a MOS (Metal-Oxide-Semiconductor) / MIS (Metal-Insulator-Semiconductor) transistor is formed by forming a compound semiconductor film having a different composition on the outermost surface of a silicon (Si) channel layer. It has been studied to improve circuit operation. As the compound semiconductor film, a silicon germanium (SiGe) film, a germanium (Ge) film, a III-V group compound semiconductor film, or the like is selected, and it is expected to improve carrier mobility compared to Si.

  As a method for selectively forming the compound semiconductor film, there is a technique for selectively growing the compound semiconductor film only in a necessary region on the Si substrate. An example of this technique is described in Patent Document 1. Patent Document 1 describes that since the SiGe layer is provided only in the P-type transistor, the performance of the N-type MOS transistor is maintained and high mobility in the P-type MOS transistor is obtained. In addition, since the gate insulating film is formed on the P-type well in the N-type transistor and on the SiGe layer in the P-type transistor, the difference in the height of the surface of the gate insulating film between the two transistors is different between the SiGe layer. It is described that it becomes only the thickness, and it is possible to suppress the occurrence of problems due to the difference in height.

  However, in the technique such as Patent Document 1, (1) the region in which the compound semiconductor film is grown is relatively narrow, and the film formation speed must be greatly different depending on the area of the base to be formed. ) The compound semiconductor film is easy to grow in a region that should not be grown, and the range of selection of process conditions becomes narrow. (3) When the mask material is left in the region that should not be grown, in order to secure its masking ability There are problems such as limitations on wet processing.

  As a method for solving these problems (1) to (3), there is a technique of removing a compound semiconductor film from an unnecessary region after being formed on a wide area of a Si substrate. An example of this technique is described in Patent Document 2. In Patent Document 2, an impurity-doped carrier supply layer and an undoped (or low-doped) channel layer have an inverse structure, a lattice-relaxed silicon germanium layer (first semiconductor layer), a tensile strained silicon layer (second And a lattice-relaxed silicon germanium layer (third semiconductor layer) are stacked to form a p-channel and n-channel heterojunction FET on the same substrate in a three-layer structure of semiconductor layers. It is described that it can be integrated. As a result, it is described that the operation speed can be increased.

JP 2004-235345 A JP-A-10-93025

  However, in the prior art exemplified in Patent Document 2, when an unnecessary portion of the compound semiconductor film is removed, the underlying structure (for example, a silicon substrate) is etched to cause damage or deterioration of the surface morphology. As a result, there is a problem of deteriorating transistor characteristics.

According to the present invention,
Preparing a substrate having an element isolation film, first and second wells separated from each other by the element isolation film, and a compound semiconductor film formed on the first and second wells;
Coating the compound semiconductor film located on the first well with a mask film;
Oxidizing the compound semiconductor film formed on the second well by performing an oxidation treatment using the mask film as a mask;
Removing the oxidized compound semiconductor film;
A method for manufacturing a semiconductor device is provided.

  Moreover, according to this invention, the semiconductor device manufactured by said method is provided.

  According to this invention, by oxidizing only the compound semiconductor film formed on the second well, the etching rate of the compound semiconductor film can be made faster than the etching rate of the underlying substrate. Thereby, the compound semiconductor film formed on the second well can be selectively removed, and damage to the second well and deterioration of the surface morphology can be suppressed. Therefore, transistor characteristics can be improved by a simple method.

  According to the present invention, transistor characteristics can be improved.

It is a figure explaining the manufacturing method of the semiconductor device which concerns on embodiment. It is a figure explaining the manufacturing method of the semiconductor device which concerns on embodiment. It is a figure explaining the manufacturing method of the semiconductor device which concerns on embodiment. It is a figure explaining the effect of the manufacturing method of the semiconductor device concerning an embodiment. It is a figure explaining the effect of the manufacturing method of the semiconductor device concerning an embodiment. It is a figure explaining the manufacturing method of the semiconductor device which concerns on a modification. It is a figure explaining the manufacturing method of the conventional semiconductor device.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

1 to 3 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to this embodiment. This manufacturing method includes STI (Shallow Trench Isolation) 109, p-type well 102 and n-type well 103 separated from each other by STI 109, and silicon formed on p-type well 102 and n-type well 103. A step of preparing a silicon substrate (Si substrate) 101 having a germanium film (SiGe film) 108 (FIG. 1A), and a SiGe film 108 located on the n-type well 103 are converted into a silicon oxide film (SiO ₂ film, (Step (b) in FIG. 1) covered with a mask film) 116, and oxidation treatment is performed using the SiO ₂ film 116 as a mask to oxidize the SiGe film 108 formed on the p-type well 102, thereby producing a silicon germanium oxide film. The step of forming the (Si _x Ge _y O _z film) 117 (FIG. 2C), and the Si _x And a step of removing the Ge _y O _z film 117 and the mask SiO ₂ film 116 (FIG. 2D).

  Hereinafter, the method for manufacturing the semiconductor device of this embodiment will be described in detail. First, the STI 109 is created on the Si substrate 101. Next, impurities are implanted into the Si substrate 101 to produce a p-type well 102 and an n-type well 103. A region where the p-type well 102 is provided is referred to as an nMOS region, and a region where the n-type well 103 is provided is referred to as a pMOS region. The nMOS region is a region where an n-type MOS transistor is formed, and the pMOS region is a region where a p-type MOS transistor is formed. Next, the SiGe film 108 is epitaxially grown on the p-type well 102 and the n-type well 103, respectively (FIG. 1A). The film thickness of the SiGe film 108 is arbitrarily determined according to the expected magnitude of strain. The Ge atom concentration of the SiGe film 108 is preferably 20% or more.

Next, a SiO ₂ film 116 is grown on the entire surface of the Si substrate 101 by using a CVD (Chemical Vapor Deposition) method. Next, a resist is applied, and the SiO ₂ film 116 is left only on the n-type well 103 by using a general exposure / development technique to expose the SiGe film 108 on the p-type well 102 (FIG. 1B). . By doing so, only the SiGe film 108 in the pMOS region can be covered with the SiO ₂ film 116. Here, the thickness of the SiO ₂ film 116 is ensured so that the SiGe film 108 on the n-type well 103 is not etched in the etching process of the Si _x Ge _y O _z film 117 described later.

Next, the exposed SiGe film 108 on the p-type well 102 is heat-treated in an oxidizing gas atmosphere. As the oxidizing gas, for example, oxygen gas, ozone gas, a mixed gas of oxygen and hydrogen, water vapor, a mixed gas of hydrochloric acid gas and oxygen, or the like can be used. Furthermore, the heat treatment apparatus can be a resistance heating Furnace called a normal oxidation furnace, or a single wafer processing apparatus using lamp heating. A silicon film containing germanium (Ge) has a very high oxidation rate. For this reason, the SiGe film 108 on the p-type well 102 is rapidly oxidized to form a thick Si _x Ge _y O _z film 117 (FIG. 2C). On the other hand, since the SiO ₂ film 116 is sufficiently thick, the diffusion of the oxidized species is sufficiently limited, and does not reach the SiGe film 108 on the n-type well 103. As a result, the oxidation rate becomes very slow, and a new SiGe oxide film on the n-type well 103 is not formed.

Next, the Si _x Ge _y O _z film 117 is removed by wet etching by immersing it in a fluorine-containing etching solution (FIG. 2D). Here, a solution containing fluorine is used as an etching solution. For example, hydrofluoric acid (HF), buffered hydrofluoric acid (mixed solution of NH ₄ F and HF), or a chemical solution obtained by appropriately diluting them with H ₂ O can be used. The Si _x Ge _y O _z film 117 has an extremely high etching rate with an HF-based chemical compared to Si. Furthermore, since the etching rate is very high even compared with the SiO ₂ film used for normal STI, it is removed without greatly affecting the underlying p-type well 102 and the surrounding STI 109. In addition, the Si _x Ge _y O _z film 117 has a higher etching rate than the SiGe film 108. Therefore, the SiGe film 108 on the n-type well 103 can be removed without affecting it. At this time, by controlling the film quality and film thickness of the SiO ₂ film _116, it is possible to simultaneously remove the SiO ₂ film 116 upon removal of the Si x _Ge y _{O z} layer 117.

Next, a gate insulating film 111 is formed on the SiGe film 108 formed only in the n-type well 103 and the exposed p-type well 102. For example, as a material of the gate insulating film 111, in addition to a general SiO ₂ film, an oxide film containing an oxynitride film (SiON, oxynitride), hafnium (Hf), zirconium (Zr), aluminum (Al), etc. Further, those containing yttrium (Y) or lanthanum (La) are used as additives. In addition to the thermal oxidation method, a CVD method, an ALD (atomic layer deposition) method, or a combination thereof with a PVD (Physical Vapor Deposition) method is appropriately selected as the film formation method. Further, an LTO (Low Temperature Oxide) deposited film, an ONO (SiO ₂ / Si ₃ N ₄ / SiO ₂ ) laminated film, or the like can be selected as appropriate.

  Next, the gate electrode 112 is formed on the gate insulating film 111 by performing etching using a resist mask (not shown). Next, ions are implanted using a resist mask (not shown) to introduce a p-type impurity into the gate electrode 112 on the n-type well 103 and to inject a p-type impurity into the surface of the n-type well 103. Thus, the p-type extension region 106 is formed. Further, an n-type impurity is introduced into the gate electrode 112 on the p-type well 102 and an n-type impurity is implanted into the surface of the p-type well 102 to form an n-type extension region 107. Next, a sidewall 113 made of a silicon oxide film or a silicon nitride film is formed on the side wall of the gate electrode 112. Next, ions are implanted at a higher concentration than the p-type extension region 106 using a resist mask (not shown) to form a p + source / drain (SD) region 104. Further, ions are implanted at a higher concentration than that of the n-type extension region 107 to form an n + source / drain (SD) region 105. Next, an interlayer insulating film 110 is formed so as to cover the entire surface of the exposed silicon substrate 101, and is planarized by CMP (Chemical Mechanical Polishing). Next, an opening is formed in the interlayer insulating film 110 so as to reach the p + SD region 104, the n + SD region 105, and the gate electrode 112, and this opening is filled with the contact metal 114. Thereafter, a wiring 115 is formed on the contact metal 114, and a CMOS (Complementary Metal Oxide Semiconductor) in which an n-type MOS transistor is formed in the nMOS region and a p-type MOS transistor is formed in the pMOS region is formed as shown in FIG. Finalize.

It continues and demonstrates the effect of this embodiment. According to the method of the present embodiment, the etching rate of the Si _x Ge _y O ₂ film 117 formed by oxidizing the SiGe film 108 is reduced by oxidizing only the SiGe film 108 formed on the p-type well 102. The p-type well 102 can be made faster. Thereby, the SiGe film 108 formed on the p-type well 102 can be selectively removed, and damage to the underlying p-type well 102 and deterioration of the surface morphology can be suppressed. Therefore, transistor characteristics can be improved by a simple method.

FIG. 7 shows a case where a SiGe film 108 is selectively grown as a compound semiconductor film on the p-type well 102 and the n-type well 103 formed on the Si substrate 101, and the SiGe film 108 is left only in the pMOS region. A conventional example is shown. In the method shown in FIG. 7, first, a SiGe film 108 is grown in a region where the surface of the Si substrate 101 in both the nMOS and pMOS regions is exposed. For the mask film 916, a resist or a hard mask such as SiO ₂ is used. After masking only the pMOS region with the mask film 916, the exposed SiGe film 108 in the nMOS region is selectively etched. As the etching, dry etching or wet etching is used. For example, in wet etching, an alkaline chemical is generally used.

  However, in this conventional example, the etching selectivity of the underlying p-type well 102 is low with respect to the SiGe film 108 by dry etching or wet etching. For this reason, it has been quite difficult to remove only the upper SiGe film 108 without affecting the lower p-type well 102. For example, when dry etching is used, the p-type well 102 after the removal of the SiGe film 108 is damaged. In addition, wet etching with an alkaline chemical solution not only makes it difficult to control the thickness of the SiGe film 108 to be removed, but also extremely deteriorates the morphology of the underlying p-type well 102 surface. Since the surface of the underlying p-type well 102 is a channel portion of the nMOS transistor that is in contact with the gate insulating film, the mobility of the nMOS transistor is degraded.

  In the technique of Patent Document 2, a strain relaxation SiGe layer, a strain Si layer, and a strain relaxation SiGe layer are sequentially stacked on a Si substrate, and the uppermost SiGe layer and the strained Si layer below it are selected only in the region where the pMOS is formed. It is described that it is removed. Although the removal method is not mentioned, a multilayer Si layer is formed under the SiGe layer, and a process of sufficiently removing not only the upper SiGe layer but also the lower Si layer is used. Therefore, in this conventional example, there is a problem of process variation, such as not etching the lower Si layer.

On the other hand, according to the method of the present embodiment, for example, an HF-based fluorine-containing chemical solution can be used to remove the Si _x Ge _y O _z film 117 in the pMOS region. With the HF chemical solution, the p-type well 102 can hardly be etched. Therefore, in the nMOS region, the Si _x Ge _y O _z film 117 can be removed while keeping the surface of the p-type well 102 serving as the channel region smooth without damage. As a result, the SiGe film 108 necessary for improving the carrier mobility of the pMOS region can be selectively formed without degrading the mobility of the nMOS transistor.

Further, by increasing the Ge atom concentration in the Si _x Ge _y O _z film 117, the oxidation rate can be made faster than that of the p-type well 102, and a sufficient etching rate can be ensured. For example, if the Ge atom concentration is 20% or more, it can be made 5 times faster than a normal Si layer. If the Ge atom concentration is 30%, the oxidation rate is 10 times or more that of a normal Si layer.

  Further, by controlling the film thickness of the SiGe film 108, the oxidation rate of the SiGe film 108 can be controlled. FIG. 4 shows the oxide film thickness with respect to the oxidation time of the SiGe film (I). FIG. 4A shows a case where the SiGe film (I) is sufficiently thick. FIG. 4B shows a case where the SiGe film (I) has a certain thickness (thinner than the SiGe film shown in FIG. 4A). As shown in the figure, it can be seen that the SiGe film (I) has a much faster oxide film formation speed than the Si substrate (II). Furthermore, although it increases monotonously when the SiGe film is sufficiently thick (FIG. 4A), it suddenly increases in a certain time when the SiGe film is limited to a certain thickness (FIG. 4B). Shows a saturation tendency. This indicates that the SiGe film is entirely an oxide film, and the oxidized species has reached the underlying silicon substrate. That is, the oxidation time and the thickness of the SiGe film 108 can be set beyond the saturation inflection point.

Further, the SiO ₂ film 116 that masks the SiGe film 108 in the pMOS region can be set sufficiently thick with respect to its oxidation time (film thickness). By doing so, oxidation of the SiGe film 108 under the SiO ₂ film 116 can be suppressed. For example, if the SiGe film 108 is 5 nm, the film thickness of the Si _x Ge _y O _z film 117 may be assumed to be about 20 nm, and if a 10-fold oxidation rate can be realized, the condition for oxidizing about 2 nm with respect to Si. Will be selected. Therefore, if the thickness of the SiO ₂ film 116 is set to about 20 nm, the SiGe film 108 under the SiO ₂ film 116 can be prevented from being oxidized.

_Further, by controlling the thickness of the Si x _Ge y _{O z} layer 117, _and, by selecting the Si x _Ge y _{O z} etchant can etch the film 117 at a high etching rate, complete SiGe film 108 in the nMOS region Can be removed.

FIG. 5 shows examples of HF-based etching rates for various oxide films. The SiO ₂ film (A), which is a mask film, has an etching rate about twice that of the Si _x Ge _y O _z film (B). STI (C) has an etch rate of about 1/5. Although not shown, the etching rate of the Si substrate and the SiGe film is almost zero in this graph. This means that the SiO ₂ film of the mask can accept a film thickness approximately twice that of the Si _x Ge _y O _z layer. In other words, it means that the 20 nm SiO ₂ film of the mask can be completely removed when removing the 20 nm Si _x Ge _y O _z layer. On the other hand, the STI can be reduced slightly (about 4 nm) as compared with the Si _x Ge _y O _z layer and the mask SiO ₂ film.

Further, by selecting the film quality and film thickness of the SiO ₂ film 116 _can be Si x _Ge y _{O z} layer 117 simultaneously with the SiO ₂ film 116 is also etched. By simultaneously removing the SiO ₂ film 116 and the Si _x Ge _y O _z film 117, the number of steps can be reduced. Further, as shown in FIG. 5, since the STI 109 is also etched in a small amount, there is a concern that the removal of the SiO ₂ film 116 and the Si _x Ge _y O _z film 117 may cause the height of the STI 109 to vary. _{If the two} films 116 and the Si _x Ge _y O _z film 117 can be removed at the same time, such a problem can be reduced.

As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.
For example, in the embodiment, the example in which the SiGe film 108 is epitaxially grown after the STI 109, the p-type well 102, and the n-type well 103 are formed on the Si substrate 101 has been described. Although the SiGe film can be stably grown by expanding the area to both the pMOS region and the nMOS region, the SiGe film can be further stably grown. As shown in FIG. 6, after the SiGe film 108 is epitaxially grown on the entire surface of the Si substrate 101 (FIG. 6A), an STI 109 is formed (FIG. 6B), and impurities are implanted to form a p-type. In this method, the well 102 and the n-type well 103 are formed (FIG. 1A). When this method is selected, film formation is always performed on the entire surface of the wafer, so that the conditions for the desired Ge concentration and film thickness are uniquely determined. In the method of the embodiment, for example, when the area of the n-type well 103 to be deposited varies depending on the product, it is necessary to change the Ge concentration and the film thickness in accordance with the area of the n-type well 103. FIG. In the method shown, such tuning for each product is not necessary, and the SiGe film 108 can be grown stably.

  In the embodiment, the SiGe film has been described as an example. Instead, a Ge film, a SiC film, or a film mainly composed of a compound semiconductor composed of a group III element and a group V element, more preferably A film made of a group III element and a group V element may be used. A compound semiconductor film composed of a group III element and a group V element has a greater oxidation selectivity with respect to the Si film at a lower temperature than the case of the SiGe film. For example, pure water can be used for etching the oxide film of a compound semiconductor composed of a group III element and a group V element. Examples of compound semiconductors composed of group III elements and group V elements include GaAs, InAs, InSb, InP, and the like. Such a compound semiconductor is suitable as a channel material for an N-type MOS transistor. Although the electron mobility of GaAs and InP is 3 to 6 times that of Si, it is suitable for low power consumption due to the wide forbidden band. InAs and InSb are The electron mobility is several tens of times that of Si. Furthermore, in the present invention, instead of the SiGe film of the embodiment, a laminated film of compound semiconductor films having different compositions may be used. Such a laminated film can be formed by arbitrarily laminating a SiGe film, a Ge film, and a compound semiconductor film made of a group III element and a group V element.

  In the embodiments, the Si substrate has been described as an example. However, an SOI (Silicon On Insulator) substrate in which a silicon film is formed on an insulating film, or an SiGe film and an Si film are stacked on the insulating film. It can also be a substrate.

  Furthermore, in the embodiment, the configuration in which the SiGe film is formed only in the pMOS region has been described as an example. However, a SiC film or a compound semiconductor film composed of a group III element and a group V element is formed only in the nMOS region. May be.

101 silicon substrate 102 p-type well 103 n-type well 104 p + source / drain region 105 n + source / drain region 106 p-type extension region 107 n-type extension region 108 silicon germanium film 109 element isolation film 110 interlayer insulating film 111 gate insulating film 112 gate electrode 113 Side wall 114 Contact metal 115 Wiring 116 Silicon oxide film 117 Silicon germanium oxide film 916 Mask film

Claims (12)

Preparing a substrate having an element isolation film, first and second wells separated from each other by the element isolation film, and a compound semiconductor film formed on the first and second wells;
Coating the compound semiconductor film located on the first well with a mask film;
Oxidizing the compound semiconductor film formed on the second well by performing an oxidation treatment using the mask film as a mask;
Removing the oxidized compound semiconductor film;
A method of manufacturing a semiconductor device including:   The method for manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor film is a film containing silicon germanium.   The method for manufacturing a semiconductor device according to claim 2, wherein a concentration of germanium atoms contained in the silicon germanium is 20% or more.   4. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of oxidizing the compound semiconductor film formed on the second well, the compound semiconductor film is heat-treated in an oxidizing gas atmosphere. 5.   5. The method of manufacturing a semiconductor device according to claim 1, wherein a silicon oxide film is formed as the mask film in the step of covering with the mask film.   6. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of removing the oxidized compound semiconductor film, the oxidized compound semiconductor film is removed by wet etching using a fluorine-containing etchant. Method.   7. The step of removing the oxidized compound semiconductor film, wherein the oxidized compound semiconductor film is removed and the mask film located on the first well is removed. Semiconductor device manufacturing method.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor film contains SiC or a compound semiconductor composed of a group III element and a group V element as a main component.   The method for manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor film is a stacked film of compound semiconductor films having different compositions.   The substrate is selected from the group consisting of a silicon substrate, an SOI (Silicon On Insulator) substrate in which a silicon film is formed on an insulating film, and a substrate in which a silicon germanium film and a silicon film are stacked on the insulating film. A method for manufacturing a semiconductor device according to claim 1. Forming a P-type MOS transistor having an N-type well as the first well;
Forming an N-type MOS transistor having a P-type well as the second well;
The method for manufacturing a semiconductor device according to claim 1, further comprising:   A semiconductor device manufactured by the method according to claim 1.

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